diff options
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 205 |
1 files changed, 37 insertions, 168 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h index fc9c98617281..142358a105c5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h @@ -12,163 +12,40 @@ #include "dpu_hw_util.h" #include "dpu_hw_mdss.h" -/** - * dpu_intr_type - HW Interrupt Type - * @DPU_IRQ_TYPE_WB_ROT_COMP: WB rotator done - * @DPU_IRQ_TYPE_WB_WFD_COMP: WB WFD done - * @DPU_IRQ_TYPE_PING_PONG_COMP: PingPong done - * @DPU_IRQ_TYPE_PING_PONG_RD_PTR: PingPong read pointer - * @DPU_IRQ_TYPE_PING_PONG_WR_PTR: PingPong write pointer - * @DPU_IRQ_TYPE_PING_PONG_AUTO_REF: PingPong auto refresh - * @DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK: PingPong Tear check - * @DPU_IRQ_TYPE_PING_PONG_TE_CHECK: PingPong TE detection - * @DPU_IRQ_TYPE_INTF_UNDER_RUN: INTF underrun - * @DPU_IRQ_TYPE_INTF_VSYNC: INTF VSYNC - * @DPU_IRQ_TYPE_CWB_OVERFLOW: Concurrent WB overflow - * @DPU_IRQ_TYPE_HIST_VIG_DONE: VIG Histogram done - * @DPU_IRQ_TYPE_HIST_VIG_RSTSEQ: VIG Histogram reset - * @DPU_IRQ_TYPE_HIST_DSPP_DONE: DSPP Histogram done - * @DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ: DSPP Histogram reset - * @DPU_IRQ_TYPE_WD_TIMER: Watchdog timer - * @DPU_IRQ_TYPE_SFI_VIDEO_IN: Video static frame INTR into static - * @DPU_IRQ_TYPE_SFI_VIDEO_OUT: Video static frame INTR out-of static - * @DPU_IRQ_TYPE_SFI_CMD_0_IN: DSI CMD0 static frame INTR into static - * @DPU_IRQ_TYPE_SFI_CMD_0_OUT: DSI CMD0 static frame INTR out-of static - * @DPU_IRQ_TYPE_SFI_CMD_1_IN: DSI CMD1 static frame INTR into static - * @DPU_IRQ_TYPE_SFI_CMD_1_OUT: DSI CMD1 static frame INTR out-of static - * @DPU_IRQ_TYPE_SFI_CMD_2_IN: DSI CMD2 static frame INTR into static - * @DPU_IRQ_TYPE_SFI_CMD_2_OUT: DSI CMD2 static frame INTR out-of static - * @DPU_IRQ_TYPE_PROG_LINE: Programmable Line interrupt - * @DPU_IRQ_TYPE_AD4_BL_DONE: AD4 backlight - * @DPU_IRQ_TYPE_CTL_START: Control start - * @DPU_IRQ_TYPE_RESERVED: Reserved for expansion - */ -enum dpu_intr_type { - DPU_IRQ_TYPE_WB_ROT_COMP, - DPU_IRQ_TYPE_WB_WFD_COMP, - DPU_IRQ_TYPE_PING_PONG_COMP, - DPU_IRQ_TYPE_PING_PONG_RD_PTR, - DPU_IRQ_TYPE_PING_PONG_WR_PTR, - DPU_IRQ_TYPE_PING_PONG_AUTO_REF, - DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, - DPU_IRQ_TYPE_PING_PONG_TE_CHECK, - DPU_IRQ_TYPE_INTF_UNDER_RUN, - DPU_IRQ_TYPE_INTF_VSYNC, - DPU_IRQ_TYPE_CWB_OVERFLOW, - DPU_IRQ_TYPE_HIST_VIG_DONE, - DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, - DPU_IRQ_TYPE_HIST_DSPP_DONE, - DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, - DPU_IRQ_TYPE_WD_TIMER, - DPU_IRQ_TYPE_SFI_VIDEO_IN, - DPU_IRQ_TYPE_SFI_VIDEO_OUT, - DPU_IRQ_TYPE_SFI_CMD_0_IN, - DPU_IRQ_TYPE_SFI_CMD_0_OUT, - DPU_IRQ_TYPE_SFI_CMD_1_IN, - DPU_IRQ_TYPE_SFI_CMD_1_OUT, - DPU_IRQ_TYPE_SFI_CMD_2_IN, - DPU_IRQ_TYPE_SFI_CMD_2_OUT, - DPU_IRQ_TYPE_PROG_LINE, - DPU_IRQ_TYPE_AD4_BL_DONE, - DPU_IRQ_TYPE_CTL_START, - DPU_IRQ_TYPE_RESERVED, +/* When making changes be sure to sync with dpu_intr_set */ +enum dpu_hw_intr_reg { + MDP_SSPP_TOP0_INTR, + MDP_SSPP_TOP0_INTR2, + MDP_SSPP_TOP0_HIST_INTR, + /* All MDP_INTFn_INTR should come sequentially */ + MDP_INTF0_INTR, + MDP_INTF1_INTR, + MDP_INTF2_INTR, + MDP_INTF3_INTR, + MDP_INTF4_INTR, + MDP_INTF5_INTR, + MDP_INTF6_INTR, + MDP_INTF7_INTR, + MDP_INTF8_INTR, + MDP_INTF1_TEAR_INTR, + MDP_INTF2_TEAR_INTR, + MDP_AD4_0_INTR, + MDP_AD4_1_INTR, + MDP_INTR_MAX, }; -struct dpu_hw_intr; - -/** - * Interrupt operations. - */ -struct dpu_hw_intr_ops { - /** - * irq_idx_lookup - Lookup IRQ index on the HW interrupt type - * Used for all irq related ops - * @intr_type: Interrupt type defined in dpu_intr_type - * @instance_idx: HW interrupt block instance - * @return: irq_idx or -EINVAL for lookup fail - */ - int (*irq_idx_lookup)( - enum dpu_intr_type intr_type, - u32 instance_idx); - - /** - * enable_irq - Enable IRQ based on lookup IRQ index - * @intr: HW interrupt handle - * @irq_idx: Lookup irq index return from irq_idx_lookup - * @return: 0 for success, otherwise failure - */ - int (*enable_irq)( - struct dpu_hw_intr *intr, - int irq_idx); - - /** - * disable_irq - Disable IRQ based on lookup IRQ index - * @intr: HW interrupt handle - * @irq_idx: Lookup irq index return from irq_idx_lookup - * @return: 0 for success, otherwise failure - */ - int (*disable_irq)( - struct dpu_hw_intr *intr, - int irq_idx); - - /** - * clear_all_irqs - Clears all the interrupts (i.e. acknowledges - * any asserted IRQs). Useful during reset. - * @intr: HW interrupt handle - * @return: 0 for success, otherwise failure - */ - int (*clear_all_irqs)( - struct dpu_hw_intr *intr); +#define MDP_INTFn_INTR(intf) (MDP_INTF0_INTR + (intf - INTF_0)) - /** - * disable_all_irqs - Disables all the interrupts. Useful during reset. - * @intr: HW interrupt handle - * @return: 0 for success, otherwise failure - */ - int (*disable_all_irqs)( - struct dpu_hw_intr *intr); +#define DPU_IRQ_IDX(reg_idx, offset) (1 + reg_idx * 32 + offset) +#define DPU_IRQ_REG(irq_idx) ((irq_idx - 1) / 32) +#define DPU_IRQ_BIT(irq_idx) ((irq_idx - 1) % 32) - /** - * dispatch_irqs - IRQ dispatcher will call the given callback - * function when a matching interrupt status bit is - * found in the irq mapping table. - * @intr: HW interrupt handle - * @cbfunc: Callback function pointer - * @arg: Argument to pass back during callback - */ - void (*dispatch_irqs)( - struct dpu_hw_intr *intr, - void (*cbfunc)(void *arg, int irq_idx), - void *arg); +#define DPU_NUM_IRQS (MDP_INTR_MAX * 32) - /** - * get_interrupt_statuses - Gets and store value from all interrupt - * status registers that are currently fired. - * @intr: HW interrupt handle - */ - void (*get_interrupt_statuses)( - struct dpu_hw_intr *intr); - - /** - * clear_intr_status_nolock() - clears the HW interrupts without lock - * @intr: HW interrupt handle - * @irq_idx: Lookup irq index return from irq_idx_lookup - */ - void (*clear_intr_status_nolock)( - struct dpu_hw_intr *intr, - int irq_idx); - - /** - * get_interrupt_status - Gets HW interrupt status, and clear if set, - * based on given lookup IRQ index. - * @intr: HW interrupt handle - * @irq_idx: Lookup irq index return from irq_idx_lookup - * @clear: True to clear irq after read - */ - u32 (*get_interrupt_status)( - struct dpu_hw_intr *intr, - int irq_idx, - bool clear); +struct dpu_hw_intr_entry { + void (*cb)(void *arg); + void *arg; + atomic_t count; }; /** @@ -177,30 +54,22 @@ struct dpu_hw_intr_ops { * @ops: function pointer mapping for IRQ handling * @cache_irq_mask: array of IRQ enable masks reg storage created during init * @save_irq_status: array of IRQ status reg storage created during init - * @irq_idx_tbl_size: total number of irq_idx mapped in the hw_interrupts * @irq_lock: spinlock for accessing IRQ resources + * @irq_cb_tbl: array of IRQ callbacks */ struct dpu_hw_intr { struct dpu_hw_blk_reg_map hw; - struct dpu_hw_intr_ops ops; - u32 *cache_irq_mask; + u32 cache_irq_mask[MDP_INTR_MAX]; u32 *save_irq_status; - u32 irq_idx_tbl_size; spinlock_t irq_lock; unsigned long irq_mask; + const struct dpu_intr_reg *intr_set; + + struct dpu_hw_intr_entry irq_tbl[DPU_NUM_IRQS]; }; -/** - * dpu_hw_intr_init(): Initializes the interrupts hw object - * @addr: mapped register io address of MDP - * @m : pointer to mdss catalog data - */ -struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, - struct dpu_mdss_cfg *m); +struct dpu_hw_intr *dpu_hw_intr_init(struct drm_device *dev, + void __iomem *addr, + const struct dpu_mdss_cfg *m); -/** - * dpu_hw_intr_destroy(): Cleanup interrutps hw object - * @intr: pointer to interrupts hw object - */ -void dpu_hw_intr_destroy(struct dpu_hw_intr *intr); #endif |