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path: root/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
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Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h')
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h46
1 files changed, 18 insertions, 28 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
index aa21fd834398..04efdcd21ceb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
@@ -1,13 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef _DPU_HW_TOP_H
@@ -16,7 +8,6 @@
#include "dpu_hw_catalog.h"
#include "dpu_hw_mdss.h"
#include "dpu_hw_util.h"
-#include "dpu_hw_blk.h"
struct dpu_hw_mdp;
@@ -38,7 +29,7 @@ struct traffic_shaper_cfg {
/**
* struct split_pipe_cfg - pipe configuration for dual display panels
- * @en : Enable/disable dual pipe confguration
+ * @en : Enable/disable dual pipe configuration
* @mode : Panel interface mode
* @intf : Interface id for main control path
* @split_flush_en: Allows both the paths to be flushed when master path is
@@ -73,7 +64,14 @@ struct dpu_vsync_source_cfg {
u32 pp_count;
u32 frame_rate;
u32 ppnumber[PINGPONG_MAX];
- u32 vsync_source;
+ enum dpu_vsync_source vsync_source;
+};
+
+enum dpu_dp_phy_sel {
+ DPU_DP_PHY_NONE,
+ DPU_DP_PHY_0,
+ DPU_DP_PHY_1,
+ DPU_DP_PHY_2,
};
/**
@@ -84,7 +82,7 @@ struct dpu_vsync_source_cfg {
* @setup_traffic_shaper : programs traffic shaper control
*/
struct dpu_hw_mdp_ops {
- /** setup_split_pipe() : Regsiters are not double buffered, thisk
+ /** setup_split_pipe() : Registers are not double buffered, thisk
* function should be called before timing control enable
* @mdp : mdp top context driver
* @cfg : upper and lower part of pipe configuration
@@ -135,11 +133,11 @@ struct dpu_hw_mdp_ops {
struct dpu_danger_safe_status *status);
/**
- * reset_ubwc - reset top level UBWC configuration
+ * dp_phy_intf_sel - configure intf to phy mapping
* @mdp: mdp top context driver
- * @m: pointer to mdss catalog data
+ * @phys: list of phys the DP interfaces should be connected to. 0 disables the INTF.
*/
- void (*reset_ubwc)(struct dpu_hw_mdp *mdp, struct dpu_mdss_cfg *m);
+ void (*dp_phy_intf_sel)(struct dpu_hw_mdp *mdp, enum dpu_dp_phy_sel phys[2]);
/**
* intf_audio_select - select the external interface for audio
@@ -153,23 +151,15 @@ struct dpu_hw_mdp {
struct dpu_hw_blk_reg_map hw;
/* top */
- enum dpu_mdp idx;
const struct dpu_mdp_cfg *caps;
/* ops */
struct dpu_hw_mdp_ops ops;
};
-/**
- * dpu_hw_mdptop_init - initializes the top driver for the passed idx
- * @idx: Interface index for which driver object is required
- * @addr: Mapped register io address of MDP
- * @m: Pointer to mdss catalog data
- */
-struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx,
- void __iomem *addr,
- const struct dpu_mdss_cfg *m);
-
-void dpu_hw_mdp_destroy(struct dpu_hw_mdp *mdp);
+struct dpu_hw_mdp *dpu_hw_mdptop_init(struct drm_device *dev,
+ const struct dpu_mdp_cfg *cfg,
+ void __iomem *addr,
+ const struct dpu_mdss_version *mdss_rev);
#endif /*_DPU_HW_TOP_H */