diff options
Diffstat (limited to 'drivers/gpu/drm/msm/dsi')
24 files changed, 3218 insertions, 5777 deletions
diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c index 75afc12a7b25..d8bb40ef820e 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.c +++ b/drivers/gpu/drm/msm/dsi/dsi.c @@ -5,12 +5,21 @@ #include "dsi.h" -struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi *msm_dsi) +bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi) { - if (!msm_dsi || !msm_dsi_device_connected(msm_dsi)) - return NULL; + unsigned long host_flags = msm_dsi_host_get_mode_flags(msm_dsi->host); - return msm_dsi->encoder; + return !(host_flags & MIPI_DSI_MODE_VIDEO); +} + +struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi) +{ + return msm_dsi_host_get_dsc_config(msm_dsi->host); +} + +bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi) +{ + return msm_dsi_host_is_wide_bus_enabled(msm_dsi->host); } static int dsi_get_phy(struct msm_dsi *msm_dsi) @@ -26,17 +35,22 @@ static int dsi_get_phy(struct msm_dsi *msm_dsi) } phy_pdev = of_find_device_by_node(phy_node); - if (phy_pdev) + if (phy_pdev) { msm_dsi->phy = platform_get_drvdata(phy_pdev); + msm_dsi->phy_dev = &phy_pdev->dev; + } of_node_put(phy_node); - if (!phy_pdev || !msm_dsi->phy) { + if (!phy_pdev) { + DRM_DEV_ERROR(&pdev->dev, "%s: phy driver is not ready\n", __func__); + return -EPROBE_DEFER; + } + if (!msm_dsi->phy) { + put_device(&phy_pdev->dev); DRM_DEV_ERROR(&pdev->dev, "%s: phy driver is not ready\n", __func__); return -EPROBE_DEFER; } - - msm_dsi->phy_dev = get_device(&phy_pdev->dev); return 0; } @@ -103,22 +117,26 @@ destroy_dsi: static int dsi_bind(struct device *dev, struct device *master, void *data) { - struct drm_device *drm = dev_get_drvdata(master); - struct msm_drm_private *priv = drm->dev_private; - struct platform_device *pdev = to_platform_device(dev); - struct msm_dsi *msm_dsi; + struct msm_drm_private *priv = dev_get_drvdata(master); + struct msm_dsi *msm_dsi = dev_get_drvdata(dev); - DBG(""); - msm_dsi = dsi_init(pdev); - if (IS_ERR(msm_dsi)) { - /* Don't fail the bind if the dsi port is not connected */ - if (PTR_ERR(msm_dsi) == -ENODEV) - return 0; - else - return PTR_ERR(msm_dsi); + /* + * Next bridge doesn't exist for the secondary DSI host in a bonded + * pair. + */ + if (!msm_dsi_is_bonded_dsi(msm_dsi) || + msm_dsi_is_master_dsi(msm_dsi)) { + struct drm_bridge *ext_bridge; + + ext_bridge = devm_drm_of_get_bridge(&msm_dsi->pdev->dev, + msm_dsi->pdev->dev.of_node, 1, 0); + if (IS_ERR(ext_bridge)) + return PTR_ERR(ext_bridge); + + msm_dsi->next_bridge = ext_bridge; } - priv->dsi[msm_dsi->id] = msm_dsi; + priv->kms->dsi[msm_dsi->id] = msm_dsi; return 0; } @@ -126,15 +144,11 @@ static int dsi_bind(struct device *dev, struct device *master, void *data) static void dsi_unbind(struct device *dev, struct device *master, void *data) { - struct drm_device *drm = dev_get_drvdata(master); - struct msm_drm_private *priv = drm->dev_private; + struct msm_drm_private *priv = dev_get_drvdata(master); struct msm_dsi *msm_dsi = dev_get_drvdata(dev); - int id = msm_dsi->id; - if (priv->dsi[id]) { - dsi_destroy(msm_dsi); - priv->dsi[id] = NULL; - } + msm_dsi_tx_buf_free(msm_dsi->host); + priv->kms->dsi[msm_dsi->id] = NULL; } static const struct component_ops dsi_ops = { @@ -142,20 +156,46 @@ static const struct component_ops dsi_ops = { .unbind = dsi_unbind, }; -static int dsi_dev_probe(struct platform_device *pdev) +int dsi_dev_attach(struct platform_device *pdev) { return component_add(&pdev->dev, &dsi_ops); } -static int dsi_dev_remove(struct platform_device *pdev) +void dsi_dev_detach(struct platform_device *pdev) { - DBG(""); component_del(&pdev->dev, &dsi_ops); +} + +static int dsi_dev_probe(struct platform_device *pdev) +{ + struct msm_dsi *msm_dsi; + + DBG(""); + msm_dsi = dsi_init(pdev); + if (IS_ERR(msm_dsi)) { + /* Don't fail the bind if the dsi port is not connected */ + if (PTR_ERR(msm_dsi) == -ENODEV) + return 0; + else + return PTR_ERR(msm_dsi); + } + return 0; } +static void dsi_dev_remove(struct platform_device *pdev) +{ + struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); + + DBG(""); + dsi_destroy(msm_dsi); +} + static const struct of_device_id dt_match[] = { { .compatible = "qcom,mdss-dsi-ctrl" }, + + /* Deprecated, don't use */ + { .compatible = "qcom,dsi-ctrl-6g-qcm2290" }, {} }; @@ -192,78 +232,33 @@ void __exit msm_dsi_unregister(void) int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, struct drm_encoder *encoder) { - struct msm_drm_private *priv; - struct drm_bridge *ext_bridge; int ret; - if (WARN_ON(!encoder) || WARN_ON(!msm_dsi) || WARN_ON(!dev)) - return -EINVAL; - - priv = dev->dev_private; msm_dsi->dev = dev; ret = msm_dsi_host_modeset_init(msm_dsi->host, dev); if (ret) { DRM_DEV_ERROR(dev->dev, "failed to modeset init host: %d\n", ret); - goto fail; + return ret; } - if (!msm_dsi_manager_validate_current_config(msm_dsi->id)) - goto fail; - - msm_dsi->encoder = encoder; - - msm_dsi->bridge = msm_dsi_manager_bridge_init(msm_dsi->id); - if (IS_ERR(msm_dsi->bridge)) { - ret = PTR_ERR(msm_dsi->bridge); - DRM_DEV_ERROR(dev->dev, "failed to create dsi bridge: %d\n", ret); - msm_dsi->bridge = NULL; - goto fail; + if (msm_dsi_is_bonded_dsi(msm_dsi) && + !msm_dsi_is_master_dsi(msm_dsi)) { + /* + * Do not return an eror here, + * Just skip creating encoder/connector for the slave-DSI. + */ + return 0; } - /* - * check if the dsi encoder output is connected to a panel or an - * external bridge. We create a connector only if we're connected to a - * drm_panel device. When we're connected to an external bridge, we - * assume that the drm_bridge driver will create the connector itself. - */ - ext_bridge = msm_dsi_host_get_bridge(msm_dsi->host); - - if (ext_bridge) - msm_dsi->connector = - msm_dsi_manager_ext_bridge_init(msm_dsi->id); - else - msm_dsi->connector = - msm_dsi_manager_connector_init(msm_dsi->id); - - if (IS_ERR(msm_dsi->connector)) { - ret = PTR_ERR(msm_dsi->connector); + ret = msm_dsi_manager_connector_init(msm_dsi, encoder); + if (ret) { DRM_DEV_ERROR(dev->dev, "failed to create dsi connector: %d\n", ret); - msm_dsi->connector = NULL; - goto fail; + return ret; } - msm_dsi_manager_setup_encoder(msm_dsi->id); - - priv->bridges[priv->num_bridges++] = msm_dsi->bridge; - priv->connectors[priv->num_connectors++] = msm_dsi->connector; - return 0; -fail: - /* bridge/connector are normally destroyed by drm: */ - if (msm_dsi->bridge) { - msm_dsi_manager_bridge_destroy(msm_dsi->bridge); - msm_dsi->bridge = NULL; - } - - /* don't destroy connector if we didn't make it */ - if (msm_dsi->connector && !msm_dsi->external_bridge) - msm_dsi->connector->funcs->destroy(msm_dsi->connector); - - msm_dsi->connector = NULL; - - return ret; } void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi) diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 9b8e9b07eced..93c028a122f3 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -12,7 +12,6 @@ #include <drm/drm_bridge.h> #include <drm/drm_crtc.h> #include <drm/drm_mipi_dsi.h> -#include <drm/drm_panel.h> #include "msm_drv.h" #include "disp/msm_disp_snapshot.h" @@ -30,68 +29,32 @@ enum msm_dsi_phy_usecase { MSM_DSI_PHY_SLAVE, }; -#define DSI_DEV_REGULATOR_MAX 8 #define DSI_BUS_CLK_MAX 4 -/* Regulators for DSI devices */ -struct dsi_reg_entry { - char name[32]; - int enable_load; - int disable_load; -}; - -struct dsi_reg_config { - int num; - struct dsi_reg_entry regs[DSI_DEV_REGULATOR_MAX]; -}; - struct msm_dsi { struct drm_device *dev; struct platform_device *pdev; - /* connector managed by us when we're connected to a drm_panel */ - struct drm_connector *connector; - /* internal dsi bridge attached to MDP interface */ - struct drm_bridge *bridge; - struct mipi_dsi_host *host; struct msm_dsi_phy *phy; + const char *te_source; - /* - * panel/external_bridge connected to dsi bridge output, only one of the - * two can be valid at a time - */ - struct drm_panel *panel; - struct drm_bridge *external_bridge; + struct drm_bridge *next_bridge; struct device *phy_dev; bool phy_enabled; - /* the encoder we are hooked to (outside of dsi block) */ - struct drm_encoder *encoder; - int id; }; /* dsi manager */ -struct drm_bridge *msm_dsi_manager_bridge_init(u8 id); -void msm_dsi_manager_bridge_destroy(struct drm_bridge *bridge); -struct drm_connector *msm_dsi_manager_connector_init(u8 id); -struct drm_connector *msm_dsi_manager_ext_bridge_init(u8 id); +int msm_dsi_manager_connector_init(struct msm_dsi *msm_dsi, + struct drm_encoder *encoder); int msm_dsi_manager_cmd_xfer(int id, const struct mipi_dsi_msg *msg); bool msm_dsi_manager_cmd_xfer_trigger(int id, u32 dma_base, u32 len); -void msm_dsi_manager_setup_encoder(int id); int msm_dsi_manager_register(struct msm_dsi *msm_dsi); void msm_dsi_manager_unregister(struct msm_dsi *msm_dsi); -bool msm_dsi_manager_validate_current_config(u8 id); - -/* msm dsi */ -static inline bool msm_dsi_device_connected(struct msm_dsi *msm_dsi) -{ - return msm_dsi->panel || msm_dsi->external_bridge; -} - -struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi *msm_dsi); +void msm_dsi_manager_tpg_enable(void); /* dsi host */ struct msm_dsi_host; @@ -107,23 +70,27 @@ void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, u32 len); int msm_dsi_host_enable(struct mipi_dsi_host *host); int msm_dsi_host_disable(struct mipi_dsi_host *host); +void msm_dsi_host_enable_irq(struct mipi_dsi_host *host); +void msm_dsi_host_disable_irq(struct mipi_dsi_host *host); int msm_dsi_host_power_on(struct mipi_dsi_host *host, struct msm_dsi_phy_shared_timings *phy_shared_timings, - bool is_dual_dsi); + bool is_bonded_dsi, struct msm_dsi_phy *phy); int msm_dsi_host_power_off(struct mipi_dsi_host *host); int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, const struct drm_display_mode *mode); -struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host); +enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, + const struct drm_display_mode *mode); unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host); -struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host); -int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer); +int msm_dsi_host_register(struct mipi_dsi_host *host); void msm_dsi_host_unregister(struct mipi_dsi_host *host); +void msm_dsi_host_set_phy_mode(struct mipi_dsi_host *host, + struct msm_dsi_phy *src_phy); int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, struct msm_dsi_phy *src_phy); void msm_dsi_host_reset_phy(struct mipi_dsi_host *host); void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, struct msm_dsi_phy_clk_request *clk_req, - bool is_dual_dsi); + bool is_bonded_dsi); void msm_dsi_host_destroy(struct mipi_dsi_host *host); int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, struct drm_device *dev); @@ -131,29 +98,39 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi); int msm_dsi_runtime_suspend(struct device *dev); int msm_dsi_runtime_resume(struct device *dev); int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host); +int dsi_link_clk_set_rate_6g_v2_9(struct msm_dsi_host *msm_host); int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host); int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host); int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host); void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host); void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host); +unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_dsi, + const struct drm_display_mode *mode); int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size); int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size); void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host); void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host); void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host); +void msm_dsi_tx_buf_free(struct mipi_dsi_host *mipi_host); int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *iova); int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *iova); int dsi_clk_init_v2(struct msm_dsi_host *msm_host); int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host); -int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi); -int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi); +int dsi_clk_init_6g_v2_9(struct msm_dsi_host *msm_host); +int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi); +int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi); void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host); +void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host); +struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host); +bool msm_dsi_host_is_wide_bus_enabled(struct mipi_dsi_host *host); + /* dsi phy */ struct msm_dsi_phy; struct msm_dsi_phy_shared_timings { u32 clk_post; u32 clk_pre; bool clk_pre_inc_by_2; + bool byte_intf_clk_div_2; }; struct msm_dsi_phy_clk_request { @@ -164,17 +141,15 @@ struct msm_dsi_phy_clk_request { void msm_dsi_phy_driver_register(void); void msm_dsi_phy_driver_unregister(void); int msm_dsi_phy_enable(struct msm_dsi_phy *phy, - struct msm_dsi_phy_clk_request *clk_req); + struct msm_dsi_phy_clk_request *clk_req, + struct msm_dsi_phy_shared_timings *shared_timings); void msm_dsi_phy_disable(struct msm_dsi_phy *phy); -void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy, - struct msm_dsi_phy_shared_timings *shared_timing); void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy, enum msm_dsi_phy_usecase uc); -int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy, - struct clk **byte_clk_provider, struct clk **pixel_clk_provider); void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy); int msm_dsi_phy_pll_restore_state(struct msm_dsi_phy *phy); void msm_dsi_phy_snapshot(struct msm_disp_state *disp_state, struct msm_dsi_phy *phy); +bool msm_dsi_phy_set_continuous_clock(struct msm_dsi_phy *phy, bool enable); #endif /* __DSI_CONNECTOR_H__ */ diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h deleted file mode 100644 index eadbcc78fd72..000000000000 --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h +++ /dev/null @@ -1,635 +0,0 @@ -#ifndef DSI_XML -#define DSI_XML - -/* Autogenerated file, DO NOT EDIT manually! - -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git - -The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) - -Copyright (C) 2013-2021 by the following authors: -- Rob Clark <robdclark@gmail.com> (robclark) -- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - - -enum dsi_traffic_mode { - NON_BURST_SYNCH_PULSE = 0, - NON_BURST_SYNCH_EVENT = 1, - BURST_MODE = 2, -}; - -enum dsi_vid_dst_format { - VID_DST_FORMAT_RGB565 = 0, - VID_DST_FORMAT_RGB666 = 1, - VID_DST_FORMAT_RGB666_LOOSE = 2, - VID_DST_FORMAT_RGB888 = 3, -}; - -enum dsi_rgb_swap { - SWAP_RGB = 0, - SWAP_RBG = 1, - SWAP_BGR = 2, - SWAP_BRG = 3, - SWAP_GRB = 4, - SWAP_GBR = 5, -}; - -enum dsi_cmd_trigger { - TRIGGER_NONE = 0, - TRIGGER_SEOF = 1, - TRIGGER_TE = 2, - TRIGGER_SW = 4, - TRIGGER_SW_SEOF = 5, - TRIGGER_SW_TE = 6, -}; - -enum dsi_cmd_dst_format { - CMD_DST_FORMAT_RGB111 = 0, - CMD_DST_FORMAT_RGB332 = 3, - CMD_DST_FORMAT_RGB444 = 4, - CMD_DST_FORMAT_RGB565 = 6, - CMD_DST_FORMAT_RGB666 = 7, - CMD_DST_FORMAT_RGB888 = 8, -}; - -enum dsi_lane_swap { - LANE_SWAP_0123 = 0, - LANE_SWAP_3012 = 1, - LANE_SWAP_2301 = 2, - LANE_SWAP_1230 = 3, - LANE_SWAP_0321 = 4, - LANE_SWAP_1032 = 5, - LANE_SWAP_2103 = 6, - LANE_SWAP_3210 = 7, -}; - -#define DSI_IRQ_CMD_DMA_DONE 0x00000001 -#define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002 -#define DSI_IRQ_CMD_MDP_DONE 0x00000100 -#define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200 -#define DSI_IRQ_VIDEO_DONE 0x00010000 -#define DSI_IRQ_MASK_VIDEO_DONE 0x00020000 -#define DSI_IRQ_BTA_DONE 0x00100000 -#define DSI_IRQ_MASK_BTA_DONE 0x00200000 -#define DSI_IRQ_ERROR 0x01000000 -#define DSI_IRQ_MASK_ERROR 0x02000000 -#define REG_DSI_6G_HW_VERSION 0x00000000 -#define DSI_6G_HW_VERSION_MAJOR__MASK 0xf0000000 -#define DSI_6G_HW_VERSION_MAJOR__SHIFT 28 -static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) -{ - return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK; -} -#define DSI_6G_HW_VERSION_MINOR__MASK 0x0fff0000 -#define DSI_6G_HW_VERSION_MINOR__SHIFT 16 -static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) -{ - return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK; -} -#define DSI_6G_HW_VERSION_STEP__MASK 0x0000ffff -#define DSI_6G_HW_VERSION_STEP__SHIFT 0 -static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) -{ - return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK; -} - -#define REG_DSI_CTRL 0x00000000 -#define DSI_CTRL_ENABLE 0x00000001 -#define DSI_CTRL_VID_MODE_EN 0x00000002 -#define DSI_CTRL_CMD_MODE_EN 0x00000004 -#define DSI_CTRL_LANE0 0x00000010 -#define DSI_CTRL_LANE1 0x00000020 -#define DSI_CTRL_LANE2 0x00000040 -#define DSI_CTRL_LANE3 0x00000080 -#define DSI_CTRL_CLK_EN 0x00000100 -#define DSI_CTRL_ECC_CHECK 0x00100000 -#define DSI_CTRL_CRC_CHECK 0x01000000 - -#define REG_DSI_STATUS0 0x00000004 -#define DSI_STATUS0_CMD_MODE_ENGINE_BUSY 0x00000001 -#define DSI_STATUS0_CMD_MODE_DMA_BUSY 0x00000002 -#define DSI_STATUS0_CMD_MODE_MDP_BUSY 0x00000004 -#define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY 0x00000008 -#define DSI_STATUS0_DSI_BUSY 0x00000010 -#define DSI_STATUS0_INTERLEAVE_OP_CONTENTION 0x80000000 - -#define REG_DSI_FIFO_STATUS 0x00000008 -#define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_OVERFLOW 0x00000001 -#define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_UNDERFLOW 0x00000008 -#define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW 0x00000080 -#define DSI_FIFO_STATUS_CMD_DMA_FIFO_RD_WATERMARK_REACH 0x00000100 -#define DSI_FIFO_STATUS_CMD_DMA_FIFO_WR_WATERMARK_REACH 0x00000200 -#define DSI_FIFO_STATUS_CMD_DMA_FIFO_UNDERFLOW 0x00000400 -#define DSI_FIFO_STATUS_DLN0_LP_FIFO_EMPTY 0x00001000 -#define DSI_FIFO_STATUS_DLN0_LP_FIFO_FULL 0x00002000 -#define DSI_FIFO_STATUS_DLN0_LP_FIFO_OVERFLOW 0x00004000 -#define DSI_FIFO_STATUS_DLN0_HS_FIFO_EMPTY 0x00010000 -#define DSI_FIFO_STATUS_DLN0_HS_FIFO_FULL 0x00020000 -#define DSI_FIFO_STATUS_DLN0_HS_FIFO_OVERFLOW 0x00040000 -#define DSI_FIFO_STATUS_DLN0_HS_FIFO_UNDERFLOW 0x00080000 -#define DSI_FIFO_STATUS_DLN1_HS_FIFO_EMPTY 0x00100000 -#define DSI_FIFO_STATUS_DLN1_HS_FIFO_FULL 0x00200000 -#define DSI_FIFO_STATUS_DLN1_HS_FIFO_OVERFLOW 0x00400000 -#define DSI_FIFO_STATUS_DLN1_HS_FIFO_UNDERFLOW 0x00800000 -#define DSI_FIFO_STATUS_DLN2_HS_FIFO_EMPTY 0x01000000 -#define DSI_FIFO_STATUS_DLN2_HS_FIFO_FULL 0x02000000 -#define DSI_FIFO_STATUS_DLN2_HS_FIFO_OVERFLOW 0x04000000 -#define DSI_FIFO_STATUS_DLN2_HS_FIFO_UNDERFLOW 0x08000000 -#define DSI_FIFO_STATUS_DLN3_HS_FIFO_EMPTY 0x10000000 -#define DSI_FIFO_STATUS_DLN3_HS_FIFO_FULL 0x20000000 -#define DSI_FIFO_STATUS_DLN3_HS_FIFO_OVERFLOW 0x40000000 -#define DSI_FIFO_STATUS_DLN3_HS_FIFO_UNDERFLOW 0x80000000 - -#define REG_DSI_VID_CFG0 0x0000000c -#define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003 -#define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT 0 -static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) -{ - return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK; -} -#define DSI_VID_CFG0_DST_FORMAT__MASK 0x00000030 -#define DSI_VID_CFG0_DST_FORMAT__SHIFT 4 -static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) -{ - return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK; -} -#define DSI_VID_CFG0_TRAFFIC_MODE__MASK 0x00000300 -#define DSI_VID_CFG0_TRAFFIC_MODE__SHIFT 8 -static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val) -{ - return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK; -} -#define DSI_VID_CFG0_BLLP_POWER_STOP 0x00001000 -#define DSI_VID_CFG0_EOF_BLLP_POWER_STOP 0x00008000 -#define DSI_VID_CFG0_HSA_POWER_STOP 0x00010000 -#define DSI_VID_CFG0_HBP_POWER_STOP 0x00100000 -#define DSI_VID_CFG0_HFP_POWER_STOP 0x01000000 -#define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000 - -#define REG_DSI_VID_CFG1 0x0000001c -#define DSI_VID_CFG1_R_SEL 0x00000001 -#define DSI_VID_CFG1_G_SEL 0x00000010 -#define DSI_VID_CFG1_B_SEL 0x00000100 -#define DSI_VID_CFG1_RGB_SWAP__MASK 0x00007000 -#define DSI_VID_CFG1_RGB_SWAP__SHIFT 12 -static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val) -{ - return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK; -} - -#define REG_DSI_ACTIVE_H 0x00000020 -#define DSI_ACTIVE_H_START__MASK 0x00000fff -#define DSI_ACTIVE_H_START__SHIFT 0 -static inline uint32_t DSI_ACTIVE_H_START(uint32_t val) -{ - return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK; -} -#define DSI_ACTIVE_H_END__MASK 0x0fff0000 -#define DSI_ACTIVE_H_END__SHIFT 16 -static inline uint32_t DSI_ACTIVE_H_END(uint32_t val) -{ - return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK; -} - -#define REG_DSI_ACTIVE_V 0x00000024 -#define DSI_ACTIVE_V_START__MASK 0x00000fff -#define DSI_ACTIVE_V_START__SHIFT 0 -static inline uint32_t DSI_ACTIVE_V_START(uint32_t val) -{ - return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK; -} -#define DSI_ACTIVE_V_END__MASK 0x0fff0000 -#define DSI_ACTIVE_V_END__SHIFT 16 -static inline uint32_t DSI_ACTIVE_V_END(uint32_t val) -{ - return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK; -} - -#define REG_DSI_TOTAL 0x00000028 -#define DSI_TOTAL_H_TOTAL__MASK 0x00000fff -#define DSI_TOTAL_H_TOTAL__SHIFT 0 -static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val) -{ - return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK; -} -#define DSI_TOTAL_V_TOTAL__MASK 0x0fff0000 -#define DSI_TOTAL_V_TOTAL__SHIFT 16 -static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val) -{ - return ((val) << DSI_TOTAL_V_TOTAL__SHIFT) & DSI_TOTAL_V_TOTAL__MASK; -} - -#define REG_DSI_ACTIVE_HSYNC 0x0000002c -#define DSI_ACTIVE_HSYNC_START__MASK 0x00000fff -#define DSI_ACTIVE_HSYNC_START__SHIFT 0 -static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val) -{ - return ((val) << DSI_ACTIVE_HSYNC_START__SHIFT) & DSI_ACTIVE_HSYNC_START__MASK; -} -#define DSI_ACTIVE_HSYNC_END__MASK 0x0fff0000 -#define DSI_ACTIVE_HSYNC_END__SHIFT 16 -static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val) -{ - return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK; -} - -#define REG_DSI_ACTIVE_VSYNC_HPOS 0x00000030 -#define DSI_ACTIVE_VSYNC_HPOS_START__MASK 0x00000fff -#define DSI_ACTIVE_VSYNC_HPOS_START__SHIFT 0 -static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val) -{ - return ((val) << DSI_ACTIVE_VSYNC_HPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_START__MASK; -} -#define DSI_ACTIVE_VSYNC_HPOS_END__MASK 0x0fff0000 -#define DSI_ACTIVE_VSYNC_HPOS_END__SHIFT 16 -static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val) -{ - return ((val) << DSI_ACTIVE_VSYNC_HPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_END__MASK; -} - -#define REG_DSI_ACTIVE_VSYNC_VPOS 0x00000034 -#define DSI_ACTIVE_VSYNC_VPOS_START__MASK 0x00000fff -#define DSI_ACTIVE_VSYNC_VPOS_START__SHIFT 0 -static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val) -{ - return ((val) << DSI_ACTIVE_VSYNC_VPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_START__MASK; -} -#define DSI_ACTIVE_VSYNC_VPOS_END__MASK 0x0fff0000 -#define DSI_ACTIVE_VSYNC_VPOS_END__SHIFT 16 -static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val) -{ - return ((val) << DSI_ACTIVE_VSYNC_VPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_END__MASK; -} - -#define REG_DSI_CMD_DMA_CTRL 0x00000038 -#define DSI_CMD_DMA_CTRL_BROADCAST_EN 0x80000000 -#define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER 0x10000000 -#define DSI_CMD_DMA_CTRL_LOW_POWER 0x04000000 - -#define REG_DSI_CMD_CFG0 0x0000003c -#define DSI_CMD_CFG0_DST_FORMAT__MASK 0x0000000f -#define DSI_CMD_CFG0_DST_FORMAT__SHIFT 0 -static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val) -{ - return ((val) << DSI_CMD_CFG0_DST_FORMAT__SHIFT) & DSI_CMD_CFG0_DST_FORMAT__MASK; -} -#define DSI_CMD_CFG0_R_SEL 0x00000010 -#define DSI_CMD_CFG0_G_SEL 0x00000100 -#define DSI_CMD_CFG0_B_SEL 0x00001000 -#define DSI_CMD_CFG0_INTERLEAVE_MAX__MASK 0x00f00000 -#define DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT 20 -static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val) -{ - return ((val) << DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT) & DSI_CMD_CFG0_INTERLEAVE_MAX__MASK; -} -#define DSI_CMD_CFG0_RGB_SWAP__MASK 0x00070000 -#define DSI_CMD_CFG0_RGB_SWAP__SHIFT 16 -static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val) -{ - return ((val) << DSI_CMD_CFG0_RGB_SWAP__SHIFT) & DSI_CMD_CFG0_RGB_SWAP__MASK; -} - -#define REG_DSI_CMD_CFG1 0x00000040 -#define DSI_CMD_CFG1_WR_MEM_START__MASK 0x000000ff -#define DSI_CMD_CFG1_WR_MEM_START__SHIFT 0 -static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val) -{ - return ((val) << DSI_CMD_CFG1_WR_MEM_START__SHIFT) & DSI_CMD_CFG1_WR_MEM_START__MASK; -} -#define DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK 0x0000ff00 -#define DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT 8 -static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val) -{ - return ((val) << DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT) & DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK; -} -#define DSI_CMD_CFG1_INSERT_DCS_COMMAND 0x00010000 - -#define REG_DSI_DMA_BASE 0x00000044 - -#define REG_DSI_DMA_LEN 0x00000048 - -#define REG_DSI_CMD_MDP_STREAM0_CTRL 0x00000054 -#define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK 0x0000003f -#define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT 0 -static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(uint32_t val) -{ - return ((val) << DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK; -} -#define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300 -#define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT 8 -static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(uint32_t val) -{ - return ((val) << DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK; -} -#define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK 0xffff0000 -#define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT 16 -static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(uint32_t val) -{ - return ((val) << DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK; -} - -#define REG_DSI_CMD_MDP_STREAM0_TOTAL 0x00000058 -#define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK 0x00000fff -#define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT 0 -static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(uint32_t val) -{ - return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK; -} -#define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK 0x0fff0000 -#define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT 16 -static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(uint32_t val) -{ - return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK; -} - -#define REG_DSI_CMD_MDP_STREAM1_CTRL 0x0000005c -#define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK 0x0000003f -#define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT 0 -static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE(uint32_t val) -{ - return ((val) << DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK; -} -#define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300 -#define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT 8 -static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL(uint32_t val) -{ - return ((val) << DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK; -} -#define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK 0xffff0000 -#define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT 16 -static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT(uint32_t val) -{ - return ((val) << DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK; -} - -#define REG_DSI_CMD_MDP_STREAM1_TOTAL 0x00000060 -#define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK 0x0000ffff -#define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT 0 -static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL(uint32_t val) -{ - return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK; -} -#define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK 0xffff0000 -#define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT 16 -static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL(uint32_t val) -{ - return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK; -} - -#define REG_DSI_ACK_ERR_STATUS 0x00000064 - -static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; } - -static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; } - -#define REG_DSI_TRIG_CTRL 0x00000080 -#define DSI_TRIG_CTRL_DMA_TRIGGER__MASK 0x00000007 -#define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT 0 -static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val) -{ - return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK; -} -#define DSI_TRIG_CTRL_MDP_TRIGGER__MASK 0x00000070 -#define DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT 4 -static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val) -{ - return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK; -} -#define DSI_TRIG_CTRL_STREAM__MASK 0x00000300 -#define DSI_TRIG_CTRL_STREAM__SHIFT 8 -static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val) -{ - return ((val) << DSI_TRIG_CTRL_STREAM__SHIFT) & DSI_TRIG_CTRL_STREAM__MASK; -} -#define DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME 0x00001000 -#define DSI_TRIG_CTRL_TE 0x80000000 - -#define REG_DSI_TRIG_DMA 0x0000008c - -#define REG_DSI_DLN0_PHY_ERR 0x000000b0 -#define DSI_DLN0_PHY_ERR_DLN0_ERR_ESC 0x00000001 -#define DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC 0x00000010 -#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL 0x00000100 -#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 0x00001000 -#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1 0x00010000 - -#define REG_DSI_LP_TIMER_CTRL 0x000000b4 -#define DSI_LP_TIMER_CTRL_LP_RX_TO__MASK 0x0000ffff -#define DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT 0 -static inline uint32_t DSI_LP_TIMER_CTRL_LP_RX_TO(uint32_t val) -{ - return ((val) << DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT) & DSI_LP_TIMER_CTRL_LP_RX_TO__MASK; -} -#define DSI_LP_TIMER_CTRL_BTA_TO__MASK 0xffff0000 -#define DSI_LP_TIMER_CTRL_BTA_TO__SHIFT 16 -static inline uint32_t DSI_LP_TIMER_CTRL_BTA_TO(uint32_t val) -{ - return ((val) << DSI_LP_TIMER_CTRL_BTA_TO__SHIFT) & DSI_LP_TIMER_CTRL_BTA_TO__MASK; -} - -#define REG_DSI_HS_TIMER_CTRL 0x000000b8 -#define DSI_HS_TIMER_CTRL_HS_TX_TO__MASK 0x0000ffff -#define DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT 0 -static inline uint32_t DSI_HS_TIMER_CTRL_HS_TX_TO(uint32_t val) -{ - return ((val) << DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT) & DSI_HS_TIMER_CTRL_HS_TX_TO__MASK; -} -#define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK 0x000f0000 -#define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT 16 -static inline uint32_t DSI_HS_TIMER_CTRL_TIMER_RESOLUTION(uint32_t val) -{ - return ((val) << DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT) & DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK; -} -#define DSI_HS_TIMER_CTRL_HS_TX_TO_STOP_EN 0x10000000 - -#define REG_DSI_TIMEOUT_STATUS 0x000000bc - -#define REG_DSI_CLKOUT_TIMING_CTRL 0x000000c0 -#define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK 0x0000003f -#define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT 0 -static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val) -{ - return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK; -} -#define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK 0x00003f00 -#define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT 8 -static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val) -{ - return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK; -} - -#define REG_DSI_EOT_PACKET_CTRL 0x000000c8 -#define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001 -#define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010 - -#define REG_DSI_LANE_STATUS 0x000000a4 -#define DSI_LANE_STATUS_DLN0_STOPSTATE 0x00000001 -#define DSI_LANE_STATUS_DLN1_STOPSTATE 0x00000002 -#define DSI_LANE_STATUS_DLN2_STOPSTATE 0x00000004 -#define DSI_LANE_STATUS_DLN3_STOPSTATE 0x00000008 -#define DSI_LANE_STATUS_CLKLN_STOPSTATE 0x00000010 -#define DSI_LANE_STATUS_DLN0_ULPS_ACTIVE_NOT 0x00000100 -#define DSI_LANE_STATUS_DLN1_ULPS_ACTIVE_NOT 0x00000200 -#define DSI_LANE_STATUS_DLN2_ULPS_ACTIVE_NOT 0x00000400 -#define DSI_LANE_STATUS_DLN3_ULPS_ACTIVE_NOT 0x00000800 -#define DSI_LANE_STATUS_CLKLN_ULPS_ACTIVE_NOT 0x00001000 -#define DSI_LANE_STATUS_DLN0_DIRECTION 0x00010000 - -#define REG_DSI_LANE_CTRL 0x000000a8 -#define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000 - -#define REG_DSI_LANE_SWAP_CTRL 0x000000ac -#define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK 0x00000007 -#define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT 0 -static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val) -{ - return ((val) << DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT) & DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK; -} - -#define REG_DSI_ERR_INT_MASK0 0x00000108 - -#define REG_DSI_INTR_CTRL 0x0000010c - -#define REG_DSI_RESET 0x00000114 - -#define REG_DSI_CLK_CTRL 0x00000118 -#define DSI_CLK_CTRL_AHBS_HCLK_ON 0x00000001 -#define DSI_CLK_CTRL_AHBM_SCLK_ON 0x00000002 -#define DSI_CLK_CTRL_PCLK_ON 0x00000004 -#define DSI_CLK_CTRL_DSICLK_ON 0x00000008 -#define DSI_CLK_CTRL_BYTECLK_ON 0x00000010 -#define DSI_CLK_CTRL_ESCCLK_ON 0x00000020 -#define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK 0x00000200 - -#define REG_DSI_CLK_STATUS 0x0000011c -#define DSI_CLK_STATUS_DSI_AON_AHBM_HCLK_ACTIVE 0x00000001 -#define DSI_CLK_STATUS_DSI_DYN_AHBM_HCLK_ACTIVE 0x00000002 -#define DSI_CLK_STATUS_DSI_AON_AHBS_HCLK_ACTIVE 0x00000004 -#define DSI_CLK_STATUS_DSI_DYN_AHBS_HCLK_ACTIVE 0x00000008 -#define DSI_CLK_STATUS_DSI_AON_DSICLK_ACTIVE 0x00000010 -#define DSI_CLK_STATUS_DSI_DYN_DSICLK_ACTIVE 0x00000020 -#define DSI_CLK_STATUS_DSI_AON_BYTECLK_ACTIVE 0x00000040 -#define DSI_CLK_STATUS_DSI_DYN_BYTECLK_ACTIVE 0x00000080 -#define DSI_CLK_STATUS_DSI_AON_ESCCLK_ACTIVE 0x00000100 -#define DSI_CLK_STATUS_DSI_AON_PCLK_ACTIVE 0x00000200 -#define DSI_CLK_STATUS_DSI_DYN_PCLK_ACTIVE 0x00000400 -#define DSI_CLK_STATUS_DSI_DYN_CMD_PCLK_ACTIVE 0x00001000 -#define DSI_CLK_STATUS_DSI_CMD_PCLK_ACTIVE 0x00002000 -#define DSI_CLK_STATUS_DSI_VID_PCLK_ACTIVE 0x00004000 -#define DSI_CLK_STATUS_DSI_CAM_BIST_PCLK_ACT 0x00008000 -#define DSI_CLK_STATUS_PLL_UNLOCKED 0x00010000 - -#define REG_DSI_PHY_RESET 0x00000128 -#define DSI_PHY_RESET_RESET 0x00000001 - -#define REG_DSI_T_CLK_PRE_EXTEND 0x0000017c -#define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK 0x00000001 - -#define REG_DSI_CMD_MODE_MDP_CTRL2 0x000001b4 -#define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK 0x0000000f -#define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT 0 -static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2(enum dsi_cmd_dst_format val) -{ - return ((val) << DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK; -} -#define DSI_CMD_MODE_MDP_CTRL2_R_SEL 0x00000010 -#define DSI_CMD_MODE_MDP_CTRL2_G_SEL 0x00000020 -#define DSI_CMD_MODE_MDP_CTRL2_B_SEL 0x00000040 -#define DSI_CMD_MODE_MDP_CTRL2_BYTE_MSB_LSB_FLIP 0x00000080 -#define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK 0x00000700 -#define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT 8 -static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP(enum dsi_rgb_swap val) -{ - return ((val) << DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK; -} -#define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK 0x00007000 -#define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT 12 -static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP(enum dsi_rgb_swap val) -{ - return ((val) << DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK; -} -#define DSI_CMD_MODE_MDP_CTRL2_BURST_MODE 0x00010000 - -#define REG_DSI_CMD_MODE_MDP_STREAM2_CTRL 0x000001b8 -#define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK 0x0000003f -#define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT 0 -static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE(uint32_t val) -{ - return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK; -} -#define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300 -#define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT 8 -static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL(uint32_t val) -{ - return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK; -} -#define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK 0xffff0000 -#define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT 16 -static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT(uint32_t val) -{ - return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK; -} - -#define REG_DSI_RDBK_DATA_CTRL 0x000001d0 -#define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff0000 -#define DSI_RDBK_DATA_CTRL_COUNT__SHIFT 16 -static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val) -{ - return ((val) << DSI_RDBK_DATA_CTRL_COUNT__SHIFT) & DSI_RDBK_DATA_CTRL_COUNT__MASK; -} -#define DSI_RDBK_DATA_CTRL_CLR 0x00000001 - -#define REG_DSI_VERSION 0x000001f0 -#define DSI_VERSION_MAJOR__MASK 0xff000000 -#define DSI_VERSION_MAJOR__SHIFT 24 -static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) -{ - return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK; -} - -#define REG_DSI_CPHY_MODE_CTRL 0x000002d4 - - -#endif /* DSI_XML */ diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c index f3f1c03c7db9..fed8e9b67011 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -9,195 +9,232 @@ static const char * const dsi_v2_bus_clk_names[] = { "core_mmss", "iface", "bus", }; +static const struct regulator_bulk_data apq8064_dsi_regulators[] = { + { .supply = "vdda", .init_load_uA = 100000 }, /* 1.2 V */ + { .supply = "avdd", .init_load_uA = 10000 }, /* 3.0 V */ + { .supply = "vddio", .init_load_uA = 100000 }, /* 1.8 V */ +}; + static const struct msm_dsi_config apq8064_dsi_cfg = { .io_offset = 0, - .reg_cfg = { - .num = 3, - .regs = { - {"vdda", 100000, 100}, /* 1.2 V */ - {"avdd", 10000, 100}, /* 3.0 V */ - {"vddio", 100000, 100}, /* 1.8 V */ - }, - }, + .regulator_data = apq8064_dsi_regulators, + .num_regulators = ARRAY_SIZE(apq8064_dsi_regulators), .bus_clk_names = dsi_v2_bus_clk_names, .num_bus_clks = ARRAY_SIZE(dsi_v2_bus_clk_names), - .io_start = { 0x4700000, 0x5800000 }, - .num_dsi = 2, + .io_start = { + { 0x4700000, 0x5800000 }, + }, }; static const char * const dsi_6g_bus_clk_names[] = { "mdp_core", "iface", "bus", "core_mmss", }; +static const struct regulator_bulk_data msm8974_apq8084_regulators[] = { + { .supply = "vdd", .init_load_uA = 150000 }, /* 3.0 V */ + { .supply = "vdda", .init_load_uA = 100000 }, /* 1.2 V */ + { .supply = "vddio", .init_load_uA = 100000 }, /* 1.8 V */ +}; + static const struct msm_dsi_config msm8974_apq8084_dsi_cfg = { .io_offset = DSI_6G_REG_SHIFT, - .reg_cfg = { - .num = 4, - .regs = { - {"gdsc", -1, -1}, - {"vdd", 150000, 100}, /* 3.0 V */ - {"vdda", 100000, 100}, /* 1.2 V */ - {"vddio", 100000, 100}, /* 1.8 V */ - }, - }, + .regulator_data = msm8974_apq8084_regulators, + .num_regulators = ARRAY_SIZE(msm8974_apq8084_regulators), .bus_clk_names = dsi_6g_bus_clk_names, .num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names), - .io_start = { 0xfd922800, 0xfd922b00 }, - .num_dsi = 2, + .io_start = { + { 0xfd922800, 0xfd922b00 }, + }, }; -static const char * const dsi_8916_bus_clk_names[] = { +static const char * const dsi_v1_3_1_clk_names[] = { "mdp_core", "iface", "bus", }; +static const struct regulator_bulk_data dsi_v1_3_1_regulators[] = { + { .supply = "vdda", .init_load_uA = 100000 }, /* 1.2 V */ + { .supply = "vddio", .init_load_uA = 100000 }, /* 1.8 V */ +}; + static const struct msm_dsi_config msm8916_dsi_cfg = { .io_offset = DSI_6G_REG_SHIFT, - .reg_cfg = { - .num = 3, - .regs = { - {"gdsc", -1, -1}, - {"vdda", 100000, 100}, /* 1.2 V */ - {"vddio", 100000, 100}, /* 1.8 V */ - }, + .regulator_data = dsi_v1_3_1_regulators, + .num_regulators = ARRAY_SIZE(dsi_v1_3_1_regulators), + .bus_clk_names = dsi_v1_3_1_clk_names, + .num_bus_clks = ARRAY_SIZE(dsi_v1_3_1_clk_names), + .io_start = { + { 0x1a98000 }, }, - .bus_clk_names = dsi_8916_bus_clk_names, - .num_bus_clks = ARRAY_SIZE(dsi_8916_bus_clk_names), - .io_start = { 0x1a98000 }, - .num_dsi = 1, -}; - -static const char * const dsi_8976_bus_clk_names[] = { - "mdp_core", "iface", "bus", }; static const struct msm_dsi_config msm8976_dsi_cfg = { .io_offset = DSI_6G_REG_SHIFT, - .reg_cfg = { - .num = 3, - .regs = { - {"gdsc", -1, -1}, - {"vdda", 100000, 100}, /* 1.2 V */ - {"vddio", 100000, 100}, /* 1.8 V */ - }, + .regulator_data = dsi_v1_3_1_regulators, + .num_regulators = ARRAY_SIZE(dsi_v1_3_1_regulators), + .bus_clk_names = dsi_v1_3_1_clk_names, + .num_bus_clks = ARRAY_SIZE(dsi_v1_3_1_clk_names), + .io_start = { + { 0x1a94000, 0x1a96000 }, }, - .bus_clk_names = dsi_8976_bus_clk_names, - .num_bus_clks = ARRAY_SIZE(dsi_8976_bus_clk_names), - .io_start = { 0x1a94000, 0x1a96000 }, - .num_dsi = 2, +}; + +static const struct regulator_bulk_data msm8994_dsi_regulators[] = { + { .supply = "vdda", .init_load_uA = 100000 }, /* 1.25 V */ + { .supply = "vddio", .init_load_uA = 100000 }, /* 1.8 V */ + { .supply = "vcca", .init_load_uA = 10000 }, /* 1.0 V */ + { .supply = "vdd", .init_load_uA = 100000 }, /* 1.8 V */ + { .supply = "lab_reg", .init_load_uA = -1 }, + { .supply = "ibb_reg", .init_load_uA = -1 }, }; static const struct msm_dsi_config msm8994_dsi_cfg = { .io_offset = DSI_6G_REG_SHIFT, - .reg_cfg = { - .num = 7, - .regs = { - {"gdsc", -1, -1}, - {"vdda", 100000, 100}, /* 1.25 V */ - {"vddio", 100000, 100}, /* 1.8 V */ - {"vcca", 10000, 100}, /* 1.0 V */ - {"vdd", 100000, 100}, /* 1.8 V */ - {"lab_reg", -1, -1}, - {"ibb_reg", -1, -1}, - }, - }, + .regulator_data = msm8994_dsi_regulators, + .num_regulators = ARRAY_SIZE(msm8994_dsi_regulators), .bus_clk_names = dsi_6g_bus_clk_names, .num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names), - .io_start = { 0xfd998000, 0xfd9a0000 }, - .num_dsi = 2, + .io_start = { + { 0xfd998000, 0xfd9a0000 }, + }, }; -static const char * const dsi_8996_bus_clk_names[] = { - "mdp_core", "iface", "bus", "core_mmss", +static const struct regulator_bulk_data msm8996_dsi_regulators[] = { + { .supply = "vdda", .init_load_uA = 18160 }, /* 1.25 V */ + { .supply = "vcca", .init_load_uA = 17000 }, /* 0.925 V */ + { .supply = "vddio", .init_load_uA = 100000 }, /* 1.8 V */ }; static const struct msm_dsi_config msm8996_dsi_cfg = { .io_offset = DSI_6G_REG_SHIFT, - .reg_cfg = { - .num = 2, - .regs = { - {"vdda", 18160, 1 }, /* 1.25 V */ - {"vcca", 17000, 32 }, /* 0.925 V */ - {"vddio", 100000, 100 },/* 1.8 V */ - }, + .regulator_data = msm8996_dsi_regulators, + .num_regulators = ARRAY_SIZE(msm8996_dsi_regulators), + .bus_clk_names = dsi_6g_bus_clk_names, + .num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names), + .io_start = { + { 0x994000, 0x996000 }, }, - .bus_clk_names = dsi_8996_bus_clk_names, - .num_bus_clks = ARRAY_SIZE(dsi_8996_bus_clk_names), - .io_start = { 0x994000, 0x996000 }, - .num_dsi = 2, }; static const char * const dsi_msm8998_bus_clk_names[] = { "iface", "bus", "core", }; +static const struct regulator_bulk_data msm8998_dsi_regulators[] = { + { .supply = "vdd", .init_load_uA = 367000 }, /* 0.9 V */ + { .supply = "vdda", .init_load_uA = 62800 }, /* 1.2 V */ +}; + static const struct msm_dsi_config msm8998_dsi_cfg = { .io_offset = DSI_6G_REG_SHIFT, - .reg_cfg = { - .num = 2, - .regs = { - {"vdd", 367000, 16 }, /* 0.9 V */ - {"vdda", 62800, 2 }, /* 1.2 V */ - }, - }, + .regulator_data = msm8998_dsi_regulators, + .num_regulators = ARRAY_SIZE(msm8998_dsi_regulators), .bus_clk_names = dsi_msm8998_bus_clk_names, .num_bus_clks = ARRAY_SIZE(dsi_msm8998_bus_clk_names), - .io_start = { 0xc994000, 0xc996000 }, - .num_dsi = 2, + .io_start = { + { 0xc994000, 0xc996000 }, + }, }; static const char * const dsi_sdm660_bus_clk_names[] = { "iface", "bus", "core", "core_mmss", }; +static const struct regulator_bulk_data sdm660_dsi_regulators[] = { + { .supply = "vdda", .init_load_uA = 12560 }, /* 1.2 V */ +}; + static const struct msm_dsi_config sdm660_dsi_cfg = { .io_offset = DSI_6G_REG_SHIFT, - .reg_cfg = { - .num = 2, - .regs = { - {"vdd", 73400, 32 }, /* 0.9 V */ - {"vdda", 12560, 4 }, /* 1.2 V */ - }, - }, + .regulator_data = sdm660_dsi_regulators, + .num_regulators = ARRAY_SIZE(sdm660_dsi_regulators), .bus_clk_names = dsi_sdm660_bus_clk_names, .num_bus_clks = ARRAY_SIZE(dsi_sdm660_bus_clk_names), - .io_start = { 0xc994000, 0xc996000 }, - .num_dsi = 2, + .io_start = { + { 0xc994000, 0xc996000 }, + }, }; -static const char * const dsi_sdm845_bus_clk_names[] = { +static const char * const dsi_v2_4_clk_names[] = { "iface", "bus", }; -static const char * const dsi_sc7180_bus_clk_names[] = { - "iface", "bus", +static const struct regulator_bulk_data dsi_v2_4_regulators[] = { + { .supply = "vdda", .init_load_uA = 21800 }, /* 1.2 V */ + { .supply = "refgen" }, }; static const struct msm_dsi_config sdm845_dsi_cfg = { .io_offset = DSI_6G_REG_SHIFT, - .reg_cfg = { - .num = 1, - .regs = { - {"vdda", 21800, 4 }, /* 1.2 V */ - }, + .regulator_data = dsi_v2_4_regulators, + .num_regulators = ARRAY_SIZE(dsi_v2_4_regulators), + .bus_clk_names = dsi_v2_4_clk_names, + .num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names), + .io_start = { + { 0xae94000, 0xae96000 }, /* SDM845 / SDM670 */ + { 0x5e94000 }, /* QCM2290 / SM6115 / SM6125 / SM6375 */ }, - .bus_clk_names = dsi_sdm845_bus_clk_names, - .num_bus_clks = ARRAY_SIZE(dsi_sdm845_bus_clk_names), - .io_start = { 0xae94000, 0xae96000 }, - .num_dsi = 2, }; -static const struct msm_dsi_config sc7180_dsi_cfg = { +static const struct regulator_bulk_data sm8550_dsi_regulators[] = { + { .supply = "vdda", .init_load_uA = 16800 }, /* 1.2 V */ +}; + +static const struct msm_dsi_config sm8550_dsi_cfg = { .io_offset = DSI_6G_REG_SHIFT, - .reg_cfg = { - .num = 1, - .regs = { - {"vdda", 21800, 4 }, /* 1.2 V */ - }, + .regulator_data = sm8550_dsi_regulators, + .num_regulators = ARRAY_SIZE(sm8550_dsi_regulators), + .bus_clk_names = dsi_v2_4_clk_names, + .num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names), + .io_start = { + { 0xae94000, 0xae96000 }, + }, +}; + +static const struct regulator_bulk_data sm8650_dsi_regulators[] = { + { .supply = "vdda", .init_load_uA = 16600 }, /* 1.2 V */ +}; + +static const struct msm_dsi_config sm8650_dsi_cfg = { + .io_offset = DSI_6G_REG_SHIFT, + .regulator_data = sm8650_dsi_regulators, + .num_regulators = ARRAY_SIZE(sm8650_dsi_regulators), + .bus_clk_names = dsi_v2_4_clk_names, + .num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names), + .io_start = { + { 0xae94000, 0xae96000 }, + }, +}; + +static const struct regulator_bulk_data sc7280_dsi_regulators[] = { + { .supply = "vdda", .init_load_uA = 8350 }, /* 1.2 V */ + { .supply = "refgen" }, +}; + +static const struct msm_dsi_config sc7280_dsi_cfg = { + .io_offset = DSI_6G_REG_SHIFT, + .regulator_data = sc7280_dsi_regulators, + .num_regulators = ARRAY_SIZE(sc7280_dsi_regulators), + .bus_clk_names = dsi_v2_4_clk_names, + .num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names), + .io_start = { + { 0xae94000, 0xae96000 }, + }, +}; + +static const struct regulator_bulk_data sa8775p_dsi_regulators[] = { + { .supply = "vdda", .init_load_uA = 8300 }, /* 1.2 V */ + { .supply = "refgen" }, +}; + +static const struct msm_dsi_config sa8775p_dsi_cfg = { + .io_offset = DSI_6G_REG_SHIFT, + .regulator_data = sa8775p_dsi_regulators, + .num_regulators = ARRAY_SIZE(sa8775p_dsi_regulators), + .bus_clk_names = dsi_v2_4_clk_names, + .num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names), + .io_start = { + { 0xae94000, 0xae96000 }, }, - .bus_clk_names = dsi_sc7180_bus_clk_names, - .num_bus_clks = ARRAY_SIZE(dsi_sc7180_bus_clk_names), - .io_start = { 0xae94000 }, - .num_dsi = 1, }; static const struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = { @@ -236,11 +273,25 @@ static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_host_ops = { .calc_clk_rate = dsi_calc_clk_rate_6g, }; +static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_9_host_ops = { + .link_clk_set_rate = dsi_link_clk_set_rate_6g_v2_9, + .link_clk_enable = dsi_link_clk_enable_6g, + .link_clk_disable = dsi_link_clk_disable_6g, + .clk_init_ver = dsi_clk_init_6g_v2_9, + .tx_buf_alloc = dsi_tx_buf_alloc_6g, + .tx_buf_get = dsi_tx_buf_get_6g, + .tx_buf_put = dsi_tx_buf_put_6g, + .dma_base_get = dsi_dma_base_get_6g, + .calc_clk_rate = dsi_calc_clk_rate_6g, +}; + static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = { {MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064, &apq8064_dsi_cfg, &msm_dsi_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0, &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0_2, + &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1, &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1_1, @@ -263,10 +314,24 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = { &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_0, &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_1, + &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_0, &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_1, - &sc7180_dsi_cfg, &msm_dsi_6g_v2_host_ops}, + &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_5_0, + &sc7280_dsi_cfg, &msm_dsi_6g_v2_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_5_1, + &sa8775p_dsi_cfg, &msm_dsi_6g_v2_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_6_0, + &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_7_0, + &sm8550_dsi_cfg, &msm_dsi_6g_v2_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_8_0, + &sm8650_dsi_cfg, &msm_dsi_6g_v2_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_9_0, + &sm8650_dsi_cfg, &msm_dsi_6g_v2_9_host_ops}, }; const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor) @@ -284,4 +349,3 @@ const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor) return cfg_hnd; } - diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h index ade9b609c7d9..38f303f2ed04 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h @@ -11,6 +11,7 @@ #define MSM_DSI_VER_MAJOR_V2 0x02 #define MSM_DSI_VER_MAJOR_6G 0x03 #define MSM_DSI_6G_VER_MINOR_V1_0 0x10000000 +#define MSM_DSI_6G_VER_MINOR_V1_0_2 0x10000002 #define MSM_DSI_6G_VER_MINOR_V1_1 0x10010000 #define MSM_DSI_6G_VER_MINOR_V1_1_1 0x10010001 #define MSM_DSI_6G_VER_MINOR_V1_2 0x10020000 @@ -22,20 +23,30 @@ #define MSM_DSI_6G_VER_MINOR_V2_2_0 0x20000000 #define MSM_DSI_6G_VER_MINOR_V2_2_1 0x20020001 #define MSM_DSI_6G_VER_MINOR_V2_3_0 0x20030000 +#define MSM_DSI_6G_VER_MINOR_V2_3_1 0x20030001 #define MSM_DSI_6G_VER_MINOR_V2_4_0 0x20040000 #define MSM_DSI_6G_VER_MINOR_V2_4_1 0x20040001 +#define MSM_DSI_6G_VER_MINOR_V2_5_0 0x20050000 +#define MSM_DSI_6G_VER_MINOR_V2_5_1 0x20050001 +#define MSM_DSI_6G_VER_MINOR_V2_6_0 0x20060000 +#define MSM_DSI_6G_VER_MINOR_V2_7_0 0x20070000 +#define MSM_DSI_6G_VER_MINOR_V2_8_0 0x20080000 +#define MSM_DSI_6G_VER_MINOR_V2_9_0 0x20090000 #define MSM_DSI_V2_VER_MINOR_8064 0x0 #define DSI_6G_REG_SHIFT 4 +/* Maximum number of configurations matched against the same hw revision */ +#define VARIANTS_MAX 2 + struct msm_dsi_config { u32 io_offset; - struct dsi_reg_config reg_cfg; + const struct regulator_bulk_data *regulator_data; + int num_regulators; const char * const *bus_clk_names; const int num_bus_clks; - const resource_size_t io_start[DSI_MAX]; - const int num_dsi; + const resource_size_t io_start[VARIANTS_MAX][DSI_MAX]; }; struct msm_dsi_host_cfg_ops { @@ -47,7 +58,7 @@ struct msm_dsi_host_cfg_ops { void* (*tx_buf_get)(struct msm_dsi_host *msm_host); void (*tx_buf_put)(struct msm_dsi_host *msm_host); int (*dma_base_get)(struct msm_dsi_host *msm_host, uint64_t *iova); - int (*calc_clk_rate)(struct msm_dsi_host *msm_host, bool is_dual_dsi); + int (*calc_clk_rate)(struct msm_dsi_host *msm_host, bool is_bonded_dsi); }; struct msm_dsi_cfg_handler { diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index ed504fe5074f..e0de545d4077 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -7,10 +7,9 @@ #include <linux/delay.h> #include <linux/dma-mapping.h> #include <linux/err.h> -#include <linux/gpio/consumer.h> #include <linux/interrupt.h> #include <linux/mfd/syscon.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/of_graph.h> #include <linux/of_irq.h> #include <linux/pinctrl/consumer.h> @@ -21,15 +20,22 @@ #include <video/mipi_display.h> +#include <drm/display/drm_dsc_helper.h> +#include <drm/drm_of.h> + #include "dsi.h" #include "dsi.xml.h" #include "sfpb.xml.h" #include "dsi_cfg.h" +#include "msm_dsc_helper.h" #include "msm_kms.h" #include "msm_gem.h" +#include "phy/dsi_phy.h" #define DSI_RESET_TOGGLE_DELAY_MS 20 +static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc); + static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) { u32 ver; @@ -48,7 +54,7 @@ static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) * scratch register which we never touch) */ - ver = msm_readl(base + REG_DSI_VERSION); + ver = readl(base + REG_DSI_VERSION); if (ver) { /* older dsi host, there is no register shift */ ver = FIELD(ver, DSI_VERSION_MAJOR); @@ -66,12 +72,12 @@ static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) * registers are shifted down, read DSI_VERSION again with * the shifted offset */ - ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); + ver = readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); ver = FIELD(ver, DSI_VERSION_MAJOR); if (ver == MSM_DSI_VER_MAJOR_6G) { /* 6G version */ *major = ver; - *minor = msm_readl(base + REG_DSI_6G_HW_VERSION); + *minor = readl(base + REG_DSI_6G_HW_VERSION); return 0; } else { return -EINVAL; @@ -103,30 +109,34 @@ struct msm_dsi_host { void __iomem *ctrl_base; phys_addr_t ctrl_size; - struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX]; + struct regulator_bulk_data *supplies; - struct clk *bus_clks[DSI_BUS_CLK_MAX]; + int num_bus_clks; + struct clk_bulk_data bus_clks[DSI_BUS_CLK_MAX]; struct clk *byte_clk; struct clk *esc_clk; struct clk *pixel_clk; - struct clk *byte_clk_src; - struct clk *pixel_clk_src; struct clk *byte_intf_clk; - u32 byte_clk_rate; - u32 pixel_clk_rate; - u32 esc_clk_rate; + /* + * Clocks which needs to be properly parented between DISPCC and DSI PHY + * PLL: + */ + struct clk *byte_src_clk; + struct clk *pixel_src_clk; + struct clk *dsi_pll_byte_clk; + struct clk *dsi_pll_pixel_clk; + + unsigned long byte_clk_rate; + unsigned long byte_intf_clk_rate; + unsigned long pixel_clk_rate; + unsigned long esc_clk_rate; /* DSI v2 specific clocks */ struct clk *src_clk; - struct clk *esc_clk_src; - struct clk *dsi_clk_src; - - u32 src_clk_rate; - struct gpio_desc *disp_en_gpio; - struct gpio_desc *te_gpio; + unsigned long src_clk_rate; const struct msm_dsi_cfg_handler *cfg_hnd; @@ -138,11 +148,11 @@ struct msm_dsi_host { u32 err_work_state; struct work_struct err_work; - struct work_struct hpd_work; struct workqueue_struct *workqueue; /* DSI 6G TX buffer*/ struct drm_gem_object *tx_gem_obj; + struct drm_gpuvm *vm; /* DSI v2 TX buffer */ void *tx_buf; @@ -155,9 +165,9 @@ struct msm_dsi_host { struct regmap *sfpb; struct drm_display_mode *mode; + struct drm_dsc_config *dsc; /* connected device info */ - struct device_node *device_node; unsigned int channel; unsigned int lanes; enum mipi_dsi_pixel_format format; @@ -167,6 +177,9 @@ struct msm_dsi_host { int dlane_swap; int num_data_lanes; + /* from phy DT */ + bool cphy_mode; + u32 dma_cmd_ctrl_restore; bool registered; @@ -175,68 +188,43 @@ struct msm_dsi_host { int irq; }; -static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt) -{ - switch (fmt) { - case MIPI_DSI_FMT_RGB565: return 16; - case MIPI_DSI_FMT_RGB666_PACKED: return 18; - case MIPI_DSI_FMT_RGB666: - case MIPI_DSI_FMT_RGB888: - default: return 24; - } -} - static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) { - return msm_readl(msm_host->ctrl_base + reg); + return readl(msm_host->ctrl_base + reg); } + static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) { - msm_writel(data, msm_host->ctrl_base + reg); + writel(data, msm_host->ctrl_base + reg); } -static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host); -static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host); - -static const struct msm_dsi_cfg_handler *dsi_get_config( - struct msm_dsi_host *msm_host) +static const struct msm_dsi_cfg_handler * +dsi_get_config(struct msm_dsi_host *msm_host) { const struct msm_dsi_cfg_handler *cfg_hnd = NULL; struct device *dev = &msm_host->pdev->dev; - struct regulator *gdsc_reg; struct clk *ahb_clk; int ret; u32 major = 0, minor = 0; - gdsc_reg = regulator_get(dev, "gdsc"); - if (IS_ERR(gdsc_reg)) { - pr_err("%s: cannot get gdsc\n", __func__); - goto exit; - } - ahb_clk = msm_clk_get(msm_host->pdev, "iface"); if (IS_ERR(ahb_clk)) { - pr_err("%s: cannot get interface clock\n", __func__); - goto put_gdsc; + dev_err_probe(dev, PTR_ERR(ahb_clk), "%s: cannot get interface clock\n", + __func__); + goto exit; } pm_runtime_get_sync(dev); - ret = regulator_enable(gdsc_reg); - if (ret) { - pr_err("%s: unable to enable gdsc\n", __func__); - goto put_gdsc; - } - ret = clk_prepare_enable(ahb_clk); if (ret) { - pr_err("%s: unable to enable ahb_clk\n", __func__); - goto disable_gdsc; + dev_err_probe(dev, ret, "%s: unable to enable ahb_clk\n", __func__); + goto runtime_put; } ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); if (ret) { - pr_err("%s: Invalid version\n", __func__); + dev_err_probe(dev, ret, "%s: Invalid version\n", __func__); goto disable_clks; } @@ -246,11 +234,8 @@ static const struct msm_dsi_cfg_handler *dsi_get_config( disable_clks: clk_disable_unprepare(ahb_clk); -disable_gdsc: - regulator_disable(gdsc_reg); +runtime_put: pm_runtime_put_sync(dev); -put_gdsc: - regulator_put(gdsc_reg); exit: return cfg_hnd; } @@ -260,76 +245,6 @@ static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host) return container_of(host, struct msm_dsi_host, base); } -static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host) -{ - struct regulator_bulk_data *s = msm_host->supplies; - const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; - int num = msm_host->cfg_hnd->cfg->reg_cfg.num; - int i; - - DBG(""); - for (i = num - 1; i >= 0; i--) - if (regs[i].disable_load >= 0) - regulator_set_load(s[i].consumer, - regs[i].disable_load); - - regulator_bulk_disable(num, s); -} - -static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host) -{ - struct regulator_bulk_data *s = msm_host->supplies; - const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; - int num = msm_host->cfg_hnd->cfg->reg_cfg.num; - int ret, i; - - DBG(""); - for (i = 0; i < num; i++) { - if (regs[i].enable_load >= 0) { - ret = regulator_set_load(s[i].consumer, - regs[i].enable_load); - if (ret < 0) { - pr_err("regulator %d set op mode failed, %d\n", - i, ret); - goto fail; - } - } - } - - ret = regulator_bulk_enable(num, s); - if (ret < 0) { - pr_err("regulator enable failed, %d\n", ret); - goto fail; - } - - return 0; - -fail: - for (i--; i >= 0; i--) - regulator_set_load(s[i].consumer, regs[i].disable_load); - return ret; -} - -static int dsi_regulator_init(struct msm_dsi_host *msm_host) -{ - struct regulator_bulk_data *s = msm_host->supplies; - const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; - int num = msm_host->cfg_hnd->cfg->reg_cfg.num; - int i, ret; - - for (i = 0; i < num; i++) - s[i].supply = regs[i].name; - - ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s); - if (ret < 0) { - pr_err("%s: failed to init regulator, ret=%d\n", - __func__, ret); - return ret; - } - - return 0; -} - int dsi_clk_init_v2(struct msm_dsi_host *msm_host) { struct platform_device *pdev = msm_host->pdev; @@ -345,21 +260,6 @@ int dsi_clk_init_v2(struct msm_dsi_host *msm_host) return ret; } - msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk); - if (!msm_host->esc_clk_src) { - ret = -ENODEV; - pr_err("%s: can't get esc clock parent. ret=%d\n", - __func__, ret); - return ret; - } - - msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk); - if (!msm_host->dsi_clk_src) { - ret = -ENODEV; - pr_err("%s: can't get src clock parent. ret=%d\n", - __func__, ret); - } - return ret; } @@ -378,6 +278,38 @@ int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host) return ret; } +int dsi_clk_init_6g_v2_9(struct msm_dsi_host *msm_host) +{ + struct device *dev = &msm_host->pdev->dev; + int ret; + + ret = dsi_clk_init_6g_v2(msm_host); + if (ret) + return ret; + + msm_host->byte_src_clk = devm_clk_get(dev, "byte_src"); + if (IS_ERR(msm_host->byte_src_clk)) + return dev_err_probe(dev, PTR_ERR(msm_host->byte_src_clk), + "can't get byte_src clock\n"); + + msm_host->dsi_pll_byte_clk = devm_clk_get(dev, "dsi_pll_byte"); + if (IS_ERR(msm_host->dsi_pll_byte_clk)) + return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_byte_clk), + "can't get dsi_pll_byte clock\n"); + + msm_host->pixel_src_clk = devm_clk_get(dev, "pixel_src"); + if (IS_ERR(msm_host->pixel_src_clk)) + return dev_err_probe(dev, PTR_ERR(msm_host->pixel_src_clk), + "can't get pixel_src clock\n"); + + msm_host->dsi_pll_pixel_clk = devm_clk_get(dev, "dsi_pll_pixel"); + if (IS_ERR(msm_host->dsi_pll_pixel_clk)) + return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_pixel_clk), + "can't get dsi_pll_pixel clock\n"); + + return 0; +} + static int dsi_clk_init(struct msm_dsi_host *msm_host) { struct platform_device *pdev = msm_host->pdev; @@ -386,100 +318,39 @@ static int dsi_clk_init(struct msm_dsi_host *msm_host) int i, ret = 0; /* get bus clocks */ - for (i = 0; i < cfg->num_bus_clks; i++) { - msm_host->bus_clks[i] = msm_clk_get(pdev, - cfg->bus_clk_names[i]); - if (IS_ERR(msm_host->bus_clks[i])) { - ret = PTR_ERR(msm_host->bus_clks[i]); - pr_err("%s: Unable to get %s clock, ret = %d\n", - __func__, cfg->bus_clk_names[i], ret); - goto exit; - } - } + for (i = 0; i < cfg->num_bus_clks; i++) + msm_host->bus_clks[i].id = cfg->bus_clk_names[i]; + msm_host->num_bus_clks = cfg->num_bus_clks; + + ret = devm_clk_bulk_get(&pdev->dev, msm_host->num_bus_clks, msm_host->bus_clks); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "Unable to get clocks\n"); /* get link and source clocks */ msm_host->byte_clk = msm_clk_get(pdev, "byte"); - if (IS_ERR(msm_host->byte_clk)) { - ret = PTR_ERR(msm_host->byte_clk); - pr_err("%s: can't find dsi_byte clock. ret=%d\n", - __func__, ret); - msm_host->byte_clk = NULL; - goto exit; - } + if (IS_ERR(msm_host->byte_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->byte_clk), + "%s: can't find dsi_byte clock\n", + __func__); msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); - if (IS_ERR(msm_host->pixel_clk)) { - ret = PTR_ERR(msm_host->pixel_clk); - pr_err("%s: can't find dsi_pixel clock. ret=%d\n", - __func__, ret); - msm_host->pixel_clk = NULL; - goto exit; - } + if (IS_ERR(msm_host->pixel_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->pixel_clk), + "%s: can't find dsi_pixel clock\n", + __func__); msm_host->esc_clk = msm_clk_get(pdev, "core"); - if (IS_ERR(msm_host->esc_clk)) { - ret = PTR_ERR(msm_host->esc_clk); - pr_err("%s: can't find dsi_esc clock. ret=%d\n", - __func__, ret); - msm_host->esc_clk = NULL; - goto exit; - } - - msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk); - if (IS_ERR(msm_host->byte_clk_src)) { - ret = PTR_ERR(msm_host->byte_clk_src); - pr_err("%s: can't find byte_clk clock. ret=%d\n", __func__, ret); - goto exit; - } - - msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk); - if (IS_ERR(msm_host->pixel_clk_src)) { - ret = PTR_ERR(msm_host->pixel_clk_src); - pr_err("%s: can't find pixel_clk clock. ret=%d\n", __func__, ret); - goto exit; - } + if (IS_ERR(msm_host->esc_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->esc_clk), + "%s: can't find dsi_esc clock\n", + __func__); if (cfg_hnd->ops->clk_init_ver) ret = cfg_hnd->ops->clk_init_ver(msm_host); -exit: - return ret; -} - -static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host) -{ - const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; - int i, ret; - - DBG("id=%d", msm_host->id); - - for (i = 0; i < cfg->num_bus_clks; i++) { - ret = clk_prepare_enable(msm_host->bus_clks[i]); - if (ret) { - pr_err("%s: failed to enable bus clock %d ret %d\n", - __func__, i, ret); - goto err; - } - } - - return 0; -err: - for (; i > 0; i--) - clk_disable_unprepare(msm_host->bus_clks[i]); return ret; } -static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host) -{ - const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; - int i; - - DBG(""); - - for (i = cfg->num_bus_clks - 1; i >= 0; i--) - clk_disable_unprepare(msm_host->bus_clks[i]); -} - int msm_dsi_runtime_suspend(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); @@ -490,7 +361,7 @@ int msm_dsi_runtime_suspend(struct device *dev) if (!msm_host->cfg_hnd) return 0; - dsi_bus_clk_disable(msm_host); + clk_bulk_disable_unprepare(msm_host->num_bus_clks, msm_host->bus_clks); return 0; } @@ -505,15 +376,15 @@ int msm_dsi_runtime_resume(struct device *dev) if (!msm_host->cfg_hnd) return 0; - return dsi_bus_clk_enable(msm_host); + return clk_bulk_prepare_enable(msm_host->num_bus_clks, msm_host->bus_clks); } int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) { int ret; - DBG("Set clk rates: pclk=%d, byteclk=%d", - msm_host->mode->clock, msm_host->byte_clk_rate); + DBG("Set clk rates: pclk=%lu, byteclk=%lu", + msm_host->pixel_clk_rate, msm_host->byte_clk_rate); ret = dev_pm_opp_set_rate(&msm_host->pdev->dev, msm_host->byte_clk_rate); @@ -529,8 +400,7 @@ int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) } if (msm_host->byte_intf_clk) { - ret = clk_set_rate(msm_host->byte_intf_clk, - msm_host->byte_clk_rate / 2); + ret = clk_set_rate(msm_host->byte_intf_clk, msm_host->byte_intf_clk_rate); if (ret) { pr_err("%s: Failed to set rate byte intf clk, %d\n", __func__, ret); @@ -541,6 +411,25 @@ int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) return 0; } +int dsi_link_clk_set_rate_6g_v2_9(struct msm_dsi_host *msm_host) +{ + struct device *dev = &msm_host->pdev->dev; + int ret; + + /* + * DSI PHY PLLs have to be enabled to allow reparenting to them, so + * cannot use assigned-clock-parents. + */ + ret = clk_set_parent(msm_host->byte_src_clk, msm_host->dsi_pll_byte_clk); + if (ret) + dev_err(dev, "Failed to parent byte_src -> dsi_pll_byte: %d\n", ret); + + ret = clk_set_parent(msm_host->pixel_src_clk, msm_host->dsi_pll_pixel_clk); + if (ret) + dev_err(dev, "Failed to parent pixel_src -> dsi_pll_pixel: %d\n", ret); + + return dsi_link_clk_set_rate_6g(msm_host); +} int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) { @@ -564,13 +453,11 @@ int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) goto pixel_clk_err; } - if (msm_host->byte_intf_clk) { - ret = clk_prepare_enable(msm_host->byte_intf_clk); - if (ret) { - pr_err("%s: Failed to enable byte intf clk\n", - __func__); - goto byte_intf_clk_err; - } + ret = clk_prepare_enable(msm_host->byte_intf_clk); + if (ret) { + pr_err("%s: Failed to enable byte intf clk\n", + __func__); + goto byte_intf_clk_err; } return 0; @@ -589,9 +476,9 @@ int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host) { int ret; - DBG("Set clk rates: pclk=%d, byteclk=%d, esc_clk=%d, dsi_src_clk=%d", - msm_host->mode->clock, msm_host->byte_clk_rate, - msm_host->esc_clk_rate, msm_host->src_clk_rate); + DBG("Set clk rates: pclk=%lu, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu", + msm_host->pixel_clk_rate, msm_host->byte_clk_rate, + msm_host->esc_clk_rate, msm_host->src_clk_rate); ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); if (ret) { @@ -666,8 +553,7 @@ void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host) dev_pm_opp_set_rate(&msm_host->pdev->dev, 0); clk_disable_unprepare(msm_host->esc_clk); clk_disable_unprepare(msm_host->pixel_clk); - if (msm_host->byte_intf_clk) - clk_disable_unprepare(msm_host->byte_intf_clk); + clk_disable_unprepare(msm_host->byte_intf_clk); clk_disable_unprepare(msm_host->byte_clk); } @@ -679,71 +565,112 @@ void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) clk_disable_unprepare(msm_host->byte_clk); } -static u32 dsi_get_pclk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi) +/** + * dsi_adjust_pclk_for_compression() - Adjust the pclk rate for compression case + * @mode: The selected mode for the DSI output + * @dsc: DRM DSC configuration for this DSI output + * + * Adjust the pclk rate by calculating a new hdisplay proportional to + * the compression ratio such that: + * new_hdisplay = old_hdisplay * compressed_bpp / uncompressed_bpp + * + * Porches do not need to be adjusted: + * - For VIDEO mode they are not compressed by DSC and are passed as is. + * - For CMD mode there are no actual porches. Instead these fields + * currently represent the overhead to the image data transfer. As such, they + * are calculated for the final mode parameters (after the compression) and + * are not to be adjusted too. + * + * FIXME: Reconsider this if/when CMD mode handling is rewritten to use + * transfer time and data overhead as a starting point of the calculations. + */ +static unsigned long dsi_adjust_pclk_for_compression(const struct drm_display_mode *mode, + const struct drm_dsc_config *dsc) { - struct drm_display_mode *mode = msm_host->mode; - u32 pclk_rate; + int new_hdisplay = DIV_ROUND_UP(mode->hdisplay * drm_dsc_get_bpp_int(dsc), + dsc->bits_per_component * 3); - pclk_rate = mode->clock * 1000; + int new_htotal = mode->htotal - mode->hdisplay + new_hdisplay; + + return mult_frac(mode->clock * 1000u, new_htotal, mode->htotal); +} + +static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode, + const struct drm_dsc_config *dsc, bool is_bonded_dsi) +{ + unsigned long pclk_rate; + + pclk_rate = mode->clock * 1000u; + + if (dsc) + pclk_rate = dsi_adjust_pclk_for_compression(mode, dsc); /* - * For dual DSI mode, the current DRM mode has the complete width of the + * For bonded DSI mode, the current DRM mode has the complete width of the * panel. Since, the complete panel is driven by two DSI controllers, * the clock rates have to be split between the two dsi controllers. * Adjust the byte and pixel clock rates for each dsi host accordingly. */ - if (is_dual_dsi) + if (is_bonded_dsi) pclk_rate /= 2; return pclk_rate; } -static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_dual_dsi) +unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_dsi, + const struct drm_display_mode *mode) { + struct msm_dsi_host *msm_host = to_msm_dsi_host(host); u8 lanes = msm_host->lanes; - u32 bpp = dsi_get_bpp(msm_host->format); - u32 pclk_rate = dsi_get_pclk_rate(msm_host, is_dual_dsi); - u64 pclk_bpp = (u64)pclk_rate * bpp; + u32 bpp = mipi_dsi_pixel_format_to_bpp(msm_host->format); + unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc, is_bonded_dsi); + unsigned long pclk_bpp; if (lanes == 0) { pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); lanes = 1; } - do_div(pclk_bpp, (8 * lanes)); + /* CPHY "byte_clk" is in units of 16 bits */ + if (msm_host->cphy_mode) + pclk_bpp = mult_frac(pclk_rate, bpp, 16 * lanes); + else + pclk_bpp = mult_frac(pclk_rate, bpp, 8 * lanes); - msm_host->pixel_clk_rate = pclk_rate; - msm_host->byte_clk_rate = pclk_bpp; + return pclk_bpp; +} - DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate, - msm_host->byte_clk_rate); +static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi) +{ + msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode, msm_host->dsc, is_bonded_dsi); + msm_host->byte_clk_rate = dsi_byte_clk_get_rate(&msm_host->base, is_bonded_dsi, + msm_host->mode); + DBG("pclk=%lu, bclk=%lu", msm_host->pixel_clk_rate, + msm_host->byte_clk_rate); } -int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi) +int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi) { if (!msm_host->mode) { pr_err("%s: mode not set\n", __func__); return -EINVAL; } - dsi_calc_pclk(msm_host, is_dual_dsi); + dsi_calc_pclk(msm_host, is_bonded_dsi); msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); return 0; } -int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi) +int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi) { - u32 bpp = dsi_get_bpp(msm_host->format); - u64 pclk_bpp; + u32 bpp = mipi_dsi_pixel_format_to_bpp(msm_host->format); unsigned int esc_mhz, esc_div; unsigned long byte_mhz; - dsi_calc_pclk(msm_host, is_dual_dsi); + dsi_calc_pclk(msm_host, is_bonded_dsi); - pclk_bpp = (u64)dsi_get_pclk_rate(msm_host, is_dual_dsi) * bpp; - do_div(pclk_bpp, 8); - msm_host->src_clk_rate = pclk_bpp; + msm_host->src_clk_rate = mult_frac(msm_host->pixel_clk_rate, bpp, 8); /* * esc clock is byte clock followed by a 4 bit divider, @@ -774,7 +701,7 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi) msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div; - DBG("esc=%d, src=%d", msm_host->esc_clk_rate, + DBG("esc=%lu, src=%lu", msm_host->esc_clk_rate, msm_host->src_clk_rate); return 0; @@ -809,8 +736,8 @@ static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags) return NON_BURST_SYNCH_EVENT; } -static inline enum dsi_vid_dst_format dsi_get_vid_fmt( - const enum mipi_dsi_pixel_format mipi_fmt) +static inline enum dsi_vid_dst_format +dsi_get_vid_fmt(const enum mipi_dsi_pixel_format mipi_fmt) { switch (mipi_fmt) { case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; @@ -821,8 +748,8 @@ static inline enum dsi_vid_dst_format dsi_get_vid_fmt( } } -static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt( - const enum mipi_dsi_pixel_format mipi_fmt) +static inline enum dsi_cmd_dst_format +dsi_get_cmd_fmt(const enum mipi_dsi_pixel_format mipi_fmt) { switch (mipi_fmt) { case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; @@ -833,27 +760,36 @@ static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt( } } -static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, - struct msm_dsi_phy_shared_timings *phy_shared_timings) +static void dsi_ctrl_disable(struct msm_dsi_host *msm_host) +{ + dsi_write(msm_host, REG_DSI_CTRL, 0); +} + +bool msm_dsi_host_is_wide_bus_enabled(struct mipi_dsi_host *host) +{ + struct msm_dsi_host *msm_host = to_msm_dsi_host(host); + + return msm_host->dsc && + (msm_host->cfg_hnd->major == MSM_DSI_VER_MAJOR_6G && + msm_host->cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V2_5_0); +} + +static void dsi_ctrl_enable(struct msm_dsi_host *msm_host, + struct msm_dsi_phy_shared_timings *phy_shared_timings, struct msm_dsi_phy *phy) { u32 flags = msm_host->mode_flags; enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; u32 data = 0, lane_ctrl = 0; - if (!enable) { - dsi_write(msm_host, REG_DSI_CTRL, 0); - return; - } - if (flags & MIPI_DSI_MODE_VIDEO) { if (flags & MIPI_DSI_MODE_VIDEO_HSE) data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE; - if (flags & MIPI_DSI_MODE_VIDEO_HFP) + if (flags & MIPI_DSI_MODE_VIDEO_NO_HFP) data |= DSI_VID_CFG0_HFP_POWER_STOP; - if (flags & MIPI_DSI_MODE_VIDEO_HBP) + if (flags & MIPI_DSI_MODE_VIDEO_NO_HBP) data |= DSI_VID_CFG0_HBP_POWER_STOP; - if (flags & MIPI_DSI_MODE_VIDEO_HSA) + if (flags & MIPI_DSI_MODE_VIDEO_NO_HSA) data |= DSI_VID_CFG0_HSA_POWER_STOP; /* Always set low power stop mode for BLLP * to let command engine send packets @@ -863,6 +799,8 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); + if (msm_dsi_host_is_wide_bus_enabled(&msm_host->base)) + data |= DSI_VID_CFG0_DATABUS_WIDEN; dsi_write(msm_host, REG_DSI_VID_CFG0, data); /* Do not swap RGB colors */ @@ -880,6 +818,18 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, /* Always insert DCS command */ data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; dsi_write(msm_host, REG_DSI_CMD_CFG1, data); + + if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) { + data = dsi_read(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2); + + if (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_3) + data |= DSI_CMD_MODE_MDP_CTRL2_BURST_MODE; + + if (msm_dsi_host_is_wide_bus_enabled(&msm_host->base)) + data |= DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN; + + dsi_write(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2, data); + } } dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, @@ -908,7 +858,7 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK); data = 0; - if (!(flags & MIPI_DSI_MODE_EOT_PACKET)) + if (!(flags & MIPI_DSI_MODE_NO_EOT_PACKET)) data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND; dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data); @@ -929,6 +879,10 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) { lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL); + + if (msm_dsi_phy_set_continuous_clock(phy, true)) + lane_ctrl &= ~DSI_LANE_CTRL_HS_REQ_SEL_PHY; + dsi_write(msm_host, REG_DSI_LANE_CTRL, lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); } @@ -936,9 +890,74 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, data |= DSI_CTRL_ENABLE; dsi_write(msm_host, REG_DSI_CTRL, data); + + if (msm_host->cphy_mode) + dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0)); +} + +static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode) +{ + struct drm_dsc_config *dsc = msm_host->dsc; + u32 reg, reg_ctrl, reg_ctrl2; + u32 slice_per_intf, total_bytes_per_intf; + u32 pkt_per_line; + u32 eol_byte_num; + u32 bytes_per_pkt; + + /* first calculate dsc parameters and then program + * compress mode registers + */ + slice_per_intf = dsc->slice_count; + + total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; + bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */ + + eol_byte_num = total_bytes_per_intf % 3; + + /* + * Typically, pkt_per_line = slice_per_intf * slice_per_pkt. + * + * Since the current driver only supports slice_per_pkt = 1, + * pkt_per_line will be equal to slice per intf for now. + */ + pkt_per_line = slice_per_intf; + + if (is_cmd_mode) /* packet data type */ + reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE); + else + reg = DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(MIPI_DSI_COMPRESSED_PIXEL_STREAM); + + /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE + * registers have similar offsets, so for below common code use + * DSI_VIDEO_COMPRESSION_MODE_XXXX for setting bits + * + * pkt_per_line is log2 encoded, >>1 works for supported values (1,2,4) + */ + if (pkt_per_line > 4) + drm_warn_once(msm_host->dev, "pkt_per_line too big"); + reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1); + reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num); + reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EN; + + if (is_cmd_mode) { + reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL); + reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2); + + reg_ctrl &= ~0xffff; + reg_ctrl |= reg; + + reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK; + reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size); + + dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl); + dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); + } else { + reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(bytes_per_pkt); + dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); + } } -static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_dual_dsi) +static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) { struct drm_display_mode *mode = msm_host->mode; u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ @@ -952,17 +971,19 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_dual_dsi) u32 va_end = va_start + mode->vdisplay; u32 hdisplay = mode->hdisplay; u32 wc; + int ret; + bool wide_bus_enabled = msm_dsi_host_is_wide_bus_enabled(&msm_host->base); DBG(""); /* - * For dual DSI mode, the current DRM mode has + * For bonded DSI mode, the current DRM mode has * the complete width of the panel. Since, the complete * panel is driven by two DSI controllers, the horizontal * timings have to be split between the two dsi controllers. * Adjust the DSI host timing values accordingly. */ - if (is_dual_dsi) { + if (is_bonded_dsi) { h_total /= 2; hs_end /= 2; ha_start /= 2; @@ -970,7 +991,57 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_dual_dsi) hdisplay /= 2; } + if (msm_host->dsc) { + struct drm_dsc_config *dsc = msm_host->dsc; + u32 bytes_per_pclk; + + /* update dsc params with timing params */ + if (!dsc || !mode->hdisplay || !mode->vdisplay) { + pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", + mode->hdisplay, mode->vdisplay); + return; + } + + dsc->pic_width = mode->hdisplay; + dsc->pic_height = mode->vdisplay; + DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height); + + /* we do the calculations for dsc parameters here so that + * panel can use these parameters + */ + ret = dsi_populate_dsc_params(msm_host, dsc); + if (ret) + return; + + /* + * DPU sends 3 bytes per pclk cycle to DSI. If widebus is + * enabled, bus width is extended to 6 bytes. + * + * Calculate the number of pclks needed to transmit one line of + * the compressed data. + + * The back/font porch and pulse width are kept intact. For + * VIDEO mode they represent timing parameters rather than + * actual data transfer, see the documentation for + * dsi_adjust_pclk_for_compression(). For CMD mode they are + * unused anyway. + */ + h_total -= hdisplay; + if (wide_bus_enabled && !(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) + bytes_per_pclk = 6; + else + bytes_per_pclk = 3; + + hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), bytes_per_pclk); + + h_total += hdisplay; + ha_end = ha_start + hdisplay; + } + if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { + if (msm_host->dsc) + dsi_update_dsc_timing(msm_host, false); + dsi_write(msm_host, REG_DSI_ACTIVE_H, DSI_ACTIVE_H_START(ha_start) | DSI_ACTIVE_H_END(ha_end)); @@ -989,8 +1060,21 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_dual_dsi) DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); } else { /* command mode */ + if (msm_host->dsc) + dsi_update_dsc_timing(msm_host, true); + /* image data and 1 byte write_memory_start cmd */ - wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; + if (!msm_host->dsc) + wc = hdisplay * mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8 + 1; + else + /* + * When DSC is enabled, WC = slice_chunk_size * slice_per_pkt + 1. + * Currently, the driver only supports default value of slice_per_pkt = 1 + * + * TODO: Expand mipi_dsi_device struct to hold slice_per_pkt info + * and adjust DSC math to account for slice_per_pkt. + */ + wc = msm_host->dsc->slice_chunk_size + 1; dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | @@ -1007,12 +1091,32 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_dual_dsi) static void dsi_sw_reset(struct msm_dsi_host *msm_host) { + u32 ctrl; + + ctrl = dsi_read(msm_host, REG_DSI_CTRL); + + if (ctrl & DSI_CTRL_ENABLE) { + dsi_write(msm_host, REG_DSI_CTRL, ctrl & ~DSI_CTRL_ENABLE); + /* + * dsi controller need to be disabled before + * clocks turned on + */ + wmb(); + } + dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); wmb(); /* clocks need to be enabled before reset */ + /* dsi controller can only be reset while clocks are running */ dsi_write(msm_host, REG_DSI_RESET, 1); msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ dsi_write(msm_host, REG_DSI_RESET, 0); + wmb(); /* controller out of reset */ + + if (ctrl & DSI_CTRL_ENABLE) { + dsi_write(msm_host, REG_DSI_CTRL, ctrl); + wmb(); /* make sure dsi controller enabled again */ + } } static void dsi_op_mode_config(struct msm_dsi_host *msm_host, @@ -1074,9 +1178,21 @@ static void dsi_wait4video_done(struct msm_dsi_host *msm_host) static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) { + u32 data; + if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) return; + data = dsi_read(msm_host, REG_DSI_STATUS0); + + /* if video mode engine is not busy, its because + * either timing engine was not turned on or the + * DSI controller has finished transmitting the video + * data already, so no need to wait in those cases + */ + if (!(data & DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY)) + return; + if (msm_host->power_on && msm_host->enabled) { dsi_wait4video_done(msm_host); /* delay 4 ms to skip BLLP */ @@ -1091,8 +1207,10 @@ int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size) uint64_t iova; u8 *data; + msm_host->vm = drm_gpuvm_get(priv->kms->vm); + data = msm_gem_kernel_new(dev, size, MSM_BO_WC, - priv->kms->aspace, + msm_host->vm, &msm_host->tx_gem_obj, &iova); if (IS_ERR(data)) { @@ -1121,10 +1239,10 @@ int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size) return 0; } -static void dsi_tx_buf_free(struct msm_dsi_host *msm_host) +void msm_dsi_tx_buf_free(struct mipi_dsi_host *host) { + struct msm_dsi_host *msm_host = to_msm_dsi_host(host); struct drm_device *dev = msm_host->dev; - struct msm_drm_private *priv; /* * This is possible if we're tearing down before we've had a chance to @@ -1135,11 +1253,11 @@ static void dsi_tx_buf_free(struct msm_dsi_host *msm_host) if (!dev) return; - priv = dev->dev_private; if (msm_host->tx_gem_obj) { - msm_gem_unpin_iova(msm_host->tx_gem_obj, priv->kms->aspace); - drm_gem_object_put(msm_host->tx_gem_obj); + msm_gem_kernel_put(msm_host->tx_gem_obj, msm_host->vm); + drm_gpuvm_put(msm_host->vm); msm_host->tx_gem_obj = NULL; + msm_host->vm = NULL; } if (msm_host->tx_buf) @@ -1223,14 +1341,15 @@ static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host, static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) { u8 *data = msg->rx_buf; + if (data && (msg->rx_len >= 1)) { *data = buf[1]; /* strip out dcs type */ return 1; - } else { - pr_err("%s: read data does not match with rx_buf len %zu\n", - __func__, msg->rx_len); - return -EINVAL; } + + pr_err("%s: read data does not match with rx_buf len %zu\n", + __func__, msg->rx_len); + return -EINVAL; } /* @@ -1239,15 +1358,16 @@ static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg) { u8 *data = msg->rx_buf; + if (data && (msg->rx_len >= 2)) { data[0] = buf[1]; /* strip out dcs type */ data[1] = buf[2]; return 2; - } else { - pr_err("%s: read data does not match with rx_buf len %zu\n", - __func__, msg->rx_len); - return -EINVAL; } + + pr_err("%s: read data does not match with rx_buf len %zu\n", + __func__, msg->rx_len); + return -EINVAL; } static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg) @@ -1268,7 +1388,7 @@ int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base) return -EINVAL; return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj, - priv->kms->aspace, dma_base); + priv->kms->vm, dma_base); } int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base) @@ -1307,8 +1427,9 @@ static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) ret = -ETIMEDOUT; else ret = len; - } else + } else { ret = len; + } return ret; } @@ -1367,20 +1488,21 @@ static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, { int len, ret; int bllp_len = msm_host->mode->hdisplay * - dsi_get_bpp(msm_host->format) / 8; + mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8; len = dsi_cmd_dma_add(msm_host, msg); - if (!len) { + if (len < 0) { pr_err("%s: failed to add cmd type = 0x%x\n", __func__, msg->type); - return -EINVAL; + return len; } - /* for video mode, do not send cmds more than - * one pixel line, since it only transmit it - * during BLLP. - */ - /* TODO: if the command is sent in LP mode, the bit rate is only + /* + * for video mode, do not send cmds more than + * one pixel line, since it only transmit it + * during BLLP. + * + * TODO: if the command is sent in LP mode, the bit rate is only * half of esc clk rate. In this case, if the video is already * actively streaming, we need to check more carefully if the * command can be fit into one BLLP. @@ -1392,49 +1514,19 @@ static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, } ret = dsi_cmd_dma_tx(msm_host, len); - if (ret < len) { - pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n", - __func__, msg->type, (*(u8 *)(msg->tx_buf)), len); - return -ECOMM; + if (ret < 0) { + pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d, ret=%d\n", + __func__, msg->type, (*(u8 *)(msg->tx_buf)), len, ret); + return ret; + } else if (ret < len) { + pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, ret=%d len=%d\n", + __func__, msg->type, (*(u8 *)(msg->tx_buf)), ret, len); + return -EIO; } return len; } -static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host) -{ - u32 data0, data1; - - data0 = dsi_read(msm_host, REG_DSI_CTRL); - data1 = data0; - data1 &= ~DSI_CTRL_ENABLE; - dsi_write(msm_host, REG_DSI_CTRL, data1); - /* - * dsi controller need to be disabled before - * clocks turned on - */ - wmb(); - - dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); - wmb(); /* make sure clocks enabled */ - - /* dsi controller can only be reset while clocks are running */ - dsi_write(msm_host, REG_DSI_RESET, 1); - msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ - dsi_write(msm_host, REG_DSI_RESET, 0); - wmb(); /* controller out of reset */ - dsi_write(msm_host, REG_DSI_CTRL, data0); - wmb(); /* make sure dsi controller enabled again */ -} - -static void dsi_hpd_worker(struct work_struct *work) -{ - struct msm_dsi_host *msm_host = - container_of(work, struct msm_dsi_host, hpd_work); - - drm_helper_hpd_irq_event(msm_host->dev); -} - static void dsi_err_worker(struct work_struct *work) { struct msm_dsi_host *msm_host = @@ -1443,7 +1535,7 @@ static void dsi_err_worker(struct work_struct *work) pr_err_ratelimited("%s: status=%x\n", __func__, status); if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) - dsi_sw_reset_restore(msm_host); + dsi_sw_reset(msm_host); /* It is safe to clear here because error irq is disabled. */ msm_host->err_work_state = 0; @@ -1578,28 +1670,6 @@ static irqreturn_t dsi_host_irq(int irq, void *ptr) return IRQ_HANDLED; } -static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host, - struct device *panel_device) -{ - msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device, - "disp-enable", - GPIOD_OUT_LOW); - if (IS_ERR(msm_host->disp_en_gpio)) { - DBG("cannot get disp-enable-gpios %ld", - PTR_ERR(msm_host->disp_en_gpio)); - return PTR_ERR(msm_host->disp_en_gpio); - } - - msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te", - GPIOD_IN); - if (IS_ERR(msm_host->te_gpio)) { - DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio)); - return PTR_ERR(msm_host->te_gpio); - } - - return 0; -} - static int dsi_host_attach(struct mipi_dsi_host *host, struct mipi_dsi_device *dsi) { @@ -1613,15 +1683,14 @@ static int dsi_host_attach(struct mipi_dsi_host *host, msm_host->lanes = dsi->lanes; msm_host->format = dsi->format; msm_host->mode_flags = dsi->mode_flags; + if (dsi->dsc) + msm_host->dsc = dsi->dsc; - /* Some gpios defined in panel DT need to be controlled by host */ - ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev); + ret = dsi_dev_attach(msm_host->pdev); if (ret) return ret; DBG("id=%d", msm_host->id); - if (msm_host->dev) - queue_work(msm_host->workqueue, &msm_host->hpd_work); return 0; } @@ -1631,11 +1700,9 @@ static int dsi_host_detach(struct mipi_dsi_host *host, { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); - msm_host->device_node = NULL; + dsi_dev_detach(msm_host->pdev); DBG("id=%d", msm_host->id); - if (msm_host->dev) - queue_work(msm_host->workqueue, &msm_host->hpd_work); return 0; } @@ -1691,14 +1758,15 @@ static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, if (!prop) { DRM_DEV_DEBUG(dev, "failed to find data lane mapping, using default\n"); + /* Set the number of date lanes to 4 by default. */ + msm_host->num_data_lanes = 4; return 0; } - num_lanes = len / sizeof(u32); - - if (num_lanes < 1 || num_lanes > 4) { + num_lanes = drm_of_get_data_lanes_count(ep, 1, 4); + if (num_lanes < 0) { DRM_DEV_ERROR(dev, "bad number of data lanes\n"); - return -EINVAL; + return num_lanes; } msm_host->num_data_lanes = num_lanes; @@ -1743,11 +1811,59 @@ static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, return -EINVAL; } +static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc) +{ + int ret; + + if (dsc->bits_per_pixel & 0xf) { + DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n"); + return -EINVAL; + } + + switch (dsc->bits_per_component) { + case 8: + case 10: + case 12: + /* + * Only 8, 10, and 12 bpc are supported for DSC 1.1 block. + * If additional bpc values need to be supported, update + * this quard with the appropriate DSC version verification. + */ + break; + default: + DRM_DEV_ERROR(&msm_host->pdev->dev, + "Unsupported bits_per_component value: %d\n", + dsc->bits_per_component); + return -EOPNOTSUPP; + } + + dsc->simple_422 = 0; + dsc->convert_rgb = 1; + dsc->vbr_enable = 0; + + drm_dsc_set_const_params(dsc); + drm_dsc_set_rc_buf_thresh(dsc); + + /* DPU supports only pre-SCR panels */ + ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR); + if (ret) { + DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n"); + return ret; + } + + dsc->initial_scale_value = drm_dsc_initial_scale_value(dsc); + dsc->line_buf_depth = dsc->bits_per_component + 1; + + return drm_dsc_compute_rc_parameters(dsc); +} + static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) { + struct msm_dsi *msm_dsi = platform_get_drvdata(msm_host->pdev); struct device *dev = &msm_host->pdev->dev; struct device_node *np = dev->of_node; - struct device_node *endpoint, *device_node; + struct device_node *endpoint; + const char *te_source; int ret = 0; /* @@ -1770,17 +1886,24 @@ static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) goto err; } - /* Get panel node from the output port's endpoint data */ - device_node = of_graph_get_remote_node(np, 1, 0); - if (!device_node) { - DRM_DEV_DEBUG(dev, "%s: no valid device\n", __func__); - ret = -ENODEV; + ret = of_property_read_string(endpoint, "qcom,te-source", &te_source); + if (ret && ret != -EINVAL) { + DRM_DEV_ERROR(dev, "%s: invalid TE source configuration %d\n", + __func__, ret); goto err; } + if (!ret) { + msm_dsi->te_source = devm_kstrdup(dev, te_source, GFP_KERNEL); + if (!msm_dsi->te_source) { + DRM_DEV_ERROR(dev, "%s: failed to allocate te_source\n", + __func__); + ret = -ENOMEM; + goto err; + } + } + ret = 0; - msm_host->device_node = device_node; - - if (of_property_read_bool(np, "syscon-sfpb")) { + if (of_property_present(np, "syscon-sfpb")) { msm_host->sfpb = syscon_regmap_lookup_by_phandle(np, "syscon-sfpb"); if (IS_ERR(msm_host->sfpb)) { @@ -1790,8 +1913,6 @@ static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) } } - of_node_put(device_node); - err: of_node_put(endpoint); @@ -1803,16 +1924,16 @@ static int dsi_host_get_id(struct msm_dsi_host *msm_host) struct platform_device *pdev = msm_host->pdev; const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; struct resource *res; - int i; + int i, j; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl"); if (!res) return -EINVAL; - for (i = 0; i < cfg->num_dsi; i++) { - if (cfg->io_start[i] == res->start) - return i; - } + for (i = 0; i < VARIANTS_MAX; i++) + for (j = 0; j < DSI_MAX; j++) + if (cfg->io_start[i][j] == res->start) + return j; return -EINVAL; } @@ -1821,77 +1942,76 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) { struct msm_dsi_host *msm_host = NULL; struct platform_device *pdev = msm_dsi->pdev; + const struct msm_dsi_config *cfg; int ret; msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); - if (!msm_host) { - ret = -ENOMEM; - goto fail; - } + if (!msm_host) + return -ENOMEM; msm_host->pdev = pdev; msm_dsi->host = &msm_host->base; ret = dsi_host_parse_dt(msm_host); - if (ret) { - pr_err("%s: failed to parse dt\n", __func__); - goto fail; - } + if (ret) + return dev_err_probe(&pdev->dev, ret, "%s: failed to parse dt\n", + __func__); - msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", "DSI CTRL", &msm_host->ctrl_size); - if (IS_ERR(msm_host->ctrl_base)) { - pr_err("%s: unable to map Dsi ctrl base\n", __func__); - ret = PTR_ERR(msm_host->ctrl_base); - goto fail; - } + msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", &msm_host->ctrl_size); + if (IS_ERR(msm_host->ctrl_base)) + return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->ctrl_base), + "%s: unable to map Dsi ctrl base\n", __func__); pm_runtime_enable(&pdev->dev); msm_host->cfg_hnd = dsi_get_config(msm_host); - if (!msm_host->cfg_hnd) { - ret = -EINVAL; - pr_err("%s: get config failed\n", __func__); - goto fail; - } + if (!msm_host->cfg_hnd) + return dev_err_probe(&pdev->dev, -EINVAL, + "%s: get config failed\n", __func__); + cfg = msm_host->cfg_hnd->cfg; msm_host->id = dsi_host_get_id(msm_host); - if (msm_host->id < 0) { - ret = msm_host->id; - pr_err("%s: unable to identify DSI host index\n", __func__); - goto fail; - } + if (msm_host->id < 0) + return dev_err_probe(&pdev->dev, msm_host->id, + "%s: unable to identify DSI host index\n", + __func__); /* fixup base address by io offset */ - msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset; + msm_host->ctrl_base += cfg->io_offset; - ret = dsi_regulator_init(msm_host); - if (ret) { - pr_err("%s: regulator init failed\n", __func__); - goto fail; - } + ret = devm_regulator_bulk_get_const(&pdev->dev, cfg->num_regulators, + cfg->regulator_data, + &msm_host->supplies); + if (ret) + return ret; ret = dsi_clk_init(msm_host); - if (ret) { - pr_err("%s: unable to initialize dsi clks\n", __func__); - goto fail; - } + if (ret) + return dev_err_probe(&pdev->dev, ret, "%s: unable to initialize dsi clks\n", __func__); msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); - if (!msm_host->rx_buf) { - ret = -ENOMEM; - pr_err("%s: alloc rx temp buf failed\n", __func__); - goto fail; - } + if (!msm_host->rx_buf) + return -ENOMEM; ret = devm_pm_opp_set_clkname(&pdev->dev, "byte"); if (ret) return ret; /* OPP table is optional */ ret = devm_pm_opp_of_add_table(&pdev->dev); - if (ret && ret != -ENODEV) { - dev_err(&pdev->dev, "invalid OPP table in device tree\n"); - return ret; - } + if (ret && ret != -ENODEV) + return dev_err_probe(&pdev->dev, ret, "invalid OPP table in device tree\n"); + + msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); + if (!msm_host->irq) + return dev_err_probe(&pdev->dev, -EINVAL, "failed to get irq\n"); + + /* do not autoenable, will be enabled later */ + ret = devm_request_irq(&pdev->dev, msm_host->irq, dsi_host_irq, + IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN, + "dsi_isr", msm_host); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "failed to request IRQ%u\n", + msm_host->irq); init_completion(&msm_host->dma_comp); init_completion(&msm_host->video_comp); @@ -1901,16 +2021,15 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) /* setup workqueue */ msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); + if (!msm_host->workqueue) + return -ENOMEM; + INIT_WORK(&msm_host->err_work, dsi_err_worker); - INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker); msm_dsi->id = msm_host->id; DBG("Dsi Host %d initialized", msm_host->id); return 0; - -fail: - return ret; } void msm_dsi_host_destroy(struct mipi_dsi_host *host) @@ -1918,9 +2037,7 @@ void msm_dsi_host_destroy(struct mipi_dsi_host *host) struct msm_dsi_host *msm_host = to_msm_dsi_host(host); DBG(""); - dsi_tx_buf_free(msm_host); if (msm_host->workqueue) { - flush_workqueue(msm_host->workqueue); destroy_workqueue(msm_host->workqueue); msm_host->workqueue = NULL; } @@ -1936,26 +2053,10 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; - struct platform_device *pdev = msm_host->pdev; int ret; - msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); - if (msm_host->irq < 0) { - ret = msm_host->irq; - DRM_DEV_ERROR(dev->dev, "failed to get irq: %d\n", ret); - return ret; - } - - ret = devm_request_irq(&pdev->dev, msm_host->irq, - dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT, - "dsi_isr", msm_host); - if (ret < 0) { - DRM_DEV_ERROR(&pdev->dev, "failed to request IRQ%u: %d\n", - msm_host->irq, ret); - return ret; - } - msm_host->dev = dev; + ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); if (ret) { pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); @@ -1965,7 +2066,7 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, return 0; } -int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer) +int msm_dsi_host_register(struct mipi_dsi_host *host) { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); int ret; @@ -1979,20 +2080,6 @@ int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer) return ret; msm_host->registered = true; - - /* If the panel driver has not been probed after host register, - * we should defer the host's probe. - * It makes sure panel is connected when fbcon detects - * connector status and gets the proper display mode to - * create framebuffer. - * Don't try to defer if there is nothing connected to the dsi - * output - */ - if (check_defer && msm_host->device_node) { - if (IS_ERR(of_drm_find_panel(msm_host->device_node))) - if (!of_drm_find_bridge(msm_host->device_node)) - return -EPROBE_DEFER; - } } return 0; @@ -2060,7 +2147,7 @@ void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, /* TODO: unvote for bus bandwidth */ cfg_hnd->ops->link_clk_disable(msm_host); - pm_runtime_put_autosuspend(&msm_host->pdev->dev); + pm_runtime_put(&msm_host->pdev->dev); } int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, @@ -2128,9 +2215,12 @@ int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, } ret = dsi_cmds2buf_tx(msm_host, msg); - if (ret < msg->tx_len) { + if (ret < 0) { pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret); return ret; + } else if (ret < msg->tx_len) { + pr_err("%s: Read cmd Tx failed, too short: %d\n", __func__, ret); + return -ECOMM; } /* @@ -2219,55 +2309,12 @@ void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, wmb(); } -int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, +void msm_dsi_host_set_phy_mode(struct mipi_dsi_host *host, struct msm_dsi_phy *src_phy) { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); - struct clk *byte_clk_provider, *pixel_clk_provider; - int ret; - ret = msm_dsi_phy_get_clk_provider(src_phy, - &byte_clk_provider, &pixel_clk_provider); - if (ret) { - pr_info("%s: can't get provider from pll, don't set parent\n", - __func__); - return 0; - } - - ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider); - if (ret) { - pr_err("%s: can't set parent to byte_clk_src. ret=%d\n", - __func__, ret); - goto exit; - } - - ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider); - if (ret) { - pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n", - __func__, ret); - goto exit; - } - - if (msm_host->dsi_clk_src) { - ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider); - if (ret) { - pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n", - __func__, ret); - goto exit; - } - } - - if (msm_host->esc_clk_src) { - ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider); - if (ret) { - pr_err("%s: can't set parent to esc_clk_src. ret=%d\n", - __func__, ret); - goto exit; - } - } - -exit: - return ret; + msm_host->cphy_mode = src_phy->cphy_mode; } void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) @@ -2285,22 +2332,43 @@ void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, struct msm_dsi_phy_clk_request *clk_req, - bool is_dual_dsi) + bool is_bonded_dsi) { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; int ret; - ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_dual_dsi); + ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi); if (ret) { pr_err("%s: unable to calc clk rate, %d\n", __func__, ret); return; } - clk_req->bitclk_rate = msm_host->byte_clk_rate * 8; + /* CPHY transmits 16 bits over 7 clock cycles + * "byte_clk" is in units of 16-bits (see dsi_calc_pclk), + * so multiply by 7 to get the "bitclk rate" + */ + if (msm_host->cphy_mode) + clk_req->bitclk_rate = msm_host->byte_clk_rate * 7; + else + clk_req->bitclk_rate = msm_host->byte_clk_rate * 8; clk_req->escclk_rate = msm_host->esc_clk_rate; } +void msm_dsi_host_enable_irq(struct mipi_dsi_host *host) +{ + struct msm_dsi_host *msm_host = to_msm_dsi_host(host); + + enable_irq(msm_host->irq); +} + +void msm_dsi_host_disable_irq(struct mipi_dsi_host *host) +{ + struct msm_dsi_host *msm_host = to_msm_dsi_host(host); + + disable_irq(msm_host->irq); +} + int msm_dsi_host_enable(struct mipi_dsi_host *host) { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); @@ -2314,7 +2382,7 @@ int msm_dsi_host_enable(struct mipi_dsi_host *host) */ /* if (msm_panel->mode == MSM_DSI_CMD_MODE) { * dsi_link_clk_disable(msm_host); - * pm_runtime_put_autosuspend(&msm_host->pdev->dev); + * pm_runtime_put(&msm_host->pdev->dev); * } */ msm_host->enabled = true; @@ -2354,7 +2422,7 @@ static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable) int msm_dsi_host_power_on(struct mipi_dsi_host *host, struct msm_dsi_phy_shared_timings *phy_shared_timings, - bool is_dual_dsi) + bool is_bonded_dsi, struct msm_dsi_phy *phy) { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; @@ -2366,9 +2434,14 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host, goto unlock_ret; } + msm_host->byte_intf_clk_rate = msm_host->byte_clk_rate; + if (phy_shared_timings->byte_intf_clk_div_2) + msm_host->byte_intf_clk_rate /= 2; + msm_dsi_sfpb_config(msm_host, true); - ret = dsi_host_regulator_enable(msm_host); + ret = regulator_bulk_enable(msm_host->cfg_hnd->cfg->num_regulators, + msm_host->supplies); if (ret) { pr_err("%s:Failed to enable vregs.ret=%d\n", __func__, ret); @@ -2392,12 +2465,9 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host, goto fail_disable_clk; } - dsi_timing_setup(msm_host, is_dual_dsi); + dsi_timing_setup(msm_host, is_bonded_dsi); dsi_sw_reset(msm_host); - dsi_ctrl_config(msm_host, true, phy_shared_timings); - - if (msm_host->disp_en_gpio) - gpiod_set_value(msm_host->disp_en_gpio, 1); + dsi_ctrl_enable(msm_host, phy_shared_timings, phy); msm_host->power_on = true; mutex_unlock(&msm_host->dev_mutex); @@ -2406,9 +2476,10 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host, fail_disable_clk: cfg_hnd->ops->link_clk_disable(msm_host); - pm_runtime_put_autosuspend(&msm_host->pdev->dev); + pm_runtime_put(&msm_host->pdev->dev); fail_disable_reg: - dsi_host_regulator_disable(msm_host); + regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, + msm_host->supplies); unlock_ret: mutex_unlock(&msm_host->dev_mutex); return ret; @@ -2425,17 +2496,15 @@ int msm_dsi_host_power_off(struct mipi_dsi_host *host) goto unlock_ret; } - dsi_ctrl_config(msm_host, false, NULL); - - if (msm_host->disp_en_gpio) - gpiod_set_value(msm_host->disp_en_gpio, 0); + dsi_ctrl_disable(msm_host); pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); cfg_hnd->ops->link_clk_disable(msm_host); - pm_runtime_put_autosuspend(&msm_host->pdev->dev); + pm_runtime_put(&msm_host->pdev->dev); - dsi_host_regulator_disable(msm_host); + regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, + msm_host->supplies); msm_dsi_sfpb_config(msm_host, false); @@ -2467,9 +2536,30 @@ int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, return 0; } -struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host) +enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, + const struct drm_display_mode *mode) { - return of_drm_find_panel(to_msm_dsi_host(host)->device_node); + struct msm_dsi_host *msm_host = to_msm_dsi_host(host); + struct drm_dsc_config *dsc = msm_host->dsc; + int pic_width = mode->hdisplay; + int pic_height = mode->vdisplay; + + if (!msm_host->dsc) + return MODE_OK; + + if (pic_width % dsc->slice_width) { + pr_err("DSI: pic_width %d has to be multiple of slice %d\n", + pic_width, dsc->slice_width); + return MODE_H_ILLEGAL; + } + + if (pic_height % dsc->slice_height) { + pr_err("DSI: pic_height %d has to be multiple of slice %d\n", + pic_height, dsc->slice_height); + return MODE_V_ILLEGAL; + } + + return MODE_OK; } unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host) @@ -2477,13 +2567,6 @@ unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host) return to_msm_dsi_host(host)->mode_flags; } -struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host) -{ - struct msm_dsi_host *msm_host = to_msm_dsi_host(host); - - return of_drm_find_bridge(msm_host->device_node); -} - void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host) { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); @@ -2495,3 +2578,71 @@ void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_ho pm_runtime_put_sync(&msm_host->pdev->dev); } + +static void msm_dsi_host_video_test_pattern_setup(struct msm_dsi_host *msm_host) +{ + u32 reg; + + reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); + + dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff); + /* draw checkered rectangle pattern */ + dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL, + DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN); + /* use 24-bit RGB test pttern */ + dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG, + DSI_TPG_VIDEO_CONFIG_BPP(VIDEO_CONFIG_24BPP) | + DSI_TPG_VIDEO_CONFIG_RGB); + + reg |= DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(VID_MDSS_GENERAL_PATTERN); + dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); + + DBG("Video test pattern setup done\n"); +} + +static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host) +{ + u32 reg; + + reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); + + /* initial value for test pattern */ + dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff); + + reg |= DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(CMD_MDP_MDSS_GENERAL_PATTERN); + + dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); + /* draw checkered rectangle pattern */ + dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2, + DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN); + + DBG("Cmd test pattern setup done\n"); +} + +void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host) +{ + struct msm_dsi_host *msm_host = to_msm_dsi_host(host); + bool is_video_mode = !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO); + u32 reg; + + if (is_video_mode) + msm_dsi_host_video_test_pattern_setup(msm_host); + else + msm_dsi_host_cmd_test_pattern_setup(msm_host); + + reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); + /* enable the test pattern generator */ + dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | DSI_TEST_PATTERN_GEN_CTRL_EN)); + + /* for command mode need to trigger one frame from tpg */ + if (!is_video_mode) + dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER, + DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER); +} + +struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host) +{ + struct msm_dsi_host *msm_host = to_msm_dsi_host(host); + + return msm_host->dsc; +} diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index 4ebfedc4a9ac..ca400924d4ee 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -3,6 +3,8 @@ * Copyright (c) 2015, The Linux Foundation. All rights reserved. */ +#include "drm/drm_bridge_connector.h" + #include "msm_kms.h" #include "dsi.h" @@ -21,14 +23,14 @@ struct msm_dsi_manager { struct msm_dsi *dsi[DSI_MAX]; - bool is_dual_dsi; + bool is_bonded_dsi; bool is_sync_needed; int master_dsi_link_id; }; static struct msm_dsi_manager msm_dsim_glb; -#define IS_DUAL_DSI() (msm_dsim_glb.is_dual_dsi) +#define IS_BONDED_DSI() (msm_dsim_glb.is_bonded_dsi) #define IS_SYNC_NEEDED() (msm_dsim_glb.is_sync_needed) #define IS_MASTER_DSI_LINK(id) (msm_dsim_glb.master_dsi_link_id == id) @@ -42,18 +44,17 @@ static inline struct msm_dsi *dsi_mgr_get_other_dsi(int id) return msm_dsim_glb.dsi[(id + 1) % DSI_MAX]; } -static int dsi_mgr_parse_dual_dsi(struct device_node *np, int id) +static int dsi_mgr_parse_of(struct device_node *np, int id) { struct msm_dsi_manager *msm_dsim = &msm_dsim_glb; - /* We assume 2 dsi nodes have the same information of dual-dsi and - * sync-mode, and only one node specifies master in case of dual mode. + /* We assume 2 dsi nodes have the same information of bonded dsi and + * sync-mode, and only one node specifies master in case of bonded mode. */ - if (!msm_dsim->is_dual_dsi) - msm_dsim->is_dual_dsi = of_property_read_bool( - np, "qcom,dual-dsi-mode"); + if (!msm_dsim->is_bonded_dsi) + msm_dsim->is_bonded_dsi = of_property_read_bool(np, "qcom,dual-dsi-mode"); - if (msm_dsim->is_dual_dsi) { + if (msm_dsim->is_bonded_dsi) { if (of_property_read_bool(np, "qcom,master-dsi")) msm_dsim->master_dsi_link_id = id; if (!msm_dsim->is_sync_needed) @@ -72,20 +73,36 @@ static int dsi_mgr_setup_components(int id) struct msm_dsi *clk_slave_dsi = dsi_mgr_get_dsi(DSI_CLOCK_SLAVE); int ret; - if (!IS_DUAL_DSI()) { - ret = msm_dsi_host_register(msm_dsi->host, true); + if (!IS_BONDED_DSI()) { + /* + * Set the usecase before calling msm_dsi_host_register(), which would + * already program the PLL source mux based on a default usecase. + */ + msm_dsi_phy_set_usecase(msm_dsi->phy, MSM_DSI_PHY_STANDALONE); + msm_dsi_host_set_phy_mode(msm_dsi->host, msm_dsi->phy); + + ret = msm_dsi_host_register(msm_dsi->host); if (ret) return ret; - - msm_dsi_phy_set_usecase(msm_dsi->phy, MSM_DSI_PHY_STANDALONE); - ret = msm_dsi_host_set_src_pll(msm_dsi->host, msm_dsi->phy); - } else if (!other_dsi) { - ret = 0; - } else { + } else if (other_dsi) { struct msm_dsi *master_link_dsi = IS_MASTER_DSI_LINK(id) ? msm_dsi : other_dsi; struct msm_dsi *slave_link_dsi = IS_MASTER_DSI_LINK(id) ? other_dsi : msm_dsi; + + /* + * PLL0 is to drive both DSI link clocks in bonded DSI mode. + * + * Set the usecase before calling msm_dsi_host_register(), which would + * already program the PLL source mux based on a default usecase. + */ + msm_dsi_phy_set_usecase(clk_master_dsi->phy, + MSM_DSI_PHY_MASTER); + msm_dsi_phy_set_usecase(clk_slave_dsi->phy, + MSM_DSI_PHY_SLAVE); + msm_dsi_host_set_phy_mode(msm_dsi->host, msm_dsi->phy); + msm_dsi_host_set_phy_mode(other_dsi->host, other_dsi->phy); + /* Register slave host first, so that slave DSI device * has a chance to probe, and do not block the master * DSI device's probe. @@ -93,40 +110,26 @@ static int dsi_mgr_setup_components(int id) * because only master DSI device adds the panel to global * panel list. The panel's device is the master DSI device. */ - ret = msm_dsi_host_register(slave_link_dsi->host, false); - if (ret) - return ret; - ret = msm_dsi_host_register(master_link_dsi->host, true); + ret = msm_dsi_host_register(slave_link_dsi->host); if (ret) return ret; - - /* PLL0 is to drive both 2 DSI link clocks in Dual DSI mode. */ - msm_dsi_phy_set_usecase(clk_master_dsi->phy, - MSM_DSI_PHY_MASTER); - msm_dsi_phy_set_usecase(clk_slave_dsi->phy, - MSM_DSI_PHY_SLAVE); - ret = msm_dsi_host_set_src_pll(msm_dsi->host, clk_master_dsi->phy); + ret = msm_dsi_host_register(master_link_dsi->host); if (ret) return ret; - ret = msm_dsi_host_set_src_pll(other_dsi->host, clk_master_dsi->phy); } - return ret; + return 0; } static int enable_phy(struct msm_dsi *msm_dsi, struct msm_dsi_phy_shared_timings *shared_timings) { struct msm_dsi_phy_clk_request clk_req; - int ret; - bool is_dual_dsi = IS_DUAL_DSI(); - - msm_dsi_host_get_phy_clk_req(msm_dsi->host, &clk_req, is_dual_dsi); + bool is_bonded_dsi = IS_BONDED_DSI(); - ret = msm_dsi_phy_enable(msm_dsi->phy, &clk_req); - msm_dsi_phy_get_shared_timings(msm_dsi->phy, shared_timings); + msm_dsi_host_get_phy_clk_req(msm_dsi->host, &clk_req, is_bonded_dsi); - return ret; + return msm_dsi_phy_enable(msm_dsi->phy, &clk_req, shared_timings); } static int @@ -138,12 +141,12 @@ dsi_mgr_phy_enable(int id, struct msm_dsi *sdsi = dsi_mgr_get_dsi(DSI_CLOCK_SLAVE); int ret; - /* In case of dual DSI, some registers in PHY1 have been programmed + /* In case of bonded DSI, some registers in PHY1 have been programmed * during PLL0 clock's set_rate. The PHY1 reset called by host1 here * will silently reset those PHY1 registers. Therefore we need to reset * and enable both PHYs before any PLL clock operation. */ - if (IS_DUAL_DSI() && mdsi && sdsi) { + if (IS_BONDED_DSI() && mdsi && sdsi) { if (!mdsi->phy_enabled && !sdsi->phy_enabled) { msm_dsi_host_reset_phy(mdsi->host); msm_dsi_host_reset_phy(sdsi->host); @@ -178,11 +181,11 @@ static void dsi_mgr_phy_disable(int id) struct msm_dsi *sdsi = dsi_mgr_get_dsi(DSI_CLOCK_SLAVE); /* disable DSI phy - * In dual-dsi configuration, the phy should be disabled for the + * In bonded dsi configuration, the phy should be disabled for the * first controller only when the second controller is disabled. */ msm_dsi->phy_enabled = false; - if (IS_DUAL_DSI() && mdsi && sdsi) { + if (IS_BONDED_DSI() && mdsi && sdsi) { if (!mdsi->phy_enabled && !sdsi->phy_enabled) { msm_dsi_phy_disable(sdsi->phy); msm_dsi_phy_disable(mdsi->phy); @@ -192,170 +195,84 @@ static void dsi_mgr_phy_disable(int id) } } -struct dsi_connector { - struct drm_connector base; - int id; -}; - struct dsi_bridge { struct drm_bridge base; int id; }; -#define to_dsi_connector(x) container_of(x, struct dsi_connector, base) #define to_dsi_bridge(x) container_of(x, struct dsi_bridge, base) -static inline int dsi_mgr_connector_get_id(struct drm_connector *connector) -{ - struct dsi_connector *dsi_connector = to_dsi_connector(connector); - return dsi_connector->id; -} - static int dsi_mgr_bridge_get_id(struct drm_bridge *bridge) { struct dsi_bridge *dsi_bridge = to_dsi_bridge(bridge); return dsi_bridge->id; } -static bool dsi_mgr_is_cmd_mode(struct msm_dsi *msm_dsi) -{ - unsigned long host_flags = msm_dsi_host_get_mode_flags(msm_dsi->host); - return !(host_flags & MIPI_DSI_MODE_VIDEO); -} - -void msm_dsi_manager_setup_encoder(int id) +static int dsi_mgr_bridge_power_on(struct drm_bridge *bridge) { + int id = dsi_mgr_bridge_get_id(bridge); struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); - struct msm_drm_private *priv = msm_dsi->dev->dev_private; - struct msm_kms *kms = priv->kms; - struct drm_encoder *encoder = msm_dsi_get_encoder(msm_dsi); + struct msm_dsi *msm_dsi1 = dsi_mgr_get_dsi(DSI_1); + struct mipi_dsi_host *host = msm_dsi->host; + struct msm_dsi_phy_shared_timings phy_shared_timings[DSI_MAX]; + bool is_bonded_dsi = IS_BONDED_DSI(); + int ret; - if (encoder && kms->funcs->set_encoder_mode) - kms->funcs->set_encoder_mode(kms, encoder, - dsi_mgr_is_cmd_mode(msm_dsi)); -} + DBG("id=%d", id); -static int msm_dsi_manager_panel_init(struct drm_connector *conn, u8 id) -{ - struct msm_drm_private *priv = conn->dev->dev_private; - struct msm_kms *kms = priv->kms; - struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); - struct msm_dsi *other_dsi = dsi_mgr_get_other_dsi(id); - struct msm_dsi *master_dsi, *slave_dsi; - struct drm_panel *panel; + ret = dsi_mgr_phy_enable(id, phy_shared_timings); + if (ret) + goto phy_en_fail; - if (IS_DUAL_DSI() && !IS_MASTER_DSI_LINK(id)) { - master_dsi = other_dsi; - slave_dsi = msm_dsi; - } else { - master_dsi = msm_dsi; - slave_dsi = other_dsi; + ret = msm_dsi_host_power_on(host, &phy_shared_timings[id], is_bonded_dsi, msm_dsi->phy); + if (ret) { + pr_err("%s: power on host %d failed, %d\n", __func__, id, ret); + goto host_on_fail; } - /* - * There is only 1 panel in the global panel list for dual DSI mode. - * Therefore slave dsi should get the drm_panel instance from master - * dsi. - */ - panel = msm_dsi_host_get_panel(master_dsi->host); - if (IS_ERR(panel)) { - DRM_ERROR("Could not find panel for %u (%ld)\n", msm_dsi->id, - PTR_ERR(panel)); - return PTR_ERR(panel); + if (is_bonded_dsi && msm_dsi1) { + ret = msm_dsi_host_power_on(msm_dsi1->host, + &phy_shared_timings[DSI_1], is_bonded_dsi, msm_dsi1->phy); + if (ret) { + pr_err("%s: power on host1 failed, %d\n", + __func__, ret); + goto host1_on_fail; + } } - if (!panel || !IS_DUAL_DSI()) - goto out; - - drm_object_attach_property(&conn->base, - conn->dev->mode_config.tile_property, 0); - /* - * Set split display info to kms once dual DSI panel is connected to - * both hosts. + * Enable before preparing the panel, disable after unpreparing, so + * that the panel can communicate over the DSI link. */ - if (other_dsi && other_dsi->panel && kms->funcs->set_split_display) { - kms->funcs->set_split_display(kms, master_dsi->encoder, - slave_dsi->encoder, - dsi_mgr_is_cmd_mode(msm_dsi)); - } + msm_dsi_host_enable_irq(host); + if (is_bonded_dsi && msm_dsi1) + msm_dsi_host_enable_irq(msm_dsi1->host); -out: - msm_dsi->panel = panel; return 0; -} - -static enum drm_connector_status dsi_mgr_connector_detect( - struct drm_connector *connector, bool force) -{ - int id = dsi_mgr_connector_get_id(connector); - struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); - - return msm_dsi->panel ? connector_status_connected : - connector_status_disconnected; -} - -static void dsi_mgr_connector_destroy(struct drm_connector *connector) -{ - struct dsi_connector *dsi_connector = to_dsi_connector(connector); - - DBG(""); - - drm_connector_cleanup(connector); - - kfree(dsi_connector); -} - -static int dsi_mgr_connector_get_modes(struct drm_connector *connector) -{ - int id = dsi_mgr_connector_get_id(connector); - struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); - struct drm_panel *panel = msm_dsi->panel; - int num; - - if (!panel) - return 0; - - /* - * In dual DSI mode, we have one connector that can be - * attached to the drm_panel. - */ - num = drm_panel_get_modes(panel, connector); - if (!num) - return 0; - - return num; -} - -static enum drm_mode_status dsi_mgr_connector_mode_valid(struct drm_connector *connector, - struct drm_display_mode *mode) -{ - int id = dsi_mgr_connector_get_id(connector); - struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); - struct drm_encoder *encoder = msm_dsi_get_encoder(msm_dsi); - struct msm_drm_private *priv = connector->dev->dev_private; - struct msm_kms *kms = priv->kms; - long actual, requested; - - DBG(""); - requested = 1000 * mode->clock; - actual = kms->funcs->round_pixclk(kms, requested, encoder); - DBG("requested=%ld, actual=%ld", requested, actual); - if (actual != requested) - return MODE_CLOCK_RANGE; - - return MODE_OK; +host1_on_fail: + msm_dsi_host_power_off(host); +host_on_fail: + dsi_mgr_phy_disable(id); +phy_en_fail: + return ret; } -static struct drm_encoder * -dsi_mgr_connector_best_encoder(struct drm_connector *connector) +static void dsi_mgr_bridge_power_off(struct drm_bridge *bridge) { - int id = dsi_mgr_connector_get_id(connector); + int id = dsi_mgr_bridge_get_id(bridge); struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); + struct msm_dsi *msm_dsi1 = dsi_mgr_get_dsi(DSI_1); + struct mipi_dsi_host *host = msm_dsi->host; + bool is_bonded_dsi = IS_BONDED_DSI(); - DBG(""); - return msm_dsi_get_encoder(msm_dsi); + msm_dsi_host_disable_irq(host); + if (is_bonded_dsi && msm_dsi1) { + msm_dsi_host_disable_irq(msm_dsi1->host); + msm_dsi_host_power_off(msm_dsi1->host); + } + msm_dsi_host_power_off(host); + dsi_mgr_phy_disable(id); } static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge) @@ -364,49 +281,19 @@ static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge) struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); struct msm_dsi *msm_dsi1 = dsi_mgr_get_dsi(DSI_1); struct mipi_dsi_host *host = msm_dsi->host; - struct drm_panel *panel = msm_dsi->panel; - struct msm_dsi_phy_shared_timings phy_shared_timings[DSI_MAX]; - bool is_dual_dsi = IS_DUAL_DSI(); + bool is_bonded_dsi = IS_BONDED_DSI(); int ret; DBG("id=%d", id); - if (!msm_dsi_device_connected(msm_dsi)) - return; - /* Do nothing with the host if it is slave-DSI in case of dual DSI */ - if (is_dual_dsi && !IS_MASTER_DSI_LINK(id)) + /* Do nothing with the host if it is slave-DSI in case of bonded DSI */ + if (is_bonded_dsi && !IS_MASTER_DSI_LINK(id)) return; - ret = dsi_mgr_phy_enable(id, phy_shared_timings); - if (ret) - goto phy_en_fail; - - ret = msm_dsi_host_power_on(host, &phy_shared_timings[id], is_dual_dsi); + ret = dsi_mgr_bridge_power_on(bridge); if (ret) { - pr_err("%s: power on host %d failed, %d\n", __func__, id, ret); - goto host_on_fail; - } - - if (is_dual_dsi && msm_dsi1) { - ret = msm_dsi_host_power_on(msm_dsi1->host, - &phy_shared_timings[DSI_1], is_dual_dsi); - if (ret) { - pr_err("%s: power on host1 failed, %d\n", - __func__, ret); - goto host1_on_fail; - } - } - - /* Always call panel functions once, because even for dual panels, - * there is only one drm_panel instance. - */ - if (panel) { - ret = drm_panel_prepare(panel); - if (ret) { - pr_err("%s: prepare panel %d failed, %d\n", __func__, - id, ret); - goto panel_prep_fail; - } + dev_err(&msm_dsi->pdev->dev, "Power on failed: %d\n", ret); + return; } ret = msm_dsi_host_enable(host); @@ -415,7 +302,7 @@ static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge) goto host_en_fail; } - if (is_dual_dsi && msm_dsi1) { + if (is_bonded_dsi && msm_dsi1) { ret = msm_dsi_host_enable(msm_dsi1->host); if (ret) { pr_err("%s: enable host1 failed, %d\n", __func__, ret); @@ -428,65 +315,19 @@ static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge) host1_en_fail: msm_dsi_host_disable(host); host_en_fail: - if (panel) - drm_panel_unprepare(panel); -panel_prep_fail: - if (is_dual_dsi && msm_dsi1) - msm_dsi_host_power_off(msm_dsi1->host); -host1_on_fail: - msm_dsi_host_power_off(host); -host_on_fail: - dsi_mgr_phy_disable(id); -phy_en_fail: - return; -} - -static void dsi_mgr_bridge_enable(struct drm_bridge *bridge) -{ - int id = dsi_mgr_bridge_get_id(bridge); - struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); - struct drm_panel *panel = msm_dsi->panel; - bool is_dual_dsi = IS_DUAL_DSI(); - int ret; - - DBG("id=%d", id); - if (!msm_dsi_device_connected(msm_dsi)) - return; - - /* Do nothing with the host if it is slave-DSI in case of dual DSI */ - if (is_dual_dsi && !IS_MASTER_DSI_LINK(id)) - return; - - if (panel) { - ret = drm_panel_enable(panel); - if (ret) { - pr_err("%s: enable panel %d failed, %d\n", __func__, id, - ret); - } - } + dsi_mgr_bridge_power_off(bridge); } -static void dsi_mgr_bridge_disable(struct drm_bridge *bridge) +void msm_dsi_manager_tpg_enable(void) { - int id = dsi_mgr_bridge_get_id(bridge); - struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); - struct drm_panel *panel = msm_dsi->panel; - bool is_dual_dsi = IS_DUAL_DSI(); - int ret; - - DBG("id=%d", id); - if (!msm_dsi_device_connected(msm_dsi)) - return; - - /* Do nothing with the host if it is slave-DSI in case of dual DSI */ - if (is_dual_dsi && !IS_MASTER_DSI_LINK(id)) - return; - - if (panel) { - ret = drm_panel_disable(panel); - if (ret) - pr_err("%s: Panel %d OFF failed, %d\n", __func__, id, - ret); + struct msm_dsi *m_dsi = dsi_mgr_get_dsi(DSI_0); + struct msm_dsi *s_dsi = dsi_mgr_get_dsi(DSI_1); + + /* if dual dsi, trigger tpg on master first then slave */ + if (m_dsi) { + msm_dsi_host_test_pattern_en(m_dsi->host); + if (IS_BONDED_DSI() && s_dsi) + msm_dsi_host_test_pattern_en(s_dsi->host); } } @@ -496,39 +337,32 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge *bridge) struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); struct msm_dsi *msm_dsi1 = dsi_mgr_get_dsi(DSI_1); struct mipi_dsi_host *host = msm_dsi->host; - struct drm_panel *panel = msm_dsi->panel; - bool is_dual_dsi = IS_DUAL_DSI(); + bool is_bonded_dsi = IS_BONDED_DSI(); int ret; DBG("id=%d", id); - if (!msm_dsi_device_connected(msm_dsi)) - return; - /* - * Do nothing with the host if it is slave-DSI in case of dual DSI. + * Do nothing with the host if it is slave-DSI in case of bonded DSI. * It is safe to call dsi_mgr_phy_disable() here because a single PHY * won't be diabled until both PHYs request disable. */ - if (is_dual_dsi && !IS_MASTER_DSI_LINK(id)) + if (is_bonded_dsi && !IS_MASTER_DSI_LINK(id)) goto disable_phy; ret = msm_dsi_host_disable(host); if (ret) pr_err("%s: host %d disable failed, %d\n", __func__, id, ret); - if (is_dual_dsi && msm_dsi1) { + if (is_bonded_dsi && msm_dsi1) { ret = msm_dsi_host_disable(msm_dsi1->host); if (ret) pr_err("%s: host1 disable failed, %d\n", __func__, ret); } - if (panel) { - ret = drm_panel_unprepare(panel); - if (ret) - pr_err("%s: Panel %d unprepare failed,%d\n", __func__, - id, ret); - } + msm_dsi_host_disable_irq(host); + if (is_bonded_dsi && msm_dsi1) + msm_dsi_host_disable_irq(msm_dsi1->host); /* Save PHY status if it is a clock source */ msm_dsi_phy_pll_save_state(msm_dsi->phy); @@ -537,7 +371,7 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge *bridge) if (ret) pr_err("%s: host %d power off failed,%d\n", __func__, id, ret); - if (is_dual_dsi && msm_dsi1) { + if (is_bonded_dsi && msm_dsi1) { ret = msm_dsi_host_power_off(msm_dsi1->host); if (ret) pr_err("%s: host1 power off failed, %d\n", @@ -556,176 +390,106 @@ static void dsi_mgr_bridge_mode_set(struct drm_bridge *bridge, struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); struct msm_dsi *other_dsi = dsi_mgr_get_other_dsi(id); struct mipi_dsi_host *host = msm_dsi->host; - bool is_dual_dsi = IS_DUAL_DSI(); + bool is_bonded_dsi = IS_BONDED_DSI(); DBG("set mode: " DRM_MODE_FMT, DRM_MODE_ARG(mode)); - if (is_dual_dsi && !IS_MASTER_DSI_LINK(id)) + if (is_bonded_dsi && !IS_MASTER_DSI_LINK(id)) return; msm_dsi_host_set_display_mode(host, adjusted_mode); - if (is_dual_dsi && other_dsi) + if (is_bonded_dsi && other_dsi) msm_dsi_host_set_display_mode(other_dsi->host, adjusted_mode); } -static const struct drm_connector_funcs dsi_mgr_connector_funcs = { - .detect = dsi_mgr_connector_detect, - .fill_modes = drm_helper_probe_single_connector_modes, - .destroy = dsi_mgr_connector_destroy, - .reset = drm_atomic_helper_connector_reset, - .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, -}; - -static const struct drm_connector_helper_funcs dsi_mgr_conn_helper_funcs = { - .get_modes = dsi_mgr_connector_get_modes, - .mode_valid = dsi_mgr_connector_mode_valid, - .best_encoder = dsi_mgr_connector_best_encoder, -}; - -static const struct drm_bridge_funcs dsi_mgr_bridge_funcs = { - .pre_enable = dsi_mgr_bridge_pre_enable, - .enable = dsi_mgr_bridge_enable, - .disable = dsi_mgr_bridge_disable, - .post_disable = dsi_mgr_bridge_post_disable, - .mode_set = dsi_mgr_bridge_mode_set, -}; - -/* initialize connector when we're connected to a drm_panel */ -struct drm_connector *msm_dsi_manager_connector_init(u8 id) +static enum drm_mode_status dsi_mgr_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) { + int id = dsi_mgr_bridge_get_id(bridge); struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); - struct drm_connector *connector = NULL; - struct dsi_connector *dsi_connector; - int ret; - - dsi_connector = kzalloc(sizeof(*dsi_connector), GFP_KERNEL); - if (!dsi_connector) - return ERR_PTR(-ENOMEM); - - dsi_connector->id = id; - - connector = &dsi_connector->base; - - ret = drm_connector_init(msm_dsi->dev, connector, - &dsi_mgr_connector_funcs, DRM_MODE_CONNECTOR_DSI); - if (ret) - return ERR_PTR(ret); - - drm_connector_helper_add(connector, &dsi_mgr_conn_helper_funcs); - - /* Enable HPD to let hpd event is handled - * when panel is attached to the host. - */ - connector->polled = DRM_CONNECTOR_POLL_HPD; - - /* Display driver doesn't support interlace now. */ - connector->interlace_allowed = 0; - connector->doublescan_allowed = 0; - - drm_connector_attach_encoder(connector, msm_dsi->encoder); - - ret = msm_dsi_manager_panel_init(connector, id); - if (ret) { - DRM_DEV_ERROR(msm_dsi->dev->dev, "init panel failed %d\n", ret); - goto fail; + struct mipi_dsi_host *host = msm_dsi->host; + struct platform_device *pdev = msm_dsi->pdev; + struct dev_pm_opp *opp; + unsigned long byte_clk_rate; + + byte_clk_rate = dsi_byte_clk_get_rate(host, IS_BONDED_DSI(), mode); + + opp = dev_pm_opp_find_freq_ceil(&pdev->dev, &byte_clk_rate); + if (!IS_ERR(opp)) { + dev_pm_opp_put(opp); + } else if (PTR_ERR(opp) == -ERANGE) { + /* + * An empty table is created by devm_pm_opp_set_clkname() even + * if there is none. Thus find_freq_ceil will still return + * -ERANGE in such case. + */ + if (dev_pm_opp_get_opp_count(&pdev->dev) != 0) + return MODE_CLOCK_RANGE; + } else { + return MODE_ERROR; } - return connector; - -fail: - connector->funcs->destroy(msm_dsi->connector); - return ERR_PTR(ret); + return msm_dsi_host_check_dsc(host, mode); } -bool msm_dsi_manager_validate_current_config(u8 id) +static int dsi_mgr_bridge_attach(struct drm_bridge *bridge, + struct drm_encoder *encoder, + enum drm_bridge_attach_flags flags) { - bool is_dual_dsi = IS_DUAL_DSI(); + int id = dsi_mgr_bridge_get_id(bridge); + struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); - /* - * For dual DSI, we only have one drm panel. For this - * use case, we register only one bridge/connector. - * Skip bridge/connector initialisation if it is - * slave-DSI for dual DSI configuration. - */ - if (is_dual_dsi && !IS_MASTER_DSI_LINK(id)) { - DBG("Skip bridge registration for slave DSI->id: %d\n", id); - return false; - } - return true; + return drm_bridge_attach(encoder, msm_dsi->next_bridge, + bridge, flags); } +static const struct drm_bridge_funcs dsi_mgr_bridge_funcs = { + .attach = dsi_mgr_bridge_attach, + .pre_enable = dsi_mgr_bridge_pre_enable, + .post_disable = dsi_mgr_bridge_post_disable, + .mode_set = dsi_mgr_bridge_mode_set, + .mode_valid = dsi_mgr_bridge_mode_valid, +}; + /* initialize bridge */ -struct drm_bridge *msm_dsi_manager_bridge_init(u8 id) +int msm_dsi_manager_connector_init(struct msm_dsi *msm_dsi, + struct drm_encoder *encoder) { - struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); - struct drm_bridge *bridge = NULL; + struct drm_device *dev = msm_dsi->dev; + struct drm_bridge *bridge; struct dsi_bridge *dsi_bridge; - struct drm_encoder *encoder; + struct drm_connector *connector; int ret; - dsi_bridge = devm_kzalloc(msm_dsi->dev->dev, - sizeof(*dsi_bridge), GFP_KERNEL); - if (!dsi_bridge) { - ret = -ENOMEM; - goto fail; - } + dsi_bridge = devm_drm_bridge_alloc(msm_dsi->dev->dev, struct dsi_bridge, base, + &dsi_mgr_bridge_funcs); + if (IS_ERR(dsi_bridge)) + return PTR_ERR(dsi_bridge); - dsi_bridge->id = id; - - encoder = msm_dsi->encoder; + dsi_bridge->id = msm_dsi->id; bridge = &dsi_bridge->base; - bridge->funcs = &dsi_mgr_bridge_funcs; - ret = drm_bridge_attach(encoder, bridge, NULL, 0); + ret = devm_drm_bridge_add(msm_dsi->dev->dev, bridge); if (ret) - goto fail; - - return bridge; - -fail: - if (bridge) - msm_dsi_manager_bridge_destroy(bridge); - - return ERR_PTR(ret); -} - -struct drm_connector *msm_dsi_manager_ext_bridge_init(u8 id) -{ - struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); - struct drm_device *dev = msm_dsi->dev; - struct drm_encoder *encoder; - struct drm_bridge *int_bridge, *ext_bridge; - struct drm_connector *connector; - struct list_head *connector_list; - - int_bridge = msm_dsi->bridge; - ext_bridge = msm_dsi->external_bridge = - msm_dsi_host_get_bridge(msm_dsi->host); - - encoder = msm_dsi->encoder; - - /* link the internal dsi bridge to the external bridge */ - drm_bridge_attach(encoder, ext_bridge, int_bridge, 0); + return ret; - /* - * we need the drm_connector created by the external bridge - * driver (or someone else) to feed it to our driver's - * priv->connector[] list, mainly for msm_fbdev_init() - */ - connector_list = &dev->mode_config.connector_list; + ret = drm_bridge_attach(encoder, bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR); + if (ret) + return ret; - list_for_each_entry(connector, connector_list, head) { - if (drm_connector_has_possible_encoder(connector, encoder)) - return connector; + connector = drm_bridge_connector_init(dev, encoder); + if (IS_ERR(connector)) { + DRM_ERROR("Unable to create bridge connector\n"); + return PTR_ERR(connector); } - return ERR_PTR(-ENODEV); -} + ret = drm_connector_attach_encoder(connector, encoder); + if (ret < 0) + return ret; -void msm_dsi_manager_bridge_destroy(struct drm_bridge *bridge) -{ + return 0; } int msm_dsi_manager_cmd_xfer(int id, const struct mipi_dsi_msg *msg) @@ -740,7 +504,7 @@ int msm_dsi_manager_cmd_xfer(int id, const struct mipi_dsi_msg *msg) if (!msg->tx_buf || !msg->tx_len) return 0; - /* In dual master case, panel requires the same commands sent to + /* In bonded master case, panel requires the same commands sent to * both DSI links. Host issues the command trigger to both links * when DSI_1 calls the cmd transfer function, no matter it happens * before or after DSI_0 cmd transfer. @@ -809,9 +573,9 @@ int msm_dsi_manager_register(struct msm_dsi *msm_dsi) msm_dsim->dsi[id] = msm_dsi; - ret = dsi_mgr_parse_dual_dsi(msm_dsi->pdev->dev.of_node, id); + ret = dsi_mgr_parse_of(msm_dsi->pdev->dev.of_node, id); if (ret) { - pr_err("%s: failed to parse dual DSI info\n", __func__); + pr_err("%s: failed to parse OF DSI info\n", __func__); goto fail; } @@ -840,3 +604,17 @@ void msm_dsi_manager_unregister(struct msm_dsi *msm_dsi) msm_dsim->dsi[msm_dsi->id] = NULL; } +bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi) +{ + return IS_BONDED_DSI(); +} + +bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi) +{ + return IS_MASTER_DSI_LINK(msm_dsi->id); +} + +const char *msm_dsi_get_te_source(struct msm_dsi *msm_dsi) +{ + return msm_dsi->te_source; +} diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h b/drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h deleted file mode 100644 index 8872d77027dd..000000000000 --- a/drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h +++ /dev/null @@ -1,228 +0,0 @@ -#ifndef DSI_PHY_10NM_XML -#define DSI_PHY_10NM_XML - -/* Autogenerated file, DO NOT EDIT manually! - -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git - -The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) - -Copyright (C) 2013-2021 by the following authors: -- Rob Clark <robdclark@gmail.com> (robclark) -- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - - -#define REG_DSI_10nm_PHY_CMN_REVISION_ID0 0x00000000 - -#define REG_DSI_10nm_PHY_CMN_REVISION_ID1 0x00000004 - -#define REG_DSI_10nm_PHY_CMN_REVISION_ID2 0x00000008 - -#define REG_DSI_10nm_PHY_CMN_REVISION_ID3 0x0000000c - -#define REG_DSI_10nm_PHY_CMN_CLK_CFG0 0x00000010 - -#define REG_DSI_10nm_PHY_CMN_CLK_CFG1 0x00000014 - -#define REG_DSI_10nm_PHY_CMN_GLBL_CTRL 0x00000018 - -#define REG_DSI_10nm_PHY_CMN_RBUF_CTRL 0x0000001c - -#define REG_DSI_10nm_PHY_CMN_VREG_CTRL 0x00000020 - -#define REG_DSI_10nm_PHY_CMN_CTRL_0 0x00000024 - -#define REG_DSI_10nm_PHY_CMN_CTRL_1 0x00000028 - -#define REG_DSI_10nm_PHY_CMN_CTRL_2 0x0000002c - -#define REG_DSI_10nm_PHY_CMN_LANE_CFG0 0x00000030 - -#define REG_DSI_10nm_PHY_CMN_LANE_CFG1 0x00000034 - -#define REG_DSI_10nm_PHY_CMN_PLL_CNTRL 0x00000038 - -#define REG_DSI_10nm_PHY_CMN_LANE_CTRL0 0x00000098 - -#define REG_DSI_10nm_PHY_CMN_LANE_CTRL1 0x0000009c - -#define REG_DSI_10nm_PHY_CMN_LANE_CTRL2 0x000000a0 - -#define REG_DSI_10nm_PHY_CMN_LANE_CTRL3 0x000000a4 - -#define REG_DSI_10nm_PHY_CMN_LANE_CTRL4 0x000000a8 - -#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0 0x000000ac - -#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1 0x000000b0 - -#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2 0x000000b4 - -#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3 0x000000b8 - -#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4 0x000000bc - -#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5 0x000000c0 - -#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6 0x000000c4 - -#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7 0x000000c8 - -#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8 0x000000cc - -#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9 0x000000d0 - -#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10 0x000000d4 - -#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11 0x000000d8 - -#define REG_DSI_10nm_PHY_CMN_PHY_STATUS 0x000000ec - -#define REG_DSI_10nm_PHY_CMN_LANE_STATUS0 0x000000f4 - -#define REG_DSI_10nm_PHY_CMN_LANE_STATUS1 0x000000f8 - -static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } - -static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } - -static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } - -static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } - -static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } - -static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; } - -static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; } - -static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; } - -static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; } - -static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; } - -static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0; } - -static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; } - -static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; } - -#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000 - -#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004 - -#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010 - -#define REG_DSI_10nm_PHY_PLL_DSM_DIVIDER 0x0000001c - -#define REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000020 - -#define REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES 0x00000024 - -#define REG_DSI_10nm_PHY_PLL_CMODE 0x0000002c - -#define REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000030 - -#define REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000054 - -#define REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000064 - -#define REG_DSI_10nm_PHY_PLL_PFILT 0x0000007c - -#define REG_DSI_10nm_PHY_PLL_IFILT 0x00000080 - -#define REG_DSI_10nm_PHY_PLL_OUTDIV 0x00000094 - -#define REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE 0x000000a4 - -#define REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000a8 - -#define REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000b4 - -#define REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000cc - -#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000d0 - -#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000d4 - -#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000d8 - -#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x0000010c - -#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000110 - -#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000114 - -#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x00000118 - -#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1 0x0000011c - -#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1 0x00000120 - -#define REG_DSI_10nm_PHY_PLL_SSC_CONTROL 0x0000013c - -#define REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000140 - -#define REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000144 - -#define REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x0000014c - -#define REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1 0x00000154 - -#define REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x0000015c - -#define REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000164 - -#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000180 - -#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY 0x00000184 - -#define REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS 0x0000018c - -#define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE 0x000001a0 - - -#endif /* DSI_PHY_10NM_XML */ diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h b/drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h deleted file mode 100644 index 0d9a5ccfb808..000000000000 --- a/drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h +++ /dev/null @@ -1,310 +0,0 @@ -#ifndef DSI_PHY_14NM_XML -#define DSI_PHY_14NM_XML - -/* Autogenerated file, DO NOT EDIT manually! - -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git - -The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) - -Copyright (C) 2013-2021 by the following authors: -- Rob Clark <robdclark@gmail.com> (robclark) -- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - - -#define REG_DSI_14nm_PHY_CMN_REVISION_ID0 0x00000000 - -#define REG_DSI_14nm_PHY_CMN_REVISION_ID1 0x00000004 - -#define REG_DSI_14nm_PHY_CMN_REVISION_ID2 0x00000008 - -#define REG_DSI_14nm_PHY_CMN_REVISION_ID3 0x0000000c - -#define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010 -#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK 0x000000f0 -#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT 4 -static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK; -} -#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK 0x000000f0 -#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT 4 -static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK; -} - -#define REG_DSI_14nm_PHY_CMN_CLK_CFG1 0x00000014 -#define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL 0x00000001 - -#define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL 0x00000018 -#define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000004 - -#define REG_DSI_14nm_PHY_CMN_CTRL_0 0x0000001c - -#define REG_DSI_14nm_PHY_CMN_CTRL_1 0x00000020 - -#define REG_DSI_14nm_PHY_CMN_HW_TRIGGER 0x00000024 - -#define REG_DSI_14nm_PHY_CMN_SW_CFG0 0x00000028 - -#define REG_DSI_14nm_PHY_CMN_SW_CFG1 0x0000002c - -#define REG_DSI_14nm_PHY_CMN_SW_CFG2 0x00000030 - -#define REG_DSI_14nm_PHY_CMN_HW_CFG0 0x00000034 - -#define REG_DSI_14nm_PHY_CMN_HW_CFG1 0x00000038 - -#define REG_DSI_14nm_PHY_CMN_HW_CFG2 0x0000003c - -#define REG_DSI_14nm_PHY_CMN_HW_CFG3 0x00000040 - -#define REG_DSI_14nm_PHY_CMN_HW_CFG4 0x00000044 - -#define REG_DSI_14nm_PHY_CMN_PLL_CNTRL 0x00000048 -#define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START 0x00000001 - -#define REG_DSI_14nm_PHY_CMN_LDO_CNTRL 0x0000004c -#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK 0x0000003f -#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT 0 -static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT) & DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK; -} - -static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } - -static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } -#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK 0x000000c0 -#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT 6 -static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT) & DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK; -} - -static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } -#define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN 0x00000001 - -static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } - -static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } - -static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; } - -static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; } - -static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0; } -#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff -#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT 0 -static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK; -} - -static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0; } -#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff -#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT 0 -static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK; -} - -static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0; } -#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff -#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 -static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK; -} - -static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0; } -#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff -#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 -static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK; -} - -static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0; } -#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff -#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT 0 -static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK; -} - -static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0; } -#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK 0x00000007 -#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT 0 -static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK; -} -#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 -#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT 4 -static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK; -} - -static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i0; } -#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK 0x00000007 -#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT 0 -static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK; -} - -static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i0; } -#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff -#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 -static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK; -} - -static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*i0; } - -static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*i0; } - -static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; } - -#define REG_DSI_14nm_PHY_PLL_IE_TRIM 0x00000000 - -#define REG_DSI_14nm_PHY_PLL_IP_TRIM 0x00000004 - -#define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM 0x00000010 - -#define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN 0x0000001c - -#define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET 0x00000028 - -#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL 0x0000002c - -#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2 0x00000030 - -#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3 0x00000034 - -#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4 0x00000038 - -#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5 0x0000003c - -#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1 0x00000040 - -#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2 0x00000044 - -#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1 0x00000048 - -#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2 0x0000004c - -#define REG_DSI_14nm_PHY_PLL_VREF_CFG1 0x0000005c - -#define REG_DSI_14nm_PHY_PLL_KVCO_CODE 0x00000058 - -#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1 0x0000006c - -#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2 0x00000070 - -#define REG_DSI_14nm_PHY_PLL_VCO_COUNT1 0x00000074 - -#define REG_DSI_14nm_PHY_PLL_VCO_COUNT2 0x00000078 - -#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1 0x0000007c - -#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2 0x00000080 - -#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3 0x00000084 - -#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN 0x00000088 - -#define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE 0x0000008c - -#define REG_DSI_14nm_PHY_PLL_DEC_START 0x00000090 - -#define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER 0x00000094 - -#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1 0x00000098 - -#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2 0x0000009c - -#define REG_DSI_14nm_PHY_PLL_SSC_PER1 0x000000a0 - -#define REG_DSI_14nm_PHY_PLL_SSC_PER2 0x000000a4 - -#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1 0x000000a8 - -#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2 0x000000ac - -#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1 0x000000b4 - -#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2 0x000000b8 - -#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3 0x000000bc - -#define REG_DSI_14nm_PHY_PLL_TXCLK_EN 0x000000c0 - -#define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL 0x000000c4 - -#define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS 0x000000cc - -#define REG_DSI_14nm_PHY_PLL_PLL_MISC1 0x000000e8 - -#define REG_DSI_14nm_PHY_PLL_CP_SET_CUR 0x000000f0 - -#define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET 0x000000f4 - -#define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET 0x000000f8 - -#define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET 0x000000fc - -#define REG_DSI_14nm_PHY_PLL_PLL_LPF1 0x00000100 - -#define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV 0x00000104 - -#define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP 0x00000108 - - -#endif /* DSI_PHY_14NM_XML */ diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h b/drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h deleted file mode 100644 index 15c7a5852c7a..000000000000 --- a/drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h +++ /dev/null @@ -1,238 +0,0 @@ -#ifndef DSI_PHY_20NM_XML -#define DSI_PHY_20NM_XML - -/* Autogenerated file, DO NOT EDIT manually! - -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git - -The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) - -Copyright (C) 2013-2021 by the following authors: -- Rob Clark <robdclark@gmail.com> (robclark) -- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - - -static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } - -static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } - -static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } - -static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } - -static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } - -static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } - -static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; } - -static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } - -static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } - -static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } - -#define REG_DSI_20nm_PHY_LNCK_CFG_0 0x00000100 - -#define REG_DSI_20nm_PHY_LNCK_CFG_1 0x00000104 - -#define REG_DSI_20nm_PHY_LNCK_CFG_2 0x00000108 - -#define REG_DSI_20nm_PHY_LNCK_CFG_3 0x0000010c - -#define REG_DSI_20nm_PHY_LNCK_CFG_4 0x00000110 - -#define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH 0x00000114 - -#define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL 0x00000118 - -#define REG_DSI_20nm_PHY_LNCK_TEST_STR0 0x0000011c - -#define REG_DSI_20nm_PHY_LNCK_TEST_STR1 0x00000120 - -#define REG_DSI_20nm_PHY_TIMING_CTRL_0 0x00000140 -#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff -#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 -static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) -{ - return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; -} - -#define REG_DSI_20nm_PHY_TIMING_CTRL_1 0x00000144 -#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff -#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 -static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) -{ - return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; -} - -#define REG_DSI_20nm_PHY_TIMING_CTRL_2 0x00000148 -#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff -#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 -static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) -{ - return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; -} - -#define REG_DSI_20nm_PHY_TIMING_CTRL_3 0x0000014c -#define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001 - -#define REG_DSI_20nm_PHY_TIMING_CTRL_4 0x00000150 -#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff -#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 -static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) -{ - return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK; -} - -#define REG_DSI_20nm_PHY_TIMING_CTRL_5 0x00000154 -#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff -#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 -static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) -{ - return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK; -} - -#define REG_DSI_20nm_PHY_TIMING_CTRL_6 0x00000158 -#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff -#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 -static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) -{ - return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; -} - -#define REG_DSI_20nm_PHY_TIMING_CTRL_7 0x0000015c -#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff -#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 -static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) -{ - return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; -} - -#define REG_DSI_20nm_PHY_TIMING_CTRL_8 0x00000160 -#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff -#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 -static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) -{ - return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK; -} - -#define REG_DSI_20nm_PHY_TIMING_CTRL_9 0x00000164 -#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 -#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 -static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) -{ - return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK; -} -#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 -#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 -static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) -{ - return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK; -} - -#define REG_DSI_20nm_PHY_TIMING_CTRL_10 0x00000168 -#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 -#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 -static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) -{ - return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK; -} - -#define REG_DSI_20nm_PHY_TIMING_CTRL_11 0x0000016c -#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff -#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 -static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) -{ - return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; -} - -#define REG_DSI_20nm_PHY_CTRL_0 0x00000170 - -#define REG_DSI_20nm_PHY_CTRL_1 0x00000174 - -#define REG_DSI_20nm_PHY_CTRL_2 0x00000178 - -#define REG_DSI_20nm_PHY_CTRL_3 0x0000017c - -#define REG_DSI_20nm_PHY_CTRL_4 0x00000180 - -#define REG_DSI_20nm_PHY_STRENGTH_0 0x00000184 - -#define REG_DSI_20nm_PHY_STRENGTH_1 0x00000188 - -#define REG_DSI_20nm_PHY_BIST_CTRL_0 0x000001b4 - -#define REG_DSI_20nm_PHY_BIST_CTRL_1 0x000001b8 - -#define REG_DSI_20nm_PHY_BIST_CTRL_2 0x000001bc - -#define REG_DSI_20nm_PHY_BIST_CTRL_3 0x000001c0 - -#define REG_DSI_20nm_PHY_BIST_CTRL_4 0x000001c4 - -#define REG_DSI_20nm_PHY_BIST_CTRL_5 0x000001c8 - -#define REG_DSI_20nm_PHY_GLBL_TEST_CTRL 0x000001d4 -#define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001 - -#define REG_DSI_20nm_PHY_LDO_CNTRL 0x000001dc - -#define REG_DSI_20nm_PHY_REGULATOR_CTRL_0 0x00000000 - -#define REG_DSI_20nm_PHY_REGULATOR_CTRL_1 0x00000004 - -#define REG_DSI_20nm_PHY_REGULATOR_CTRL_2 0x00000008 - -#define REG_DSI_20nm_PHY_REGULATOR_CTRL_3 0x0000000c - -#define REG_DSI_20nm_PHY_REGULATOR_CTRL_4 0x00000010 - -#define REG_DSI_20nm_PHY_REGULATOR_CTRL_5 0x00000014 - -#define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018 - - -#endif /* DSI_PHY_20NM_XML */ diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h b/drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h deleted file mode 100644 index 5148f4d5b182..000000000000 --- a/drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h +++ /dev/null @@ -1,385 +0,0 @@ -#ifndef DSI_PHY_28NM_XML -#define DSI_PHY_28NM_XML - -/* Autogenerated file, DO NOT EDIT manually! - -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git - -The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) - -Copyright (C) 2013-2021 by the following authors: -- Rob Clark <robdclark@gmail.com> (robclark) -- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - - -static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } - -#define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100 - -#define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104 - -#define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108 - -#define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c - -#define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110 - -#define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114 - -#define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118 - -#define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c - -#define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120 - -#define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140 -#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff -#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; -} - -#define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144 -#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff -#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; -} - -#define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148 -#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff -#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; -} - -#define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c -#define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001 - -#define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150 -#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff -#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK; -} - -#define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154 -#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff -#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK; -} - -#define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158 -#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff -#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; -} - -#define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c -#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff -#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; -} - -#define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160 -#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff -#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK; -} - -#define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164 -#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 -#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK; -} -#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 -#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 -static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK; -} - -#define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168 -#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 -#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK; -} - -#define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c -#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff -#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; -} - -#define REG_DSI_28nm_PHY_CTRL_0 0x00000170 - -#define REG_DSI_28nm_PHY_CTRL_1 0x00000174 - -#define REG_DSI_28nm_PHY_CTRL_2 0x00000178 - -#define REG_DSI_28nm_PHY_CTRL_3 0x0000017c - -#define REG_DSI_28nm_PHY_CTRL_4 0x00000180 - -#define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184 - -#define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188 - -#define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4 - -#define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8 - -#define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc - -#define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0 - -#define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4 - -#define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8 - -#define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4 -#define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001 - -#define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc - -#define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000 - -#define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004 - -#define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008 - -#define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c - -#define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010 - -#define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014 - -#define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018 - -#define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000 -#define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001 - -#define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004 - -#define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008 - -#define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c - -#define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010 -#define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002 - -#define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014 - -#define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018 - -#define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c - -#define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020 -#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001 -#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002 -#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004 -#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008 - -#define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024 - -#define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028 - -#define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c - -#define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030 - -#define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034 - -#define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038 -#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f -#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK; -} -#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040 - -#define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c -#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f -#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK; -} -#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040 -#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6 -static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK; -} - -#define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040 -#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff -#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK; -} - -#define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044 -#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff -#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK; -} - -#define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048 - -#define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c - -#define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050 - -#define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054 - -#define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058 - -#define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c - -#define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060 - -#define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064 - -#define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068 -#define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001 - -#define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c - -#define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070 - -#define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074 - -#define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078 - -#define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c - -#define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080 - -#define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084 - -#define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088 - -#define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c - -#define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090 - -#define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094 - -#define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098 - -#define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c - -#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0 - -#define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4 - -#define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8 - -#define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac - -#define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0 - -#define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4 - -#define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8 - -#define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc - -#define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0 -#define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001 - -#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4 - -#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8 - -#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc - -#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0 - -#define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4 - - -#endif /* DSI_PHY_28NM_XML */ diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h b/drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h deleted file mode 100644 index 446fe9ffc9c4..000000000000 --- a/drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h +++ /dev/null @@ -1,287 +0,0 @@ -#ifndef DSI_PHY_28NM_8960_XML -#define DSI_PHY_28NM_8960_XML - -/* Autogenerated file, DO NOT EDIT manually! - -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git - -The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) - -Copyright (C) 2013-2021 by the following authors: -- Rob Clark <robdclark@gmail.com> (robclark) -- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - - -static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; } - -#define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100 - -#define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104 - -#define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108 - -#define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH 0x0000010c - -#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0 0x00000114 - -#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1 0x00000118 - -#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0 0x00000140 -#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff -#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 -static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) -{ - return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; -} - -#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1 0x00000144 -#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff -#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 -static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) -{ - return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; -} - -#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2 0x00000148 -#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff -#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 -static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) -{ - return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; -} - -#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3 0x0000014c - -#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4 0x00000150 -#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff -#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 -static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) -{ - return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK; -} - -#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5 0x00000154 -#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff -#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 -static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) -{ - return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK; -} - -#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6 0x00000158 -#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff -#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 -static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) -{ - return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; -} - -#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7 0x0000015c -#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff -#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 -static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) -{ - return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; -} - -#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8 0x00000160 -#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff -#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 -static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) -{ - return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK; -} - -#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9 0x00000164 -#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 -#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 -static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) -{ - return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK; -} -#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 -#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 -static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) -{ - return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK; -} - -#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10 0x00000168 -#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 -#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 -static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) -{ - return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK; -} - -#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11 0x0000016c -#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff -#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 -static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) -{ - return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; -} - -#define REG_DSI_28nm_8960_PHY_CTRL_0 0x00000170 - -#define REG_DSI_28nm_8960_PHY_CTRL_1 0x00000174 - -#define REG_DSI_28nm_8960_PHY_CTRL_2 0x00000178 - -#define REG_DSI_28nm_8960_PHY_CTRL_3 0x0000017c - -#define REG_DSI_28nm_8960_PHY_STRENGTH_0 0x00000180 - -#define REG_DSI_28nm_8960_PHY_STRENGTH_1 0x00000184 - -#define REG_DSI_28nm_8960_PHY_STRENGTH_2 0x00000188 - -#define REG_DSI_28nm_8960_PHY_BIST_CTRL_0 0x0000018c - -#define REG_DSI_28nm_8960_PHY_BIST_CTRL_1 0x00000190 - -#define REG_DSI_28nm_8960_PHY_BIST_CTRL_2 0x00000194 - -#define REG_DSI_28nm_8960_PHY_BIST_CTRL_3 0x00000198 - -#define REG_DSI_28nm_8960_PHY_BIST_CTRL_4 0x0000019c - -#define REG_DSI_28nm_8960_PHY_LDO_CTRL 0x000001b0 - -#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0 0x00000000 - -#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1 0x00000004 - -#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2 0x00000008 - -#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3 0x0000000c - -#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4 0x00000010 - -#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5 0x00000014 - -#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG 0x00000018 - -#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER 0x00000028 - -#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0 0x0000002c - -#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1 0x00000030 - -#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2 0x00000034 - -#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0 0x00000038 - -#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1 0x0000003c - -#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2 0x00000040 - -#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3 0x00000044 - -#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4 0x00000048 - -#define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS 0x00000050 -#define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY 0x00000010 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_0 0x00000000 -#define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE 0x00000001 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_2 0x00000008 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_3 0x0000000c - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_4 0x00000010 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_5 0x00000014 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_6 0x00000018 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_7 0x0000001c - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_8 0x00000020 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_9 0x00000024 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_10 0x00000028 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_11 0x0000002c - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_12 0x00000030 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_13 0x00000034 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_14 0x00000038 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_15 0x0000003c - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_16 0x00000040 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_17 0x00000044 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_18 0x00000048 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_19 0x0000004c - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_20 0x00000050 - -#define REG_DSI_28nm_8960_PHY_PLL_RDY 0x00000080 -#define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY 0x00000001 - - -#endif /* DSI_PHY_28NM_8960_XML */ diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy_5nm.xml.h b/drivers/gpu/drm/msm/dsi/dsi_phy_5nm.xml.h deleted file mode 100644 index 404c890a29f1..000000000000 --- a/drivers/gpu/drm/msm/dsi/dsi_phy_5nm.xml.h +++ /dev/null @@ -1,480 +0,0 @@ -#ifndef DSI_PHY_5NM_XML -#define DSI_PHY_5NM_XML - -/* Autogenerated file, DO NOT EDIT manually! - -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git - -The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) - -Copyright (C) 2013-2021 by the following authors: -- Rob Clark <robdclark@gmail.com> (robclark) -- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - - -#define REG_DSI_5nm_PHY_CMN_REVISION_ID0 0x00000000 - -#define REG_DSI_5nm_PHY_CMN_REVISION_ID1 0x00000004 - -#define REG_DSI_5nm_PHY_CMN_REVISION_ID2 0x00000008 - -#define REG_DSI_5nm_PHY_CMN_REVISION_ID3 0x0000000c - -#define REG_DSI_5nm_PHY_CMN_CLK_CFG0 0x00000010 - -#define REG_DSI_5nm_PHY_CMN_CLK_CFG1 0x00000014 - -#define REG_DSI_5nm_PHY_CMN_GLBL_CTRL 0x00000018 - -#define REG_DSI_5nm_PHY_CMN_RBUF_CTRL 0x0000001c - -#define REG_DSI_5nm_PHY_CMN_VREG_CTRL_0 0x00000020 - -#define REG_DSI_5nm_PHY_CMN_CTRL_0 0x00000024 - -#define REG_DSI_5nm_PHY_CMN_CTRL_1 0x00000028 - -#define REG_DSI_5nm_PHY_CMN_CTRL_2 0x0000002c - -#define REG_DSI_5nm_PHY_CMN_CTRL_3 0x00000030 - -#define REG_DSI_5nm_PHY_CMN_LANE_CFG0 0x00000034 - -#define REG_DSI_5nm_PHY_CMN_LANE_CFG1 0x00000038 - -#define REG_DSI_5nm_PHY_CMN_PLL_CNTRL 0x0000003c - -#define REG_DSI_5nm_PHY_CMN_DPHY_SOT 0x00000040 - -#define REG_DSI_5nm_PHY_CMN_LANE_CTRL0 0x000000a0 - -#define REG_DSI_5nm_PHY_CMN_LANE_CTRL1 0x000000a4 - -#define REG_DSI_5nm_PHY_CMN_LANE_CTRL2 0x000000a8 - -#define REG_DSI_5nm_PHY_CMN_LANE_CTRL3 0x000000ac - -#define REG_DSI_5nm_PHY_CMN_LANE_CTRL4 0x000000b0 - -#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_0 0x000000b4 - -#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_1 0x000000b8 - -#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_2 0x000000bc - -#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_3 0x000000c0 - -#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_4 0x000000c4 - -#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_5 0x000000c8 - -#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_6 0x000000cc - -#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_7 0x000000d0 - -#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_8 0x000000d4 - -#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_9 0x000000d8 - -#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_10 0x000000dc - -#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_11 0x000000e0 - -#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_12 0x000000e4 - -#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_13 0x000000e8 - -#define REG_DSI_5nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0 0x000000ec - -#define REG_DSI_5nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1 0x000000f0 - -#define REG_DSI_5nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL 0x000000f4 - -#define REG_DSI_5nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL 0x000000f8 - -#define REG_DSI_5nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL 0x000000fc - -#define REG_DSI_5nm_PHY_CMN_GLBL_LPTX_STR_CTRL 0x00000100 - -#define REG_DSI_5nm_PHY_CMN_GLBL_PEMPH_CTRL_0 0x00000104 - -#define REG_DSI_5nm_PHY_CMN_GLBL_PEMPH_CTRL_1 0x00000108 - -#define REG_DSI_5nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL 0x0000010c - -#define REG_DSI_5nm_PHY_CMN_VREG_CTRL_1 0x00000110 - -#define REG_DSI_5nm_PHY_CMN_CTRL_4 0x00000114 - -#define REG_DSI_5nm_PHY_CMN_PHY_STATUS 0x00000140 - -#define REG_DSI_5nm_PHY_CMN_LANE_STATUS0 0x00000148 - -#define REG_DSI_5nm_PHY_CMN_LANE_STATUS1 0x0000014c - -static inline uint32_t REG_DSI_5nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } - -static inline uint32_t REG_DSI_5nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } - -static inline uint32_t REG_DSI_5nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } - -static inline uint32_t REG_DSI_5nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } - -static inline uint32_t REG_DSI_5nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; } - -static inline uint32_t REG_DSI_5nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; } - -static inline uint32_t REG_DSI_5nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; } - -static inline uint32_t REG_DSI_5nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; } - -#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000 - -#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004 - -#define REG_DSI_5nm_PHY_PLL_INT_LOOP_SETTINGS 0x00000008 - -#define REG_DSI_5nm_PHY_PLL_INT_LOOP_SETTINGS_TWO 0x0000000c - -#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010 - -#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FOUR 0x00000014 - -#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FIVE 0x00000018 - -#define REG_DSI_5nm_PHY_PLL_INT_LOOP_CONTROLS 0x0000001c - -#define REG_DSI_5nm_PHY_PLL_DSM_DIVIDER 0x00000020 - -#define REG_DSI_5nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000024 - -#define REG_DSI_5nm_PHY_PLL_SYSTEM_MUXES 0x00000028 - -#define REG_DSI_5nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x0000002c - -#define REG_DSI_5nm_PHY_PLL_CMODE 0x00000030 - -#define REG_DSI_5nm_PHY_PLL_PSM_CTRL 0x00000034 - -#define REG_DSI_5nm_PHY_PLL_RSM_CTRL 0x00000038 - -#define REG_DSI_5nm_PHY_PLL_VCO_TUNE_MAP 0x0000003c - -#define REG_DSI_5nm_PHY_PLL_PLL_CNTRL 0x00000040 - -#define REG_DSI_5nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000044 - -#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW 0x00000048 - -#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH 0x0000004c - -#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS 0x00000050 - -#define REG_DSI_5nm_PHY_PLL_BAND_SEL_MIN 0x00000054 - -#define REG_DSI_5nm_PHY_PLL_BAND_SEL_MAX 0x00000058 - -#define REG_DSI_5nm_PHY_PLL_BAND_SEL_PFILT 0x0000005c - -#define REG_DSI_5nm_PHY_PLL_BAND_SEL_IFILT 0x00000060 - -#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO 0x00000064 - -#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000068 - -#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x0000006c - -#define REG_DSI_5nm_PHY_PLL_BAND_SEL_ICODE_HIGH 0x00000070 - -#define REG_DSI_5nm_PHY_PLL_BAND_SEL_ICODE_LOW 0x00000074 - -#define REG_DSI_5nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000078 - -#define REG_DSI_5nm_PHY_PLL_FREQ_DETECT_THRESH 0x0000007c - -#define REG_DSI_5nm_PHY_PLL_FREQ_DET_REFCLK_HIGH 0x00000080 - -#define REG_DSI_5nm_PHY_PLL_FREQ_DET_REFCLK_LOW 0x00000084 - -#define REG_DSI_5nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH 0x00000088 - -#define REG_DSI_5nm_PHY_PLL_FREQ_DET_PLLCLK_LOW 0x0000008c - -#define REG_DSI_5nm_PHY_PLL_PFILT 0x00000090 - -#define REG_DSI_5nm_PHY_PLL_IFILT 0x00000094 - -#define REG_DSI_5nm_PHY_PLL_PLL_GAIN 0x00000098 - -#define REG_DSI_5nm_PHY_PLL_ICODE_LOW 0x0000009c - -#define REG_DSI_5nm_PHY_PLL_ICODE_HIGH 0x000000a0 - -#define REG_DSI_5nm_PHY_PLL_LOCKDET 0x000000a4 - -#define REG_DSI_5nm_PHY_PLL_OUTDIV 0x000000a8 - -#define REG_DSI_5nm_PHY_PLL_FASTLOCK_CONTROL 0x000000ac - -#define REG_DSI_5nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE 0x000000b0 - -#define REG_DSI_5nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO 0x000000b4 - -#define REG_DSI_5nm_PHY_PLL_CORE_OVERRIDE 0x000000b8 - -#define REG_DSI_5nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000bc - -#define REG_DSI_5nm_PHY_PLL_RATE_CHANGE 0x000000c0 - -#define REG_DSI_5nm_PHY_PLL_PLL_DIGITAL_TIMERS 0x000000c4 - -#define REG_DSI_5nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000c8 - -#define REG_DSI_5nm_PHY_PLL_DECIMAL_DIV_START 0x000000cc - -#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_LOW 0x000000d0 - -#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_MID 0x000000d4 - -#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_HIGH 0x000000d8 - -#define REG_DSI_5nm_PHY_PLL_DEC_FRAC_MUXES 0x000000dc - -#define REG_DSI_5nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000e0 - -#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000e4 - -#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000e8 - -#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000ec - -#define REG_DSI_5nm_PHY_PLL_DECIMAL_DIV_START_2 0x000000f0 - -#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_LOW_2 0x000000f4 - -#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_MID_2 0x000000f8 - -#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_HIGH_2 0x000000fc - -#define REG_DSI_5nm_PHY_PLL_MASH_CONTROL 0x00000100 - -#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_LOW 0x00000104 - -#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_HIGH 0x00000108 - -#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_LOW 0x0000010c - -#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_HIGH 0x00000110 - -#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_LOW 0x00000114 - -#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_HIGH 0x00000118 - -#define REG_DSI_5nm_PHY_PLL_SSC_MUX_CONTROL 0x0000011c - -#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x00000120 - -#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000124 - -#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000128 - -#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x0000012c - -#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_LOW_1 0x00000130 - -#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_HIGH_1 0x00000134 - -#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_LOW_2 0x00000138 - -#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_HIGH_2 0x0000013c - -#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_LOW_2 0x00000140 - -#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_HIGH_2 0x00000144 - -#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_LOW_2 0x00000148 - -#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_HIGH_2 0x0000014c - -#define REG_DSI_5nm_PHY_PLL_SSC_CONTROL 0x00000150 - -#define REG_DSI_5nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000154 - -#define REG_DSI_5nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000158 - -#define REG_DSI_5nm_PHY_PLL_PLL_LOCKDET_RATE_2 0x0000015c - -#define REG_DSI_5nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x00000160 - -#define REG_DSI_5nm_PHY_PLL_PLL_PROP_GAIN_RATE_2 0x00000164 - -#define REG_DSI_5nm_PHY_PLL_PLL_BAND_SEL_RATE_1 0x00000168 - -#define REG_DSI_5nm_PHY_PLL_PLL_BAND_SEL_RATE_2 0x0000016c - -#define REG_DSI_5nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x00000170 - -#define REG_DSI_5nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2 0x00000174 - -#define REG_DSI_5nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000178 - -#define REG_DSI_5nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 0x0000017c - -#define REG_DSI_5nm_PHY_PLL_PLL_FASTLOCK_EN_BAND 0x00000180 - -#define REG_DSI_5nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID 0x00000184 - -#define REG_DSI_5nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x00000188 - -#define REG_DSI_5nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x0000018c - -#define REG_DSI_5nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000190 - -#define REG_DSI_5nm_PHY_PLL_PLL_LOCK_DELAY 0x00000194 - -#define REG_DSI_5nm_PHY_PLL_PLL_LOCK_MIN_DELAY 0x00000198 - -#define REG_DSI_5nm_PHY_PLL_CLOCK_INVERTERS 0x0000019c - -#define REG_DSI_5nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES 0x000001a0 - -#define REG_DSI_5nm_PHY_PLL_BIAS_CONTROL_1 0x000001a4 - -#define REG_DSI_5nm_PHY_PLL_BIAS_CONTROL_2 0x000001a8 - -#define REG_DSI_5nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1 0x000001ac - -#define REG_DSI_5nm_PHY_PLL_COMMON_STATUS_ONE 0x000001b0 - -#define REG_DSI_5nm_PHY_PLL_COMMON_STATUS_TWO 0x000001b4 - -#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL 0x000001b8 - -#define REG_DSI_5nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW 0x000001bc - -#define REG_DSI_5nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH 0x000001c0 - -#define REG_DSI_5nm_PHY_PLL_FD_OUT_LOW 0x000001c4 - -#define REG_DSI_5nm_PHY_PLL_FD_OUT_HIGH 0x000001c8 - -#define REG_DSI_5nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1 0x000001cc - -#define REG_DSI_5nm_PHY_PLL_PLL_MISC_CONFIG 0x000001d0 - -#define REG_DSI_5nm_PHY_PLL_FLL_CONFIG 0x000001d4 - -#define REG_DSI_5nm_PHY_PLL_FLL_FREQ_ACQ_TIME 0x000001d8 - -#define REG_DSI_5nm_PHY_PLL_FLL_CODE0 0x000001dc - -#define REG_DSI_5nm_PHY_PLL_FLL_CODE1 0x000001e0 - -#define REG_DSI_5nm_PHY_PLL_FLL_GAIN0 0x000001e4 - -#define REG_DSI_5nm_PHY_PLL_FLL_GAIN1 0x000001e8 - -#define REG_DSI_5nm_PHY_PLL_SW_RESET 0x000001ec - -#define REG_DSI_5nm_PHY_PLL_FAST_PWRUP 0x000001f0 - -#define REG_DSI_5nm_PHY_PLL_LOCKTIME0 0x000001f4 - -#define REG_DSI_5nm_PHY_PLL_LOCKTIME1 0x000001f8 - -#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS_SEL 0x000001fc - -#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS0 0x00000200 - -#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS1 0x00000204 - -#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS2 0x00000208 - -#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS3 0x0000020c - -#define REG_DSI_5nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES 0x00000210 - -#define REG_DSI_5nm_PHY_PLL_VCO_CONFIG 0x00000214 - -#define REG_DSI_5nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS 0x00000218 - -#define REG_DSI_5nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS 0x0000021c - -#define REG_DSI_5nm_PHY_PLL_RESET_SM_STATUS 0x00000220 - -#define REG_DSI_5nm_PHY_PLL_TDC_OFFSET 0x00000224 - -#define REG_DSI_5nm_PHY_PLL_PS3_PWRDOWN_CONTROLS 0x00000228 - -#define REG_DSI_5nm_PHY_PLL_PS4_PWRDOWN_CONTROLS 0x0000022c - -#define REG_DSI_5nm_PHY_PLL_PLL_RST_CONTROLS 0x00000230 - -#define REG_DSI_5nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS 0x00000234 - -#define REG_DSI_5nm_PHY_PLL_PSM_CLK_CONTROLS 0x00000238 - -#define REG_DSI_5nm_PHY_PLL_SYSTEM_MUXES_2 0x0000023c - -#define REG_DSI_5nm_PHY_PLL_VCO_CONFIG_1 0x00000240 - -#define REG_DSI_5nm_PHY_PLL_VCO_CONFIG_2 0x00000244 - -#define REG_DSI_5nm_PHY_PLL_CLOCK_INVERTERS_1 0x00000248 - -#define REG_DSI_5nm_PHY_PLL_CLOCK_INVERTERS_2 0x0000024c - -#define REG_DSI_5nm_PHY_PLL_CMODE_1 0x00000250 - -#define REG_DSI_5nm_PHY_PLL_CMODE_2 0x00000254 - -#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1 0x00000258 - -#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2 0x0000025c - -#define REG_DSI_5nm_PHY_PLL_PERF_OPTIMIZE 0x00000260 - - -#endif /* DSI_PHY_5NM_XML */ diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h b/drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h deleted file mode 100644 index 782f6b332baf..000000000000 --- a/drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h +++ /dev/null @@ -1,482 +0,0 @@ -#ifndef DSI_PHY_7NM_XML -#define DSI_PHY_7NM_XML - -/* Autogenerated file, DO NOT EDIT manually! - -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git - -The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) - -Copyright (C) 2013-2021 by the following authors: -- Rob Clark <robdclark@gmail.com> (robclark) -- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - - -#define REG_DSI_7nm_PHY_CMN_REVISION_ID0 0x00000000 - -#define REG_DSI_7nm_PHY_CMN_REVISION_ID1 0x00000004 - -#define REG_DSI_7nm_PHY_CMN_REVISION_ID2 0x00000008 - -#define REG_DSI_7nm_PHY_CMN_REVISION_ID3 0x0000000c - -#define REG_DSI_7nm_PHY_CMN_CLK_CFG0 0x00000010 - -#define REG_DSI_7nm_PHY_CMN_CLK_CFG1 0x00000014 - -#define REG_DSI_7nm_PHY_CMN_GLBL_CTRL 0x00000018 - -#define REG_DSI_7nm_PHY_CMN_RBUF_CTRL 0x0000001c - -#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_0 0x00000020 - -#define REG_DSI_7nm_PHY_CMN_CTRL_0 0x00000024 - -#define REG_DSI_7nm_PHY_CMN_CTRL_1 0x00000028 - -#define REG_DSI_7nm_PHY_CMN_CTRL_2 0x0000002c - -#define REG_DSI_7nm_PHY_CMN_CTRL_3 0x00000030 - -#define REG_DSI_7nm_PHY_CMN_LANE_CFG0 0x00000034 - -#define REG_DSI_7nm_PHY_CMN_LANE_CFG1 0x00000038 - -#define REG_DSI_7nm_PHY_CMN_PLL_CNTRL 0x0000003c - -#define REG_DSI_7nm_PHY_CMN_DPHY_SOT 0x00000040 - -#define REG_DSI_7nm_PHY_CMN_LANE_CTRL0 0x000000a0 - -#define REG_DSI_7nm_PHY_CMN_LANE_CTRL1 0x000000a4 - -#define REG_DSI_7nm_PHY_CMN_LANE_CTRL2 0x000000a8 - -#define REG_DSI_7nm_PHY_CMN_LANE_CTRL3 0x000000ac - -#define REG_DSI_7nm_PHY_CMN_LANE_CTRL4 0x000000b0 - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0 0x000000b4 - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1 0x000000b8 - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2 0x000000bc - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3 0x000000c0 - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4 0x000000c4 - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5 0x000000c8 - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6 0x000000cc - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7 0x000000d0 - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8 0x000000d4 - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9 0x000000d8 - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10 0x000000dc - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11 0x000000e0 - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12 0x000000e4 - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13 0x000000e8 - -#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0 0x000000ec - -#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1 0x000000f0 - -#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL 0x000000f4 - -#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL 0x000000f8 - -#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL 0x000000fc - -#define REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL 0x00000100 - -#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0 0x00000104 - -#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1 0x00000108 - -#define REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL 0x0000010c - -#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_1 0x00000110 - -#define REG_DSI_7nm_PHY_CMN_CTRL_4 0x00000114 - -#define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4 0x00000128 - -#define REG_DSI_7nm_PHY_CMN_PHY_STATUS 0x00000140 - -#define REG_DSI_7nm_PHY_CMN_LANE_STATUS0 0x00000148 - -#define REG_DSI_7nm_PHY_CMN_LANE_STATUS1 0x0000014c - -static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } - -static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } - -static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } - -static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } - -static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; } - -static inline uint32_t REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; } - -static inline uint32_t REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; } - -static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; } - -#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000 - -#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004 - -#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS 0x00000008 - -#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS_TWO 0x0000000c - -#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010 - -#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FOUR 0x00000014 - -#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE 0x00000018 - -#define REG_DSI_7nm_PHY_PLL_INT_LOOP_CONTROLS 0x0000001c - -#define REG_DSI_7nm_PHY_PLL_DSM_DIVIDER 0x00000020 - -#define REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000024 - -#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES 0x00000028 - -#define REG_DSI_7nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x0000002c - -#define REG_DSI_7nm_PHY_PLL_CMODE 0x00000030 - -#define REG_DSI_7nm_PHY_PLL_PSM_CTRL 0x00000034 - -#define REG_DSI_7nm_PHY_PLL_RSM_CTRL 0x00000038 - -#define REG_DSI_7nm_PHY_PLL_VCO_TUNE_MAP 0x0000003c - -#define REG_DSI_7nm_PHY_PLL_PLL_CNTRL 0x00000040 - -#define REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000044 - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW 0x00000048 - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH 0x0000004c - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS 0x00000050 - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MIN 0x00000054 - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MAX 0x00000058 - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_PFILT 0x0000005c - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_IFILT 0x00000060 - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO 0x00000064 - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000068 - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x0000006c - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_HIGH 0x00000070 - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_LOW 0x00000074 - -#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000078 - -#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_THRESH 0x0000007c - -#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_HIGH 0x00000080 - -#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_LOW 0x00000084 - -#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH 0x00000088 - -#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_LOW 0x0000008c - -#define REG_DSI_7nm_PHY_PLL_PFILT 0x00000090 - -#define REG_DSI_7nm_PHY_PLL_IFILT 0x00000094 - -#define REG_DSI_7nm_PHY_PLL_PLL_GAIN 0x00000098 - -#define REG_DSI_7nm_PHY_PLL_ICODE_LOW 0x0000009c - -#define REG_DSI_7nm_PHY_PLL_ICODE_HIGH 0x000000a0 - -#define REG_DSI_7nm_PHY_PLL_LOCKDET 0x000000a4 - -#define REG_DSI_7nm_PHY_PLL_OUTDIV 0x000000a8 - -#define REG_DSI_7nm_PHY_PLL_FASTLOCK_CONTROL 0x000000ac - -#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE 0x000000b0 - -#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO 0x000000b4 - -#define REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE 0x000000b8 - -#define REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000bc - -#define REG_DSI_7nm_PHY_PLL_RATE_CHANGE 0x000000c0 - -#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS 0x000000c4 - -#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000c8 - -#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START 0x000000cc - -#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW 0x000000d0 - -#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID 0x000000d4 - -#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH 0x000000d8 - -#define REG_DSI_7nm_PHY_PLL_DEC_FRAC_MUXES 0x000000dc - -#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000e0 - -#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000e4 - -#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000e8 - -#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000ec - -#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_2 0x000000f0 - -#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_2 0x000000f4 - -#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_2 0x000000f8 - -#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_2 0x000000fc - -#define REG_DSI_7nm_PHY_PLL_MASH_CONTROL 0x00000100 - -#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW 0x00000104 - -#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH 0x00000108 - -#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW 0x0000010c - -#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH 0x00000110 - -#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW 0x00000114 - -#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH 0x00000118 - -#define REG_DSI_7nm_PHY_PLL_SSC_MUX_CONTROL 0x0000011c - -#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x00000120 - -#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000124 - -#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000128 - -#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x0000012c - -#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1 0x00000130 - -#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1 0x00000134 - -#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_2 0x00000138 - -#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_2 0x0000013c - -#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_2 0x00000140 - -#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_2 0x00000144 - -#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_2 0x00000148 - -#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_2 0x0000014c - -#define REG_DSI_7nm_PHY_PLL_SSC_CONTROL 0x00000150 - -#define REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000154 - -#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000158 - -#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_2 0x0000015c - -#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x00000160 - -#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_2 0x00000164 - -#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1 0x00000168 - -#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_2 0x0000016c - -#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x00000170 - -#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2 0x00000174 - -#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000178 - -#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 0x0000017c - -#define REG_DSI_7nm_PHY_PLL_PLL_FASTLOCK_EN_BAND 0x00000180 - -#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID 0x00000184 - -#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x00000188 - -#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x0000018c - -#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000190 - -#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY 0x00000194 - -#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_MIN_DELAY 0x00000198 - -#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS 0x0000019c - -#define REG_DSI_7nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES 0x000001a0 - -#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_1 0x000001a4 - -#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_2 0x000001a8 - -#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1 0x000001ac - -#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE 0x000001b0 - -#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_TWO 0x000001b4 - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL 0x000001b8 - -#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW 0x000001bc - -#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH 0x000001c0 - -#define REG_DSI_7nm_PHY_PLL_FD_OUT_LOW 0x000001c4 - -#define REG_DSI_7nm_PHY_PLL_FD_OUT_HIGH 0x000001c8 - -#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1 0x000001cc - -#define REG_DSI_7nm_PHY_PLL_PLL_MISC_CONFIG 0x000001d0 - -#define REG_DSI_7nm_PHY_PLL_FLL_CONFIG 0x000001d4 - -#define REG_DSI_7nm_PHY_PLL_FLL_FREQ_ACQ_TIME 0x000001d8 - -#define REG_DSI_7nm_PHY_PLL_FLL_CODE0 0x000001dc - -#define REG_DSI_7nm_PHY_PLL_FLL_CODE1 0x000001e0 - -#define REG_DSI_7nm_PHY_PLL_FLL_GAIN0 0x000001e4 - -#define REG_DSI_7nm_PHY_PLL_FLL_GAIN1 0x000001e8 - -#define REG_DSI_7nm_PHY_PLL_SW_RESET 0x000001ec - -#define REG_DSI_7nm_PHY_PLL_FAST_PWRUP 0x000001f0 - -#define REG_DSI_7nm_PHY_PLL_LOCKTIME0 0x000001f4 - -#define REG_DSI_7nm_PHY_PLL_LOCKTIME1 0x000001f8 - -#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS_SEL 0x000001fc - -#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS0 0x00000200 - -#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS1 0x00000204 - -#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS2 0x00000208 - -#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS3 0x0000020c - -#define REG_DSI_7nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES 0x00000210 - -#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG 0x00000214 - -#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS 0x00000218 - -#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS 0x0000021c - -#define REG_DSI_7nm_PHY_PLL_RESET_SM_STATUS 0x00000220 - -#define REG_DSI_7nm_PHY_PLL_TDC_OFFSET 0x00000224 - -#define REG_DSI_7nm_PHY_PLL_PS3_PWRDOWN_CONTROLS 0x00000228 - -#define REG_DSI_7nm_PHY_PLL_PS4_PWRDOWN_CONTROLS 0x0000022c - -#define REG_DSI_7nm_PHY_PLL_PLL_RST_CONTROLS 0x00000230 - -#define REG_DSI_7nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS 0x00000234 - -#define REG_DSI_7nm_PHY_PLL_PSM_CLK_CONTROLS 0x00000238 - -#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES_2 0x0000023c - -#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1 0x00000240 - -#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_2 0x00000244 - -#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_1 0x00000248 - -#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_2 0x0000024c - -#define REG_DSI_7nm_PHY_PLL_CMODE_1 0x00000250 - -#define REG_DSI_7nm_PHY_PLL_CMODE_2 0x00000254 - -#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1 0x00000258 - -#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2 0x0000025c - -#define REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE 0x00000260 - - -#endif /* DSI_PHY_7NM_XML */ diff --git a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h deleted file mode 100644 index fbb6a7a6b940..000000000000 --- a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h +++ /dev/null @@ -1,132 +0,0 @@ -#ifndef MMSS_CC_XML -#define MMSS_CC_XML - -/* Autogenerated file, DO NOT EDIT manually! - -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git - -The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) - -Copyright (C) 2013-2021 by the following authors: -- Rob Clark <robdclark@gmail.com> (robclark) -- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - - -enum mmss_cc_clk { - CLK = 0, - PCLK = 1, -}; - -#define REG_MMSS_CC_AHB 0x00000008 - -static inline uint32_t __offset_CLK(enum mmss_cc_clk idx) -{ - switch (idx) { - case CLK: return 0x0000004c; - case PCLK: return 0x00000130; - default: return INVALID_IDX(idx); - } -} -static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); } - -static inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); } -#define MMSS_CC_CLK_CC_CLK_EN 0x00000001 -#define MMSS_CC_CLK_CC_ROOT_EN 0x00000004 -#define MMSS_CC_CLK_CC_MND_EN 0x00000020 -#define MMSS_CC_CLK_CC_MND_MODE__MASK 0x000000c0 -#define MMSS_CC_CLK_CC_MND_MODE__SHIFT 6 -static inline uint32_t MMSS_CC_CLK_CC_MND_MODE(uint32_t val) -{ - return ((val) << MMSS_CC_CLK_CC_MND_MODE__SHIFT) & MMSS_CC_CLK_CC_MND_MODE__MASK; -} -#define MMSS_CC_CLK_CC_PMXO_SEL__MASK 0x00000300 -#define MMSS_CC_CLK_CC_PMXO_SEL__SHIFT 8 -static inline uint32_t MMSS_CC_CLK_CC_PMXO_SEL(uint32_t val) -{ - return ((val) << MMSS_CC_CLK_CC_PMXO_SEL__SHIFT) & MMSS_CC_CLK_CC_PMXO_SEL__MASK; -} - -static inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i0); } -#define MMSS_CC_CLK_MD_D__MASK 0x000000ff -#define MMSS_CC_CLK_MD_D__SHIFT 0 -static inline uint32_t MMSS_CC_CLK_MD_D(uint32_t val) -{ - return ((val) << MMSS_CC_CLK_MD_D__SHIFT) & MMSS_CC_CLK_MD_D__MASK; -} -#define MMSS_CC_CLK_MD_M__MASK 0x0000ff00 -#define MMSS_CC_CLK_MD_M__SHIFT 8 -static inline uint32_t MMSS_CC_CLK_MD_M(uint32_t val) -{ - return ((val) << MMSS_CC_CLK_MD_M__SHIFT) & MMSS_CC_CLK_MD_M__MASK; -} - -static inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i0); } -#define MMSS_CC_CLK_NS_SRC__MASK 0x0000000f -#define MMSS_CC_CLK_NS_SRC__SHIFT 0 -static inline uint32_t MMSS_CC_CLK_NS_SRC(uint32_t val) -{ - return ((val) << MMSS_CC_CLK_NS_SRC__SHIFT) & MMSS_CC_CLK_NS_SRC__MASK; -} -#define MMSS_CC_CLK_NS_PRE_DIV_FUNC__MASK 0x00fff000 -#define MMSS_CC_CLK_NS_PRE_DIV_FUNC__SHIFT 12 -static inline uint32_t MMSS_CC_CLK_NS_PRE_DIV_FUNC(uint32_t val) -{ - return ((val) << MMSS_CC_CLK_NS_PRE_DIV_FUNC__SHIFT) & MMSS_CC_CLK_NS_PRE_DIV_FUNC__MASK; -} -#define MMSS_CC_CLK_NS_VAL__MASK 0xff000000 -#define MMSS_CC_CLK_NS_VAL__SHIFT 24 -static inline uint32_t MMSS_CC_CLK_NS_VAL(uint32_t val) -{ - return ((val) << MMSS_CC_CLK_NS_VAL__SHIFT) & MMSS_CC_CLK_NS_VAL__MASK; -} - -#define REG_MMSS_CC_DSI2_PIXEL_CC 0x00000094 - -#define REG_MMSS_CC_DSI2_PIXEL_NS 0x000000e4 - -#define REG_MMSS_CC_DSI2_PIXEL_CC2 0x00000264 - - -#endif /* MMSS_CC_XML */ diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 6ca6bfd4809b..4ea681130dba 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -5,6 +5,9 @@ #include <linux/clk-provider.h> #include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> +#include <dt-bindings/phy/phy.h> #include "dsi_phy.h" @@ -346,9 +349,11 @@ int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing, } else { timing->shared_timings.clk_pre = linear_inter(tmax, tmin, pcnt2, 0, false); - timing->shared_timings.clk_pre_inc_by_2 = 0; + timing->shared_timings.clk_pre_inc_by_2 = 0; } + timing->shared_timings.byte_intf_clk_div_2 = true; + timing->ta_go = 3; timing->ta_sure = 0; timing->ta_get = 4; @@ -453,6 +458,8 @@ int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, tmax = 255; timing->shared_timings.clk_pre = DIV_ROUND_UP((tmax - tmin) * 125, 10000) + tmin; + timing->shared_timings.byte_intf_clk_div_2 = true; + DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d", timing->shared_timings.clk_pre, timing->shared_timings.clk_post, timing->clk_zero, timing->clk_trail, timing->clk_prepare, timing->hs_exit, @@ -461,102 +468,49 @@ int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, return 0; } -static int dsi_phy_regulator_init(struct msm_dsi_phy *phy) -{ - struct regulator_bulk_data *s = phy->supplies; - const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs; - struct device *dev = &phy->pdev->dev; - int num = phy->cfg->reg_cfg.num; - int i, ret; - - for (i = 0; i < num; i++) - s[i].supply = regs[i].name; - - ret = devm_regulator_bulk_get(dev, num, s); - if (ret < 0) { - if (ret != -EPROBE_DEFER) { - DRM_DEV_ERROR(dev, - "%s: failed to init regulator, ret=%d\n", - __func__, ret); - } - - return ret; - } - - return 0; -} - -static void dsi_phy_regulator_disable(struct msm_dsi_phy *phy) +int msm_dsi_cphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, + struct msm_dsi_phy_clk_request *clk_req) { - struct regulator_bulk_data *s = phy->supplies; - const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs; - int num = phy->cfg->reg_cfg.num; - int i; - - DBG(""); - for (i = num - 1; i >= 0; i--) - if (regs[i].disable_load >= 0) - regulator_set_load(s[i].consumer, regs[i].disable_load); - - regulator_bulk_disable(num, s); -} + const unsigned long bit_rate = clk_req->bitclk_rate; + const unsigned long esc_rate = clk_req->escclk_rate; + s32 ui, ui_x7; + s32 tmax, tmin; + s32 coeff = 1000; /* Precision, should avoid overflow */ + s32 temp; -static int dsi_phy_regulator_enable(struct msm_dsi_phy *phy) -{ - struct regulator_bulk_data *s = phy->supplies; - const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs; - struct device *dev = &phy->pdev->dev; - int num = phy->cfg->reg_cfg.num; - int ret, i; - - DBG(""); - for (i = 0; i < num; i++) { - if (regs[i].enable_load >= 0) { - ret = regulator_set_load(s[i].consumer, - regs[i].enable_load); - if (ret < 0) { - DRM_DEV_ERROR(dev, - "regulator %d set op mode failed, %d\n", - i, ret); - goto fail; - } - } - } + if (!bit_rate || !esc_rate) + return -EINVAL; - ret = regulator_bulk_enable(num, s); - if (ret < 0) { - DRM_DEV_ERROR(dev, "regulator enable failed, %d\n", ret); - goto fail; - } + ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000); + ui_x7 = ui * 7; - return 0; + temp = S_DIV_ROUND_UP(38 * coeff, ui_x7); + tmin = max_t(s32, temp, 0); + temp = (95 * coeff) / ui_x7; + tmax = max_t(s32, temp, 0); + timing->clk_prepare = linear_inter(tmax, tmin, 50, 0, false); -fail: - for (i--; i >= 0; i--) - regulator_set_load(s[i].consumer, regs[i].disable_load); - return ret; -} + tmin = DIV_ROUND_UP(50 * coeff, ui_x7); + tmax = 255; + timing->hs_rqst = linear_inter(tmax, tmin, 1, 0, false); -static int dsi_phy_enable_resource(struct msm_dsi_phy *phy) -{ - struct device *dev = &phy->pdev->dev; - int ret; + tmin = DIV_ROUND_UP(100 * coeff, ui_x7) - 1; + tmax = 255; + timing->hs_exit = linear_inter(tmax, tmin, 10, 0, false); - pm_runtime_get_sync(dev); + tmin = 1; + tmax = 32; + timing->shared_timings.clk_post = linear_inter(tmax, tmin, 80, 0, false); - ret = clk_prepare_enable(phy->ahb_clk); - if (ret) { - DRM_DEV_ERROR(dev, "%s: can't enable ahb clk, %d\n", __func__, ret); - pm_runtime_put_sync(dev); - } + tmin = min_t(s32, 64, S_DIV_ROUND_UP(262 * coeff, ui_x7) - 1); + tmax = 64; + timing->shared_timings.clk_pre = linear_inter(tmax, tmin, 20, 0, false); - return ret; -} + DBG("%d, %d, %d, %d, %d", + timing->shared_timings.clk_pre, timing->shared_timings.clk_post, + timing->clk_prepare, timing->hs_exit, timing->hs_rqst); -static void dsi_phy_disable_resource(struct msm_dsi_phy *phy) -{ - clk_disable_unprepare(phy->ahb_clk); - pm_runtime_put_autosuspend(&phy->pdev->dev); + return 0; } static const struct of_device_id dsi_phy_dt_match[] = { @@ -567,6 +521,10 @@ static const struct of_device_id dsi_phy_dt_match[] = { .data = &dsi_phy_28nm_hpm_famb_cfgs }, { .compatible = "qcom,dsi-phy-28nm-lp", .data = &dsi_phy_28nm_lp_cfgs }, + { .compatible = "qcom,dsi-phy-28nm-8226", + .data = &dsi_phy_28nm_8226_cfgs }, + { .compatible = "qcom,dsi-phy-28nm-8937", + .data = &dsi_phy_28nm_8937_cfgs }, #endif #ifdef CONFIG_DRM_MSM_DSI_20NM_PHY { .compatible = "qcom,dsi-phy-20nm", @@ -579,8 +537,16 @@ static const struct of_device_id dsi_phy_dt_match[] = { #ifdef CONFIG_DRM_MSM_DSI_14NM_PHY { .compatible = "qcom,dsi-phy-14nm", .data = &dsi_phy_14nm_cfgs }, + { .compatible = "qcom,dsi-phy-14nm-2290", + .data = &dsi_phy_14nm_2290_cfgs }, { .compatible = "qcom,dsi-phy-14nm-660", .data = &dsi_phy_14nm_660_cfgs }, + { .compatible = "qcom,dsi-phy-14nm-8953", + .data = &dsi_phy_14nm_8953_cfgs }, + { .compatible = "qcom,sm6125-dsi-phy-14nm", + .data = &dsi_phy_14nm_2290_cfgs }, + { .compatible = "qcom,sm6150-dsi-phy-14nm", + .data = &dsi_phy_14nm_6150_cfgs }, #endif #ifdef CONFIG_DRM_MSM_DSI_10NM_PHY { .compatible = "qcom,dsi-phy-10nm", @@ -593,6 +559,24 @@ static const struct of_device_id dsi_phy_dt_match[] = { .data = &dsi_phy_7nm_cfgs }, { .compatible = "qcom,dsi-phy-7nm-8150", .data = &dsi_phy_7nm_8150_cfgs }, + { .compatible = "qcom,sa8775p-dsi-phy-5nm", + .data = &dsi_phy_5nm_8775p_cfgs }, + { .compatible = "qcom,sar2130p-dsi-phy-5nm", + .data = &dsi_phy_5nm_sar2130p_cfgs }, + { .compatible = "qcom,sc7280-dsi-phy-7nm", + .data = &dsi_phy_7nm_7280_cfgs }, + { .compatible = "qcom,sm6375-dsi-phy-7nm", + .data = &dsi_phy_7nm_6375_cfgs }, + { .compatible = "qcom,sm8350-dsi-phy-5nm", + .data = &dsi_phy_5nm_8350_cfgs }, + { .compatible = "qcom,sm8450-dsi-phy-5nm", + .data = &dsi_phy_5nm_8450_cfgs }, + { .compatible = "qcom,sm8550-dsi-phy-4nm", + .data = &dsi_phy_4nm_8550_cfgs }, + { .compatible = "qcom,sm8650-dsi-phy-4nm", + .data = &dsi_phy_4nm_8650_cfgs }, + { .compatible = "qcom,sm8750-dsi-phy-3nm", + .data = &dsi_phy_3nm_8750_cfgs }, #endif {} }; @@ -625,17 +609,13 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) { struct msm_dsi_phy *phy; struct device *dev = &pdev->dev; - const struct of_device_id *match; + u32 phy_type; int ret; phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); if (!phy) return -ENOMEM; - match = of_match_node(dsi_phy_dt_match, dev->of_node); - if (!match) - return -ENODEV; - phy->provided_clocks = devm_kzalloc(dev, struct_size(phy->provided_clocks, hws, NUM_PROVIDED_CLKS), GFP_KERNEL); @@ -644,102 +624,98 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) phy->provided_clocks->num = NUM_PROVIDED_CLKS; - phy->cfg = match->data; + phy->cfg = of_device_get_match_data(&pdev->dev); + if (!phy->cfg) + return -ENODEV; + phy->pdev = pdev; phy->id = dsi_phy_get_id(phy); - if (phy->id < 0) { - ret = phy->id; - DRM_DEV_ERROR(dev, "%s: couldn't identify PHY index, %d\n", - __func__, ret); - goto fail; - } + if (phy->id < 0) + return dev_err_probe(dev, phy->id, + "Couldn't identify PHY index\n"); phy->regulator_ldo_mode = of_property_read_bool(dev->of_node, "qcom,dsi-phy-regulator-ldo-mode"); + if (!of_property_read_u32(dev->of_node, "phy-type", &phy_type)) + phy->cphy_mode = (phy_type == PHY_TYPE_CPHY); - phy->base = msm_ioremap_size(pdev, "dsi_phy", "DSI_PHY", &phy->base_size); - if (IS_ERR(phy->base)) { - DRM_DEV_ERROR(dev, "%s: failed to map phy base\n", __func__); - ret = -ENOMEM; - goto fail; - } + phy->base = msm_ioremap_size(pdev, "dsi_phy", &phy->base_size); + if (IS_ERR(phy->base)) + return dev_err_probe(dev, PTR_ERR(phy->base), + "Failed to map phy base\n"); - phy->pll_base = msm_ioremap_size(pdev, "dsi_pll", "DSI_PLL", &phy->pll_size); - if (IS_ERR(phy->pll_base)) { - DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__); - ret = -ENOMEM; - goto fail; - } + phy->pll_base = msm_ioremap_size(pdev, "dsi_pll", &phy->pll_size); + if (IS_ERR(phy->pll_base)) + return dev_err_probe(dev, PTR_ERR(phy->pll_base), + "Failed to map pll base\n"); if (phy->cfg->has_phy_lane) { - phy->lane_base = msm_ioremap_size(pdev, "dsi_phy_lane", "DSI_PHY_LANE", &phy->lane_size); - if (IS_ERR(phy->lane_base)) { - DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n", __func__); - ret = -ENOMEM; - goto fail; - } + phy->lane_base = msm_ioremap_size(pdev, "dsi_phy_lane", &phy->lane_size); + if (IS_ERR(phy->lane_base)) + return dev_err_probe(dev, PTR_ERR(phy->lane_base), + "Failed to map phy lane base\n"); } if (phy->cfg->has_phy_regulator) { - phy->reg_base = msm_ioremap_size(pdev, "dsi_phy_regulator", "DSI_PHY_REG", &phy->reg_size); - if (IS_ERR(phy->reg_base)) { - DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy regulator base\n", __func__); - ret = -ENOMEM; - goto fail; - } + phy->reg_base = msm_ioremap_size(pdev, "dsi_phy_regulator", &phy->reg_size); + if (IS_ERR(phy->reg_base)) + return dev_err_probe(dev, PTR_ERR(phy->reg_base), + "Failed to map phy regulator base\n"); + } + + if (phy->cfg->ops.parse_dt_properties) { + ret = phy->cfg->ops.parse_dt_properties(phy); + if (ret) + return ret; } - ret = dsi_phy_regulator_init(phy); + ret = devm_regulator_bulk_get_const(dev, phy->cfg->num_regulators, + phy->cfg->regulator_data, + &phy->supplies); if (ret) - goto fail; + return ret; - phy->ahb_clk = msm_clk_get(pdev, "iface"); - if (IS_ERR(phy->ahb_clk)) { - DRM_DEV_ERROR(dev, "%s: Unable to get ahb clk\n", __func__); - ret = PTR_ERR(phy->ahb_clk); - goto fail; - } + platform_set_drvdata(pdev, phy); - /* PLL init will call into clk_register which requires - * register access, so we need to enable power and ahb clock. - */ - ret = dsi_phy_enable_resource(phy); + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; + + ret = devm_pm_clk_create(dev); if (ret) - goto fail; + return ret; + + ret = pm_clk_add(dev, "iface"); + if (ret < 0) + return dev_err_probe(dev, ret, "Unable to get iface clk\n"); if (phy->cfg->ops.pll_init) { ret = phy->cfg->ops.pll_init(phy); - if (ret) { - DRM_DEV_INFO(dev, - "%s: pll init failed: %d, need separate pll clk driver\n", - __func__, ret); - goto fail; - } + if (ret) + return dev_err_probe(dev, ret, + "PLL init failed; need separate clk driver\n"); } ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, phy->provided_clocks); - if (ret) { - DRM_DEV_ERROR(dev, "%s: failed to register clk provider: %d\n", __func__, ret); - goto fail; - } - - dsi_phy_disable_resource(phy); - - platform_set_drvdata(pdev, phy); + if (ret) + return dev_err_probe(dev, ret, + "Failed to register clk provider\n"); return 0; - -fail: - return ret; } +static const struct dev_pm_ops dsi_phy_pm_ops = { + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver dsi_phy_platform_driver = { .probe = dsi_phy_driver_probe, .driver = { .name = "msm_dsi_phy", .of_match_table = dsi_phy_dt_match, + .pm = &dsi_phy_pm_ops, }, }; @@ -754,22 +730,25 @@ void __exit msm_dsi_phy_driver_unregister(void) } int msm_dsi_phy_enable(struct msm_dsi_phy *phy, - struct msm_dsi_phy_clk_request *clk_req) + struct msm_dsi_phy_clk_request *clk_req, + struct msm_dsi_phy_shared_timings *shared_timings) { - struct device *dev = &phy->pdev->dev; + struct device *dev; int ret; if (!phy || !phy->cfg->ops.enable) return -EINVAL; - ret = dsi_phy_enable_resource(phy); + dev = &phy->pdev->dev; + + ret = pm_runtime_resume_and_get(dev); if (ret) { - DRM_DEV_ERROR(dev, "%s: resource enable failed, %d\n", + DRM_DEV_ERROR(dev, "%s: resume failed, %d\n", __func__, ret); goto res_en_fail; } - ret = dsi_phy_regulator_enable(phy); + ret = regulator_bulk_enable(phy->cfg->num_regulators, phy->supplies); if (ret) { DRM_DEV_ERROR(dev, "%s: regulator enable failed, %d\n", __func__, ret); @@ -782,6 +761,9 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy, goto phy_en_fail; } + memcpy(shared_timings, &phy->timing.shared_timings, + sizeof(*shared_timings)); + /* * Resetting DSI PHY silently changes its PLL registers to reset status, * which will confuse clock driver and result in wrong output rate of @@ -803,9 +785,9 @@ pll_restor_fail: if (phy->cfg->ops.disable) phy->cfg->ops.disable(phy); phy_en_fail: - dsi_phy_regulator_disable(phy); + regulator_bulk_disable(phy->cfg->num_regulators, phy->supplies); reg_en_fail: - dsi_phy_disable_resource(phy); + pm_runtime_put(dev); res_en_fail: return ret; } @@ -817,15 +799,8 @@ void msm_dsi_phy_disable(struct msm_dsi_phy *phy) phy->cfg->ops.disable(phy); - dsi_phy_regulator_disable(phy); - dsi_phy_disable_resource(phy); -} - -void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy, - struct msm_dsi_phy_shared_timings *shared_timings) -{ - memcpy(shared_timings, &phy->timing.shared_timings, - sizeof(*shared_timings)); + regulator_bulk_disable(phy->cfg->num_regulators, phy->supplies); + pm_runtime_put(&phy->pdev->dev); } void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy, @@ -835,15 +810,13 @@ void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy, phy->usecase = uc; } -int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy, - struct clk **byte_clk_provider, struct clk **pixel_clk_provider) +/* Returns true if we have to clear DSI_LANE_CTRL.HS_REQ_SEL_PHY */ +bool msm_dsi_phy_set_continuous_clock(struct msm_dsi_phy *phy, bool enable) { - if (byte_clk_provider) - *byte_clk_provider = phy->provided_clocks->hws[DSI_BYTE_PLL_CLK]->clk; - if (pixel_clk_provider) - *pixel_clk_provider = phy->provided_clocks->hws[DSI_PIXEL_PLL_CLK]->clk; + if (!phy || !phy->cfg->ops.set_continuous_clock) + return false; - return 0; + return phy->cfg->ops.set_continuous_clock(phy, enable); } void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 5b0feef87127..3cbf08231492 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -6,17 +6,13 @@ #ifndef __DSI_PHY_H__ #define __DSI_PHY_H__ +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/regulator/consumer.h> #include "dsi.h" -#define dsi_phy_read(offset) msm_readl((offset)) -#define dsi_phy_write(offset, data) msm_writel((data), (offset)) -#define dsi_phy_write_udelay(offset, data, delay_us) { msm_writel((data), (offset)); udelay(delay_us); } -#define dsi_phy_write_ndelay(offset, data, delay_ns) { msm_writel((data), (offset)); ndelay(delay_ns); } - struct msm_dsi_phy_ops { int (*pll_init)(struct msm_dsi_phy *phy); int (*enable)(struct msm_dsi_phy *phy, @@ -24,10 +20,13 @@ struct msm_dsi_phy_ops { void (*disable)(struct msm_dsi_phy *phy); void (*save_pll_state)(struct msm_dsi_phy *phy); int (*restore_pll_state)(struct msm_dsi_phy *phy); + bool (*set_continuous_clock)(struct msm_dsi_phy *phy, bool enable); + int (*parse_dt_properties)(struct msm_dsi_phy *phy); }; struct msm_dsi_phy_cfg { - struct dsi_reg_config reg_cfg; + const struct regulator_bulk_data *regulator_data; + int num_regulators; struct msm_dsi_phy_ops ops; unsigned long min_pll_rate; @@ -43,14 +42,28 @@ struct msm_dsi_phy_cfg { extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs; -extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8937_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_14nm_6150_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_7nm_6375_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8775p_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs; struct msm_dsi_dphy_timing { u32 clk_zero; @@ -75,9 +88,9 @@ struct msm_dsi_dphy_timing { u8 hs_halfbyte_en_ckln; }; -#define DSI_BYTE_PLL_CLK 0 -#define DSI_PIXEL_PLL_CLK 1 -#define NUM_PROVIDED_CLKS 2 +#define NUM_PROVIDED_CLKS (DSI_PIXEL_PLL_CLK + 1) + +#define DSI_LANE_MAX 5 struct msm_dsi_phy { struct platform_device *pdev; @@ -91,14 +104,15 @@ struct msm_dsi_phy { phys_addr_t lane_size; int id; - struct clk *ahb_clk; - struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX]; + struct regulator_bulk_data *supplies; struct msm_dsi_dphy_timing timing; const struct msm_dsi_phy_cfg *cfg; + void *tuning_cfg; enum msm_dsi_phy_usecase usecase; bool regulator_ldo_mode; + bool cphy_mode; struct clk_hw *vco_hw; bool pll_on; @@ -119,5 +133,7 @@ int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing, struct msm_dsi_phy_clk_request *clk_req); int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, struct msm_dsi_phy_clk_request *clk_req); +int msm_dsi_cphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, + struct msm_dsi_phy_clk_request *clk_req); #endif /* __DSI_PHY_H__ */ diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index e46b10fc793a..ec486ff02c9b 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -3,6 +3,7 @@ * Copyright (c) 2018, The Linux Foundation */ +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/iopoll.h> @@ -83,8 +84,20 @@ struct dsi_pll_10nm { #define to_pll_10nm(x) container_of(x, struct dsi_pll_10nm, clk_hw) +/** + * struct dsi_phy_10nm_tuning_cfg - Holds 10nm PHY tuning config parameters. + * @rescode_offset_top: Offset for pull-up legs rescode. + * @rescode_offset_bot: Offset for pull-down legs rescode. + * @vreg_ctrl: vreg ctrl to drive LDO level + */ +struct dsi_phy_10nm_tuning_cfg { + u8 rescode_offset_top[DSI_LANE_MAX]; + u8 rescode_offset_bot[DSI_LANE_MAX]; + u8 vreg_ctrl; +}; + /* - * Global list of private DSI PLL struct pointers. We need this for Dual DSI + * Global list of private DSI PLL struct pointers. We need this for bonded DSI * mode, where the master PLL's clk_ops needs access the slave's private data */ static struct dsi_pll_10nm *pll_10nm_list[DSI_MAX]; @@ -175,20 +188,20 @@ static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll, struct dsi_pll_config * if (config->enable_ssc) { pr_debug("SSC is enabled\n"); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1, - config->ssc_stepsize & 0xff); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1, - config->ssc_stepsize >> 8); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1, - config->ssc_div_per & 0xff); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1, - config->ssc_div_per >> 8); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1, - config->ssc_adj_per & 0xff); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1, - config->ssc_adj_per >> 8); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL, - SSC_EN | (config->ssc_center ? SSC_CENTER : 0)); + writel(config->ssc_stepsize & 0xff, + base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1); + writel(config->ssc_stepsize >> 8, + base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1); + writel(config->ssc_div_per & 0xff, + base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1); + writel(config->ssc_div_per >> 8, + base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1); + writel(config->ssc_adj_per & 0xff, + base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1); + writel(config->ssc_adj_per >> 8, + base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1); + writel(SSC_EN | (config->ssc_center ? SSC_CENTER : 0), + base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL); } } @@ -196,46 +209,43 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_10nm *pll) { void __iomem *base = pll->phy->pll_base; - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE, 0x80); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_DSM_DIVIDER, 0x00); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE, - 0xba); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_OUTDIV, 0x00); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE, 0x00); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x08); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1, 0xc0); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0xfa); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, - 0x4c); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PFILT, 0x29); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_IFILT, 0x3f); + writel(0x80, base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE); + writel(0x03, base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO); + writel(0x00, base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE); + writel(0x00, base + REG_DSI_10nm_PHY_PLL_DSM_DIVIDER); + writel(0x4e, base + REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER); + writel(0x40, base + REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS); + writel(0xba, base + REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE); + writel(0x0c, base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE); + writel(0x00, base + REG_DSI_10nm_PHY_PLL_OUTDIV); + writel(0x00, base + REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE); + writel(0x08, base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO); + writel(0x08, base + REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1); + writel(0xc0, base + REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1); + writel(0xfa, base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1); + writel(0x4c, base + REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1); + writel(0x80, base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE); + writel(0x29, base + REG_DSI_10nm_PHY_PLL_PFILT); + writel(0x3f, base + REG_DSI_10nm_PHY_PLL_IFILT); } static void dsi_pll_commit(struct dsi_pll_10nm *pll, struct dsi_pll_config *config) { void __iomem *base = pll->phy->pll_base; - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1, - config->decimal_div_start); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1, - config->frac_div_start & 0xff); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1, - (config->frac_div_start & 0xff00) >> 8); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1, - (config->frac_div_start & 0x30000) >> 16); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1, 64); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY, 0x06); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CMODE, 0x10); - dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS, - config->pll_clock_inverters); + writel(0x12, base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE); + writel(config->decimal_div_start, + base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1); + writel(config->frac_div_start & 0xff, + base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1); + writel((config->frac_div_start & 0xff00) >> 8, + base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1); + writel((config->frac_div_start & 0x30000) >> 16, + base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1); + writel(64, base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1); + writel(0x06, base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY); + writel(0x10, base + REG_DSI_10nm_PHY_PLL_CMODE); + writel(config->pll_clock_inverters, base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS); } static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, @@ -290,21 +300,19 @@ static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll) static void dsi_pll_disable_pll_bias(struct dsi_pll_10nm *pll) { - u32 data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0); + u32 data = readl(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0); - dsi_phy_write(pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0); - dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0, - data & ~BIT(5)); + writel(0, pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES); + writel(data & ~BIT(5), pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0); ndelay(250); } static void dsi_pll_enable_pll_bias(struct dsi_pll_10nm *pll) { - u32 data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0); + u32 data = readl(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0); - dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0, - data | BIT(5)); - dsi_phy_write(pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0xc0); + writel(data | BIT(5), pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0); + writel(0xc0, pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES); ndelay(250); } @@ -312,18 +320,16 @@ static void dsi_pll_disable_global_clk(struct dsi_pll_10nm *pll) { u32 data; - data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); - dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, - data & ~BIT(5)); + data = readl(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); + writel(data & ~BIT(5), pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); } static void dsi_pll_enable_global_clk(struct dsi_pll_10nm *pll) { u32 data; - data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); - dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, - data | BIT(5)); + data = readl(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); + writel(data | BIT(5), pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); } static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw) @@ -343,8 +349,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw) } /* Start PLL */ - dsi_phy_write(pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, - 0x01); + writel(0x01, pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL); /* * ensure all PLL configurations are written prior to checking @@ -365,11 +370,9 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw) if (pll_10nm->slave) dsi_pll_enable_global_clk(pll_10nm->slave); - dsi_phy_write(pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, - 0x01); + writel(0x01, pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL); if (pll_10nm->slave) - dsi_phy_write(pll_10nm->slave->phy->base + - REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0x01); + writel(0x01, pll_10nm->slave->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL); error: return rc; @@ -377,7 +380,7 @@ error: static void dsi_pll_disable_sub(struct dsi_pll_10nm *pll) { - dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0); + writel(0, pll->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL); dsi_pll_disable_pll_bias(pll); } @@ -391,7 +394,7 @@ static void dsi_pll_10nm_vco_unprepare(struct clk_hw *hw) * powering down the PLL */ dsi_pll_disable_global_clk(pll_10nm); - dsi_phy_write(pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0); + writel(0, pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL); dsi_pll_disable_sub(pll_10nm); if (pll_10nm->slave) { dsi_pll_disable_global_clk(pll_10nm->slave); @@ -414,13 +417,13 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw, u32 dec; u64 pll_freq, tmp64; - dec = dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1); + dec = readl(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1); dec &= 0xff; - frac = dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1); - frac |= ((dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1) & + frac = readl(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1); + frac |= ((readl(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1) & 0xff) << 8); - frac |= ((dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1) & + frac |= ((readl(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1) & 0x3) << 16); /* @@ -441,21 +444,19 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw, return (unsigned long)vco_rate; } -static long dsi_pll_10nm_clk_round_rate(struct clk_hw *hw, - unsigned long rate, unsigned long *parent_rate) +static int dsi_pll_10nm_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw); - if (rate < pll_10nm->phy->cfg->min_pll_rate) - return pll_10nm->phy->cfg->min_pll_rate; - else if (rate > pll_10nm->phy->cfg->max_pll_rate) - return pll_10nm->phy->cfg->max_pll_rate; - else - return rate; + req->rate = clamp_t(unsigned long, req->rate, + pll_10nm->phy->cfg->min_pll_rate, pll_10nm->phy->cfg->max_pll_rate); + + return 0; } static const struct clk_ops clk_ops_dsi_pll_10nm_vco = { - .round_rate = dsi_pll_10nm_clk_round_rate, + .determine_rate = dsi_pll_10nm_clk_determine_rate, .set_rate = dsi_pll_10nm_vco_set_rate, .recalc_rate = dsi_pll_10nm_vco_recalc_rate, .prepare = dsi_pll_10nm_vco_prepare, @@ -473,15 +474,15 @@ static void dsi_10nm_pll_save_state(struct msm_dsi_phy *phy) void __iomem *phy_base = pll_10nm->phy->base; u32 cmn_clk_cfg0, cmn_clk_cfg1; - cached->pll_out_div = dsi_phy_read(pll_10nm->phy->pll_base + - REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); + cached->pll_out_div = readl(pll_10nm->phy->pll_base + + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); cached->pll_out_div &= 0x3; - cmn_clk_cfg0 = dsi_phy_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0); + cmn_clk_cfg0 = readl(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0); cached->bit_clk_div = cmn_clk_cfg0 & 0xf; cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4; - cmn_clk_cfg1 = dsi_phy_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); + cmn_clk_cfg1 = readl(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); cached->pll_mux = cmn_clk_cfg1 & 0x3; DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x", @@ -497,18 +498,18 @@ static int dsi_10nm_pll_restore_state(struct msm_dsi_phy *phy) u32 val; int ret; - val = dsi_phy_read(pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); + val = readl(pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); val &= ~0x3; val |= cached->pll_out_div; - dsi_phy_write(pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, val); + writel(val, pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); - dsi_phy_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0, - cached->bit_clk_div | (cached->pix_clk_div << 4)); + writel(cached->bit_clk_div | (cached->pix_clk_div << 4), + phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0); - val = dsi_phy_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); + val = readl(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); val &= ~0x3; val |= cached->pll_mux; - dsi_phy_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val); + writel(val, phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); ret = dsi_pll_10nm_vco_set_rate(phy->vco_hw, pll_10nm->vco_current_rate, @@ -546,7 +547,7 @@ static int dsi_10nm_set_usecase(struct msm_dsi_phy *phy) } /* set PLL src */ - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, (data << 2)); + writel(data << 2, base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); return 0; } @@ -559,62 +560,59 @@ static int dsi_10nm_set_usecase(struct msm_dsi_phy *phy) */ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **provided_clocks) { - char clk_name[32], parent[32], vco_name[32]; - char parent2[32], parent3[32], parent4[32]; + char clk_name[32]; struct clk_init_data vco_init = { - .parent_names = (const char *[]){ "xo" }, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "ref", + }, .num_parents = 1, - .name = vco_name, + .name = clk_name, .flags = CLK_IGNORE_UNUSED, .ops = &clk_ops_dsi_pll_10nm_vco, }; struct device *dev = &pll_10nm->phy->pdev->dev; - struct clk_hw *hw; + struct clk_hw *hw, *pll_out_div, *pll_bit, *pll_by_2_bit; + struct clk_hw *pll_post_out_div, *pclk_mux; int ret; DBG("DSI%d", pll_10nm->phy->id); - snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->phy->id); + snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_10nm->phy->id); pll_10nm->clk_hw.init = &vco_init; ret = devm_clk_hw_register(dev, &pll_10nm->clk_hw); if (ret) return ret; - snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id); - snprintf(parent, 32, "dsi%dvco_clk", pll_10nm->phy->id); + snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_out_div_clk", pll_10nm->phy->id); - hw = devm_clk_hw_register_divider(dev, clk_name, - parent, CLK_SET_RATE_PARENT, - pll_10nm->phy->pll_base + - REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, - 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); + pll_out_div = devm_clk_hw_register_divider_parent_hw(dev, clk_name, + &pll_10nm->clk_hw, CLK_SET_RATE_PARENT, + pll_10nm->phy->pll_base + + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, + 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL); + if (IS_ERR(pll_out_div)) { + ret = PTR_ERR(pll_out_div); goto fail; } - snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id); - snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id); + snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_bit_clk", pll_10nm->phy->id); /* BIT CLK: DIV_CTRL_3_0 */ - hw = devm_clk_hw_register_divider(dev, clk_name, parent, - CLK_SET_RATE_PARENT, - pll_10nm->phy->base + - REG_DSI_10nm_PHY_CMN_CLK_CFG0, - 0, 4, CLK_DIVIDER_ONE_BASED, - &pll_10nm->postdiv_lock); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); + pll_bit = devm_clk_hw_register_divider_parent_hw(dev, clk_name, + pll_out_div, CLK_SET_RATE_PARENT, + pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG0, + 0, 4, CLK_DIVIDER_ONE_BASED, &pll_10nm->postdiv_lock); + if (IS_ERR(pll_bit)) { + ret = PTR_ERR(pll_bit); goto fail; } - snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->phy->id); - snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id); + snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_byteclk", pll_10nm->phy->id); /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */ - hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, - CLK_SET_RATE_PARENT, 1, 8); + hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, clk_name, + pll_bit, CLK_SET_RATE_PARENT, 1, 8); if (IS_ERR(hw)) { ret = PTR_ERR(hw); goto fail; @@ -622,52 +620,45 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov provided_clocks[DSI_BYTE_PLL_CLK] = hw; - snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->phy->id); - snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id); + snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_by_2_bit_clk", pll_10nm->phy->id); - hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, - 0, 1, 2); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); + pll_by_2_bit = devm_clk_hw_register_fixed_factor_parent_hw(dev, + clk_name, pll_bit, 0, 1, 2); + if (IS_ERR(pll_by_2_bit)) { + ret = PTR_ERR(pll_by_2_bit); goto fail; } - snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->phy->id); - snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id); + snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_post_out_div_clk", pll_10nm->phy->id); - hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, - 0, 1, 4); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); + pll_post_out_div = devm_clk_hw_register_fixed_factor_parent_hw(dev, + clk_name, pll_out_div, 0, 1, 4); + if (IS_ERR(pll_post_out_div)) { + ret = PTR_ERR(pll_post_out_div); goto fail; } - snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_10nm->phy->id); - snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id); - snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->phy->id); - snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id); - snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->phy->id); - - hw = devm_clk_hw_register_mux(dev, clk_name, - ((const char *[]){ - parent, parent2, parent3, parent4 - }), 4, 0, pll_10nm->phy->base + - REG_DSI_10nm_PHY_CMN_CLK_CFG1, - 0, 2, 0, NULL); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); + snprintf(clk_name, sizeof(clk_name), "dsi%d_pclk_mux", pll_10nm->phy->id); + + pclk_mux = devm_clk_hw_register_mux_parent_hws(dev, clk_name, + ((const struct clk_hw *[]){ + pll_bit, + pll_by_2_bit, + pll_out_div, + pll_post_out_div, + }), 4, 0, pll_10nm->phy->base + + REG_DSI_10nm_PHY_CMN_CLK_CFG1, 0, 2, 0, NULL); + if (IS_ERR(pclk_mux)) { + ret = PTR_ERR(pclk_mux); goto fail; } - snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->phy->id); - snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->phy->id); + snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_dsiclk", pll_10nm->phy->id); /* PIX CLK DIV : DIV_CTRL_7_4*/ - hw = devm_clk_hw_register_divider(dev, clk_name, parent, - 0, pll_10nm->phy->base + - REG_DSI_10nm_PHY_CMN_CLK_CFG0, - 4, 4, CLK_DIVIDER_ONE_BASED, - &pll_10nm->postdiv_lock); + hw = devm_clk_hw_register_divider_parent_hw(dev, clk_name, pclk_mux, + 0, pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG0, + 4, 4, CLK_DIVIDER_ONE_BASED, &pll_10nm->postdiv_lock); if (IS_ERR(hw)) { ret = PTR_ERR(hw); goto fail; @@ -711,6 +702,13 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy) /* TODO: Remove this when we have proper display handover support */ msm_dsi_phy_pll_save_state(phy); + /* + * Store also proper vco_current_rate, because its value will be used in + * dsi_10nm_pll_restore_state(). + */ + if (!dsi_pll_10nm_vco_recalc_rate(&pll_10nm->clk_hw, VCO_REF_CLK_RATE)) + pll_10nm->vco_current_rate = pll_10nm->phy->cfg->min_pll_rate; + return 0; } @@ -719,7 +717,7 @@ static int dsi_phy_hw_v3_0_is_pll_on(struct msm_dsi_phy *phy) void __iomem *base = phy->base; u32 data = 0; - data = dsi_phy_read(base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL); + data = readl(base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL); mb(); /* make sure read happened */ return (data & BIT(0)); @@ -735,11 +733,9 @@ static void dsi_phy_hw_v3_0_config_lpcdrx(struct msm_dsi_phy *phy, bool enable) * corresponding to the logical data lane 0 */ if (enable) - dsi_phy_write(lane_base + - REG_DSI_10nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0x3); + writel(0x3, lane_base + REG_DSI_10nm_PHY_LN_LPRX_CTRL(phy_lane_0)); else - dsi_phy_write(lane_base + - REG_DSI_10nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0); + writel(0, lane_base + REG_DSI_10nm_PHY_LN_LPRX_CTRL(phy_lane_0)); } static void dsi_phy_hw_v3_0_lane_settings(struct msm_dsi_phy *phy) @@ -747,46 +743,47 @@ static void dsi_phy_hw_v3_0_lane_settings(struct msm_dsi_phy *phy) int i; u8 tx_dctrl[] = { 0x00, 0x00, 0x00, 0x04, 0x01 }; void __iomem *lane_base = phy->lane_base; + struct dsi_phy_10nm_tuning_cfg *tuning_cfg = phy->tuning_cfg; if (phy->cfg->quirks & DSI_PHY_10NM_QUIRK_OLD_TIMINGS) tx_dctrl[3] = 0x02; /* Strength ctrl settings */ for (i = 0; i < 5; i++) { - dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(i), - 0x55); + writel(0x55, lane_base + REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(i)); /* * Disable LPRX and CDRX for all lanes. And later on, it will * be only enabled for the physical data lane corresponding * to the logical data lane 0 */ - dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_LPRX_CTRL(i), 0); - dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_PIN_SWAP(i), 0x0); - dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(i), - 0x88); + writel(0, lane_base + REG_DSI_10nm_PHY_LN_LPRX_CTRL(i)); + writel(0x0, lane_base + REG_DSI_10nm_PHY_LN_PIN_SWAP(i)); + writel(0x88, lane_base + REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(i)); } dsi_phy_hw_v3_0_config_lpcdrx(phy, true); /* other settings */ for (i = 0; i < 5; i++) { - dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG0(i), 0x0); - dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG1(i), 0x0); - dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG2(i), 0x0); - dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG3(i), - i == 4 ? 0x80 : 0x0); - dsi_phy_write(lane_base + - REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(i), 0x0); - dsi_phy_write(lane_base + - REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(i), 0x0); - dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(i), - tx_dctrl[i]); + writel(0, lane_base + REG_DSI_10nm_PHY_LN_CFG0(i)); + writel(0, lane_base + REG_DSI_10nm_PHY_LN_CFG1(i)); + writel(0, lane_base + REG_DSI_10nm_PHY_LN_CFG2(i)); + writel(i == 4 ? 0x80 : 0x0, lane_base + REG_DSI_10nm_PHY_LN_CFG3(i)); + + /* platform specific dsi phy drive strength adjustment */ + writel(tuning_cfg->rescode_offset_top[i], + lane_base + REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(i)); + writel(tuning_cfg->rescode_offset_bot[i], + lane_base + REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(i)); + + writel(tx_dctrl[i], + lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(i)); } if (!(phy->cfg->quirks & DSI_PHY_10NM_QUIRK_OLD_TIMINGS)) { /* Toggle BIT 0 to release freeze I/0 */ - dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x05); - dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x04); + writel(0x05, lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3)); + writel(0x04, lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3)); } } @@ -799,6 +796,7 @@ static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy, u32 const timeout_us = 1000; struct msm_dsi_dphy_timing *timing = &phy->timing; void __iomem *base = phy->base; + struct dsi_phy_10nm_tuning_cfg *tuning_cfg = phy->tuning_cfg; u32 data; DBG(""); @@ -823,63 +821,51 @@ static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy, /* de-assert digital and pll power down */ data = BIT(6) | BIT(5); - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, data); + writel(data, base + REG_DSI_10nm_PHY_CMN_CTRL_0); /* Assert PLL core reset */ - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0x00); + writel(0x00, base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL); /* turn off resync FIFO */ - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0x00); + writel(0x00, base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL); /* Select MS1 byte-clk */ - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_GLBL_CTRL, 0x10); + writel(0x10, base + REG_DSI_10nm_PHY_CMN_GLBL_CTRL); - /* Enable LDO */ - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_VREG_CTRL, 0x59); + /* Enable LDO with platform specific drive level/amplitude adjustment */ + writel(tuning_cfg->vreg_ctrl, base + REG_DSI_10nm_PHY_CMN_VREG_CTRL); /* Configure PHY lane swap (TODO: we need to calculate this) */ - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_LANE_CFG0, 0x21); - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_LANE_CFG1, 0x84); + writel(0x21, base + REG_DSI_10nm_PHY_CMN_LANE_CFG0); + writel(0x84, base + REG_DSI_10nm_PHY_CMN_LANE_CFG1); /* DSI PHY timings */ - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0, - timing->hs_halfbyte_en); - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1, - timing->clk_zero); - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2, - timing->clk_prepare); - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3, - timing->clk_trail); - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4, - timing->hs_exit); - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5, - timing->hs_zero); - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6, - timing->hs_prepare); - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7, - timing->hs_trail); - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8, - timing->hs_rqst); - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9, - timing->ta_go | (timing->ta_sure << 3)); - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10, - timing->ta_get); - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11, - 0x00); + writel(timing->hs_halfbyte_en, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0); + writel(timing->clk_zero, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1); + writel(timing->clk_prepare, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2); + writel(timing->clk_trail, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3); + writel(timing->hs_exit, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4); + writel(timing->hs_zero, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5); + writel(timing->hs_prepare, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6); + writel(timing->hs_trail, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7); + writel(timing->hs_rqst, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8); + writel(timing->ta_go | (timing->ta_sure << 3), base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9); + writel(timing->ta_get, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10); + writel(0x00, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11); /* Remove power down from all blocks */ - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, 0x7f); + writel(0x7f, base + REG_DSI_10nm_PHY_CMN_CTRL_0); /* power up lanes */ - data = dsi_phy_read(base + REG_DSI_10nm_PHY_CMN_CTRL_0); + data = readl(base + REG_DSI_10nm_PHY_CMN_CTRL_0); /* TODO: only power up lanes that are used */ data |= 0x1F; - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, data); - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_LANE_CTRL0, 0x1F); + writel(data, base + REG_DSI_10nm_PHY_CMN_CTRL_0); + writel(0x1F, base + REG_DSI_10nm_PHY_CMN_LANE_CTRL0); /* Select full-rate mode */ - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_2, 0x40); + writel(0x40, base + REG_DSI_10nm_PHY_CMN_CTRL_2); ret = dsi_10nm_set_usecase(phy); if (ret) { @@ -907,35 +893,122 @@ static void dsi_10nm_phy_disable(struct msm_dsi_phy *phy) pr_warn("Turning OFF PHY while PLL is on\n"); dsi_phy_hw_v3_0_config_lpcdrx(phy, false); - data = dsi_phy_read(base + REG_DSI_10nm_PHY_CMN_CTRL_0); + data = readl(base + REG_DSI_10nm_PHY_CMN_CTRL_0); /* disable all lanes */ data &= ~0x1F; - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, data); - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_LANE_CTRL0, 0); + writel(data, base + REG_DSI_10nm_PHY_CMN_CTRL_0); + writel(0, base + REG_DSI_10nm_PHY_CMN_LANE_CTRL0); /* Turn off all PHY blocks */ - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, 0x00); + writel(0x00, base + REG_DSI_10nm_PHY_CMN_CTRL_0); /* make sure phy is turned off */ wmb(); DBG("DSI%d PHY disabled", phy->id); } +static int dsi_10nm_phy_parse_dt(struct msm_dsi_phy *phy) +{ + struct device *dev = &phy->pdev->dev; + struct dsi_phy_10nm_tuning_cfg *tuning_cfg; + s8 offset_top[DSI_LANE_MAX] = { 0 }; /* No offset */ + s8 offset_bot[DSI_LANE_MAX] = { 0 }; /* No offset */ + u32 ldo_level = 400; /* 400mV */ + u8 level; + int ret, i; + + tuning_cfg = devm_kzalloc(dev, sizeof(*tuning_cfg), GFP_KERNEL); + if (!tuning_cfg) + return -ENOMEM; + + /* Drive strength adjustment parameters */ + ret = of_property_read_u8_array(dev->of_node, "qcom,phy-rescode-offset-top", + offset_top, DSI_LANE_MAX); + if (ret && ret != -EINVAL) { + DRM_DEV_ERROR(dev, "failed to parse qcom,phy-rescode-offset-top, %d\n", ret); + return ret; + } + + for (i = 0; i < DSI_LANE_MAX; i++) { + if (offset_top[i] < -32 || offset_top[i] > 31) { + DRM_DEV_ERROR(dev, + "qcom,phy-rescode-offset-top value %d is not in range [-32..31]\n", + offset_top[i]); + return -EINVAL; + } + tuning_cfg->rescode_offset_top[i] = 0x3f & offset_top[i]; + } + + ret = of_property_read_u8_array(dev->of_node, "qcom,phy-rescode-offset-bot", + offset_bot, DSI_LANE_MAX); + if (ret && ret != -EINVAL) { + DRM_DEV_ERROR(dev, "failed to parse qcom,phy-rescode-offset-bot, %d\n", ret); + return ret; + } + + for (i = 0; i < DSI_LANE_MAX; i++) { + if (offset_bot[i] < -32 || offset_bot[i] > 31) { + DRM_DEV_ERROR(dev, + "qcom,phy-rescode-offset-bot value %d is not in range [-32..31]\n", + offset_bot[i]); + return -EINVAL; + } + tuning_cfg->rescode_offset_bot[i] = 0x3f & offset_bot[i]; + } + + /* Drive level/amplitude adjustment parameters */ + ret = of_property_read_u32(dev->of_node, "qcom,phy-drive-ldo-level", &ldo_level); + if (ret && ret != -EINVAL) { + DRM_DEV_ERROR(dev, "failed to parse qcom,phy-drive-ldo-level, %d\n", ret); + return ret; + } + + switch (ldo_level) { + case 375: + level = 0; + break; + case 400: + level = 1; + break; + case 425: + level = 2; + break; + case 450: + level = 3; + break; + case 475: + level = 4; + break; + case 500: + level = 5; + break; + default: + DRM_DEV_ERROR(dev, "qcom,phy-drive-ldo-level %d is not supported\n", ldo_level); + return -EINVAL; + } + tuning_cfg->vreg_ctrl = 0x58 | (0x7 & level); + + phy->tuning_cfg = tuning_cfg; + + return 0; +} + +static const struct regulator_bulk_data dsi_phy_10nm_regulators[] = { + { .supply = "vdds", .init_load_uA = 36000 }, +}; + const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = { .has_phy_lane = true, - .reg_cfg = { - .num = 1, - .regs = { - {"vdds", 36000, 32}, - }, - }, + .regulator_data = dsi_phy_10nm_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_10nm_regulators), .ops = { .enable = dsi_10nm_phy_enable, .disable = dsi_10nm_phy_disable, .pll_init = dsi_pll_10nm_init, .save_pll_state = dsi_10nm_pll_save_state, .restore_pll_state = dsi_10nm_pll_restore_state, + .parse_dt_properties = dsi_10nm_phy_parse_dt, }, .min_pll_rate = 1000000000UL, .max_pll_rate = 3500000000UL, @@ -945,18 +1018,15 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = { const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = { .has_phy_lane = true, - .reg_cfg = { - .num = 1, - .regs = { - {"vdds", 36000, 32}, - }, - }, + .regulator_data = dsi_phy_10nm_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_10nm_regulators), .ops = { .enable = dsi_10nm_phy_enable, .disable = dsi_10nm_phy_disable, .pll_init = dsi_pll_10nm_init, .save_pll_state = dsi_10nm_pll_save_state, .restore_pll_state = dsi_10nm_pll_restore_state, + .parse_dt_properties = dsi_10nm_phy_parse_dt, }, .min_pll_rate = 1000000000UL, .max_pll_rate = 3500000000UL, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index a34cf151c517..fdefcbd9c284 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, The Linux Foundation. All rights reserved. */ +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/delay.h> @@ -86,7 +87,7 @@ struct dsi_pll_14nm { /* * Private struct for N1/N2 post-divider clocks. These clocks are similar to * the generic clk_divider class of clocks. The only difference is that it - * also sets the slave DSI PLL's post-dividers if in Dual DSI mode + * also sets the slave DSI PLL's post-dividers if in bonded DSI mode */ struct dsi_pll_14nm_postdiv { struct clk_hw hw; @@ -102,7 +103,7 @@ struct dsi_pll_14nm_postdiv { #define to_pll_14nm_postdiv(_hw) container_of(_hw, struct dsi_pll_14nm_postdiv, hw) /* - * Global list of private DSI PLL struct pointers. We need this for Dual DSI + * Global list of private DSI PLL struct pointers. We need this for bonded DSI * mode, where the master PLL's clk_ops needs access the slave's private data */ static struct dsi_pll_14nm *pll_14nm_list[DSI_MAX]; @@ -110,14 +111,13 @@ static struct dsi_pll_14nm *pll_14nm_list[DSI_MAX]; static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm, u32 nb_tries, u32 timeout_us) { - bool pll_locked = false; + bool pll_locked = false, pll_ready = false; void __iomem *base = pll_14nm->phy->pll_base; u32 tries, val; tries = nb_tries; while (tries--) { - val = dsi_phy_read(base + - REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS); + val = readl(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS); pll_locked = !!(val & BIT(5)); if (pll_locked) @@ -126,23 +126,24 @@ static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm, udelay(timeout_us); } - if (!pll_locked) { - tries = nb_tries; - while (tries--) { - val = dsi_phy_read(base + - REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS); - pll_locked = !!(val & BIT(0)); + if (!pll_locked) + goto out; - if (pll_locked) - break; + tries = nb_tries; + while (tries--) { + val = readl(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS); + pll_ready = !!(val & BIT(0)); + + if (pll_ready) + break; - udelay(timeout_us); - } + udelay(timeout_us); } - DBG("DSI PLL is %slocked", pll_locked ? "" : "*not* "); +out: + DBG("DSI PLL is %slocked, %sready", pll_locked ? "" : "*not* ", pll_ready ? "" : "*not* "); - return pll_locked; + return pll_locked && pll_ready; } static void dsi_pll_14nm_config_init(struct dsi_pll_config *pconf) @@ -213,9 +214,7 @@ static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll, struct dsi_pll_conf DBG("vco_clk_rate=%lld ref_clk_rate=%lld", vco_clk_rate, fref); dec_start_multiple = div_u64(vco_clk_rate * multiplier, fref); - div_u64_rem(dec_start_multiple, multiplier, &div_frac_start); - - dec_start = div_u64(dec_start_multiple, multiplier); + dec_start = div_u64_rem(dec_start_multiple, multiplier, &div_frac_start); pconf->dec_start = (u32)dec_start; pconf->div_frac_start = div_frac_start; @@ -290,29 +289,29 @@ static void pll_db_commit_ssc(struct dsi_pll_14nm *pll, struct dsi_pll_config *p data = pconf->ssc_adj_period; data &= 0x0ff; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data); + writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1); data = (pconf->ssc_adj_period >> 8); data &= 0x03; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data); + writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2); data = pconf->ssc_period; data &= 0x0ff; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data); + writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_PER1); data = (pconf->ssc_period >> 8); data &= 0x0ff; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data); + writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_PER2); data = pconf->ssc_step_size; data &= 0x0ff; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data); + writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1); data = (pconf->ssc_step_size >> 8); data &= 0x0ff; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data); + writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2); data = (pconf->ssc_center & 0x01); data <<= 1; data |= 0x01; /* enable */ - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data); + writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER); wmb(); /* make sure register committed */ } @@ -325,43 +324,45 @@ static void pll_db_commit_common(struct dsi_pll_14nm *pll, /* confgiure the non frequency dependent pll registers */ data = 0; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data); + writel(data, base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET); - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, 1); + writel(1, base + REG_DSI_14nm_PHY_PLL_TXCLK_EN); - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, 48); - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, 4 << 3); /* bandgap_timer */ - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, 5); /* pll_wakeup_timer */ + writel(48, base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL); + /* bandgap_timer */ + writel(4 << 3, base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2); + /* pll_wakeup_timer */ + writel(5, base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5); data = pconf->pll_vco_div_ref & 0xff; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1, data); + writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1); data = (pconf->pll_vco_div_ref >> 8) & 0x3; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2, data); + writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2); data = pconf->pll_kvco_div_ref & 0xff; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1, data); + writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1); data = (pconf->pll_kvco_div_ref >> 8) & 0x3; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2, data); + writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2); - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, 16); + writel(16, base + REG_DSI_14nm_PHY_PLL_PLL_MISC1); - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, 4); + writel(4, base + REG_DSI_14nm_PHY_PLL_IE_TRIM); - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, 4); + writel(4, base + REG_DSI_14nm_PHY_PLL_IP_TRIM); - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, 1 << 3 | 1); + writel(1 << 3 | 1, base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR); - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, 0 << 3 | 0); + writel(0 << 3 | 0, base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET); - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, 0 << 3 | 0); + writel(0 << 3 | 0, base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET); - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, 4 << 3 | 4); + writel(4 << 3 | 4, base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET); - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, 1 << 4 | 11); + writel(1 << 4 | 11, base + REG_DSI_14nm_PHY_PLL_PLL_LPF1); - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, 7); + writel(7, base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM); - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, 1 << 4 | 2); + writel(1 << 4 | 2, base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL); } static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm) @@ -371,13 +372,14 @@ static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm) /* de assert pll start and apply pll sw reset */ /* stop pll */ - dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0); + writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL); /* pll sw reset */ - dsi_phy_write_udelay(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x20, 10); + writel(0x20, cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1); + udelay(10); wmb(); /* make sure register committed */ - dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0); + writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1); wmb(); /* make sure register committed */ } @@ -390,50 +392,50 @@ static void pll_db_commit_14nm(struct dsi_pll_14nm *pll, DBG("DSI%d PLL", pll->phy->id); - dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, 0x3c); + writel(0x3c, cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL); pll_db_commit_common(pll, pconf); pll_14nm_software_reset(pll); /* Use the /2 path in Mux */ - dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, 1); + writel(1, cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1); data = 0xff; /* data, clk, pll normal operation */ - dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0, data); + writel(data, cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0); /* configure the frequency dependent pll registers */ data = pconf->dec_start; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DEC_START, data); + writel(data, base + REG_DSI_14nm_PHY_PLL_DEC_START); data = pconf->div_frac_start & 0xff; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1, data); + writel(data, base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1); data = (pconf->div_frac_start >> 8) & 0xff; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2, data); + writel(data, base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2); data = (pconf->div_frac_start >> 16) & 0xf; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3, data); + writel(data, base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3); data = pconf->plllock_cmp & 0xff; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1, data); + writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1); data = (pconf->plllock_cmp >> 8) & 0xff; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2, data); + writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2); data = (pconf->plllock_cmp >> 16) & 0x3; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3, data); + writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3); data = pconf->plllock_cnt << 1 | 0 << 3; /* plllock_rng */ - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN, data); + writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN); data = pconf->pll_vco_count & 0xff; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1, data); + writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1); data = (pconf->pll_vco_count >> 8) & 0xff; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2, data); + writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2); data = pconf->pll_kvco_count & 0xff; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1, data); + writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1); data = (pconf->pll_kvco_count >> 8) & 0x3; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2, data); + writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2); /* * High nibble configures the post divider internal to the VCO. It's @@ -444,7 +446,7 @@ static void pll_db_commit_14nm(struct dsi_pll_14nm *pll, * 2: divided by 4 * 3: divided by 8 */ - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, 0 << 4 | 3); + writel(0 << 4 | 3, base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV); if (pconf->ssc_en) pll_db_commit_ssc(pll, pconf); @@ -499,16 +501,16 @@ static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw, u32 dec_start; u64 ref_clk = parent_rate; - dec_start = dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DEC_START); + dec_start = readl(base + REG_DSI_14nm_PHY_PLL_DEC_START); dec_start &= 0x0ff; DBG("dec_start = %x", dec_start); - div_frac_start = (dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3) + div_frac_start = (readl(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3) & 0xf) << 16; - div_frac_start |= (dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2) + div_frac_start |= (readl(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2) & 0xff) << 8; - div_frac_start |= dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1) + div_frac_start |= readl(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1) & 0xff; DBG("div_frac_start = %x", div_frac_start); @@ -541,8 +543,11 @@ static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw) if (unlikely(pll_14nm->phy->pll_on)) return 0; - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10); - dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1); + if (dsi_pll_14nm_vco_recalc_rate(hw, VCO_REF_CLK_RATE) == 0) + dsi_pll_14nm_vco_set_rate(hw, pll_14nm->phy->cfg->min_pll_rate, VCO_REF_CLK_RATE); + + writel(0x10, base + REG_DSI_14nm_PHY_PLL_VREF_CFG1); + writel(1, cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL); locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS, POLL_TIMEOUT_US); @@ -568,26 +573,24 @@ static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw) if (unlikely(!pll_14nm->phy->pll_on)) return; - dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0); + writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL); pll_14nm->phy->pll_on = false; } -static long dsi_pll_14nm_clk_round_rate(struct clk_hw *hw, - unsigned long rate, unsigned long *parent_rate) +static int dsi_pll_14nm_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); - if (rate < pll_14nm->phy->cfg->min_pll_rate) - return pll_14nm->phy->cfg->min_pll_rate; - else if (rate > pll_14nm->phy->cfg->max_pll_rate) - return pll_14nm->phy->cfg->max_pll_rate; - else - return rate; + req->rate = clamp_t(unsigned long, req->rate, + pll_14nm->phy->cfg->min_pll_rate, pll_14nm->phy->cfg->max_pll_rate); + + return 0; } static const struct clk_ops clk_ops_dsi_pll_14nm_vco = { - .round_rate = dsi_pll_14nm_clk_round_rate, + .determine_rate = dsi_pll_14nm_clk_determine_rate, .set_rate = dsi_pll_14nm_vco_set_rate, .recalc_rate = dsi_pll_14nm_vco_recalc_rate, .prepare = dsi_pll_14nm_vco_prepare, @@ -610,25 +613,27 @@ static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw, DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, parent_rate); - val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift; + val = readl(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift; val &= div_mask(width); return divider_recalc_rate(hw, parent_rate, val, NULL, postdiv->flags, width); } -static long dsi_pll_14nm_postdiv_round_rate(struct clk_hw *hw, - unsigned long rate, - unsigned long *prate) +static int dsi_pll_14nm_postdiv_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); struct dsi_pll_14nm *pll_14nm = postdiv->pll; - DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, rate); + DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, req->rate); - return divider_round_rate(hw, rate, prate, NULL, - postdiv->width, - postdiv->flags); + req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate, + NULL, + postdiv->width, + postdiv->flags); + + return 0; } static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, @@ -652,20 +657,20 @@ static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, spin_lock_irqsave(lock, flags); - val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); + val = readl(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); val &= ~(div_mask(width) << shift); val |= value << shift; - dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val); + writel(val, base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); - /* If we're master in dual DSI mode, then the slave PLL's post-dividers + /* If we're master in bonded DSI mode, then the slave PLL's post-dividers * follow the master's post dividers */ if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) { struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; void __iomem *slave_base = pll_14nm_slave->phy->base; - dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val); + writel(val, slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); } spin_unlock_irqrestore(lock, flags); @@ -675,7 +680,7 @@ static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = { .recalc_rate = dsi_pll_14nm_postdiv_recalc_rate, - .round_rate = dsi_pll_14nm_postdiv_round_rate, + .determine_rate = dsi_pll_14nm_postdiv_determine_rate, .set_rate = dsi_pll_14nm_postdiv_set_rate, }; @@ -690,7 +695,7 @@ static void dsi_14nm_pll_save_state(struct msm_dsi_phy *phy) void __iomem *cmn_base = pll_14nm->phy->base; u32 data; - data = dsi_phy_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); + data = readl(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); cached_state->n1postdiv = data & 0xf; cached_state->n2postdiv = (data >> 4) & 0xf; @@ -713,7 +718,7 @@ static int dsi_14nm_pll_restore_state(struct msm_dsi_phy *phy) cached_state->vco_rate, 0); if (ret) { DRM_DEV_ERROR(&pll_14nm->phy->pdev->dev, - "restore vco rate failed. ret=%d\n", ret); + "restore vco rate failed. ret=%d\n", ret); return ret; } @@ -722,14 +727,14 @@ static int dsi_14nm_pll_restore_state(struct msm_dsi_phy *phy) DBG("DSI%d PLL restore state %x %x", pll_14nm->phy->id, cached_state->n1postdiv, cached_state->n2postdiv); - dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data); + writel(data, cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); /* also restore post-dividers for slave DSI PLL */ if (phy->usecase == MSM_DSI_PHY_MASTER) { struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; void __iomem *slave_base = pll_14nm_slave->phy->base; - dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data); + writel(data, slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); } return 0; @@ -757,23 +762,23 @@ static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy) return -EINVAL; } - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN, clkbuflr_en); + writel(clkbuflr_en, base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN); if (bandgap) - dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP, bandgap); + writel(bandgap, base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP); return 0; } static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm, const char *name, - const char *parent_name, + const struct clk_hw *parent_hw, unsigned long flags, u8 shift) { struct dsi_pll_14nm_postdiv *pll_postdiv; struct device *dev = &pll_14nm->phy->pdev->dev; struct clk_init_data postdiv_init = { - .parent_names = (const char *[]) { parent_name }, + .parent_hws = (const struct clk_hw *[]) { parent_hw }, .num_parents = 1, .name = name, .flags = flags, @@ -802,70 +807,70 @@ static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm, static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **provided_clocks) { - char clk_name[32], parent[32], vco_name[32]; + char clk_name[32]; struct clk_init_data vco_init = { - .parent_names = (const char *[]){ "xo" }, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "ref", + }, .num_parents = 1, - .name = vco_name, + .name = clk_name, .flags = CLK_IGNORE_UNUSED, .ops = &clk_ops_dsi_pll_14nm_vco, }; struct device *dev = &pll_14nm->phy->pdev->dev; - struct clk_hw *hw; + struct clk_hw *hw, *n1_postdiv, *n1_postdivby2; int ret; DBG("DSI%d", pll_14nm->phy->id); - snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->phy->id); + snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_14nm->phy->id); pll_14nm->clk_hw.init = &vco_init; ret = devm_clk_hw_register(dev, &pll_14nm->clk_hw); if (ret) return ret; - snprintf(clk_name, 32, "dsi%dn1_postdiv_clk", pll_14nm->phy->id); - snprintf(parent, 32, "dsi%dvco_clk", pll_14nm->phy->id); + snprintf(clk_name, sizeof(clk_name), "dsi%dn1_postdiv_clk", pll_14nm->phy->id); /* N1 postdiv, bits 0-3 in REG_DSI_14nm_PHY_CMN_CLK_CFG0 */ - hw = pll_14nm_postdiv_register(pll_14nm, clk_name, parent, - CLK_SET_RATE_PARENT, 0); - if (IS_ERR(hw)) - return PTR_ERR(hw); + n1_postdiv = pll_14nm_postdiv_register(pll_14nm, clk_name, + &pll_14nm->clk_hw, CLK_SET_RATE_PARENT, 0); + if (IS_ERR(n1_postdiv)) + return PTR_ERR(n1_postdiv); - snprintf(clk_name, 32, "dsi%dpllbyte", pll_14nm->phy->id); - snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->phy->id); + snprintf(clk_name, sizeof(clk_name), "dsi%dpllbyte", pll_14nm->phy->id); /* DSI Byte clock = VCO_CLK / N1 / 8 */ - hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, - CLK_SET_RATE_PARENT, 1, 8); + hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, clk_name, + n1_postdiv, CLK_SET_RATE_PARENT, 1, 8); if (IS_ERR(hw)) return PTR_ERR(hw); provided_clocks[DSI_BYTE_PLL_CLK] = hw; - snprintf(clk_name, 32, "dsi%dn1_postdivby2_clk", pll_14nm->phy->id); - snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->phy->id); + snprintf(clk_name, sizeof(clk_name), "dsi%dn1_postdivby2_clk", pll_14nm->phy->id); /* * Skip the mux for now, force DSICLK_SEL to 1, Add a /2 divider * on the way. Don't let it set parent. */ - hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 2); - if (IS_ERR(hw)) - return PTR_ERR(hw); + n1_postdivby2 = devm_clk_hw_register_fixed_factor_parent_hw(dev, + clk_name, n1_postdiv, 0, 1, 2); + if (IS_ERR(n1_postdivby2)) + return PTR_ERR(n1_postdivby2); - snprintf(clk_name, 32, "dsi%dpll", pll_14nm->phy->id); - snprintf(parent, 32, "dsi%dn1_postdivby2_clk", pll_14nm->phy->id); + snprintf(clk_name, sizeof(clk_name), "dsi%dpll", pll_14nm->phy->id); /* DSI pixel clock = VCO_CLK / N1 / 2 / N2 * This is the output of N2 post-divider, bits 4-7 in * REG_DSI_14nm_PHY_CMN_CLK_CFG0. Don't let it set parent. */ - hw = pll_14nm_postdiv_register(pll_14nm, clk_name, parent, 0, 4); + hw = pll_14nm_postdiv_register(pll_14nm, clk_name, n1_postdivby2, + 0, 4); if (IS_ERR(hw)) return PTR_ERR(hw); - provided_clocks[DSI_PIXEL_PLL_CLK] = hw; + provided_clocks[DSI_PIXEL_PLL_CLK] = hw; return 0; } @@ -916,27 +921,27 @@ static void dsi_14nm_dphy_set_timing(struct msm_dsi_phy *phy, u32 halfbyte_en = clk_ln ? timing->hs_halfbyte_en_ckln : timing->hs_halfbyte_en; - dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(lane_idx), - DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); - dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(lane_idx), - DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(zero)); - dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(lane_idx), - DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(prepare)); - dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(lane_idx), - DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(trail)); - dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(lane_idx), - DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(rqst)); - dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG0(lane_idx), - DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(prep_dly)); - dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG1(lane_idx), - halfbyte_en ? DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN : 0); - dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(lane_idx), - DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(timing->ta_go) | - DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(timing->ta_sure)); - dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(lane_idx), - DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(timing->ta_get)); - dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(lane_idx), - DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(0xa0)); + writel(DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(timing->hs_exit), + base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(lane_idx)); + writel(DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(zero), + base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(lane_idx)); + writel(DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(prepare), + base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(lane_idx)); + writel(DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(trail), + base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(lane_idx)); + writel(DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(rqst), + base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(lane_idx)); + writel(DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(prep_dly), + base + REG_DSI_14nm_PHY_LN_CFG0(lane_idx)); + writel(halfbyte_en ? DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN : 0, + base + REG_DSI_14nm_PHY_LN_CFG1(lane_idx)); + writel(DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(timing->ta_go) | + DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(timing->ta_sure), + base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(lane_idx)); + writel(DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(timing->ta_get), + base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(lane_idx)); + writel(DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(0xa0), + base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(lane_idx)); } static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, @@ -952,86 +957,90 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, if (msm_dsi_dphy_timing_calc_v2(timing, clk_req)) { DRM_DEV_ERROR(&phy->pdev->dev, - "%s: D-PHY timing calculation failed\n", __func__); + "%s: D-PHY timing calculation failed\n", + __func__); return -EINVAL; } data = 0x1c; if (phy->usecase != MSM_DSI_PHY_STANDALONE) data |= DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(32); - dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data); + writel(data, base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL); - dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, 0x1); + writel(0x1, base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL); /* 4 data lanes + 1 clk lane configuration */ for (i = 0; i < 5; i++) { - dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_VREG_CNTRL(i), - 0x1d); - - dsi_phy_write(lane_base + - REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(i), 0xff); - dsi_phy_write(lane_base + - REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(i), - (i == PHY_14NM_CKLN_IDX) ? 0x00 : 0x06); - - dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_CFG3(i), - (i == PHY_14NM_CKLN_IDX) ? 0x8f : 0x0f); - dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_CFG2(i), 0x10); - dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_TEST_DATAPATH(i), - 0); - dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_TEST_STR(i), - 0x88); + writel(0x1d, lane_base + REG_DSI_14nm_PHY_LN_VREG_CNTRL(i)); + + writel(0xff, lane_base + REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(i)); + writel(i == PHY_14NM_CKLN_IDX ? 0x00 : 0x06, + lane_base + REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(i)); + + writel(i == PHY_14NM_CKLN_IDX ? 0x8f : 0x0f, + lane_base + REG_DSI_14nm_PHY_LN_CFG3(i)); + writel(0x10, lane_base + REG_DSI_14nm_PHY_LN_CFG2(i)); + writel(0, lane_base + REG_DSI_14nm_PHY_LN_TEST_DATAPATH(i)); + writel(0x88, lane_base + REG_DSI_14nm_PHY_LN_TEST_STR(i)); dsi_14nm_dphy_set_timing(phy, timing, i); } /* Make sure PLL is not start */ - dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0x00); + writel(0x00, base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL); wmb(); /* make sure everything is written before reset and enable */ /* reset digital block */ - dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x80); + writel(0x80, base + REG_DSI_14nm_PHY_CMN_CTRL_1); wmb(); /* ensure reset is asserted */ udelay(100); - dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x00); + writel(0x00, base + REG_DSI_14nm_PHY_CMN_CTRL_1); - glbl_test_ctrl = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL); + glbl_test_ctrl = readl(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL); if (phy->id == DSI_1 && phy->usecase == MSM_DSI_PHY_SLAVE) glbl_test_ctrl |= DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL; else glbl_test_ctrl &= ~DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL; - dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, glbl_test_ctrl); + writel(glbl_test_ctrl, base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL); ret = dsi_14nm_set_usecase(phy); if (ret) { DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n", - __func__, ret); + __func__, ret); return ret; } /* Remove power down from PLL and all lanes */ - dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_0, 0xff); + writel(0xff, base + REG_DSI_14nm_PHY_CMN_CTRL_0); return 0; } static void dsi_14nm_phy_disable(struct msm_dsi_phy *phy) { - dsi_phy_write(phy->base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, 0); - dsi_phy_write(phy->base + REG_DSI_14nm_PHY_CMN_CTRL_0, 0); + writel(0, phy->base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL); + writel(0, phy->base + REG_DSI_14nm_PHY_CMN_CTRL_0); /* ensure that the phy is completely disabled */ wmb(); } +static const struct regulator_bulk_data dsi_phy_14nm_17mA_regulators[] = { + { .supply = "vcca", .init_load_uA = 17000 }, +}; + +static const struct regulator_bulk_data dsi_phy_14nm_73p4mA_regulators[] = { + { .supply = "vcca", .init_load_uA = 73400 }, +}; + +static const struct regulator_bulk_data dsi_phy_14nm_36mA_regulators[] = { + { .supply = "vdda", .init_load_uA = 36000 }, +}; + const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { .has_phy_lane = true, - .reg_cfg = { - .num = 1, - .regs = { - {"vcca", 17000, 32}, - }, - }, + .regulator_data = dsi_phy_14nm_17mA_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_14nm_17mA_regulators), .ops = { .enable = dsi_14nm_phy_enable, .disable = dsi_14nm_phy_disable, @@ -1047,12 +1056,25 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { .has_phy_lane = true, - .reg_cfg = { - .num = 1, - .regs = { - {"vcca", 17000, 32}, - }, + .regulator_data = dsi_phy_14nm_73p4mA_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_14nm_73p4mA_regulators), + .ops = { + .enable = dsi_14nm_phy_enable, + .disable = dsi_14nm_phy_disable, + .pll_init = dsi_pll_14nm_init, + .save_pll_state = dsi_14nm_pll_save_state, + .restore_pll_state = dsi_14nm_pll_restore_state, }, + .min_pll_rate = VCO_MIN_RATE, + .max_pll_rate = VCO_MAX_RATE, + .io_start = { 0xc994400, 0xc996400 }, + .num_dsi_phy = 2, +}; + +const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = { + .has_phy_lane = true, + .regulator_data = dsi_phy_14nm_17mA_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_14nm_17mA_regulators), .ops = { .enable = dsi_14nm_phy_enable, .disable = dsi_14nm_phy_disable, @@ -1062,6 +1084,38 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { }, .min_pll_rate = VCO_MIN_RATE, .max_pll_rate = VCO_MAX_RATE, - .io_start = { 0xc994400, 0xc996000 }, + .io_start = { 0x1a94400, 0x1a96400 }, .num_dsi_phy = 2, }; + +const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = { + .has_phy_lane = true, + .ops = { + .enable = dsi_14nm_phy_enable, + .disable = dsi_14nm_phy_disable, + .pll_init = dsi_pll_14nm_init, + .save_pll_state = dsi_14nm_pll_save_state, + .restore_pll_state = dsi_14nm_pll_restore_state, + }, + .min_pll_rate = VCO_MIN_RATE, + .max_pll_rate = VCO_MAX_RATE, + .io_start = { 0x5e94400 }, + .num_dsi_phy = 1, +}; + +const struct msm_dsi_phy_cfg dsi_phy_14nm_6150_cfgs = { + .has_phy_lane = true, + .regulator_data = dsi_phy_14nm_36mA_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_14nm_36mA_regulators), + .ops = { + .enable = dsi_14nm_phy_enable, + .disable = dsi_14nm_phy_disable, + .pll_init = dsi_pll_14nm_init, + .save_pll_state = dsi_14nm_pll_save_state, + .restore_pll_state = dsi_14nm_pll_restore_state, + }, + .min_pll_rate = VCO_MIN_RATE, + .max_pll_rate = VCO_MAX_RATE, + .io_start = { 0xae94400 }, + .num_dsi_phy = 1, +}; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c index ee7c418a1c29..cee34b76c3d2 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c @@ -12,32 +12,32 @@ static void dsi_20nm_dphy_set_timing(struct msm_dsi_phy *phy, { void __iomem *base = phy->base; - dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_0, - DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); - dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_1, - DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); - dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_2, - DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); + writel(DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero), + base + REG_DSI_20nm_PHY_TIMING_CTRL_0); + writel(DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail), + base + REG_DSI_20nm_PHY_TIMING_CTRL_1); + writel(DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare), + base + REG_DSI_20nm_PHY_TIMING_CTRL_2); if (timing->clk_zero & BIT(8)) - dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_3, - DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8); - dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_4, - DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); - dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_5, - DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); - dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_6, - DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); - dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_7, - DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail)); - dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_8, - DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst)); - dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_9, - DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) | - DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure)); - dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_10, - DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get)); - dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_11, - DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0)); + writel(DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8, + base + REG_DSI_20nm_PHY_TIMING_CTRL_3); + writel(DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit), + base + REG_DSI_20nm_PHY_TIMING_CTRL_4); + writel(DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero), + base + REG_DSI_20nm_PHY_TIMING_CTRL_5); + writel(DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare), + base + REG_DSI_20nm_PHY_TIMING_CTRL_6); + writel(DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail), + base + REG_DSI_20nm_PHY_TIMING_CTRL_7); + writel(DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst), + base + REG_DSI_20nm_PHY_TIMING_CTRL_8); + writel(DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) | + DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure), + base + REG_DSI_20nm_PHY_TIMING_CTRL_9); + writel(DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get), + base + REG_DSI_20nm_PHY_TIMING_CTRL_10); + writel(DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0), + base + REG_DSI_20nm_PHY_TIMING_CTRL_11); } static void dsi_20nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable) @@ -45,23 +45,23 @@ static void dsi_20nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable) void __iomem *base = phy->reg_base; if (!enable) { - dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0); + writel(0, base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG); return; } if (phy->regulator_ldo_mode) { - dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x1d); + writel(0x1d, phy->base + REG_DSI_20nm_PHY_LDO_CNTRL); return; } /* non LDO mode */ - dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_1, 0x03); - dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_2, 0x03); - dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_3, 0x00); - dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_4, 0x20); - dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0x01); - dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x00); - dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_0, 0x03); + writel(0x03, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_1); + writel(0x03, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_2); + writel(0x00, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_3); + writel(0x20, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_4); + writel(0x01, base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG); + writel(0x00, phy->base + REG_DSI_20nm_PHY_LDO_CNTRL); + writel(0x03, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_0); } static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, @@ -83,61 +83,60 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, dsi_20nm_phy_regulator_ctrl(phy, true); - dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff); + writel(0xff, base + REG_DSI_20nm_PHY_STRENGTH_0); - val = dsi_phy_read(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL); + val = readl(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL); if (phy->id == DSI_1 && phy->usecase == MSM_DSI_PHY_STANDALONE) val |= DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL; else val &= ~DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL; - dsi_phy_write(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL, val); + writel(val, base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL); for (i = 0; i < 4; i++) { - dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_3(i), - (i >> 1) * 0x40); - dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_0(i), 0x01); - dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_1(i), 0x46); - dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_0(i), 0x02); - dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_1(i), 0xa0); - dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_4(i), cfg_4[i]); + writel((i >> 1) * 0x40, base + REG_DSI_20nm_PHY_LN_CFG_3(i)); + writel(0x01, base + REG_DSI_20nm_PHY_LN_TEST_STR_0(i)); + writel(0x46, base + REG_DSI_20nm_PHY_LN_TEST_STR_1(i)); + writel(0x02, base + REG_DSI_20nm_PHY_LN_CFG_0(i)); + writel(0xa0, base + REG_DSI_20nm_PHY_LN_CFG_1(i)); + writel(cfg_4[i], base + REG_DSI_20nm_PHY_LN_CFG_4(i)); } - dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_3, 0x80); - dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR0, 0x01); - dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR1, 0x46); - dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_0, 0x00); - dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_1, 0xa0); - dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_2, 0x00); - dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_4, 0x00); + writel(0x80, base + REG_DSI_20nm_PHY_LNCK_CFG_3); + writel(0x01, base + REG_DSI_20nm_PHY_LNCK_TEST_STR0); + writel(0x46, base + REG_DSI_20nm_PHY_LNCK_TEST_STR1); + writel(0x00, base + REG_DSI_20nm_PHY_LNCK_CFG_0); + writel(0xa0, base + REG_DSI_20nm_PHY_LNCK_CFG_1); + writel(0x00, base + REG_DSI_20nm_PHY_LNCK_CFG_2); + writel(0x00, base + REG_DSI_20nm_PHY_LNCK_CFG_4); dsi_20nm_dphy_set_timing(phy, timing); - dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_1, 0x00); + writel(0x00, base + REG_DSI_20nm_PHY_CTRL_1); - dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_1, 0x06); + writel(0x06, base + REG_DSI_20nm_PHY_STRENGTH_1); /* make sure everything is written before enable */ wmb(); - dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_0, 0x7f); + writel(0x7f, base + REG_DSI_20nm_PHY_CTRL_0); return 0; } static void dsi_20nm_phy_disable(struct msm_dsi_phy *phy) { - dsi_phy_write(phy->base + REG_DSI_20nm_PHY_CTRL_0, 0); + writel(0, phy->base + REG_DSI_20nm_PHY_CTRL_0); dsi_20nm_phy_regulator_ctrl(phy, false); } +static const struct regulator_bulk_data dsi_phy_20nm_regulators[] = { + { .supply = "vddio", .init_load_uA = 100000 }, /* 1.8 V */ + { .supply = "vcca", .init_load_uA = 10000 }, /* 1.0 V */ +}; + const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = { .has_phy_regulator = true, - .reg_cfg = { - .num = 2, - .regs = { - {"vddio", 100000, 100}, /* 1.8 V */ - {"vcca", 10000, 100}, /* 1.0 V */ - }, - }, + .regulator_data = dsi_phy_20nm_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_20nm_regulators), .ops = { .enable = dsi_20nm_phy_enable, .disable = dsi_20nm_phy_disable, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index 2da673a2add6..d00e415b9a99 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -3,6 +3,7 @@ * Copyright (c) 2015, The Linux Foundation. All rights reserved. */ +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> #include <linux/clk.h> #include <linux/clk-provider.h> @@ -37,6 +38,7 @@ /* v2.0.0 28nm LP implementation */ #define DSI_PHY_28NM_QUIRK_PHY_LP BIT(0) +#define DSI_PHY_28NM_QUIRK_PHY_8226 BIT(1) #define LPFR_LUT_SIZE 10 struct lpfr_cfg { @@ -82,7 +84,7 @@ static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, u32 val; while (nb_tries--) { - val = dsi_phy_read(pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_STATUS); + val = readl(pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_STATUS); pll_locked = !!(val & DSI_28nm_PHY_PLL_STATUS_PLL_RDY); if (pll_locked) @@ -103,9 +105,10 @@ static void pll_28nm_software_reset(struct dsi_pll_28nm *pll_28nm) * Add HW recommended delays after toggling the software * reset bit off and back on. */ - dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, - DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET, 1); - dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1); + writel(DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET, base + REG_DSI_28nm_PHY_PLL_TEST_CFG); + udelay(1); + writel(0, base + REG_DSI_28nm_PHY_PLL_TEST_CFG); + udelay(1); } /* @@ -127,7 +130,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, VERB("rate=%lu, parent's=%lu", rate, parent_rate); /* Force postdiv2 to be div-4 */ - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG, 3); + writel(3, base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG); /* Configure the Loop filter resistance */ for (i = 0; i < LPFR_LUT_SIZE; i++) @@ -138,11 +141,11 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, rate); return -EINVAL; } - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFR_CFG, lpfr_lut[i].resistance); + writel(lpfr_lut[i].resistance, base + REG_DSI_28nm_PHY_PLL_LPFR_CFG); /* Loop filter capacitance values : c1 and c2 */ - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70); - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15); + writel(0x70, base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG); + writel(0x15, base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG); rem = rate % VCO_REF_CLK_RATE; if (rem) { @@ -167,7 +170,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, DBG("Generated VCO Clock: %lu", gen_vco_clk); rem = 0; - sdm_cfg1 = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1); + sdm_cfg1 = readl(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1); sdm_cfg1 &= ~DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK; if (frac_n_mode) { sdm_cfg0 = 0x0; @@ -194,17 +197,17 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, cal_cfg10 = (u32)((gen_vco_clk % (256 * 1000000)) / 1000000); DBG("cal_cfg10=%d, cal_cfg11=%d", cal_cfg10, cal_cfg11); - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG, 0x02); - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG3, 0x2b); - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG4, 0x06); - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); + writel(0x02, base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG); + writel(0x2b, base + REG_DSI_28nm_PHY_PLL_CAL_CFG3); + writel(0x06, base + REG_DSI_28nm_PHY_PLL_CAL_CFG4); + writel(0x0d, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2); - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1); - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2, - DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(sdm_cfg2)); - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3, - DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(sdm_cfg3)); - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00); + writel(sdm_cfg1, base + REG_DSI_28nm_PHY_PLL_SDM_CFG1); + writel(DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(sdm_cfg2), + base + REG_DSI_28nm_PHY_PLL_SDM_CFG2); + writel(DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(sdm_cfg3), + base + REG_DSI_28nm_PHY_PLL_SDM_CFG3); + writel(0, base + REG_DSI_28nm_PHY_PLL_SDM_CFG4); /* Add hardware recommended delay for correct PLL configuration */ if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP) @@ -212,18 +215,18 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, else udelay(1); - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg); - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00); - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_VCOLPF_CFG, 0x31); - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0, sdm_cfg0); - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG0, 0x12); - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG6, 0x30); - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG7, 0x00); - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG8, 0x60); - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG9, 0x00); - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG10, cal_cfg10 & 0xff); - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG11, cal_cfg11 & 0xff); - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_EFUSE_CFG, 0x20); + writel(refclk_cfg, base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG); + writel(0x00, base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG); + writel(0x31, base + REG_DSI_28nm_PHY_PLL_VCOLPF_CFG); + writel(sdm_cfg0, base + REG_DSI_28nm_PHY_PLL_SDM_CFG0); + writel(0x12, base + REG_DSI_28nm_PHY_PLL_CAL_CFG0); + writel(0x30, base + REG_DSI_28nm_PHY_PLL_CAL_CFG6); + writel(0x00, base + REG_DSI_28nm_PHY_PLL_CAL_CFG7); + writel(0x60, base + REG_DSI_28nm_PHY_PLL_CAL_CFG8); + writel(0x00, base + REG_DSI_28nm_PHY_PLL_CAL_CFG9); + writel(cal_cfg10 & 0xff, base + REG_DSI_28nm_PHY_PLL_CAL_CFG10); + writel(cal_cfg11 & 0xff, base + REG_DSI_28nm_PHY_PLL_CAL_CFG11); + writel(0x20, base + REG_DSI_28nm_PHY_PLL_EFUSE_CFG); return 0; } @@ -249,27 +252,27 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, VERB("parent_rate=%lu", parent_rate); /* Check to see if the ref clk doubler is enabled */ - doubler = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) & + doubler = readl(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) & DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR; ref_clk += (doubler * VCO_REF_CLK_RATE); /* see if it is integer mode or sdm mode */ - sdm0 = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0); + sdm0 = readl(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0); if (sdm0 & DSI_28nm_PHY_PLL_SDM_CFG0_BYP) { /* integer mode */ sdm_byp_div = FIELD( - dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0), + readl(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0), DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV) + 1; vco_rate = ref_clk * sdm_byp_div; } else { /* sdm mode */ sdm_dc_off = FIELD( - dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1), + readl(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1), DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET); DBG("sdm_dc_off = %d", sdm_dc_off); - sdm2 = FIELD(dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2), + sdm2 = FIELD(readl(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2), DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0); - sdm3 = FIELD(dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3), + sdm3 = FIELD(readl(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3), DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8); sdm_freq_seed = (sdm3 << 8) | sdm2; DBG("sdm_freq_seed = %d", sdm_freq_seed); @@ -302,26 +305,30 @@ static int _dsi_pll_28nm_vco_prepare_hpm(struct dsi_pll_28nm *pll_28nm) * Add necessary delays recommended by hardware. */ val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; - dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); + writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG); + udelay(1); val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; - dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); + writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG); + udelay(200); val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; - dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); + writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG); + udelay(500); val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; - dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); + writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG); + udelay(600); for (i = 0; i < 2; i++) { /* DSI Uniphy lock detect setting */ - dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, - 0x0c, 100); - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); + writel(0x0c, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2); + udelay(100); + writel(0x0d, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2); /* poll for PLL ready status */ - locked = pll_28nm_poll_for_ready(pll_28nm, - max_reads, timeout_us); + locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, + timeout_us); if (locked) break; @@ -332,22 +339,28 @@ static int _dsi_pll_28nm_vco_prepare_hpm(struct dsi_pll_28nm *pll_28nm) * Add necessary delays recommended by hardware. */ val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; - dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); + writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG); + udelay(1); val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; - dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); + writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG); + udelay(200); val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; - dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 250); + writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG); + udelay(250); val &= ~DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; - dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); + writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG); + udelay(200); val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; - dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); + writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG); + udelay(500); val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; - dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); + writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG); + udelay(600); } if (unlikely(!locked)) @@ -377,6 +390,80 @@ static int dsi_pll_28nm_vco_prepare_hpm(struct clk_hw *hw) return ret; } +static int dsi_pll_28nm_vco_prepare_8226(struct clk_hw *hw) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); + struct device *dev = &pll_28nm->phy->pdev->dev; + void __iomem *base = pll_28nm->phy->pll_base; + u32 max_reads = 5, timeout_us = 100; + bool locked; + u32 val; + int i; + + DBG("id=%d", pll_28nm->phy->id); + + pll_28nm_software_reset(pll_28nm); + + /* + * PLL power up sequence. + * Add necessary delays recommended by hardware. + */ + writel(0x34, base + REG_DSI_28nm_PHY_PLL_CAL_CFG1); + + val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; + writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG); + udelay(200); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; + writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG); + udelay(200); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; + writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG); + udelay(600); + + for (i = 0; i < 7; i++) { + /* DSI Uniphy lock detect setting */ + writel(0x0d, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2); + writel(0x0c, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2); + udelay(100); + writel(0x0d, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2); + + /* poll for PLL ready status */ + locked = pll_28nm_poll_for_ready(pll_28nm, + max_reads, timeout_us); + if (locked) + break; + + pll_28nm_software_reset(pll_28nm); + + /* + * PLL power up sequence. + * Add necessary delays recommended by hardware. + */ + writel(0x00, base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG); + udelay(50); + + val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; + writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG); + udelay(100); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; + writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG); + udelay(600); + } + + if (unlikely(!locked)) + DRM_DEV_ERROR(dev, "DSI PLL lock failed\n"); + else + DBG("DSI PLL Lock success"); + + return locked ? 0 : -EINVAL; +} + static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); @@ -397,21 +484,27 @@ static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw) * PLL power up sequence. * Add necessary delays recommended by hardware. */ - dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34, 500); + writel(0x34, base + REG_DSI_28nm_PHY_PLL_CAL_CFG1); + ndelay(500); val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; - dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); + writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG); + ndelay(500); val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; - dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); + writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG); + ndelay(500); val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B | DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; - dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); + writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG); + ndelay(500); /* DSI PLL toggle lock detect setting */ - dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x04, 500); - dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x05, 512); + writel(0x04, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2); + ndelay(500); + writel(0x05, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2); + udelay(512); locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us); @@ -435,26 +528,25 @@ static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw) if (unlikely(!pll_28nm->phy->pll_on)) return; - dsi_phy_write(pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00); + writel(0, pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_GLB_CFG); pll_28nm->phy->pll_on = false; } -static long dsi_pll_28nm_clk_round_rate(struct clk_hw *hw, - unsigned long rate, unsigned long *parent_rate) +static int dsi_pll_28nm_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); - if (rate < pll_28nm->phy->cfg->min_pll_rate) - return pll_28nm->phy->cfg->min_pll_rate; - else if (rate > pll_28nm->phy->cfg->max_pll_rate) - return pll_28nm->phy->cfg->max_pll_rate; - else - return rate; + req->rate = clamp_t(unsigned long, req->rate, + pll_28nm->phy->cfg->min_pll_rate, + pll_28nm->phy->cfg->max_pll_rate); + + return 0; } static const struct clk_ops clk_ops_dsi_pll_28nm_vco_hpm = { - .round_rate = dsi_pll_28nm_clk_round_rate, + .determine_rate = dsi_pll_28nm_clk_determine_rate, .set_rate = dsi_pll_28nm_clk_set_rate, .recalc_rate = dsi_pll_28nm_clk_recalc_rate, .prepare = dsi_pll_28nm_vco_prepare_hpm, @@ -463,7 +555,7 @@ static const struct clk_ops clk_ops_dsi_pll_28nm_vco_hpm = { }; static const struct clk_ops clk_ops_dsi_pll_28nm_vco_lp = { - .round_rate = dsi_pll_28nm_clk_round_rate, + .determine_rate = dsi_pll_28nm_clk_determine_rate, .set_rate = dsi_pll_28nm_clk_set_rate, .recalc_rate = dsi_pll_28nm_clk_recalc_rate, .prepare = dsi_pll_28nm_vco_prepare_lp, @@ -471,6 +563,15 @@ static const struct clk_ops clk_ops_dsi_pll_28nm_vco_lp = { .is_enabled = dsi_pll_28nm_clk_is_enabled, }; +static const struct clk_ops clk_ops_dsi_pll_28nm_vco_8226 = { + .determine_rate = dsi_pll_28nm_clk_determine_rate, + .set_rate = dsi_pll_28nm_clk_set_rate, + .recalc_rate = dsi_pll_28nm_clk_recalc_rate, + .prepare = dsi_pll_28nm_vco_prepare_8226, + .unprepare = dsi_pll_28nm_vco_unprepare, + .is_enabled = dsi_pll_28nm_clk_is_enabled, +}; + /* * PLL Callbacks */ @@ -482,10 +583,10 @@ static void dsi_28nm_pll_save_state(struct msm_dsi_phy *phy) void __iomem *base = pll_28nm->phy->pll_base; cached_state->postdiv3 = - dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG); + readl(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG); cached_state->postdiv1 = - dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG); - cached_state->byte_mux = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_VREG_CFG); + readl(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG); + cached_state->byte_mux = readl(base + REG_DSI_28nm_PHY_PLL_VREG_CFG); if (dsi_pll_28nm_clk_is_enabled(phy->vco_hw)) cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw); else @@ -507,85 +608,80 @@ static int dsi_28nm_pll_restore_state(struct msm_dsi_phy *phy) return ret; } - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG, - cached_state->postdiv3); - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG, - cached_state->postdiv1); - dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_VREG_CFG, - cached_state->byte_mux); + writel(cached_state->postdiv3, base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG); + writel(cached_state->postdiv1, base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG); + writel(cached_state->byte_mux, base + REG_DSI_28nm_PHY_PLL_VREG_CFG); return 0; } static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **provided_clocks) { - char clk_name[32], parent1[32], parent2[32], vco_name[32]; + char clk_name[32]; struct clk_init_data vco_init = { - .parent_names = (const char *[]){ "xo" }, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "ref", .name = "xo", + }, .num_parents = 1, - .name = vco_name, + .name = clk_name, .flags = CLK_IGNORE_UNUSED, }; struct device *dev = &pll_28nm->phy->pdev->dev; - struct clk_hw *hw; + struct clk_hw *hw, *analog_postdiv, *indirect_path_div2, *byte_mux; int ret; DBG("%d", pll_28nm->phy->id); if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP) vco_init.ops = &clk_ops_dsi_pll_28nm_vco_lp; + else if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_8226) + vco_init.ops = &clk_ops_dsi_pll_28nm_vco_8226; else vco_init.ops = &clk_ops_dsi_pll_28nm_vco_hpm; - snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->phy->id); + snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_28nm->phy->id); pll_28nm->clk_hw.init = &vco_init; ret = devm_clk_hw_register(dev, &pll_28nm->clk_hw); if (ret) return ret; - snprintf(clk_name, 32, "dsi%danalog_postdiv_clk", pll_28nm->phy->id); - snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->phy->id); - hw = devm_clk_hw_register_divider(dev, clk_name, - parent1, CLK_SET_RATE_PARENT, + snprintf(clk_name, sizeof(clk_name), "dsi%danalog_postdiv_clk", pll_28nm->phy->id); + analog_postdiv = devm_clk_hw_register_divider_parent_hw(dev, clk_name, + &pll_28nm->clk_hw, CLK_SET_RATE_PARENT, pll_28nm->phy->pll_base + - REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG, + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG, 0, 4, 0, NULL); - if (IS_ERR(hw)) - return PTR_ERR(hw); - - snprintf(clk_name, 32, "dsi%dindirect_path_div2_clk", pll_28nm->phy->id); - snprintf(parent1, 32, "dsi%danalog_postdiv_clk", pll_28nm->phy->id); - hw = devm_clk_hw_register_fixed_factor(dev, clk_name, - parent1, CLK_SET_RATE_PARENT, - 1, 2); - if (IS_ERR(hw)) - return PTR_ERR(hw); - - snprintf(clk_name, 32, "dsi%dpll", pll_28nm->phy->id); - snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->phy->id); - hw = devm_clk_hw_register_divider(dev, clk_name, - parent1, 0, pll_28nm->phy->pll_base + + if (IS_ERR(analog_postdiv)) + return PTR_ERR(analog_postdiv); + + snprintf(clk_name, sizeof(clk_name), "dsi%dindirect_path_div2_clk", pll_28nm->phy->id); + indirect_path_div2 = devm_clk_hw_register_fixed_factor_parent_hw(dev, + clk_name, analog_postdiv, CLK_SET_RATE_PARENT, 1, 2); + if (IS_ERR(indirect_path_div2)) + return PTR_ERR(indirect_path_div2); + + snprintf(clk_name, sizeof(clk_name), "dsi%dpll", pll_28nm->phy->id); + hw = devm_clk_hw_register_divider_parent_hw(dev, clk_name, + &pll_28nm->clk_hw, 0, pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG, - 0, 8, 0, NULL); + 0, 8, 0, NULL); if (IS_ERR(hw)) return PTR_ERR(hw); provided_clocks[DSI_PIXEL_PLL_CLK] = hw; - snprintf(clk_name, 32, "dsi%dbyte_mux", pll_28nm->phy->id); - snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->phy->id); - snprintf(parent2, 32, "dsi%dindirect_path_div2_clk", pll_28nm->phy->id); - hw = devm_clk_hw_register_mux(dev, clk_name, - ((const char *[]){ - parent1, parent2 + snprintf(clk_name, sizeof(clk_name), "dsi%dbyte_mux", pll_28nm->phy->id); + byte_mux = devm_clk_hw_register_mux_parent_hws(dev, clk_name, + ((const struct clk_hw *[]){ + &pll_28nm->clk_hw, + indirect_path_div2, }), 2, CLK_SET_RATE_PARENT, pll_28nm->phy->pll_base + - REG_DSI_28nm_PHY_PLL_VREG_CFG, 1, 1, 0, NULL); - if (IS_ERR(hw)) - return PTR_ERR(hw); + REG_DSI_28nm_PHY_PLL_VREG_CFG, 1, 1, 0, NULL); + if (IS_ERR(byte_mux)) + return PTR_ERR(byte_mux); - snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->phy->id); - snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->phy->id); - hw = devm_clk_hw_register_fixed_factor(dev, clk_name, - parent1, CLK_SET_RATE_PARENT, 1, 4); + snprintf(clk_name, sizeof(clk_name), "dsi%dpllbyte", pll_28nm->phy->id); + hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, clk_name, + byte_mux, CLK_SET_RATE_PARENT, 1, 4); if (IS_ERR(hw)) return PTR_ERR(hw); provided_clocks[DSI_BYTE_PLL_CLK] = hw; @@ -624,72 +720,71 @@ static void dsi_28nm_dphy_set_timing(struct msm_dsi_phy *phy, { void __iomem *base = phy->base; - dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_0, - DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); - dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_1, - DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); - dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_2, - DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); + writel(DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero), + base + REG_DSI_28nm_PHY_TIMING_CTRL_0); + writel(DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail), + base + REG_DSI_28nm_PHY_TIMING_CTRL_1); + writel(DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare), + base + REG_DSI_28nm_PHY_TIMING_CTRL_2); if (timing->clk_zero & BIT(8)) - dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_3, - DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8); - dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_4, - DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); - dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_5, - DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); - dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_6, - DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); - dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_7, - DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail)); - dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_8, - DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst)); - dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_9, - DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) | - DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure)); - dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_10, - DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get)); - dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_11, - DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0)); + writel(DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8, + base + REG_DSI_28nm_PHY_TIMING_CTRL_3); + writel(DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit), + base + REG_DSI_28nm_PHY_TIMING_CTRL_4); + writel(DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero), + base + REG_DSI_28nm_PHY_TIMING_CTRL_5); + writel(DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare), + base + REG_DSI_28nm_PHY_TIMING_CTRL_6); + writel(DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail), + base + REG_DSI_28nm_PHY_TIMING_CTRL_7); + writel(DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst), + base + REG_DSI_28nm_PHY_TIMING_CTRL_8); + writel(DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) | + DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure), + base + REG_DSI_28nm_PHY_TIMING_CTRL_9); + writel(DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get), + base + REG_DSI_28nm_PHY_TIMING_CTRL_10); + writel(DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0), + base + REG_DSI_28nm_PHY_TIMING_CTRL_11); } static void dsi_28nm_phy_regulator_enable_dcdc(struct msm_dsi_phy *phy) { void __iomem *base = phy->reg_base; - dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x0); - dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 1); - dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5, 0); - dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3, 0); - dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2, 0x3); - dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x9); - dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x7); - dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4, 0x20); - dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x00); + writel(0x0, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0); + writel(1, base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG); + writel(0, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5); + writel(0, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3); + writel(0x3, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2); + writel(0x9, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1); + writel(0x7, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0); + writel(0x20, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4); + writel(0x00, phy->base + REG_DSI_28nm_PHY_LDO_CNTRL); } static void dsi_28nm_phy_regulator_enable_ldo(struct msm_dsi_phy *phy) { void __iomem *base = phy->reg_base; - dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x0); - dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 0); - dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5, 0x7); - dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3, 0); - dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2, 0x1); - dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x1); - dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4, 0x20); + writel(0x0, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0); + writel(0, base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG); + writel(0x7, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5); + writel(0, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3); + writel(0x1, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2); + writel(0x1, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1); + writel(0x20, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4); if (phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP) - dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x05); + writel(0x05, phy->base + REG_DSI_28nm_PHY_LDO_CNTRL); else - dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x0d); + writel(0x0d, phy->base + REG_DSI_28nm_PHY_LDO_CNTRL); } static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable) { if (!enable) { - dsi_phy_write(phy->reg_base + - REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 0); + writel(0, phy->reg_base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG); return; } @@ -711,53 +806,54 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, if (msm_dsi_dphy_timing_calc(timing, clk_req)) { DRM_DEV_ERROR(&phy->pdev->dev, - "%s: D-PHY timing calculation failed\n", __func__); + "%s: D-PHY timing calculation failed\n", + __func__); return -EINVAL; } - dsi_phy_write(base + REG_DSI_28nm_PHY_STRENGTH_0, 0xff); + writel(0xff, base + REG_DSI_28nm_PHY_STRENGTH_0); dsi_28nm_phy_regulator_ctrl(phy, true); dsi_28nm_dphy_set_timing(phy, timing); - dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_1, 0x00); - dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f); + writel(0x00, base + REG_DSI_28nm_PHY_CTRL_1); + writel(0x5f, base + REG_DSI_28nm_PHY_CTRL_0); - dsi_phy_write(base + REG_DSI_28nm_PHY_STRENGTH_1, 0x6); + writel(0x6, base + REG_DSI_28nm_PHY_STRENGTH_1); for (i = 0; i < 4; i++) { - dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_0(i), 0); - dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_1(i), 0); - dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_2(i), 0); - dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_3(i), 0); - dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(i), 0); - dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_DATAPATH(i), 0); - dsi_phy_write(base + REG_DSI_28nm_PHY_LN_DEBUG_SEL(i), 0); - dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_0(i), 0x1); - dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_1(i), 0x97); + writel(0, base + REG_DSI_28nm_PHY_LN_CFG_0(i)); + writel(0, base + REG_DSI_28nm_PHY_LN_CFG_1(i)); + writel(0, base + REG_DSI_28nm_PHY_LN_CFG_2(i)); + writel(0, base + REG_DSI_28nm_PHY_LN_CFG_3(i)); + writel(0, base + REG_DSI_28nm_PHY_LN_CFG_4(i)); + writel(0, base + REG_DSI_28nm_PHY_LN_TEST_DATAPATH(i)); + writel(0, base + REG_DSI_28nm_PHY_LN_DEBUG_SEL(i)); + writel(0x1, base + REG_DSI_28nm_PHY_LN_TEST_STR_0(i)); + writel(0x97, base + REG_DSI_28nm_PHY_LN_TEST_STR_1(i)); } - dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_4, 0); - dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_1, 0xc0); - dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR0, 0x1); - dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR1, 0xbb); + writel(0, base + REG_DSI_28nm_PHY_LNCK_CFG_4); + writel(0xc0, base + REG_DSI_28nm_PHY_LNCK_CFG_1); + writel(0x1, base + REG_DSI_28nm_PHY_LNCK_TEST_STR0); + writel(0xbb, base + REG_DSI_28nm_PHY_LNCK_TEST_STR1); - dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f); + writel(0x5f, base + REG_DSI_28nm_PHY_CTRL_0); - val = dsi_phy_read(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL); + val = readl(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL); if (phy->id == DSI_1 && phy->usecase == MSM_DSI_PHY_SLAVE) val &= ~DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL; else val |= DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL; - dsi_phy_write(base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL, val); + writel(val, base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL); return 0; } static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy) { - dsi_phy_write(phy->base + REG_DSI_28nm_PHY_CTRL_0, 0); + writel(0, phy->base + REG_DSI_28nm_PHY_CTRL_0); dsi_28nm_phy_regulator_ctrl(phy, false); /* @@ -767,14 +863,14 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy) wmb(); } +static const struct regulator_bulk_data dsi_phy_28nm_regulators[] = { + { .supply = "vddio", .init_load_uA = 100000 }, +}; + const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = { .has_phy_regulator = true, - .reg_cfg = { - .num = 1, - .regs = { - {"vddio", 100000, 100}, - }, - }, + .regulator_data = dsi_phy_28nm_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_28nm_regulators), .ops = { .enable = dsi_28nm_phy_enable, .disable = dsi_28nm_phy_disable, @@ -790,12 +886,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = { const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = { .has_phy_regulator = true, - .reg_cfg = { - .num = 1, - .regs = { - {"vddio", 100000, 100}, - }, - }, + .regulator_data = dsi_phy_28nm_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_28nm_regulators), .ops = { .enable = dsi_28nm_phy_enable, .disable = dsi_28nm_phy_disable, @@ -811,12 +903,8 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = { const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { .has_phy_regulator = true, - .reg_cfg = { - .num = 1, - .regs = { - {"vddio", 100000, 100}, /* 1.8 V */ - }, - }, + .regulator_data = dsi_phy_28nm_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_28nm_regulators), .ops = { .enable = dsi_28nm_phy_enable, .disable = dsi_28nm_phy_disable, @@ -831,3 +919,38 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { .quirks = DSI_PHY_28NM_QUIRK_PHY_LP, }; +const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs = { + .has_phy_regulator = true, + .regulator_data = dsi_phy_28nm_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_28nm_regulators), + .ops = { + .enable = dsi_28nm_phy_enable, + .disable = dsi_28nm_phy_disable, + .pll_init = dsi_pll_28nm_init, + .save_pll_state = dsi_28nm_pll_save_state, + .restore_pll_state = dsi_28nm_pll_restore_state, + }, + .min_pll_rate = VCO_MIN_RATE, + .max_pll_rate = VCO_MAX_RATE, + .io_start = { 0xfd922b00 }, + .num_dsi_phy = 1, + .quirks = DSI_PHY_28NM_QUIRK_PHY_8226, +}; + +const struct msm_dsi_phy_cfg dsi_phy_28nm_8937_cfgs = { + .has_phy_regulator = true, + .regulator_data = dsi_phy_28nm_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_28nm_regulators), + .ops = { + .enable = dsi_28nm_phy_enable, + .disable = dsi_28nm_phy_disable, + .pll_init = dsi_pll_28nm_init, + .save_pll_state = dsi_28nm_pll_save_state, + .restore_pll_state = dsi_28nm_pll_restore_state, + }, + .min_pll_rate = VCO_MIN_RATE, + .max_pll_rate = VCO_MAX_RATE, + .io_start = { 0x1a94400, 0x1a96400 }, + .num_dsi_phy = 2, + .quirks = DSI_PHY_28NM_QUIRK_PHY_LP, +}; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c index aaa37456f4ee..8dcce9581dc3 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c @@ -3,6 +3,7 @@ * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. */ +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> #include <linux/clk-provider.h> #include <linux/delay.h> @@ -74,7 +75,7 @@ static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, u32 val; while (nb_tries--) { - val = dsi_phy_read(pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_RDY); + val = readl(pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_RDY); pll_locked = !!(val & DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY); if (pll_locked) @@ -103,30 +104,25 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, val = VCO_REF_CLK_RATE / 10; fb_divider = (temp * VCO_PREF_DIV_RATIO) / val; fb_divider = fb_divider / 2 - 1; - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1, - fb_divider & 0xff); + writel(fb_divider & 0xff, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1); - val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2); + val = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2); val |= (fb_divider >> 8) & 0x07; - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2, - val); + writel(val, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2); - val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); + val = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); val |= (VCO_PREF_DIV_RATIO - 1) & 0x3f; - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3, - val); + writel(val, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_6, - 0xf); + writel(0xf, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_6); - val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); + val = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); val |= 0x7 << 4; - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, - val); + writel(val, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); return 0; } @@ -149,16 +145,16 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, VERB("parent_rate=%lu", parent_rate); - status = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0); + status = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0); if (status & DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE) { - fb_divider = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1); + fb_divider = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1); fb_divider &= 0xff; - temp = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2) & 0x07; + temp = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2) & 0x07; fb_divider = (temp << 8) | fb_divider; fb_divider += 1; - ref_divider = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); + ref_divider = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); ref_divider &= 0x3f; ref_divider += 1; @@ -195,18 +191,18 @@ static int dsi_pll_28nm_vco_prepare(struct clk_hw *hw) * 2: divide by 8 to get bit clock divider * 3: write it to POSTDIV1 */ - val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9); + val = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9); byte_div = val + 1; bit_div = byte_div / 8; - val = dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); + val = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); val &= ~0xf; val |= (bit_div - 1); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val); + writel(val, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); /* enable the PLL */ - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, - DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE); + writel(DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE, + base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0); locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us); @@ -230,26 +226,24 @@ static void dsi_pll_28nm_vco_unprepare(struct clk_hw *hw) if (unlikely(!pll_28nm->phy->pll_on)) return; - dsi_phy_write(pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00); + writel(0x00, pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0); pll_28nm->phy->pll_on = false; } -static long dsi_pll_28nm_clk_round_rate(struct clk_hw *hw, - unsigned long rate, unsigned long *parent_rate) +static int dsi_pll_28nm_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); - if (rate < pll_28nm->phy->cfg->min_pll_rate) - return pll_28nm->phy->cfg->min_pll_rate; - else if (rate > pll_28nm->phy->cfg->max_pll_rate) - return pll_28nm->phy->cfg->max_pll_rate; - else - return rate; + req->rate = clamp_t(unsigned long, req->rate, + pll_28nm->phy->cfg->min_pll_rate, pll_28nm->phy->cfg->max_pll_rate); + + return 0; } static const struct clk_ops clk_ops_dsi_pll_28nm_vco = { - .round_rate = dsi_pll_28nm_clk_round_rate, + .determine_rate = dsi_pll_28nm_clk_determine_rate, .set_rate = dsi_pll_28nm_clk_set_rate, .recalc_rate = dsi_pll_28nm_clk_recalc_rate, .prepare = dsi_pll_28nm_vco_prepare, @@ -277,7 +271,7 @@ static unsigned long clk_bytediv_recalc_rate(struct clk_hw *hw, struct clk_bytediv *bytediv = to_clk_bytediv(hw); unsigned int div; - div = dsi_phy_read(bytediv->reg) & 0xff; + div = readl(bytediv->reg) & 0xff; return parent_rate / (div + 1); } @@ -300,18 +294,20 @@ static unsigned int get_vco_mul_factor(unsigned long byte_clk_rate) return 8; } -static long clk_bytediv_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int clk_bytediv_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { unsigned long best_parent; unsigned int factor; - factor = get_vco_mul_factor(rate); + factor = get_vco_mul_factor(req->rate); + + best_parent = req->rate * factor; + req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent); - best_parent = rate * factor; - *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent); + req->rate = req->best_parent_rate / factor; - return *prate / factor; + return 0; } static int clk_bytediv_set_rate(struct clk_hw *hw, unsigned long rate, @@ -323,16 +319,16 @@ static int clk_bytediv_set_rate(struct clk_hw *hw, unsigned long rate, factor = get_vco_mul_factor(rate); - val = dsi_phy_read(bytediv->reg); + val = readl(bytediv->reg); val |= (factor - 1) & 0xff; - dsi_phy_write(bytediv->reg, val); + writel(val, bytediv->reg); return 0; } /* Our special byte clock divider ops */ static const struct clk_ops clk_bytediv_ops = { - .round_rate = clk_bytediv_round_rate, + .determine_rate = clk_bytediv_determine_rate, .set_rate = clk_bytediv_set_rate, .recalc_rate = clk_bytediv_recalc_rate, }; @@ -347,11 +343,11 @@ static void dsi_28nm_pll_save_state(struct msm_dsi_phy *phy) void __iomem *base = pll_28nm->phy->pll_base; cached_state->postdiv3 = - dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10); + readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10); cached_state->postdiv2 = - dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9); + readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9); cached_state->postdiv1 = - dsi_phy_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); + readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw); } @@ -367,25 +363,24 @@ static int dsi_28nm_pll_restore_state(struct msm_dsi_phy *phy) cached_state->vco_rate, 0); if (ret) { DRM_DEV_ERROR(&pll_28nm->phy->pdev->dev, - "restore vco rate failed. ret=%d\n", ret); + "restore vco rate failed. ret=%d\n", ret); return ret; } - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10, - cached_state->postdiv3); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9, - cached_state->postdiv2); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, - cached_state->postdiv1); + writel(cached_state->postdiv3, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10); + writel(cached_state->postdiv2, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9); + writel(cached_state->postdiv1, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); return 0; } static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **provided_clocks) { - char *clk_name, *parent_name, *vco_name; + char clk_name[32]; struct clk_init_data vco_init = { - .parent_names = (const char *[]){ "pxo" }, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "ref", + }, .num_parents = 1, .flags = CLK_IGNORE_UNUSED, .ops = &clk_ops_dsi_pll_28nm_vco, @@ -402,20 +397,8 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov if (!bytediv) return -ENOMEM; - vco_name = devm_kzalloc(dev, 32, GFP_KERNEL); - if (!vco_name) - return -ENOMEM; - - parent_name = devm_kzalloc(dev, 32, GFP_KERNEL); - if (!parent_name) - return -ENOMEM; - - clk_name = devm_kzalloc(dev, 32, GFP_KERNEL); - if (!clk_name) - return -ENOMEM; - - snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->phy->id); - vco_init.name = vco_name; + snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_28nm->phy->id); + vco_init.name = clk_name; pll_28nm->clk_hw.init = &vco_init; @@ -427,13 +410,14 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov bytediv->hw.init = &bytediv_init; bytediv->reg = pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9; - snprintf(parent_name, 32, "dsi%dvco_clk", pll_28nm->phy->id); - snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->phy->id); + snprintf(clk_name, sizeof(clk_name), "dsi%dpllbyte", pll_28nm->phy->id + 1); bytediv_init.name = clk_name; bytediv_init.ops = &clk_bytediv_ops; bytediv_init.flags = CLK_SET_RATE_PARENT; - bytediv_init.parent_names = (const char * const *) &parent_name; + bytediv_init.parent_hws = (const struct clk_hw*[]){ + &pll_28nm->clk_hw, + }; bytediv_init.num_parents = 1; /* DIV2 */ @@ -442,12 +426,12 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov return ret; provided_clocks[DSI_BYTE_PLL_CLK] = &bytediv->hw; - snprintf(clk_name, 32, "dsi%dpll", pll_28nm->phy->id); + snprintf(clk_name, sizeof(clk_name), "dsi%dpll", pll_28nm->phy->id + 1); /* DIV3 */ - hw = devm_clk_hw_register_divider(dev, clk_name, - parent_name, 0, pll_28nm->phy->pll_base + + hw = devm_clk_hw_register_divider_parent_hw(dev, clk_name, + &pll_28nm->clk_hw, 0, pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10, - 0, 8, 0, NULL); + 0, 8, 0, NULL); if (IS_ERR(hw)) return PTR_ERR(hw); provided_clocks[DSI_PIXEL_PLL_CLK] = hw; @@ -486,53 +470,52 @@ static void dsi_28nm_dphy_set_timing(struct msm_dsi_phy *phy, { void __iomem *base = phy->base; - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_0, - DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_1, - DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_2, - DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_3, 0x0); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_4, - DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_5, - DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_6, - DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_7, - DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail)); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_8, - DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst)); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_9, - DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) | - DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure)); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_10, - DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get)); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_11, - DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(0)); + writel(DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero), + base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_0); + writel(DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail), + base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_1); + writel(DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare), + base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_2); + writel(0, base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_3); + writel(DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit), + base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_4); + writel(DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero), + base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_5); + writel(DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare), + base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_6); + writel(DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail), + base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_7); + writel(DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst), + base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_8); + writel(DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) | + DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure), + base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_9); + writel(DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get), + base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_10); + writel(DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(0), + base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_11); } static void dsi_28nm_phy_regulator_init(struct msm_dsi_phy *phy) { void __iomem *base = phy->reg_base; - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0, 0x3); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1, 1); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2, 1); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3, 0); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4, - 0x100); + writel(0x3, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0); + writel(1, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1); + writel(1, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2); + writel(0, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3); + writel(0x100, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4); } static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy) { void __iomem *base = phy->reg_base; - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0, 0x3); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1, 0xa); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2, 0x4); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3, 0x0); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4, 0x20); + writel(0x3, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0); + writel(0xa, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1); + writel(0x4, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2); + writel(0x0, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3); + writel(0x20, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4); } static void dsi_28nm_phy_calibration(struct msm_dsi_phy *phy) @@ -541,21 +524,20 @@ static void dsi_28nm_phy_calibration(struct msm_dsi_phy *phy) u32 status; int i = 5000; - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG, - 0x3); + writel(0x3, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2, 0x0); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1, 0x5a); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3, 0x10); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4, 0x1); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0, 0x1); + writel(0x0, base + REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2); + writel(0x5a, base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1); + writel(0x10, base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3); + writel(0x1, base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4); + writel(0x1, base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER, 0x1); + writel(0x1, base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER); usleep_range(5000, 6000); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER, 0x0); + writel(0x0, base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER); do { - status = dsi_phy_read(base + + status = readl(base + REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS); if (!(status & DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY)) @@ -571,23 +553,20 @@ static void dsi_28nm_phy_lane_config(struct msm_dsi_phy *phy) int i; for (i = 0; i < 4; i++) { - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_CFG_0(i), 0x80); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_CFG_1(i), 0x45); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_CFG_2(i), 0x00); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(i), - 0x00); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(i), - 0x01); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(i), - 0x66); + writel(0x80, base + REG_DSI_28nm_8960_PHY_LN_CFG_0(i)); + writel(0x45, base + REG_DSI_28nm_8960_PHY_LN_CFG_1(i)); + writel(0x00, base + REG_DSI_28nm_8960_PHY_LN_CFG_2(i)); + writel(0x00, base + REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(i)); + writel(0x01, base + REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(i)); + writel(0x66, base + REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(i)); } - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_CFG_0, 0x40); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_CFG_1, 0x67); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_CFG_2, 0x0); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH, 0x0); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0, 0x1); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1, 0x88); + writel(0x40, base + REG_DSI_28nm_8960_PHY_LNCK_CFG_0); + writel(0x67, base + REG_DSI_28nm_8960_PHY_LNCK_CFG_1); + writel(0x0, base + REG_DSI_28nm_8960_PHY_LNCK_CFG_2); + writel(0x0, base + REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH); + writel(0x1, base + REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0); + writel(0x88, base + REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1); } static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, @@ -600,24 +579,25 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, if (msm_dsi_dphy_timing_calc(timing, clk_req)) { DRM_DEV_ERROR(&phy->pdev->dev, - "%s: D-PHY timing calculation failed\n", __func__); + "%s: D-PHY timing calculation failed\n", + __func__); return -EINVAL; } dsi_28nm_phy_regulator_init(phy); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LDO_CTRL, 0x04); + writel(0x04, base + REG_DSI_28nm_8960_PHY_LDO_CTRL); /* strength control */ - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_STRENGTH_0, 0xff); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_STRENGTH_1, 0x00); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_STRENGTH_2, 0x06); + writel(0xff, base + REG_DSI_28nm_8960_PHY_STRENGTH_0); + writel(0x00, base + REG_DSI_28nm_8960_PHY_STRENGTH_1); + writel(0x06, base + REG_DSI_28nm_8960_PHY_STRENGTH_2); /* phy ctrl */ - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_CTRL_0, 0x5f); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_CTRL_1, 0x00); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_CTRL_2, 0x00); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_CTRL_3, 0x10); + writel(0x5f, base + REG_DSI_28nm_8960_PHY_CTRL_0); + writel(0x00, base + REG_DSI_28nm_8960_PHY_CTRL_1); + writel(0x00, base + REG_DSI_28nm_8960_PHY_CTRL_2); + writel(0x10, base + REG_DSI_28nm_8960_PHY_CTRL_3); dsi_28nm_phy_regulator_ctrl(phy); @@ -625,10 +605,10 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, dsi_28nm_phy_lane_config(phy); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_BIST_CTRL_4, 0x0f); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_BIST_CTRL_1, 0x03); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_BIST_CTRL_0, 0x03); - dsi_phy_write(base + REG_DSI_28nm_8960_PHY_BIST_CTRL_4, 0x0); + writel(0x0f, base + REG_DSI_28nm_8960_PHY_BIST_CTRL_4); + writel(0x03, base + REG_DSI_28nm_8960_PHY_BIST_CTRL_1); + writel(0x03, base + REG_DSI_28nm_8960_PHY_BIST_CTRL_0); + writel(0x0, base + REG_DSI_28nm_8960_PHY_BIST_CTRL_4); dsi_28nm_dphy_set_timing(phy, timing); @@ -637,7 +617,7 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy) { - dsi_phy_write(phy->base + REG_DSI_28nm_8960_PHY_CTRL_0, 0x0); + writel(0x0, phy->base + REG_DSI_28nm_8960_PHY_CTRL_0); /* * Wait for the registers writes to complete in order to @@ -646,14 +626,14 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy) wmb(); } +static const struct regulator_bulk_data dsi_phy_28nm_8960_regulators[] = { + { .supply = "vddio", .init_load_uA = 100000 }, /* 1.8 V */ +}; + const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = { .has_phy_regulator = true, - .reg_cfg = { - .num = 1, - .regs = { - {"vddio", 100000, 100}, /* 1.8 V */ - }, - }, + .regulator_data = dsi_phy_28nm_8960_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_28nm_8960_regulators), .ops = { .enable = dsi_28nm_phy_enable, .disable = dsi_28nm_phy_disable, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 7c23d4c47338..c5e1d2016bcc 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -3,6 +3,8 @@ * Copyright (c) 2018, The Linux Foundation */ +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> +#include <linux/bitfield.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/iopoll.h> @@ -39,8 +41,18 @@ #define VCO_REF_CLK_RATE 19200000 #define FRAC_BITS 18 +/* Hardware is pre V4.1 */ +#define DSI_PHY_7NM_QUIRK_PRE_V4_1 BIT(0) /* Hardware is V4.1 */ -#define DSI_PHY_7NM_QUIRK_V4_1 BIT(0) +#define DSI_PHY_7NM_QUIRK_V4_1 BIT(1) +/* Hardware is V4.2 */ +#define DSI_PHY_7NM_QUIRK_V4_2 BIT(2) +/* Hardware is V4.3 */ +#define DSI_PHY_7NM_QUIRK_V4_3 BIT(3) +/* Hardware is V5.2 */ +#define DSI_PHY_7NM_QUIRK_V5_2 BIT(4) +/* Hardware is V7.0 */ +#define DSI_PHY_7NM_QUIRK_V7_0 BIT(5) struct dsi_pll_config { bool enable_ssc; @@ -75,6 +87,16 @@ struct dsi_pll_7nm { /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */ spinlock_t postdiv_lock; + /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG1 register */ + spinlock_t pclk_mux_lock; + + /* + * protects REG_DSI_7nm_PHY_CMN_CTRL_0 register and pll_enable_cnt + * member + */ + spinlock_t pll_enable_lock; + int pll_enable_cnt; + struct pll_7nm_cached_state cached_state; struct dsi_pll_7nm *slave; @@ -83,11 +105,14 @@ struct dsi_pll_7nm { #define to_pll_7nm(x) container_of(x, struct dsi_pll_7nm, clk_hw) /* - * Global list of private DSI PLL struct pointers. We need this for Dual DSI + * Global list of private DSI PLL struct pointers. We need this for bonded DSI * mode, where the master PLL's clk_ops needs access the slave's private data */ static struct dsi_pll_7nm *pll_7nm_list[DSI_MAX]; +static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll); +static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll); + static void dsi_pll_setup_config(struct dsi_pll_config *config) { config->ssc_freq = 31500; @@ -114,20 +139,60 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config multiplier = 1 << FRAC_BITS; dec_multiple = div_u64(pll_freq * multiplier, divider); - div_u64_rem(dec_multiple, multiplier, &frac); + dec = div_u64_rem(dec_multiple, multiplier, &frac); - dec = div_u64(dec_multiple, multiplier); - - if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)) + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) { config->pll_clock_inverters = 0x28; - else if (pll_freq <= 1000000000ULL) - config->pll_clock_inverters = 0xa0; - else if (pll_freq <= 2500000000ULL) - config->pll_clock_inverters = 0x20; - else if (pll_freq <= 3020000000ULL) - config->pll_clock_inverters = 0x00; - else - config->pll_clock_inverters = 0x40; + } else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { + if (pll_freq < 163000000ULL) + config->pll_clock_inverters = 0xa0; + else if (pll_freq < 175000000ULL) + config->pll_clock_inverters = 0x20; + else if (pll_freq < 325000000ULL) + config->pll_clock_inverters = 0xa0; + else if (pll_freq < 350000000ULL) + config->pll_clock_inverters = 0x20; + else if (pll_freq < 650000000ULL) + config->pll_clock_inverters = 0xa0; + else if (pll_freq < 700000000ULL) + config->pll_clock_inverters = 0x20; + else if (pll_freq < 1300000000ULL) + config->pll_clock_inverters = 0xa0; + else if (pll_freq < 2500000000ULL) + config->pll_clock_inverters = 0x20; + else if (pll_freq < 4000000000ULL) + config->pll_clock_inverters = 0x00; + else + config->pll_clock_inverters = 0x40; + } else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + if (pll_freq <= 1300000000ULL) + config->pll_clock_inverters = 0xa0; + else if (pll_freq <= 2500000000ULL) + config->pll_clock_inverters = 0x20; + else if (pll_freq <= 4000000000ULL) + config->pll_clock_inverters = 0x00; + else + config->pll_clock_inverters = 0x40; + } else if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { + if (pll_freq <= 1000000000ULL) + config->pll_clock_inverters = 0xa0; + else if (pll_freq <= 2500000000ULL) + config->pll_clock_inverters = 0x20; + else if (pll_freq <= 3020000000ULL) + config->pll_clock_inverters = 0x00; + else + config->pll_clock_inverters = 0x40; + } else { + /* 4.2, 4.3 */ + if (pll_freq <= 1000000000ULL) + config->pll_clock_inverters = 0xa0; + else if (pll_freq <= 2500000000ULL) + config->pll_clock_inverters = 0x20; + else if (pll_freq <= 3500000000ULL) + config->pll_clock_inverters = 0x00; + else + config->pll_clock_inverters = 0x40; + } config->decimal_div_start = dec; config->frac_div_start = frac; @@ -177,20 +242,20 @@ static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *c if (config->enable_ssc) { pr_debug("SSC is enabled\n"); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1, - config->ssc_stepsize & 0xff); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1, - config->ssc_stepsize >> 8); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1, - config->ssc_div_per & 0xff); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1, - config->ssc_div_per >> 8); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1, - config->ssc_adj_per & 0xff); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1, - config->ssc_adj_per >> 8); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL, - SSC_EN | (config->ssc_center ? SSC_CENTER : 0)); + writel(config->ssc_stepsize & 0xff, + base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1); + writel(config->ssc_stepsize >> 8, + base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1); + writel(config->ssc_div_per & 0xff, + base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1); + writel(config->ssc_div_per >> 8, + base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1); + writel(config->ssc_adj_per & 0xff, + base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1); + writel(config->ssc_adj_per >> 8, + base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1); + writel(SSC_EN | (config->ssc_center ? SSC_CENTER : 0), + base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL); } } @@ -199,46 +264,62 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) void __iomem *base = pll->phy->pll_base; u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00; - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) if (pll->vco_current_rate >= 3100000000ULL) analog_controls_five_1 = 0x03; + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { if (pll->vco_current_rate < 1520000000ULL) vco_config_1 = 0x08; else if (pll->vco_current_rate < 2990000000ULL) vco_config_1 = 0x01; } - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1, - analog_controls_five_1); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE, 0x01); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DSM_DIVIDER, 0x00); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE, 0xba); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_OUTDIV, 0x00); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE, 0x00); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x0a); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1, 0xc0); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x84); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x82); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, 0x4c); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x29); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, - pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22); + if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) || + (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) { + if (pll->vco_current_rate < 1520000000ULL) + vco_config_1 = 0x08; + else if (pll->vco_current_rate >= 2990000000ULL) + vco_config_1 = 0x01; + } - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); + if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || + (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { + if (pll->vco_current_rate < 1557000000ULL) + vco_config_1 = 0x08; + else + vco_config_1 = 0x01; + } + + writel(analog_controls_five_1, base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1); + writel(vco_config_1, base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1); + writel(0x01, base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE); + writel(0x03, base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO); + writel(0x00, base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE); + writel(0x00, base + REG_DSI_7nm_PHY_PLL_DSM_DIVIDER); + writel(0x4e, base + REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER); + writel(0x40, base + REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS); + writel(0xba, base + REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE); + writel(0x0c, base + REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE); + writel(0x00, base + REG_DSI_7nm_PHY_PLL_OUTDIV); + writel(0x00, base + REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE); + writel(0x08, base + REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO); + writel(0x0a, base + REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1); + writel(0xc0, base + REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1); + writel(0x84, base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1); + writel(0x82, base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1); + writel(0x4c, base + REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1); + writel(0x80, base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE); + writel(0x29, base + REG_DSI_7nm_PHY_PLL_PFILT); + writel(0x2f, base + REG_DSI_7nm_PHY_PLL_PFILT); + writel(0x2a, base + REG_DSI_7nm_PHY_PLL_IFILT); + writel(!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) ? 0x3f : 0x22, + base + REG_DSI_7nm_PHY_PLL_IFILT); + + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) { + writel(0x22, base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE); if (pll->slave) - dsi_phy_write(pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); + writel(0x22, pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE); } } @@ -246,18 +327,21 @@ static void dsi_pll_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *confi { void __iomem *base = pll->phy->pll_base; - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1, config->decimal_div_start); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1, - config->frac_div_start & 0xff); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1, - (config->frac_div_start & 0xff00) >> 8); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1, - (config->frac_div_start & 0x30000) >> 16); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, 0x40); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06); - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, 0x10); /* TODO: 0x00 for CPHY */ - dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS, config->pll_clock_inverters); + writel(0x12, base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE); + writel(config->decimal_div_start, + base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1); + writel(config->frac_div_start & 0xff, + base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1); + writel((config->frac_div_start & 0xff00) >> 8, + base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1); + writel((config->frac_div_start & 0x30000) >> 16, + base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1); + writel(0x40, base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1); + writel(0x06, base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY); + writel(pll->phy->cphy_mode ? 0x00 : 0x10, + base + REG_DSI_7nm_PHY_PLL_CMODE_1); + writel(config->pll_clock_inverters, + base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_1); } static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, @@ -266,6 +350,7 @@ static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw); struct dsi_pll_config config; + dsi_pll_enable_pll_bias(pll_7nm); DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->phy->id, rate, parent_rate); @@ -283,6 +368,7 @@ static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, dsi_pll_ssc_commit(pll_7nm, &config); + dsi_pll_disable_pll_bias(pll_7nm); /* flush, ensure all register writes are done*/ wmb(); @@ -311,39 +397,82 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll) static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll) { - u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); + unsigned long flags; + u32 data; + + spin_lock_irqsave(&pll->pll_enable_lock, flags); + --pll->pll_enable_cnt; + if (pll->pll_enable_cnt < 0) { + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); + DRM_DEV_ERROR_RATELIMITED(&pll->phy->pdev->dev, + "bug: imbalance in disabling PLL bias\n"); + return; + } else if (pll->pll_enable_cnt > 0) { + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); + return; + } /* else: == 0 */ - dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0); - dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0, data & ~BIT(5)); + data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); + data &= ~DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB; + writel(0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES); + writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); ndelay(250); } static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll) { - u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); + unsigned long flags; + u32 data; + + spin_lock_irqsave(&pll->pll_enable_lock, flags); + pll->pll_enable_cnt++; + WARN_ON(pll->pll_enable_cnt == INT_MAX); - dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0, data | BIT(5)); - dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0); + data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); + data |= DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB; + writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); + + writel(0xc0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES); + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); ndelay(250); } -static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll) +static void dsi_pll_cmn_clk_cfg0_write(struct dsi_pll_7nm *pll, u32 val) { - u32 data; + unsigned long flags; - data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); - dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data & ~BIT(5)); + spin_lock_irqsave(&pll->postdiv_lock, flags); + writel(val, pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG0); + spin_unlock_irqrestore(&pll->postdiv_lock, flags); } -static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll) +static void dsi_pll_cmn_clk_cfg1_update(struct dsi_pll_7nm *pll, u32 mask, + u32 val) { + unsigned long flags; u32 data; - dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04); + spin_lock_irqsave(&pll->pclk_mux_lock, flags); + data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); + data &= ~mask; + data |= val & mask; + + writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); + spin_unlock_irqrestore(&pll->pclk_mux_lock, flags); +} + +static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll) +{ + dsi_pll_cmn_clk_cfg1_update(pll, DSI_7nm_PHY_CMN_CLK_CFG1_CLK_EN, 0); +} - data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); - dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, - data | BIT(5) | BIT(4)); +static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll) +{ + u32 cfg_1 = DSI_7nm_PHY_CMN_CLK_CFG1_CLK_EN | DSI_7nm_PHY_CMN_CLK_CFG1_CLK_EN_SEL; + + writel(0x04, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_3); + dsi_pll_cmn_clk_cfg1_update(pll, cfg_1, cfg_1); } static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll) @@ -353,9 +482,9 @@ static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll) * coming out of a CX or analog rail power collapse while * ensuring that the pads maintain LP00 or LP11 state */ - dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0)); + writel(BIT(0), pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4); wmb(); /* Ensure that the reset is deasserted */ - dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0); + writel(0, pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4); wmb(); /* Ensure that the reset is deasserted */ } @@ -369,7 +498,7 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw) dsi_pll_enable_pll_bias(pll_7nm->slave); /* Start PLL */ - dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x01); + writel(BIT(0), pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL); /* * ensure all PLL configurations are written prior to checking @@ -399,13 +528,17 @@ static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw) if (pll_7nm->slave) dsi_pll_enable_global_clk(pll_7nm->slave); + writel(0x1, pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL); + if (pll_7nm->slave) + writel(0x1, pll_7nm->slave->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL); + error: return rc; } static void dsi_pll_disable_sub(struct dsi_pll_7nm *pll) { - dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0); + writel(0, pll->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL); dsi_pll_disable_pll_bias(pll); } @@ -419,7 +552,7 @@ static void dsi_pll_7nm_vco_unprepare(struct clk_hw *hw) * powering down the PLL */ dsi_pll_disable_global_clk(pll_7nm); - dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0); + writel(0, pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL); dsi_pll_disable_sub(pll_7nm); if (pll_7nm->slave) { dsi_pll_disable_global_clk(pll_7nm->slave); @@ -442,13 +575,14 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw, u32 dec; u64 pll_freq, tmp64; - dec = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1); + dsi_pll_enable_pll_bias(pll_7nm); + dec = readl(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1); dec &= 0xff; - frac = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1); - frac |= ((dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1) & + frac = readl(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1); + frac |= ((readl(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1) & 0xff) << 8); - frac |= ((dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1) & + frac |= ((readl(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1) & 0x3) << 16); /* @@ -466,24 +600,24 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw, DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x", pll_7nm->phy->id, (unsigned long)vco_rate, dec, frac); + dsi_pll_disable_pll_bias(pll_7nm); + return (unsigned long)vco_rate; } -static long dsi_pll_7nm_clk_round_rate(struct clk_hw *hw, - unsigned long rate, unsigned long *parent_rate) +static int dsi_pll_7nm_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw); - if (rate < pll_7nm->phy->cfg->min_pll_rate) - return pll_7nm->phy->cfg->min_pll_rate; - else if (rate > pll_7nm->phy->cfg->max_pll_rate) - return pll_7nm->phy->cfg->max_pll_rate; - else - return rate; + req->rate = clamp_t(unsigned long, req->rate, + pll_7nm->phy->cfg->min_pll_rate, pll_7nm->phy->cfg->max_pll_rate); + + return 0; } static const struct clk_ops clk_ops_dsi_pll_7nm_vco = { - .round_rate = dsi_pll_7nm_clk_round_rate, + .determine_rate = dsi_pll_7nm_clk_determine_rate, .set_rate = dsi_pll_7nm_vco_set_rate, .recalc_rate = dsi_pll_7nm_vco_recalc_rate, .prepare = dsi_pll_7nm_vco_prepare, @@ -501,17 +635,19 @@ static void dsi_7nm_pll_save_state(struct msm_dsi_phy *phy) void __iomem *phy_base = pll_7nm->phy->base; u32 cmn_clk_cfg0, cmn_clk_cfg1; - cached->pll_out_div = dsi_phy_read(pll_7nm->phy->pll_base + - REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); + dsi_pll_enable_pll_bias(pll_7nm); + cached->pll_out_div = readl(pll_7nm->phy->pll_base + + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); cached->pll_out_div &= 0x3; - cmn_clk_cfg0 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0); - cached->bit_clk_div = cmn_clk_cfg0 & 0xf; - cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4; + cmn_clk_cfg0 = readl(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0); + cached->bit_clk_div = FIELD_GET(DSI_7nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK, cmn_clk_cfg0); + cached->pix_clk_div = FIELD_GET(DSI_7nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK, cmn_clk_cfg0); - cmn_clk_cfg1 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); - cached->pll_mux = cmn_clk_cfg1 & 0x3; + cmn_clk_cfg1 = readl(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); + cached->pll_mux = FIELD_GET(DSI_7nm_PHY_CMN_CLK_CFG1_DSICLK_SEL__MASK, cmn_clk_cfg1); + dsi_pll_disable_pll_bias(pll_7nm); DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x", pll_7nm->phy->id, cached->pll_out_div, cached->bit_clk_div, cached->pix_clk_div, cached->pll_mux); @@ -521,22 +657,19 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy) { struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw); struct pll_7nm_cached_state *cached = &pll_7nm->cached_state; - void __iomem *phy_base = pll_7nm->phy->base; u32 val; int ret; - val = dsi_phy_read(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); + val = readl(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); val &= ~0x3; val |= cached->pll_out_div; - dsi_phy_write(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, val); + writel(val, pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); - dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0, - cached->bit_clk_div | (cached->pix_clk_div << 4)); - - val = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); - val &= ~0x3; - val |= cached->pll_mux; - dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val); + dsi_pll_cmn_clk_cfg0_write(pll_7nm, + DSI_7nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(cached->bit_clk_div) | + DSI_7nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(cached->pix_clk_div)); + dsi_pll_cmn_clk_cfg1_update(pll_7nm, DSI_7nm_PHY_CMN_CLK_CFG1_DSICLK_SEL__MASK, + cached->pll_mux); ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw, pll_7nm->vco_current_rate, @@ -565,6 +698,9 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) break; case MSM_DSI_PHY_MASTER: pll_7nm->slave = pll_7nm_list[(pll_7nm->phy->id + 1) % DSI_MAX]; + /* v7.0: Enable ATB_EN0 and alternate clock output to external phy */ + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0) + writel(0x07, base + REG_DSI_7nm_PHY_CMN_CTRL_5); break; case MSM_DSI_PHY_SLAVE: data = 0x1; /* external PLL */ @@ -574,7 +710,8 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) } /* set PLL src */ - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, (data << 2)); + dsi_pll_cmn_clk_cfg1_update(pll_7nm, DSI_7nm_PHY_CMN_CLK_CFG1_BITCLK_SEL__MASK, + DSI_7nm_PHY_CMN_CLK_CFG1_BITCLK_SEL(data)); return 0; } @@ -587,62 +724,60 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) */ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provided_clocks) { - char clk_name[32], parent[32], vco_name[32]; - char parent2[32], parent3[32], parent4[32]; + char clk_name[32]; struct clk_init_data vco_init = { - .parent_names = (const char *[]){ "bi_tcxo" }, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "ref", + }, .num_parents = 1, - .name = vco_name, + .name = clk_name, .flags = CLK_IGNORE_UNUSED, .ops = &clk_ops_dsi_pll_7nm_vco, }; struct device *dev = &pll_7nm->phy->pdev->dev; - struct clk_hw *hw; + struct clk_hw *hw, *pll_out_div, *pll_bit, *pll_by_2_bit; + struct clk_hw *pll_post_out_div, *phy_pll_out_dsi_parent; int ret; DBG("DSI%d", pll_7nm->phy->id); - snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->phy->id); + snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_7nm->phy->id); pll_7nm->clk_hw.init = &vco_init; ret = devm_clk_hw_register(dev, &pll_7nm->clk_hw); if (ret) return ret; - snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id); - snprintf(parent, 32, "dsi%dvco_clk", pll_7nm->phy->id); + snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_out_div_clk", pll_7nm->phy->id); - hw = devm_clk_hw_register_divider(dev, clk_name, - parent, CLK_SET_RATE_PARENT, - pll_7nm->phy->pll_base + - REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, - 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); + pll_out_div = devm_clk_hw_register_divider_parent_hw(dev, clk_name, + &pll_7nm->clk_hw, CLK_SET_RATE_PARENT, + pll_7nm->phy->pll_base + + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, + 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL); + if (IS_ERR(pll_out_div)) { + ret = PTR_ERR(pll_out_div); goto fail; } - snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id); - snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id); + snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_bit_clk", pll_7nm->phy->id); /* BIT CLK: DIV_CTRL_3_0 */ - hw = devm_clk_hw_register_divider(dev, clk_name, parent, - CLK_SET_RATE_PARENT, - pll_7nm->phy->base + - REG_DSI_7nm_PHY_CMN_CLK_CFG0, - 0, 4, CLK_DIVIDER_ONE_BASED, - &pll_7nm->postdiv_lock); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); + pll_bit = devm_clk_hw_register_divider_parent_hw(dev, clk_name, + pll_out_div, CLK_SET_RATE_PARENT, + pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG0, + 0, 4, CLK_DIVIDER_ONE_BASED, &pll_7nm->postdiv_lock); + if (IS_ERR(pll_bit)) { + ret = PTR_ERR(pll_bit); goto fail; } - snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_7nm->phy->id); - snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id); + snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_byteclk", pll_7nm->phy->id); /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */ - hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, - CLK_SET_RATE_PARENT, 1, 8); + hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, clk_name, + pll_bit, CLK_SET_RATE_PARENT, 1, + pll_7nm->phy->cphy_mode ? 7 : 8); if (IS_ERR(hw)) { ret = PTR_ERR(hw); goto fail; @@ -650,52 +785,61 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide provided_clocks[DSI_BYTE_PLL_CLK] = hw; - snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id); - snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id); + snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id); - hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, - 0, 1, 2); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); + pll_by_2_bit = devm_clk_hw_register_fixed_factor_parent_hw(dev, + clk_name, pll_bit, 0, 1, 2); + if (IS_ERR(pll_by_2_bit)) { + ret = PTR_ERR(pll_by_2_bit); goto fail; } - snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id); - snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id); + snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id); - hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, - 0, 1, 4); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); + if (pll_7nm->phy->cphy_mode) + pll_post_out_div = devm_clk_hw_register_fixed_factor_parent_hw( + dev, clk_name, pll_out_div, 0, 2, 7); + else + pll_post_out_div = devm_clk_hw_register_fixed_factor_parent_hw( + dev, clk_name, pll_out_div, 0, 1, 4); + if (IS_ERR(pll_post_out_div)) { + ret = PTR_ERR(pll_post_out_div); goto fail; } - snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->phy->id); - snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id); - snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id); - snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id); - snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id); - - hw = devm_clk_hw_register_mux(dev, clk_name, - ((const char *[]){ - parent, parent2, parent3, parent4 - }), 4, 0, pll_7nm->phy->base + - REG_DSI_7nm_PHY_CMN_CLK_CFG1, - 0, 2, 0, NULL); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); - goto fail; + /* in CPHY mode, pclk_mux will always have post_out_div as parent + * don't register a pclk_mux clock and just use post_out_div instead + */ + if (pll_7nm->phy->cphy_mode) { + dsi_pll_cmn_clk_cfg1_update(pll_7nm, + DSI_7nm_PHY_CMN_CLK_CFG1_DSICLK_SEL__MASK, + DSI_7nm_PHY_CMN_CLK_CFG1_DSICLK_SEL(3)); + phy_pll_out_dsi_parent = pll_post_out_div; + } else { + snprintf(clk_name, sizeof(clk_name), "dsi%d_pclk_mux", pll_7nm->phy->id); + + hw = devm_clk_hw_register_mux_parent_hws(dev, clk_name, + ((const struct clk_hw *[]){ + pll_bit, + pll_by_2_bit, + }), 2, 0, pll_7nm->phy->base + + REG_DSI_7nm_PHY_CMN_CLK_CFG1, + 0, 1, 0, &pll_7nm->pclk_mux_lock); + if (IS_ERR(hw)) { + ret = PTR_ERR(hw); + goto fail; + } + + phy_pll_out_dsi_parent = hw; } - snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_7nm->phy->id); - snprintf(parent, 32, "dsi%d_pclk_mux", pll_7nm->phy->id); + snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_dsiclk", pll_7nm->phy->id); /* PIX CLK DIV : DIV_CTRL_7_4*/ - hw = devm_clk_hw_register_divider(dev, clk_name, parent, - 0, pll_7nm->phy->base + - REG_DSI_7nm_PHY_CMN_CLK_CFG0, - 4, 4, CLK_DIVIDER_ONE_BASED, - &pll_7nm->postdiv_lock); + hw = devm_clk_hw_register_divider_parent_hw(dev, clk_name, + phy_pll_out_dsi_parent, 0, + pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG0, + 4, 4, CLK_DIVIDER_ONE_BASED, &pll_7nm->postdiv_lock); if (IS_ERR(hw)) { ret = PTR_ERR(hw); goto fail; @@ -725,6 +869,8 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) pll_7nm_list[phy->id] = pll_7nm; spin_lock_init(&pll_7nm->postdiv_lock); + spin_lock_init(&pll_7nm->pclk_mux_lock); + spin_lock_init(&pll_7nm->pll_enable_lock); pll_7nm->phy = phy; @@ -738,6 +884,12 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) /* TODO: Remove this when we have proper display handover support */ msm_dsi_phy_pll_save_state(phy); + /* + * Store also proper vco_current_rate, because its value will be used in + * dsi_7nm_pll_restore_state(). + */ + if (!dsi_pll_7nm_vco_recalc_rate(&pll_7nm->clk_hw, VCO_REF_CLK_RATE)) + pll_7nm->vco_current_rate = pll_7nm->phy->cfg->min_pll_rate; return 0; } @@ -747,7 +899,7 @@ static int dsi_phy_hw_v4_0_is_pll_on(struct msm_dsi_phy *phy) void __iomem *base = phy->base; u32 data = 0; - data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL); + data = readl(base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL); mb(); /* make sure read happened */ return (data & BIT(0)); @@ -763,11 +915,9 @@ static void dsi_phy_hw_v4_0_config_lpcdrx(struct msm_dsi_phy *phy, bool enable) * corresponding to the logical data lane 0 */ if (enable) - dsi_phy_write(lane_base + - REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0x3); + writel(0x3, lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0)); else - dsi_phy_write(lane_base + - REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0); + writel(0, lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0)); } static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy) @@ -778,7 +928,7 @@ static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy) const u8 *tx_dctrl = tx_dctrl_0; void __iomem *lane_base = phy->lane_base; - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) + if (!(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) tx_dctrl = tx_dctrl_1; /* Strength ctrl settings */ @@ -788,18 +938,18 @@ static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy) * be only enabled for the physical data lane corresponding * to the logical data lane 0 */ - dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(i), 0); - dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_PIN_SWAP(i), 0x0); + writel(0, lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(i)); + writel(0x0, lane_base + REG_DSI_7nm_PHY_LN_PIN_SWAP(i)); } dsi_phy_hw_v4_0_config_lpcdrx(phy, true); /* other settings */ for (i = 0; i < 5; i++) { - dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG0(i), 0x0); - dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG1(i), 0x0); - dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG2(i), i == 4 ? 0x8a : 0xa); - dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_TX_DCTRL(i), tx_dctrl[i]); + writel(0x0, lane_base + REG_DSI_7nm_PHY_LN_CFG0(i)); + writel(0x0, lane_base + REG_DSI_7nm_PHY_LN_CFG1(i)); + writel(i == 4 ? 0x8a : 0xa, lane_base + REG_DSI_7nm_PHY_LN_CFG2(i)); + writel(tx_dctrl[i], lane_base + REG_DSI_7nm_PHY_LN_TX_DCTRL(i)); } } @@ -813,21 +963,35 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, struct msm_dsi_dphy_timing *timing = &phy->timing; void __iomem *base = phy->base; bool less_than_1500_mhz; - u32 vreg_ctrl_0, glbl_str_swi_cal_sel_ctrl, glbl_hstx_str_ctrl_0; + u32 vreg_ctrl_0, vreg_ctrl_1, lane_ctrl0; + u32 glbl_pemph_ctrl_0; + u32 glbl_str_swi_cal_sel_ctrl, glbl_hstx_str_ctrl_0; u32 glbl_rescode_top_ctrl, glbl_rescode_bot_ctrl; u32 data; DBG(""); - if (msm_dsi_dphy_timing_calc_v4(timing, clk_req)) { + if (phy->cphy_mode) + ret = msm_dsi_cphy_timing_calc_v4(timing, clk_req); + else + ret = msm_dsi_dphy_timing_calc_v4(timing, clk_req); + if (ret) { DRM_DEV_ERROR(&phy->pdev->dev, - "%s: D-PHY timing calculation failed\n", __func__); + "%s: PHY timing calculation failed\n", __func__); return -EINVAL; } if (dsi_phy_hw_v4_0_is_pll_on(phy)) pr_warn("PLL turned on before configuring PHY\n"); + /* Request for REFGEN READY */ + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) || + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { + writel(0x1, phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10); + udelay(500); + } + /* wait for REFGEN READY */ ret = readl_poll_timeout_atomic(base + REG_DSI_7nm_PHY_CMN_PHY_STATUS, status, (status & BIT(0)), @@ -842,62 +1006,135 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, /* Alter PHY configurations if data rate less than 1.5GHZ*/ less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000); - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { + glbl_str_swi_cal_sel_ctrl = 0x00; + if (phy->cphy_mode) { + vreg_ctrl_0 = 0x51; + vreg_ctrl_1 = 0x55; + glbl_hstx_str_ctrl_0 = 0x00; + glbl_pemph_ctrl_0 = 0x11; + lane_ctrl0 = 0x17; + } else { vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; - glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00; - glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c; - glbl_str_swi_cal_sel_ctrl = 0x00; + vreg_ctrl_1 = 0x5c; glbl_hstx_str_ctrl_0 = 0x88; + glbl_pemph_ctrl_0 = 0x00; + lane_ctrl0 = 0x1f; + } + + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { + if (phy->cphy_mode) { + /* TODO: different for second phy */ + vreg_ctrl_0 = 0x57; + vreg_ctrl_1 = 0x41; + glbl_rescode_top_ctrl = 0x3d; + glbl_rescode_bot_ctrl = 0x38; + } else { + vreg_ctrl_0 = 0x56; + vreg_ctrl_1 = 0x19; + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x03; + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3c; + } + } else if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + if (phy->cphy_mode) { + vreg_ctrl_0 = 0x45; + vreg_ctrl_1 = 0x41; + glbl_rescode_top_ctrl = 0x00; + glbl_rescode_bot_ctrl = 0x00; + } else { + vreg_ctrl_0 = 0x44; + vreg_ctrl_1 = 0x19; + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x03; + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3c; + } + } else if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) { + if (phy->cphy_mode) { + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; + } else { + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; + } + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) { + if (phy->cphy_mode) { + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; + } else { + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x00; + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; + } + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { + if (phy->cphy_mode) { + glbl_hstx_str_ctrl_0 = 0x88; + glbl_rescode_top_ctrl = 0x00; + glbl_rescode_bot_ctrl = 0x3c; + } else { + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00; + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c; + } } else { - vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; - glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00; - glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88; + if (phy->cphy_mode) { + glbl_str_swi_cal_sel_ctrl = 0x03; + glbl_hstx_str_ctrl_0 = 0x66; + } else { + vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; + glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00; + glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88; + } glbl_rescode_top_ctrl = 0x03; glbl_rescode_bot_ctrl = 0x3c; } /* de-assert digital and pll power down */ - data = BIT(6) | BIT(5); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data); + data = DSI_7nm_PHY_CMN_CTRL_0_DIGTOP_PWRDN_B | + DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB; + writel(data, base + REG_DSI_7nm_PHY_CMN_CTRL_0); /* Assert PLL core reset */ - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x00); + writel(0x00, base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL); /* turn off resync FIFO */ - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0x00); + writel(0x00, base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL); /* program CMN_CTRL_4 for minor_ver 2 chipsets*/ - data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0); - data = data & (0xf0); - if (data == 0x20) - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_4, 0x04); + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0) || + (readl(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0) & (0xf0)) == 0x20) + writel(0x04, base + REG_DSI_7nm_PHY_CMN_CTRL_4); /* Configure PHY lane swap (TODO: we need to calculate this) */ - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CFG0, 0x21); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CFG1, 0x84); + writel(0x21, base + REG_DSI_7nm_PHY_CMN_LANE_CFG0); + writel(0x84, base + REG_DSI_7nm_PHY_CMN_LANE_CFG1); + + if (phy->cphy_mode) + writel(BIT(6), base + REG_DSI_7nm_PHY_CMN_GLBL_CTRL); /* Enable LDO */ - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_0, vreg_ctrl_0); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_1, 0x5c); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x00); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL, - glbl_str_swi_cal_sel_ctrl); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0, - glbl_hstx_str_ctrl_0); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0, 0x00); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL, - glbl_rescode_top_ctrl); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL, - glbl_rescode_bot_ctrl); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL, 0x55); + writel(vreg_ctrl_0, base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_0); + writel(vreg_ctrl_1, base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_1); + + writel(0x00, base + REG_DSI_7nm_PHY_CMN_CTRL_3); + writel(glbl_str_swi_cal_sel_ctrl, + base + REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL); + writel(glbl_hstx_str_ctrl_0, + base + REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0); + writel(glbl_pemph_ctrl_0, + base + REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0); + if (phy->cphy_mode) + writel(0x01, base + REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1); + writel(glbl_rescode_top_ctrl, + base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL); + writel(glbl_rescode_bot_ctrl, + base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL); + writel(0x55, base + REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL); /* Remove power down from all blocks */ - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, 0x7f); + writel(0x7f, base + REG_DSI_7nm_PHY_CMN_CTRL_0); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0, 0x1f); + writel(lane_ctrl0, base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0); /* Select full-rate mode */ - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_2, 0x40); + if (!phy->cphy_mode) + writel(0x40, base + REG_DSI_7nm_PHY_CMN_CTRL_2); ret = dsi_7nm_set_usecase(phy); if (ret) { @@ -907,22 +1144,36 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, } /* DSI PHY timings */ - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0, 0x00); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1, timing->clk_zero); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2, timing->clk_prepare); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3, timing->clk_trail); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4, timing->hs_exit); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5, timing->hs_zero); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6, timing->hs_prepare); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7, timing->hs_trail); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8, timing->hs_rqst); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9, 0x02); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10, 0x04); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11, 0x00); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12, - timing->shared_timings.clk_pre); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13, - timing->shared_timings.clk_post); + if (phy->cphy_mode) { + writel(0x00, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0); + writel(timing->hs_exit, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4); + writel(timing->shared_timings.clk_pre, + base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5); + writel(timing->clk_prepare, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6); + writel(timing->shared_timings.clk_post, + base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7); + writel(timing->hs_rqst, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8); + writel(0x02, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9); + writel(0x04, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10); + writel(0x00, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11); + } else { + writel(0x00, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0); + writel(timing->clk_zero, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1); + writel(timing->clk_prepare, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2); + writel(timing->clk_trail, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3); + writel(timing->hs_exit, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4); + writel(timing->hs_zero, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5); + writel(timing->hs_prepare, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6); + writel(timing->hs_trail, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7); + writel(timing->hs_rqst, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8); + writel(0x02, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9); + writel(0x04, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10); + writel(0x00, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11); + writel(timing->shared_timings.clk_pre, + base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12); + writel(timing->shared_timings.clk_post, + base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13); + } /* DSI lane settings */ dsi_phy_hw_v4_0_lane_settings(phy); @@ -932,6 +1183,21 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, return 0; } +static bool dsi_7nm_set_continuous_clock(struct msm_dsi_phy *phy, bool enable) +{ + void __iomem *base = phy->base; + u32 data; + + data = readl(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL1); + if (enable) + data |= BIT(5) | BIT(6); + else + data &= ~(BIT(5) | BIT(6)); + writel(data, base + REG_DSI_7nm_PHY_CMN_LANE_CTRL1); + + return enable; +} + static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy) { void __iomem *base = phy->base; @@ -943,35 +1209,68 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy) pr_warn("Turning OFF PHY while PLL is on\n"); dsi_phy_hw_v4_0_config_lpcdrx(phy, false); - data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_CTRL_0); + + /* Turn off REFGEN Vote */ + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) || + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { + writel(0x0, base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10); + wmb(); + /* Delay to ensure HW removes vote before PHY shut down */ + udelay(2); + } + + data = readl(base + REG_DSI_7nm_PHY_CMN_CTRL_0); /* disable all lanes */ data &= ~0x1F; - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data); - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0, 0); + writel(data, base + REG_DSI_7nm_PHY_CMN_CTRL_0); + writel(0, base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0); /* Turn off all PHY blocks */ - dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, 0x00); + writel(0x00, base + REG_DSI_7nm_PHY_CMN_CTRL_0); + /* make sure phy is turned off */ wmb(); DBG("DSI%d PHY disabled", phy->id); } +static const struct regulator_bulk_data dsi_phy_7nm_36mA_regulators[] = { + { .supply = "vdds", .init_load_uA = 36000 }, +}; + +static const struct regulator_bulk_data dsi_phy_7nm_37750uA_regulators[] = { + { .supply = "vdds", .init_load_uA = 37550 }, +}; + +static const struct regulator_bulk_data dsi_phy_7nm_48000uA_regulators[] = { + { .supply = "vdds", .init_load_uA = 48000 }, +}; + +static const struct regulator_bulk_data dsi_phy_7nm_98000uA_regulators[] = { + { .supply = "vdds", .init_load_uA = 98000 }, +}; + +static const struct regulator_bulk_data dsi_phy_7nm_97800uA_regulators[] = { + { .supply = "vdds", .init_load_uA = 97800 }, +}; + +static const struct regulator_bulk_data dsi_phy_7nm_98400uA_regulators[] = { + { .supply = "vdds", .init_load_uA = 98400 }, +}; + const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { .has_phy_lane = true, - .reg_cfg = { - .num = 1, - .regs = { - {"vdds", 36000, 32}, - }, - }, + .regulator_data = dsi_phy_7nm_36mA_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_36mA_regulators), .ops = { .enable = dsi_7nm_phy_enable, .disable = dsi_7nm_phy_disable, .pll_init = dsi_pll_7nm_init, .save_pll_state = dsi_7nm_pll_save_state, .restore_pll_state = dsi_7nm_pll_restore_state, + .set_continuous_clock = dsi_7nm_set_continuous_clock, }, .min_pll_rate = 600000000UL, #ifdef CONFIG_64BIT @@ -984,23 +1283,224 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { .quirks = DSI_PHY_7NM_QUIRK_V4_1, }; -const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = { +const struct msm_dsi_phy_cfg dsi_phy_7nm_6375_cfgs = { .has_phy_lane = true, - .reg_cfg = { - .num = 1, - .regs = { - {"vdds", 36000, 32}, - }, + .ops = { + .enable = dsi_7nm_phy_enable, + .disable = dsi_7nm_phy_disable, + .pll_init = dsi_pll_7nm_init, + .save_pll_state = dsi_7nm_pll_save_state, + .restore_pll_state = dsi_7nm_pll_restore_state, }, + .min_pll_rate = 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate = 5000000000ULL, +#else + .max_pll_rate = ULONG_MAX, +#endif + .io_start = { 0x5e94400 }, + .num_dsi_phy = 1, + .quirks = DSI_PHY_7NM_QUIRK_V4_1, +}; + +const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = { + .has_phy_lane = true, + .regulator_data = dsi_phy_7nm_36mA_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_36mA_regulators), .ops = { .enable = dsi_7nm_phy_enable, .disable = dsi_7nm_phy_disable, .pll_init = dsi_pll_7nm_init, .save_pll_state = dsi_7nm_pll_save_state, .restore_pll_state = dsi_7nm_pll_restore_state, + .set_continuous_clock = dsi_7nm_set_continuous_clock, }, .min_pll_rate = 1000000000UL, .max_pll_rate = 3500000000UL, .io_start = { 0xae94400, 0xae96400 }, .num_dsi_phy = 2, + .quirks = DSI_PHY_7NM_QUIRK_PRE_V4_1, +}; + +const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = { + .has_phy_lane = true, + .regulator_data = dsi_phy_7nm_37750uA_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_37750uA_regulators), + .ops = { + .enable = dsi_7nm_phy_enable, + .disable = dsi_7nm_phy_disable, + .pll_init = dsi_pll_7nm_init, + .save_pll_state = dsi_7nm_pll_save_state, + .restore_pll_state = dsi_7nm_pll_restore_state, + }, + .min_pll_rate = 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate = 5000000000ULL, +#else + .max_pll_rate = ULONG_MAX, +#endif + .io_start = { 0xae94400 }, + .num_dsi_phy = 1, + .quirks = DSI_PHY_7NM_QUIRK_V4_1, +}; + +const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs = { + .has_phy_lane = true, + .regulator_data = dsi_phy_7nm_37750uA_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_37750uA_regulators), + .ops = { + .enable = dsi_7nm_phy_enable, + .disable = dsi_7nm_phy_disable, + .pll_init = dsi_pll_7nm_init, + .save_pll_state = dsi_7nm_pll_save_state, + .restore_pll_state = dsi_7nm_pll_restore_state, + .set_continuous_clock = dsi_7nm_set_continuous_clock, + }, + .min_pll_rate = 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate = 5000000000UL, +#else + .max_pll_rate = ULONG_MAX, +#endif + .io_start = { 0xae94400, 0xae96400 }, + .num_dsi_phy = 2, + .quirks = DSI_PHY_7NM_QUIRK_V4_2, +}; + +const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = { + .has_phy_lane = true, + .regulator_data = dsi_phy_7nm_97800uA_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_97800uA_regulators), + .ops = { + .enable = dsi_7nm_phy_enable, + .disable = dsi_7nm_phy_disable, + .pll_init = dsi_pll_7nm_init, + .save_pll_state = dsi_7nm_pll_save_state, + .restore_pll_state = dsi_7nm_pll_restore_state, + .set_continuous_clock = dsi_7nm_set_continuous_clock, + }, + .min_pll_rate = 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate = 5000000000UL, +#else + .max_pll_rate = ULONG_MAX, +#endif + .io_start = { 0xae94400, 0xae96400 }, + .num_dsi_phy = 2, + .quirks = DSI_PHY_7NM_QUIRK_V4_3, +}; + +const struct msm_dsi_phy_cfg dsi_phy_5nm_8775p_cfgs = { + .has_phy_lane = true, + .regulator_data = dsi_phy_7nm_48000uA_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_48000uA_regulators), + .ops = { + .enable = dsi_7nm_phy_enable, + .disable = dsi_7nm_phy_disable, + .pll_init = dsi_pll_7nm_init, + .save_pll_state = dsi_7nm_pll_save_state, + .restore_pll_state = dsi_7nm_pll_restore_state, + .set_continuous_clock = dsi_7nm_set_continuous_clock, + }, + .min_pll_rate = 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate = 5000000000UL, +#else + .max_pll_rate = ULONG_MAX, +#endif + .io_start = { 0xae94400, 0xae96400 }, + .num_dsi_phy = 2, + .quirks = DSI_PHY_7NM_QUIRK_V4_2, +}; + +const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs = { + .has_phy_lane = true, + .regulator_data = dsi_phy_7nm_97800uA_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_97800uA_regulators), + .ops = { + .enable = dsi_7nm_phy_enable, + .disable = dsi_7nm_phy_disable, + .pll_init = dsi_pll_7nm_init, + .save_pll_state = dsi_7nm_pll_save_state, + .restore_pll_state = dsi_7nm_pll_restore_state, + .set_continuous_clock = dsi_7nm_set_continuous_clock, + }, + .min_pll_rate = 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate = 5000000000UL, +#else + .max_pll_rate = ULONG_MAX, +#endif + .io_start = { 0xae95000, 0xae97000 }, + .num_dsi_phy = 2, + .quirks = DSI_PHY_7NM_QUIRK_V5_2, +}; + +const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs = { + .has_phy_lane = true, + .regulator_data = dsi_phy_7nm_98400uA_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_98400uA_regulators), + .ops = { + .enable = dsi_7nm_phy_enable, + .disable = dsi_7nm_phy_disable, + .pll_init = dsi_pll_7nm_init, + .save_pll_state = dsi_7nm_pll_save_state, + .restore_pll_state = dsi_7nm_pll_restore_state, + .set_continuous_clock = dsi_7nm_set_continuous_clock, + }, + .min_pll_rate = 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate = 5000000000UL, +#else + .max_pll_rate = ULONG_MAX, +#endif + .io_start = { 0xae95000, 0xae97000 }, + .num_dsi_phy = 2, + .quirks = DSI_PHY_7NM_QUIRK_V5_2, +}; + +const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs = { + .has_phy_lane = true, + .regulator_data = dsi_phy_7nm_98000uA_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators), + .ops = { + .enable = dsi_7nm_phy_enable, + .disable = dsi_7nm_phy_disable, + .pll_init = dsi_pll_7nm_init, + .save_pll_state = dsi_7nm_pll_save_state, + .restore_pll_state = dsi_7nm_pll_restore_state, + .set_continuous_clock = dsi_7nm_set_continuous_clock, + }, + .min_pll_rate = 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate = 5000000000UL, +#else + .max_pll_rate = ULONG_MAX, +#endif + .io_start = { 0xae95000, 0xae97000 }, + .num_dsi_phy = 2, + .quirks = DSI_PHY_7NM_QUIRK_V5_2, +}; + +const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs = { + .has_phy_lane = true, + .regulator_data = dsi_phy_7nm_98000uA_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators), + .ops = { + .enable = dsi_7nm_phy_enable, + .disable = dsi_7nm_phy_disable, + .pll_init = dsi_pll_7nm_init, + .save_pll_state = dsi_7nm_pll_save_state, + .restore_pll_state = dsi_7nm_pll_restore_state, + .set_continuous_clock = dsi_7nm_set_continuous_clock, + }, + .min_pll_rate = 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate = 5000000000UL, +#else + .max_pll_rate = ULONG_MAX, +#endif + .io_start = { 0xae95000, 0xae97000 }, + .num_dsi_phy = 2, + .quirks = DSI_PHY_7NM_QUIRK_V7_0, }; diff --git a/drivers/gpu/drm/msm/dsi/sfpb.xml.h b/drivers/gpu/drm/msm/dsi/sfpb.xml.h deleted file mode 100644 index 1f5e9e9f9803..000000000000 --- a/drivers/gpu/drm/msm/dsi/sfpb.xml.h +++ /dev/null @@ -1,71 +0,0 @@ -#ifndef SFPB_XML -#define SFPB_XML - -/* Autogenerated file, DO NOT EDIT manually! - -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git - -The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) - -Copyright (C) 2013-2021 by the following authors: -- Rob Clark <robdclark@gmail.com> (robclark) -- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - - -enum sfpb_ahb_arb_master_port_en { - SFPB_MASTER_PORT_ENABLE = 3, - SFPB_MASTER_PORT_DISABLE = 0, -}; - -#define REG_SFPB_GPREG 0x00000058 -#define SFPB_GPREG_MASTER_PORT_EN__MASK 0x00001800 -#define SFPB_GPREG_MASTER_PORT_EN__SHIFT 11 -static inline uint32_t SFPB_GPREG_MASTER_PORT_EN(enum sfpb_ahb_arb_master_port_en val) -{ - return ((val) << SFPB_GPREG_MASTER_PORT_EN__SHIFT) & SFPB_GPREG_MASTER_PORT_EN__MASK; -} - - -#endif /* SFPB_XML */ |