diff options
Diffstat (limited to 'drivers/gpu/drm/msm/msm_mdss.c')
| -rw-r--r-- | drivers/gpu/drm/msm/msm_mdss.c | 279 |
1 files changed, 206 insertions, 73 deletions
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index e13c5c12b775..bf9a33e925ac 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -3,6 +3,7 @@ * Copyright (c) 2018, The Linux Foundation */ +#include <linux/bitfield.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/interconnect.h> @@ -10,24 +11,23 @@ #include <linux/irqchip.h> #include <linux/irqdesc.h> #include <linux/irqchip/chained_irq.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/reset.h> -#include "msm_drv.h" -#include "msm_kms.h" - -/* for DPU_HW_* defines */ -#include "disp/dpu1/dpu_hw_catalog.h" +#include <linux/soc/qcom/ubwc.h> -#define HW_REV 0x0 -#define HW_INTR_STATUS 0x0010 +#include "msm_kms.h" -#define UBWC_STATIC 0x144 -#define UBWC_CTRL_2 0x150 -#define UBWC_PREDICTION_MODE 0x154 +#include <generated/mdss.xml.h> #define MIN_IB_BW 400000000UL /* Min ib vote 400MB */ +struct msm_mdss_data { + u32 reg_bus_bw; +}; + struct msm_mdss { struct device *dev; @@ -39,45 +39,38 @@ struct msm_mdss { unsigned long enabled_mask; struct irq_domain *domain; } irq_controller; - struct icc_path *path[2]; - u32 num_paths; + const struct qcom_ubwc_cfg_data *mdss_data; + u32 reg_bus_bw; + struct icc_path *mdp_path[2]; + u32 num_mdp_paths; + struct icc_path *reg_bus_path; }; static int msm_mdss_parse_data_bus_icc_path(struct device *dev, struct msm_mdss *msm_mdss) { - struct icc_path *path0 = of_icc_get(dev, "mdp0-mem"); - struct icc_path *path1 = of_icc_get(dev, "mdp1-mem"); + struct icc_path *path0; + struct icc_path *path1; + struct icc_path *reg_bus_path; + path0 = devm_of_icc_get(dev, "mdp0-mem"); if (IS_ERR_OR_NULL(path0)) return PTR_ERR_OR_ZERO(path0); - msm_mdss->path[0] = path0; - msm_mdss->num_paths = 1; + msm_mdss->mdp_path[0] = path0; + msm_mdss->num_mdp_paths = 1; + path1 = devm_of_icc_get(dev, "mdp1-mem"); if (!IS_ERR_OR_NULL(path1)) { - msm_mdss->path[1] = path1; - msm_mdss->num_paths++; + msm_mdss->mdp_path[1] = path1; + msm_mdss->num_mdp_paths++; } - return 0; -} - -static void msm_mdss_put_icc_path(void *data) -{ - struct msm_mdss *msm_mdss = data; - int i; - - for (i = 0; i < msm_mdss->num_paths; i++) - icc_put(msm_mdss->path[i]); -} + reg_bus_path = of_icc_get(dev, "cpu-cfg"); + if (!IS_ERR_OR_NULL(reg_bus_path)) + msm_mdss->reg_bus_path = reg_bus_path; -static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long bw) -{ - int i; - - for (i = 0; i < msm_mdss->num_paths; i++) - icc_set_bw(msm_mdss->path[i], 0, Bps_to_icc(bw)); + return 0; } static void msm_mdss_irq(struct irq_desc *desc) @@ -88,7 +81,7 @@ static void msm_mdss_irq(struct irq_desc *desc) chained_irq_enter(chip, desc); - interrupts = readl_relaxed(msm_mdss->mmio + HW_INTR_STATUS); + interrupts = readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_INTR_STATUS); while (interrupts) { irq_hw_number_t hwirq = fls(interrupts) - 1; @@ -161,8 +154,7 @@ static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss) dev = msm_mdss->dev; - domain = irq_domain_add_linear(dev->of_node, 32, - &msm_mdss_irqdomain_ops, msm_mdss); + domain = irq_domain_create_linear(dev_fwnode(dev), 32, &msm_mdss_irqdomain_ops, msm_mdss); if (!domain) { dev_err(dev, "failed to add irq_domain\n"); return -EINVAL; @@ -174,16 +166,97 @@ static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss) return 0; } +static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss) +{ + const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data; + u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); + + if (data->ubwc_bank_spread) + value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; + + if (data->ubwc_enc_version == UBWC_1_0) + value |= MDSS_UBWC_STATIC_UBWC_MIN_ACC_LEN(1); + + writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); +} + +static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss) +{ + const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data; + u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) | + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); + + if (data->macrotile_mode) + value |= MDSS_UBWC_STATIC_MACROTILE_MODE; + + if (data->ubwc_enc_version == UBWC_3_0) + value |= MDSS_UBWC_STATIC_UBWC_AMSBC; + + if (data->ubwc_enc_version == UBWC_1_0) + value |= MDSS_UBWC_STATIC_UBWC_MIN_ACC_LEN(1); + + writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); +} + +static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss) +{ + const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data; + u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); + + if (data->ubwc_bank_spread) + value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; + + if (data->macrotile_mode) + value |= MDSS_UBWC_STATIC_MACROTILE_MODE; + + writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); + + if (data->ubwc_enc_version == UBWC_3_0) { + writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); + writel_relaxed(0, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE); + } else { + if (data->ubwc_dec_version == UBWC_4_3) + writel_relaxed(3, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); + else + writel_relaxed(2, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); + writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE); + } +} + +static void msm_mdss_setup_ubwc_dec_50(struct msm_mdss *msm_mdss) +{ + const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data; + u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); + + if (data->ubwc_bank_spread) + value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; + + if (data->macrotile_mode) + value |= MDSS_UBWC_STATIC_MACROTILE_MODE; + + writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); + + writel_relaxed(4, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); + writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE); +} + static int msm_mdss_enable(struct msm_mdss *msm_mdss) { - int ret; + int ret, i; /* * Several components have AXI clocks that can only be turned on if * the interconnect is enabled (non-zero bandwidth). Let's make sure * that the interconnects are at least at a minimum amount. */ - msm_mdss_icc_request_bw(msm_mdss, MIN_IB_BW); + for (i = 0; i < msm_mdss->num_mdp_paths; i++) + icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW)); + + icc_set_bw(msm_mdss->reg_bus_path, 0, + msm_mdss->reg_bus_bw); ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); if (ret) { @@ -192,32 +265,44 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) } /* - * HW_REV requires MDSS_MDP_CLK, which is not enabled by the mdss on - * mdp5 hardware. Skip reading it for now. + * Register access requires MDSS_MDP_CLK, which is not enabled by the + * mdss on mdp5 hardware. Skip it for now. */ - if (msm_mdss->is_mdp5) + if (msm_mdss->is_mdp5 || !msm_mdss->mdss_data) return 0; /* * ubwc config is part of the "mdss" region which is not accessible * from the rest of the driver. hardcode known configurations here + * + * Decoder version can be read from the UBWC_DEC_HW_VERSION reg, + * UBWC_n and the rest of params comes from hw data. */ - switch (readl_relaxed(msm_mdss->mmio + HW_REV)) { - case DPU_HW_VER_500: - case DPU_HW_VER_501: - writel_relaxed(0x420, msm_mdss->mmio + UBWC_STATIC); + switch (msm_mdss->mdss_data->ubwc_dec_version) { + case 0: /* no UBWC */ + case UBWC_1_0: + /* do nothing */ + break; + case UBWC_2_0: + msm_mdss_setup_ubwc_dec_20(msm_mdss); + break; + case UBWC_3_0: + msm_mdss_setup_ubwc_dec_30(msm_mdss); break; - case DPU_HW_VER_600: - /* TODO: 0x102e for LP_DDR4 */ - writel_relaxed(0x103e, msm_mdss->mmio + UBWC_STATIC); - writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2); - writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE); + case UBWC_4_0: + case UBWC_4_3: + msm_mdss_setup_ubwc_dec_40(msm_mdss); break; - case DPU_HW_VER_620: - writel_relaxed(0x1e, msm_mdss->mmio + UBWC_STATIC); + case UBWC_5_0: + msm_mdss_setup_ubwc_dec_50(msm_mdss); break; - case DPU_HW_VER_720: - writel_relaxed(0x101e, msm_mdss->mmio + UBWC_STATIC); + default: + dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n", + msm_mdss->mdss_data->ubwc_dec_version); + dev_err(msm_mdss->dev, "HW_REV: 0x%x\n", + readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_VERSION)); + dev_err(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n", + readl_relaxed(msm_mdss->mmio + REG_MDSS_UBWC_DEC_HW_VERSION)); break; } @@ -226,8 +311,15 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) static int msm_mdss_disable(struct msm_mdss *msm_mdss) { + int i; + clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks); - msm_mdss_icc_request_bw(msm_mdss, 0); + + for (i = 0; i < msm_mdss->num_mdp_paths; i++) + icc_set_bw(msm_mdss->mdp_path[i], 0, 0); + + if (msm_mdss->reg_bus_path) + icc_set_bw(msm_mdss->reg_bus_path, 0, 0); return 0; } @@ -303,6 +395,7 @@ static int mdp5_mdss_parse_clock(struct platform_device *pdev, struct clk_bulk_d static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5) { + const struct msm_mdss_data *mdss_data; struct msm_mdss *msm_mdss; int ret; int irq; @@ -315,18 +408,25 @@ static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5 if (!msm_mdss) return ERR_PTR(-ENOMEM); + msm_mdss->mdss_data = qcom_ubwc_config_get_data(); + if (IS_ERR(msm_mdss->mdss_data)) + return ERR_CAST(msm_mdss->mdss_data); + + mdss_data = of_device_get_match_data(&pdev->dev); + if (!mdss_data) + return ERR_PTR(-EINVAL); + + msm_mdss->reg_bus_bw = mdss_data->reg_bus_bw; + msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss"); if (IS_ERR(msm_mdss->mmio)) return ERR_CAST(msm_mdss->mmio); - dev_dbg(&pdev->dev, "mapped mdss address space @%pK\n", msm_mdss->mmio); + dev_dbg(&pdev->dev, "mapped mdss address space @%p\n", msm_mdss->mmio); ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss); if (ret) return ERR_PTR(ret); - ret = devm_add_action_or_reset(&pdev->dev, msm_mdss_put_icc_path, msm_mdss); - if (ret) - return ERR_PTR(ret); if (is_mdp5) ret = mdp5_mdss_parse_clock(pdev, &msm_mdss->clocks); @@ -426,27 +526,60 @@ static int mdss_probe(struct platform_device *pdev) return 0; } -static int mdss_remove(struct platform_device *pdev) +static void mdss_remove(struct platform_device *pdev) { struct msm_mdss *mdss = platform_get_drvdata(pdev); of_platform_depopulate(&pdev->dev); msm_mdss_destroy(mdss); - - return 0; } +static const struct msm_mdss_data data_57k = { + .reg_bus_bw = 57000, +}; + +static const struct msm_mdss_data data_74k = { + .reg_bus_bw = 74000, +}; + +static const struct msm_mdss_data data_76k8 = { + .reg_bus_bw = 76800, +}; + +static const struct msm_mdss_data data_153k6 = { + .reg_bus_bw = 153600, +}; + static const struct of_device_id mdss_dt_match[] = { - { .compatible = "qcom,mdss" }, - { .compatible = "qcom,msm8998-mdss" }, - { .compatible = "qcom,qcm2290-mdss" }, - { .compatible = "qcom,sdm845-mdss" }, - { .compatible = "qcom,sc7180-mdss" }, - { .compatible = "qcom,sc7280-mdss" }, - { .compatible = "qcom,sc8180x-mdss" }, - { .compatible = "qcom,sm8150-mdss" }, - { .compatible = "qcom,sm8250-mdss" }, + { .compatible = "qcom,mdss", .data = &data_153k6 }, + { .compatible = "qcom,glymur-mdss", .data = &data_57k }, + { .compatible = "qcom,msm8998-mdss", .data = &data_76k8 }, + { .compatible = "qcom,qcm2290-mdss", .data = &data_76k8 }, + { .compatible = "qcom,qcs8300-mdss", .data = &data_74k }, + { .compatible = "qcom,sa8775p-mdss", .data = &data_74k }, + { .compatible = "qcom,sar2130p-mdss", .data = &data_74k }, + { .compatible = "qcom,sdm670-mdss", .data = &data_76k8 }, + { .compatible = "qcom,sdm845-mdss", .data = &data_76k8 }, + { .compatible = "qcom,sc7180-mdss", .data = &data_76k8 }, + { .compatible = "qcom,sc7280-mdss", .data = &data_74k }, + { .compatible = "qcom,sc8180x-mdss", .data = &data_76k8 }, + { .compatible = "qcom,sc8280xp-mdss", .data = &data_76k8 }, + { .compatible = "qcom,sm6115-mdss", .data = &data_76k8 }, + { .compatible = "qcom,sm6125-mdss", .data = &data_76k8 }, + { .compatible = "qcom,sm6150-mdss", .data = &data_76k8 }, + { .compatible = "qcom,sm6350-mdss", .data = &data_76k8 }, + { .compatible = "qcom,sm6375-mdss", .data = &data_76k8 }, + { .compatible = "qcom,sm7150-mdss", .data = &data_76k8 }, + { .compatible = "qcom,sm8150-mdss", .data = &data_76k8 }, + { .compatible = "qcom,sm8250-mdss", .data = &data_76k8 }, + { .compatible = "qcom,sm8350-mdss", .data = &data_74k }, + { .compatible = "qcom,sm8450-mdss", .data = &data_74k }, + { .compatible = "qcom,sm8550-mdss", .data = &data_57k }, + { .compatible = "qcom,sm8650-mdss", .data = &data_57k }, + { .compatible = "qcom,sm8750-mdss", .data = &data_57k }, + /* TODO: x1e8: Add reg_bus_bw with real value */ + { .compatible = "qcom,x1e80100-mdss", .data = &data_153k6 }, {} }; MODULE_DEVICE_TABLE(of, mdss_dt_match); |