diff options
Diffstat (limited to 'drivers/gpu/drm/omapdrm/omap_crtc.c')
| -rw-r--r-- | drivers/gpu/drm/omapdrm/omap_crtc.c | 1099 |
1 files changed, 630 insertions, 469 deletions
diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c index 11a5263a5e9f..1c2a1920c0a6 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c @@ -1,688 +1,849 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * drivers/gpu/drm/omapdrm/omap_crtc.c - * - * Copyright (C) 2011 Texas Instruments + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ * Author: Rob Clark <rob@ti.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. */ -#include "omap_drv.h" +#include <linux/math64.h> +#include <drm/drm_atomic.h> +#include <drm/drm_atomic_helper.h> +#include <drm/drm_crtc.h> #include <drm/drm_mode.h> -#include "drm_crtc.h" -#include "drm_crtc_helper.h" +#include <drm/drm_print.h> +#include <drm/drm_vblank.h> + +#include "omap_drv.h" + +#define to_omap_crtc_state(x) container_of(x, struct omap_crtc_state, base) + +struct omap_crtc_state { + /* Must be first. */ + struct drm_crtc_state base; + /* Shadow values for legacy userspace support. */ + unsigned int rotation; + unsigned int zpos; + bool manually_updated; +}; #define to_omap_crtc(x) container_of(x, struct omap_crtc, base) struct omap_crtc { struct drm_crtc base; - struct drm_plane *plane; const char *name; - int pipe; + struct omap_drm_pipeline *pipe; enum omap_channel channel; - struct omap_overlay_manager_info info; - /* - * Temporary: eventually this will go away, but it is needed - * for now to keep the output's happy. (They only need - * mgr->id.) Eventually this will be replaced w/ something - * more common-panel-framework-y - */ - struct omap_overlay_manager *mgr; + struct videomode vm; + + bool ignore_digit_sync_lost; - struct omap_video_timings timings; bool enabled; - bool full_update; + bool pending; + wait_queue_head_t pending_wait; + struct drm_pending_vblank_event *event; + struct delayed_work update_work; - struct omap_drm_apply apply; + void (*framedone_handler)(void *); + void *framedone_handler_data; +}; - struct omap_drm_irq apply_irq; - struct omap_drm_irq error_irq; +/* ----------------------------------------------------------------------------- + * Helper Functions + */ - /* list of in-progress apply's: */ - struct list_head pending_applies; +struct videomode *omap_crtc_timings(struct drm_crtc *crtc) +{ + struct omap_crtc *omap_crtc = to_omap_crtc(crtc); + return &omap_crtc->vm; +} - /* list of queued apply's: */ - struct list_head queued_applies; +enum omap_channel omap_crtc_channel(struct drm_crtc *crtc) +{ + struct omap_crtc *omap_crtc = to_omap_crtc(crtc); + return omap_crtc->channel; +} - /* for handling queued and in-progress applies: */ - struct work_struct apply_work; +static bool omap_crtc_is_pending(struct drm_crtc *crtc) +{ + struct omap_crtc *omap_crtc = to_omap_crtc(crtc); + unsigned long flags; + bool pending; - /* if there is a pending flip, these will be non-null: */ - struct drm_pending_vblank_event *event; - struct drm_framebuffer *old_fb; - - /* for handling page flips without caring about what - * the callback is called from. Possibly we should just - * make omap_gem always call the cb from the worker so - * we don't have to care about this.. - * - * XXX maybe fold into apply_work?? - */ - struct work_struct page_flip_work; -}; + spin_lock_irqsave(&crtc->dev->event_lock, flags); + pending = omap_crtc->pending; + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); -uint32_t pipe2vbl(struct drm_crtc *crtc) + return pending; +} + +int omap_crtc_wait_pending(struct drm_crtc *crtc) { struct omap_crtc *omap_crtc = to_omap_crtc(crtc); - return dispc_mgr_get_vsync_irq(omap_crtc->channel); + /* + * Timeout is set to a "sufficiently" high value, which should cover + * a single frame refresh even on slower displays. + */ + return wait_event_timeout(omap_crtc->pending_wait, + !omap_crtc_is_pending(crtc), + msecs_to_jiffies(250)); } +/* ----------------------------------------------------------------------------- + * DSS Manager Functions + */ + /* * Manager-ops, callbacks from output when they need to configure * the upstream part of the video pipe. - * - * Most of these we can ignore until we add support for command-mode - * panels.. for video-mode the crtc-helpers already do an adequate - * job of sequencing the setup of the video pipe in the proper order */ -/* ovl-mgr-id -> crtc */ -static struct omap_crtc *omap_crtcs[8]; +void omap_crtc_dss_start_update(struct omap_drm_private *priv, + enum omap_channel channel) +{ + dispc_mgr_enable(priv->dispc, channel, true); +} -/* we can probably ignore these until we support command-mode panels: */ -static int omap_crtc_connect(struct omap_overlay_manager *mgr, - struct omap_dss_device *dst) +/* Called only from the encoder enable/disable and suspend/resume handlers. */ +void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable) { - if (mgr->output) - return -EINVAL; + struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state); + struct drm_device *dev = crtc->dev; + struct omap_drm_private *priv = dev->dev_private; + struct omap_crtc *omap_crtc = to_omap_crtc(crtc); + enum omap_channel channel = omap_crtc->channel; + struct omap_irq_wait *wait; + u32 framedone_irq, vsync_irq; + int ret; - if ((mgr->supported_outputs & dst->id) == 0) - return -EINVAL; + if (WARN_ON(omap_crtc->enabled == enable)) + return; - dst->manager = mgr; - mgr->output = dst; + if (omap_state->manually_updated) { + omap_irq_enable_framedone(crtc, enable); + omap_crtc->enabled = enable; + return; + } - return 0; -} + if (omap_crtc->pipe->output->type == OMAP_DISPLAY_TYPE_HDMI) { + dispc_mgr_enable(priv->dispc, channel, enable); + omap_crtc->enabled = enable; + return; + } -static void omap_crtc_disconnect(struct omap_overlay_manager *mgr, - struct omap_dss_device *dst) -{ - mgr->output->manager = NULL; - mgr->output = NULL; -} + if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) { + /* + * Digit output produces some sync lost interrupts during the + * first frame when enabling, so we need to ignore those. + */ + omap_crtc->ignore_digit_sync_lost = true; + } -static void omap_crtc_start_update(struct omap_overlay_manager *mgr) -{ + framedone_irq = dispc_mgr_get_framedone_irq(priv->dispc, + channel); + vsync_irq = dispc_mgr_get_vsync_irq(priv->dispc, channel); + + if (enable) { + wait = omap_irq_wait_init(dev, vsync_irq, 1); + } else { + /* + * When we disable the digit output, we need to wait for + * FRAMEDONE to know that DISPC has finished with the output. + * + * OMAP2/3 does not have FRAMEDONE irq for digit output, and in + * that case we need to use vsync interrupt, and wait for both + * even and odd frames. + */ + + if (framedone_irq) + wait = omap_irq_wait_init(dev, framedone_irq, 1); + else + wait = omap_irq_wait_init(dev, vsync_irq, 2); + } + + dispc_mgr_enable(priv->dispc, channel, enable); + omap_crtc->enabled = enable; + + ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100)); + if (ret) { + dev_err(dev->dev, "%s: timeout waiting for %s\n", + omap_crtc->name, enable ? "enable" : "disable"); + } + + if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) { + omap_crtc->ignore_digit_sync_lost = false; + /* make sure the irq handler sees the value above */ + mb(); + } } -static int omap_crtc_enable(struct omap_overlay_manager *mgr) + +int omap_crtc_dss_enable(struct omap_drm_private *priv, enum omap_channel channel) { + struct drm_crtc *crtc = priv->channels[channel]->crtc; + struct omap_crtc *omap_crtc = to_omap_crtc(crtc); + + dispc_mgr_set_timings(priv->dispc, omap_crtc->channel, + &omap_crtc->vm); + omap_crtc_set_enabled(&omap_crtc->base, true); + return 0; } -static void omap_crtc_disable(struct omap_overlay_manager *mgr) +void omap_crtc_dss_disable(struct omap_drm_private *priv, enum omap_channel channel) { + struct drm_crtc *crtc = priv->channels[channel]->crtc; + struct omap_crtc *omap_crtc = to_omap_crtc(crtc); + + omap_crtc_set_enabled(&omap_crtc->base, false); } -static void omap_crtc_set_timings(struct omap_overlay_manager *mgr, - const struct omap_video_timings *timings) +void omap_crtc_dss_set_timings(struct omap_drm_private *priv, + enum omap_channel channel, + const struct videomode *vm) { - struct omap_crtc *omap_crtc = omap_crtcs[mgr->id]; + struct drm_crtc *crtc = priv->channels[channel]->crtc; + struct omap_crtc *omap_crtc = to_omap_crtc(crtc); + DBG("%s", omap_crtc->name); - omap_crtc->timings = *timings; - omap_crtc->full_update = true; + omap_crtc->vm = *vm; } -static void omap_crtc_set_lcd_config(struct omap_overlay_manager *mgr, +void omap_crtc_dss_set_lcd_config(struct omap_drm_private *priv, + enum omap_channel channel, const struct dss_lcd_mgr_config *config) { - struct omap_crtc *omap_crtc = omap_crtcs[mgr->id]; + struct drm_crtc *crtc = priv->channels[channel]->crtc; + struct omap_crtc *omap_crtc = to_omap_crtc(crtc); + DBG("%s", omap_crtc->name); - dispc_mgr_set_lcd_config(omap_crtc->channel, config); + dispc_mgr_set_lcd_config(priv->dispc, omap_crtc->channel, + config); } -static int omap_crtc_register_framedone_handler( - struct omap_overlay_manager *mgr, +int omap_crtc_dss_register_framedone( + struct omap_drm_private *priv, enum omap_channel channel, void (*handler)(void *), void *data) { + struct drm_crtc *crtc = priv->channels[channel]->crtc; + struct omap_crtc *omap_crtc = to_omap_crtc(crtc); + struct drm_device *dev = omap_crtc->base.dev; + + if (omap_crtc->framedone_handler) + return -EBUSY; + + dev_dbg(dev->dev, "register framedone %s", omap_crtc->name); + + omap_crtc->framedone_handler = handler; + omap_crtc->framedone_handler_data = data; + return 0; } -static void omap_crtc_unregister_framedone_handler( - struct omap_overlay_manager *mgr, +void omap_crtc_dss_unregister_framedone( + struct omap_drm_private *priv, enum omap_channel channel, void (*handler)(void *), void *data) { -} + struct drm_crtc *crtc = priv->channels[channel]->crtc; + struct omap_crtc *omap_crtc = to_omap_crtc(crtc); + struct drm_device *dev = omap_crtc->base.dev; -static const struct dss_mgr_ops mgr_ops = { - .connect = omap_crtc_connect, - .disconnect = omap_crtc_disconnect, - .start_update = omap_crtc_start_update, - .enable = omap_crtc_enable, - .disable = omap_crtc_disable, - .set_timings = omap_crtc_set_timings, - .set_lcd_config = omap_crtc_set_lcd_config, - .register_framedone_handler = omap_crtc_register_framedone_handler, - .unregister_framedone_handler = omap_crtc_unregister_framedone_handler, -}; + dev_dbg(dev->dev, "unregister framedone %s", omap_crtc->name); -/* - * CRTC funcs: + WARN_ON(omap_crtc->framedone_handler != handler); + WARN_ON(omap_crtc->framedone_handler_data != data); + + omap_crtc->framedone_handler = NULL; + omap_crtc->framedone_handler_data = NULL; +} + +/* ----------------------------------------------------------------------------- + * Setup, Flush and Page Flip */ -static void omap_crtc_destroy(struct drm_crtc *crtc) +void omap_crtc_error_irq(struct drm_crtc *crtc, u32 irqstatus) { struct omap_crtc *omap_crtc = to_omap_crtc(crtc); - DBG("%s", omap_crtc->name); - - WARN_ON(omap_crtc->apply_irq.registered); - omap_irq_unregister(crtc->dev, &omap_crtc->error_irq); - - omap_crtc->plane->funcs->destroy(omap_crtc->plane); - drm_crtc_cleanup(crtc); + if (omap_crtc->ignore_digit_sync_lost) { + irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT; + if (!irqstatus) + return; + } - kfree(omap_crtc); + DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus); } -static void omap_crtc_dpms(struct drm_crtc *crtc, int mode) +void omap_crtc_vblank_irq(struct drm_crtc *crtc) { - struct omap_drm_private *priv = crtc->dev->dev_private; struct omap_crtc *omap_crtc = to_omap_crtc(crtc); - bool enabled = (mode == DRM_MODE_DPMS_ON); - int i; + struct drm_device *dev = omap_crtc->base.dev; + struct omap_drm_private *priv = dev->dev_private; + bool pending; - DBG("%s: %d", omap_crtc->name, mode); + spin_lock(&crtc->dev->event_lock); + /* + * If the dispc is busy we're racing the flush operation. Try again on + * the next vblank interrupt. + */ + if (dispc_mgr_go_busy(priv->dispc, omap_crtc->channel)) { + spin_unlock(&crtc->dev->event_lock); + return; + } - if (enabled != omap_crtc->enabled) { - omap_crtc->enabled = enabled; - omap_crtc->full_update = true; - omap_crtc_apply(crtc, &omap_crtc->apply); + /* Send the vblank event if one has been requested. */ + if (omap_crtc->event) { + drm_crtc_send_vblank_event(crtc, omap_crtc->event); + omap_crtc->event = NULL; + } - /* also enable our private plane: */ - WARN_ON(omap_plane_dpms(omap_crtc->plane, mode)); + pending = omap_crtc->pending; + omap_crtc->pending = false; + spin_unlock(&crtc->dev->event_lock); - /* and any attached overlay planes: */ - for (i = 0; i < priv->num_planes; i++) { - struct drm_plane *plane = priv->planes[i]; - if (plane->crtc == crtc) - WARN_ON(omap_plane_dpms(plane, mode)); - } - } -} + if (pending) + drm_crtc_vblank_put(crtc); -static bool omap_crtc_mode_fixup(struct drm_crtc *crtc, - const struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -{ - return true; + /* Wake up omap_atomic_complete. */ + wake_up(&omap_crtc->pending_wait); + + DBG("%s: apply done", omap_crtc->name); } -static int omap_crtc_mode_set(struct drm_crtc *crtc, - struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode, - int x, int y, - struct drm_framebuffer *old_fb) +void omap_crtc_framedone_irq(struct drm_crtc *crtc, uint32_t irqstatus) { struct omap_crtc *omap_crtc = to_omap_crtc(crtc); - mode = adjusted_mode; + if (!omap_crtc->framedone_handler) + return; - DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x", - omap_crtc->name, mode->base.id, mode->name, - mode->vrefresh, mode->clock, - mode->hdisplay, mode->hsync_start, - mode->hsync_end, mode->htotal, - mode->vdisplay, mode->vsync_start, - mode->vsync_end, mode->vtotal, - mode->type, mode->flags); + omap_crtc->framedone_handler(omap_crtc->framedone_handler_data); - copy_timings_drm_to_omap(&omap_crtc->timings, mode); - omap_crtc->full_update = true; + spin_lock(&crtc->dev->event_lock); + /* Send the vblank event if one has been requested. */ + if (omap_crtc->event) { + drm_crtc_send_vblank_event(crtc, omap_crtc->event); + omap_crtc->event = NULL; + } + omap_crtc->pending = false; + spin_unlock(&crtc->dev->event_lock); - return omap_plane_mode_set(omap_crtc->plane, crtc, crtc->fb, - 0, 0, mode->hdisplay, mode->vdisplay, - x << 16, y << 16, - mode->hdisplay << 16, mode->vdisplay << 16, - NULL, NULL); + /* Wake up omap_atomic_complete. */ + wake_up(&omap_crtc->pending_wait); } -static void omap_crtc_prepare(struct drm_crtc *crtc) +void omap_crtc_flush(struct drm_crtc *crtc) { struct omap_crtc *omap_crtc = to_omap_crtc(crtc); - DBG("%s", omap_crtc->name); - omap_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); + struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state); + + if (!omap_state->manually_updated) + return; + + if (!delayed_work_pending(&omap_crtc->update_work)) + schedule_delayed_work(&omap_crtc->update_work, 0); } -static void omap_crtc_commit(struct drm_crtc *crtc) +static void omap_crtc_manual_display_update(struct work_struct *data) { - struct omap_crtc *omap_crtc = to_omap_crtc(crtc); - DBG("%s", omap_crtc->name); - omap_crtc_dpms(crtc, DRM_MODE_DPMS_ON); + struct omap_crtc *omap_crtc = + container_of(data, struct omap_crtc, update_work.work); + struct omap_dss_device *dssdev = omap_crtc->pipe->output; + struct drm_device *dev = omap_crtc->base.dev; + int ret; + + if (!dssdev || !dssdev->dsi_ops || !dssdev->dsi_ops->update) + return; + + ret = dssdev->dsi_ops->update(dssdev); + if (ret < 0) { + spin_lock_irq(&dev->event_lock); + omap_crtc->pending = false; + spin_unlock_irq(&dev->event_lock); + wake_up(&omap_crtc->pending_wait); + } } -static int omap_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, - struct drm_framebuffer *old_fb) +static s16 omap_crtc_s31_32_to_s2_8(s64 coef) { - struct omap_crtc *omap_crtc = to_omap_crtc(crtc); - struct drm_plane *plane = omap_crtc->plane; - struct drm_display_mode *mode = &crtc->mode; + u64 sign_bit = 1ULL << 63; + u64 cbits = (u64)coef; + + s16 ret = clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x1ff); - return omap_plane_mode_set(plane, crtc, crtc->fb, - 0, 0, mode->hdisplay, mode->vdisplay, - x << 16, y << 16, - mode->hdisplay << 16, mode->vdisplay << 16, - NULL, NULL); + if (cbits & sign_bit) + ret = -ret; + + return ret; } -static void vblank_cb(void *arg) +static void omap_crtc_cpr_coefs_from_ctm(const struct drm_color_ctm *ctm, + struct omap_dss_cpr_coefs *cpr) { - struct drm_crtc *crtc = arg; - struct drm_device *dev = crtc->dev; + cpr->rr = omap_crtc_s31_32_to_s2_8(ctm->matrix[0]); + cpr->rg = omap_crtc_s31_32_to_s2_8(ctm->matrix[1]); + cpr->rb = omap_crtc_s31_32_to_s2_8(ctm->matrix[2]); + cpr->gr = omap_crtc_s31_32_to_s2_8(ctm->matrix[3]); + cpr->gg = omap_crtc_s31_32_to_s2_8(ctm->matrix[4]); + cpr->gb = omap_crtc_s31_32_to_s2_8(ctm->matrix[5]); + cpr->br = omap_crtc_s31_32_to_s2_8(ctm->matrix[6]); + cpr->bg = omap_crtc_s31_32_to_s2_8(ctm->matrix[7]); + cpr->bb = omap_crtc_s31_32_to_s2_8(ctm->matrix[8]); +} + +static void omap_crtc_write_crtc_properties(struct drm_crtc *crtc) +{ + struct omap_drm_private *priv = crtc->dev->dev_private; struct omap_crtc *omap_crtc = to_omap_crtc(crtc); - unsigned long flags; + struct omap_overlay_manager_info info; - spin_lock_irqsave(&dev->event_lock, flags); + memset(&info, 0, sizeof(info)); - /* wakeup userspace */ - if (omap_crtc->event) - drm_send_vblank_event(dev, omap_crtc->pipe, omap_crtc->event); + info.default_color = 0x000000; + info.trans_enabled = false; + info.partial_alpha_enabled = false; - omap_crtc->event = NULL; - omap_crtc->old_fb = NULL; + if (crtc->state->ctm) { + struct drm_color_ctm *ctm = crtc->state->ctm->data; - spin_unlock_irqrestore(&dev->event_lock, flags); + info.cpr_enable = true; + omap_crtc_cpr_coefs_from_ctm(ctm, &info.cpr_coefs); + } else { + info.cpr_enable = false; + } + + dispc_mgr_setup(priv->dispc, omap_crtc->channel, &info); } -static void page_flip_worker(struct work_struct *work) +/* ----------------------------------------------------------------------------- + * CRTC Functions + */ + +static void omap_crtc_destroy(struct drm_crtc *crtc) { - struct omap_crtc *omap_crtc = - container_of(work, struct omap_crtc, page_flip_work); - struct drm_crtc *crtc = &omap_crtc->base; - struct drm_display_mode *mode = &crtc->mode; - struct drm_gem_object *bo; + struct omap_crtc *omap_crtc = to_omap_crtc(crtc); - mutex_lock(&crtc->mutex); - omap_plane_mode_set(omap_crtc->plane, crtc, crtc->fb, - 0, 0, mode->hdisplay, mode->vdisplay, - crtc->x << 16, crtc->y << 16, - mode->hdisplay << 16, mode->vdisplay << 16, - vblank_cb, crtc); - mutex_unlock(&crtc->mutex); + DBG("%s", omap_crtc->name); - bo = omap_framebuffer_bo(crtc->fb, 0); - drm_gem_object_unreference_unlocked(bo); + drm_crtc_cleanup(crtc); + + kfree(omap_crtc); } -static void page_flip_cb(void *arg) +static void omap_crtc_arm_event(struct drm_crtc *crtc) { - struct drm_crtc *crtc = arg; struct omap_crtc *omap_crtc = to_omap_crtc(crtc); - struct omap_drm_private *priv = crtc->dev->dev_private; - /* avoid assumptions about what ctxt we are called from: */ - queue_work(priv->wq, &omap_crtc->page_flip_work); + WARN_ON(omap_crtc->pending); + omap_crtc->pending = true; + + if (crtc->state->event) { + omap_crtc->event = crtc->state->event; + crtc->state->event = NULL; + } } -static int omap_crtc_page_flip_locked(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_pending_vblank_event *event) +static void omap_crtc_atomic_enable(struct drm_crtc *crtc, + struct drm_atomic_state *state) { - struct drm_device *dev = crtc->dev; + struct omap_drm_private *priv = crtc->dev->dev_private; struct omap_crtc *omap_crtc = to_omap_crtc(crtc); - struct drm_gem_object *bo; + struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state); + int ret; - DBG("%d -> %d (event=%p)", crtc->fb ? crtc->fb->base.id : -1, - fb->base.id, event); + DBG("%s", omap_crtc->name); - if (omap_crtc->old_fb) { - dev_err(dev->dev, "already a pending flip\n"); - return -EINVAL; - } + dispc_runtime_get(priv->dispc); - omap_crtc->event = event; - crtc->fb = fb; + /* manual updated display will not trigger vsync irq */ + if (omap_state->manually_updated) + return; - /* - * Hold a reference temporarily until the crtc is updated - * and takes the reference to the bo. This avoids it - * getting freed from under us: - */ - bo = omap_framebuffer_bo(fb, 0); - drm_gem_object_reference(bo); + drm_crtc_vblank_on(crtc); - omap_gem_op_async(bo, OMAP_GEM_READ, page_flip_cb, crtc); + ret = drm_crtc_vblank_get(crtc); + WARN_ON(ret != 0); - return 0; + spin_lock_irq(&crtc->dev->event_lock); + omap_crtc_arm_event(crtc); + spin_unlock_irq(&crtc->dev->event_lock); } -static int omap_crtc_set_property(struct drm_crtc *crtc, - struct drm_property *property, uint64_t val) +static void omap_crtc_atomic_disable(struct drm_crtc *crtc, + struct drm_atomic_state *state) { - struct omap_crtc *omap_crtc = to_omap_crtc(crtc); struct omap_drm_private *priv = crtc->dev->dev_private; + struct omap_crtc *omap_crtc = to_omap_crtc(crtc); + struct drm_device *dev = crtc->dev; + + DBG("%s", omap_crtc->name); - if (property == priv->rotation_prop) { - crtc->invert_dimensions = - !!(val & ((1LL << DRM_ROTATE_90) | (1LL << DRM_ROTATE_270))); + spin_lock_irq(&crtc->dev->event_lock); + if (crtc->state->event) { + drm_crtc_send_vblank_event(crtc, crtc->state->event); + crtc->state->event = NULL; } + spin_unlock_irq(&crtc->dev->event_lock); - return omap_plane_set_property(omap_crtc->plane, property, val); -} + cancel_delayed_work(&omap_crtc->update_work); -static const struct drm_crtc_funcs omap_crtc_funcs = { - .set_config = drm_crtc_helper_set_config, - .destroy = omap_crtc_destroy, - .page_flip = omap_crtc_page_flip_locked, - .set_property = omap_crtc_set_property, -}; + if (!omap_crtc_wait_pending(crtc)) + dev_warn(dev->dev, "manual display update did not finish!"); -static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = { - .dpms = omap_crtc_dpms, - .mode_fixup = omap_crtc_mode_fixup, - .mode_set = omap_crtc_mode_set, - .prepare = omap_crtc_prepare, - .commit = omap_crtc_commit, - .mode_set_base = omap_crtc_mode_set_base, -}; + drm_crtc_vblank_off(crtc); -const struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc) -{ - struct omap_crtc *omap_crtc = to_omap_crtc(crtc); - return &omap_crtc->timings; + dispc_runtime_put(priv->dispc); } -enum omap_channel omap_crtc_channel(struct drm_crtc *crtc) +static enum drm_mode_status omap_crtc_mode_valid(struct drm_crtc *crtc, + const struct drm_display_mode *mode) { + struct omap_drm_private *priv = crtc->dev->dev_private; struct omap_crtc *omap_crtc = to_omap_crtc(crtc); - return omap_crtc->channel; + struct videomode vm = {0}; + int r; + + drm_display_mode_to_videomode(mode, &vm); + + /* + * DSI might not call this, since the supplied mode is not a + * valid DISPC mode. DSI will calculate and configure the + * proper DISPC mode later. + */ + if (omap_crtc->pipe->output->type != OMAP_DISPLAY_TYPE_DSI) { + r = dispc_mgr_check_timings(priv->dispc, + omap_crtc->channel, + &vm); + if (r) + return r; + } + + /* Check for bandwidth limit */ + if (priv->max_bandwidth) { + /* + * Estimation for the bandwidth need of a given mode with one + * full screen plane: + * bandwidth = resolution * 32bpp * (pclk / (vtotal * htotal)) + * ^^ Refresh rate ^^ + * + * The interlaced mode is taken into account by using the + * pixelclock in the calculation. + * + * The equation is rearranged for 64bit arithmetic. + */ + uint64_t bandwidth = mode->clock * 1000; + unsigned int bpp = 4; + + bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp; + bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal); + + /* + * Reject modes which would need more bandwidth if used with one + * full resolution plane (most common use case). + */ + if (priv->max_bandwidth < bandwidth) + return MODE_BAD; + } + + return MODE_OK; } -static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus) +static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc) { - struct omap_crtc *omap_crtc = - container_of(irq, struct omap_crtc, error_irq); - struct drm_crtc *crtc = &omap_crtc->base; - DRM_ERROR("%s: errors: %08x\n", omap_crtc->name, irqstatus); - /* avoid getting in a flood, unregister the irq until next vblank */ - omap_irq_unregister(crtc->dev, &omap_crtc->error_irq); + struct omap_crtc *omap_crtc = to_omap_crtc(crtc); + struct drm_display_mode *mode = &crtc->state->adjusted_mode; + + DBG("%s: set mode: " DRM_MODE_FMT, + omap_crtc->name, DRM_MODE_ARG(mode)); + + drm_display_mode_to_videomode(mode, &omap_crtc->vm); } -static void omap_crtc_apply_irq(struct omap_drm_irq *irq, uint32_t irqstatus) +static bool omap_crtc_is_manually_updated(struct drm_crtc *crtc) { - struct omap_crtc *omap_crtc = - container_of(irq, struct omap_crtc, apply_irq); - struct drm_crtc *crtc = &omap_crtc->base; - - if (!omap_crtc->error_irq.registered) - omap_irq_register(crtc->dev, &omap_crtc->error_irq); - - if (!dispc_mgr_go_busy(omap_crtc->channel)) { - struct omap_drm_private *priv = - crtc->dev->dev_private; - DBG("%s: apply done", omap_crtc->name); - omap_irq_unregister(crtc->dev, &omap_crtc->apply_irq); - queue_work(priv->wq, &omap_crtc->apply_work); - } + struct omap_crtc *omap_crtc = to_omap_crtc(crtc); + struct omap_dss_device *dssdev = omap_crtc->pipe->output; + + if (!dssdev || !dssdev->dsi_ops || !dssdev->dsi_ops->is_video_mode) + return false; + + if (dssdev->dsi_ops->is_video_mode(dssdev)) + return false; + + DBG("detected manually updated display!"); + return true; } -static void apply_worker(struct work_struct *work) +static int omap_crtc_atomic_check(struct drm_crtc *crtc, + struct drm_atomic_state *state) { - struct omap_crtc *omap_crtc = - container_of(work, struct omap_crtc, apply_work); - struct drm_crtc *crtc = &omap_crtc->base; - struct drm_device *dev = crtc->dev; - struct omap_drm_apply *apply, *n; - bool need_apply; + struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, + crtc); + struct drm_plane_state *pri_state; - /* - * Synchronize everything on mode_config.mutex, to keep - * the callbacks and list modification all serialized - * with respect to modesetting ioctls from userspace. - */ - mutex_lock(&crtc->mutex); - dispc_runtime_get(); + if (crtc_state->color_mgmt_changed && crtc_state->degamma_lut) { + unsigned int length = crtc_state->degamma_lut->length / + sizeof(struct drm_color_lut); - /* - * If we are still pending a previous update, wait.. when the - * pending update completes, we get kicked again. - */ - if (omap_crtc->apply_irq.registered) - goto out; - - /* finish up previous apply's: */ - list_for_each_entry_safe(apply, n, - &omap_crtc->pending_applies, pending_node) { - apply->post_apply(apply); - list_del(&apply->pending_node); + if (length < 2) + return -EINVAL; } - need_apply = !list_empty(&omap_crtc->queued_applies); + pri_state = drm_atomic_get_new_plane_state(state, + crtc->primary); + if (pri_state) { + struct omap_crtc_state *omap_crtc_state = + to_omap_crtc_state(crtc_state); - /* then handle the next round of of queued apply's: */ - list_for_each_entry_safe(apply, n, - &omap_crtc->queued_applies, queued_node) { - apply->pre_apply(apply); - list_del(&apply->queued_node); - apply->queued = false; - list_add_tail(&apply->pending_node, - &omap_crtc->pending_applies); + /* Mirror new values for zpos and rotation in omap_crtc_state */ + omap_crtc_state->zpos = pri_state->zpos; + omap_crtc_state->rotation = pri_state->rotation; + + /* Check if this CRTC is for a manually updated display */ + omap_crtc_state->manually_updated = omap_crtc_is_manually_updated(crtc); } - if (need_apply) { - enum omap_channel channel = omap_crtc->channel; + return 0; +} - DBG("%s: GO", omap_crtc->name); +static void omap_crtc_atomic_begin(struct drm_crtc *crtc, + struct drm_atomic_state *state) +{ +} - if (dispc_mgr_is_enabled(channel)) { - omap_irq_register(dev, &omap_crtc->apply_irq); - dispc_mgr_go(channel); - } else { - struct omap_drm_private *priv = dev->dev_private; - queue_work(priv->wq, &omap_crtc->apply_work); +static void omap_crtc_atomic_flush(struct drm_crtc *crtc, + struct drm_atomic_state *state) +{ + struct omap_drm_private *priv = crtc->dev->dev_private; + struct omap_crtc *omap_crtc = to_omap_crtc(crtc); + struct omap_crtc_state *omap_crtc_state = to_omap_crtc_state(crtc->state); + int ret; + + if (crtc->state->color_mgmt_changed) { + struct drm_color_lut *lut = NULL; + unsigned int length = 0; + + if (crtc->state->degamma_lut) { + lut = (struct drm_color_lut *) + crtc->state->degamma_lut->data; + length = crtc->state->degamma_lut->length / + sizeof(*lut); } + dispc_mgr_set_gamma(priv->dispc, omap_crtc->channel, + lut, length); } -out: - dispc_runtime_put(); - mutex_unlock(&crtc->mutex); -} + omap_crtc_write_crtc_properties(crtc); -int omap_crtc_apply(struct drm_crtc *crtc, - struct omap_drm_apply *apply) -{ - struct omap_crtc *omap_crtc = to_omap_crtc(crtc); + /* Only flush the CRTC if it is currently enabled. */ + if (!omap_crtc->enabled) + return; - WARN_ON(!mutex_is_locked(&crtc->mutex)); + DBG("%s: GO", omap_crtc->name); - /* no need to queue it again if it is already queued: */ - if (apply->queued) - return 0; + if (omap_crtc_state->manually_updated) { + /* send new image for page flips and modeset changes */ + spin_lock_irq(&crtc->dev->event_lock); + omap_crtc_flush(crtc); + omap_crtc_arm_event(crtc); + spin_unlock_irq(&crtc->dev->event_lock); + return; + } - apply->queued = true; - list_add_tail(&apply->queued_node, &omap_crtc->queued_applies); + ret = drm_crtc_vblank_get(crtc); + WARN_ON(ret != 0); + + spin_lock_irq(&crtc->dev->event_lock); + dispc_mgr_go(priv->dispc, omap_crtc->channel); + omap_crtc_arm_event(crtc); + spin_unlock_irq(&crtc->dev->event_lock); +} + +static int omap_crtc_atomic_set_property(struct drm_crtc *crtc, + struct drm_crtc_state *state, + struct drm_property *property, + u64 val) +{ + struct omap_drm_private *priv = crtc->dev->dev_private; + struct drm_plane_state *plane_state; /* - * If there are no currently pending updates, then go ahead and - * kick the worker immediately, otherwise it will run again when - * the current update finishes. + * Delegate property set to the primary plane. Get the plane state and + * set the property directly, the shadow copy will be assigned in the + * omap_crtc_atomic_check callback. This way updates to plane state will + * always be mirrored in the crtc state correctly. */ - if (list_empty(&omap_crtc->pending_applies)) { - struct omap_drm_private *priv = crtc->dev->dev_private; - queue_work(priv->wq, &omap_crtc->apply_work); - } + plane_state = drm_atomic_get_plane_state(state->state, crtc->primary); + if (IS_ERR(plane_state)) + return PTR_ERR(plane_state); + + if (property == crtc->primary->rotation_property) + plane_state->rotation = val; + else if (property == priv->zorder_prop) + plane_state->zpos = val; + else + return -EINVAL; return 0; } -/* called only from apply */ -static void set_enabled(struct drm_crtc *crtc, bool enable) +static int omap_crtc_atomic_get_property(struct drm_crtc *crtc, + const struct drm_crtc_state *state, + struct drm_property *property, + u64 *val) { - struct drm_device *dev = crtc->dev; - struct omap_crtc *omap_crtc = to_omap_crtc(crtc); - enum omap_channel channel = omap_crtc->channel; - struct omap_irq_wait *wait = NULL; + struct omap_drm_private *priv = crtc->dev->dev_private; + struct omap_crtc_state *omap_state = to_omap_crtc_state(state); - if (dispc_mgr_is_enabled(channel) == enable) - return; + if (property == crtc->primary->rotation_property) + *val = omap_state->rotation; + else if (property == priv->zorder_prop) + *val = omap_state->zpos; + else + return -EINVAL; - /* ignore sync-lost irqs during enable/disable */ - omap_irq_unregister(crtc->dev, &omap_crtc->error_irq); + return 0; +} - if (dispc_mgr_get_framedone_irq(channel)) { - if (!enable) { - wait = omap_irq_wait_init(dev, - dispc_mgr_get_framedone_irq(channel), 1); - } - } else { - /* - * When we disable digit output, we need to wait until fields - * are done. Otherwise the DSS is still working, and turning - * off the clocks prevents DSS from going to OFF mode. And when - * enabling, we need to wait for the extra sync losts - */ - wait = omap_irq_wait_init(dev, - dispc_mgr_get_vsync_irq(channel), 2); - } +static void omap_crtc_reset(struct drm_crtc *crtc) +{ + struct omap_crtc_state *state; - dispc_mgr_enable(channel, enable); + if (crtc->state) + __drm_atomic_helper_crtc_destroy_state(crtc->state); - if (wait) { - int ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100)); - if (ret) { - dev_err(dev->dev, "%s: timeout waiting for %s\n", - omap_crtc->name, enable ? "enable" : "disable"); - } - } + kfree(crtc->state); - omap_irq_register(crtc->dev, &omap_crtc->error_irq); + state = kzalloc(sizeof(*state), GFP_KERNEL); + if (state) + __drm_atomic_helper_crtc_reset(crtc, &state->base); } -static void omap_crtc_pre_apply(struct omap_drm_apply *apply) +static struct drm_crtc_state * +omap_crtc_duplicate_state(struct drm_crtc *crtc) { - struct omap_crtc *omap_crtc = - container_of(apply, struct omap_crtc, apply); - struct drm_crtc *crtc = &omap_crtc->base; - struct drm_encoder *encoder = NULL; - - DBG("%s: enabled=%d, full=%d", omap_crtc->name, - omap_crtc->enabled, omap_crtc->full_update); - - if (omap_crtc->full_update) { - struct omap_drm_private *priv = crtc->dev->dev_private; - int i; - for (i = 0; i < priv->num_encoders; i++) { - if (priv->encoders[i]->crtc == crtc) { - encoder = priv->encoders[i]; - break; - } - } - } + struct omap_crtc_state *state, *current_state; - if (!omap_crtc->enabled) { - set_enabled(&omap_crtc->base, false); - if (encoder) - omap_encoder_set_enabled(encoder, false); - } else { - if (encoder) { - omap_encoder_set_enabled(encoder, false); - omap_encoder_update(encoder, omap_crtc->mgr, - &omap_crtc->timings); - omap_encoder_set_enabled(encoder, true); - omap_crtc->full_update = false; - } + if (WARN_ON(!crtc->state)) + return NULL; - dispc_mgr_setup(omap_crtc->channel, &omap_crtc->info); - dispc_mgr_set_timings(omap_crtc->channel, - &omap_crtc->timings); - set_enabled(&omap_crtc->base, true); - } + current_state = to_omap_crtc_state(crtc->state); - omap_crtc->full_update = false; -} + state = kmalloc(sizeof(*state), GFP_KERNEL); + if (!state) + return NULL; -static void omap_crtc_post_apply(struct omap_drm_apply *apply) -{ - /* nothing needed for post-apply */ + __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); + + state->zpos = current_state->zpos; + state->rotation = current_state->rotation; + state->manually_updated = current_state->manually_updated; + + return &state->base; } -static const char *channel_names[] = { - [OMAP_DSS_CHANNEL_LCD] = "lcd", - [OMAP_DSS_CHANNEL_DIGIT] = "tv", - [OMAP_DSS_CHANNEL_LCD2] = "lcd2", +static const struct drm_crtc_funcs omap_crtc_funcs = { + .reset = omap_crtc_reset, + .set_config = drm_atomic_helper_set_config, + .destroy = omap_crtc_destroy, + .page_flip = drm_atomic_helper_page_flip, + .atomic_duplicate_state = omap_crtc_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, + .atomic_set_property = omap_crtc_atomic_set_property, + .atomic_get_property = omap_crtc_atomic_get_property, + .enable_vblank = omap_irq_enable_vblank, + .disable_vblank = omap_irq_disable_vblank, }; -void omap_crtc_pre_init(void) -{ - dss_install_mgr_ops(&mgr_ops); -} +static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = { + .mode_set_nofb = omap_crtc_mode_set_nofb, + .atomic_check = omap_crtc_atomic_check, + .atomic_begin = omap_crtc_atomic_begin, + .atomic_flush = omap_crtc_atomic_flush, + .atomic_enable = omap_crtc_atomic_enable, + .atomic_disable = omap_crtc_atomic_disable, + .mode_valid = omap_crtc_mode_valid, +}; + +/* ----------------------------------------------------------------------------- + * Init and Cleanup + */ + +static const char *channel_names[] = { + [OMAP_DSS_CHANNEL_LCD] = "lcd", + [OMAP_DSS_CHANNEL_DIGIT] = "tv", + [OMAP_DSS_CHANNEL_LCD2] = "lcd2", + [OMAP_DSS_CHANNEL_LCD3] = "lcd3", +}; /* initialize crtc */ struct drm_crtc *omap_crtc_init(struct drm_device *dev, - struct drm_plane *plane, enum omap_channel channel, int id) + struct omap_drm_pipeline *pipe, + struct drm_plane *plane) { + struct omap_drm_private *priv = dev->dev_private; struct drm_crtc *crtc = NULL; struct omap_crtc *omap_crtc; - struct omap_overlay_manager_info *info; + enum omap_channel channel; + int ret; + + channel = pipe->output->dispc_channel; DBG("%s", channel_names[channel]); omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL); if (!omap_crtc) - goto fail; + return ERR_PTR(-ENOMEM); crtc = &omap_crtc->base; - INIT_WORK(&omap_crtc->page_flip_work, page_flip_worker); - INIT_WORK(&omap_crtc->apply_work, apply_worker); - - INIT_LIST_HEAD(&omap_crtc->pending_applies); - INIT_LIST_HEAD(&omap_crtc->queued_applies); - - omap_crtc->apply.pre_apply = omap_crtc_pre_apply; - omap_crtc->apply.post_apply = omap_crtc_post_apply; + init_waitqueue_head(&omap_crtc->pending_wait); + omap_crtc->pipe = pipe; omap_crtc->channel = channel; - omap_crtc->plane = plane; - omap_crtc->plane->crtc = crtc; omap_crtc->name = channel_names[channel]; - omap_crtc->pipe = id; - - omap_crtc->apply_irq.irqmask = pipe2vbl(crtc); - omap_crtc->apply_irq.irq = omap_crtc_apply_irq; - - omap_crtc->error_irq.irqmask = - dispc_mgr_get_sync_lost_irq(channel); - omap_crtc->error_irq.irq = omap_crtc_error_irq; - omap_irq_register(dev, &omap_crtc->error_irq); - - /* temporary: */ - omap_crtc->mgr = omap_dss_get_overlay_manager(channel); - /* TODO: fix hard-coded setup.. add properties! */ - info = &omap_crtc->info; - info->default_color = 0x00000000; - info->trans_key = 0x00000000; - info->trans_key_type = OMAP_DSS_COLOR_KEY_GFX_DST; - info->trans_enabled = false; + /* + * We want to refresh manually updated displays from dirty callback, + * which is called quite often (e.g. for each drawn line). This will + * be used to do the display update asynchronously to avoid blocking + * the rendering process and merges multiple dirty calls into one + * update if they arrive very fast. We also call this function for + * atomic display updates (e.g. for page flips), which means we do + * not need extra locking. Atomic updates should be synchronous, but + * need to wait for the framedone interrupt anyways. + */ + INIT_DELAYED_WORK(&omap_crtc->update_work, + omap_crtc_manual_display_update); + + ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL, + &omap_crtc_funcs, NULL); + if (ret < 0) { + dev_err(dev->dev, "%s(): could not init crtc for: %s\n", + __func__, pipe->output->name); + kfree(omap_crtc); + return ERR_PTR(ret); + } - drm_crtc_init(dev, crtc, &omap_crtc_funcs); drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs); - omap_plane_install_properties(omap_crtc->plane, &crtc->base); - - omap_crtcs[channel] = omap_crtc; + /* The dispc API adapts to what ever size, but the HW supports + * 256 element gamma table for LCDs and 1024 element table for + * OMAP_DSS_CHANNEL_DIGIT. X server assumes 256 element gamma + * tables so lets use that. Size of HW gamma table can be + * extracted with dispc_mgr_gamma_size(). If it returns 0 + * gamma table is not supported. + */ + if (dispc_mgr_gamma_size(priv->dispc, channel)) { + unsigned int gamma_lut_size = 256; - return crtc; + drm_crtc_enable_color_mgmt(crtc, gamma_lut_size, true, 0); + drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size); + } -fail: - if (crtc) - omap_crtc_destroy(crtc); + omap_plane_install_properties(crtc->primary, &crtc->base); - return NULL; + return crtc; } |