diff options
Diffstat (limited to 'drivers/gpu/drm/rcar-du/rcar_du_regs.h')
| -rw-r--r-- | drivers/gpu/drm/rcar-du/rcar_du_regs.h | 445 |
1 files changed, 0 insertions, 445 deletions
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_regs.h b/drivers/gpu/drm/rcar-du/rcar_du_regs.h deleted file mode 100644 index 69f21f19b51c..000000000000 --- a/drivers/gpu/drm/rcar-du/rcar_du_regs.h +++ /dev/null @@ -1,445 +0,0 @@ -/* - * rcar_du_regs.h -- R-Car Display Unit Registers Definitions - * - * Copyright (C) 2013 Renesas Electronics Corporation - * - * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - */ - -#ifndef __RCAR_DU_REGS_H__ -#define __RCAR_DU_REGS_H__ - -#define DISP2_REG_OFFSET 0x30000 - -/* ----------------------------------------------------------------------------- - * Display Control Registers - */ - -#define DSYSR 0x00000 /* display 1 */ -#define D2SYSR 0x30000 /* display 2 */ -#define DSYSR_ILTS (1 << 29) -#define DSYSR_DSEC (1 << 20) -#define DSYSR_IUPD (1 << 16) -#define DSYSR_DRES (1 << 9) -#define DSYSR_DEN (1 << 8) -#define DSYSR_TVM_MASTER (0 << 6) -#define DSYSR_TVM_SWITCH (1 << 6) -#define DSYSR_TVM_TVSYNC (2 << 6) -#define DSYSR_TVM_MASK (3 << 6) -#define DSYSR_SCM_INT_NONE (0 << 4) -#define DSYSR_SCM_INT_SYNC (2 << 4) -#define DSYSR_SCM_INT_VIDEO (3 << 4) - -#define DSMR 0x00004 -#define D2SMR 0x30004 -#define DSMR_VSPM (1 << 28) -#define DSMR_ODPM (1 << 27) -#define DSMR_DIPM_DISP (0 << 25) -#define DSMR_DIPM_CSYNC (1 << 25) -#define DSMR_DIPM_DE (3 << 25) -#define DSMR_DIPM_MASK (3 << 25) -#define DSMR_CSPM (1 << 24) -#define DSMR_DIL (1 << 19) -#define DSMR_VSL (1 << 18) -#define DSMR_HSL (1 << 17) -#define DSMR_DDIS (1 << 16) -#define DSMR_CDEL (1 << 15) -#define DSMR_CDEM_CDE (0 << 13) -#define DSMR_CDEM_LOW (2 << 13) -#define DSMR_CDEM_HIGH (3 << 13) -#define DSMR_CDEM_MASK (3 << 13) -#define DSMR_CDED (1 << 12) -#define DSMR_ODEV (1 << 8) -#define DSMR_CSY_VH_OR (0 << 6) -#define DSMR_CSY_333 (2 << 6) -#define DSMR_CSY_222 (3 << 6) -#define DSMR_CSY_MASK (3 << 6) - -#define DSSR 0x00008 -#define D2SSR 0x30008 -#define DSSR_VC1FB_DSA0 (0 << 30) -#define DSSR_VC1FB_DSA1 (1 << 30) -#define DSSR_VC1FB_DSA2 (2 << 30) -#define DSSR_VC1FB_INIT (3 << 30) -#define DSSR_VC1FB_MASK (3 << 30) -#define DSSR_VC0FB_DSA0 (0 << 28) -#define DSSR_VC0FB_DSA1 (1 << 28) -#define DSSR_VC0FB_DSA2 (2 << 28) -#define DSSR_VC0FB_INIT (3 << 28) -#define DSSR_VC0FB_MASK (3 << 28) -#define DSSR_DFB(n) (1 << ((n)+15)) -#define DSSR_TVR (1 << 15) -#define DSSR_FRM (1 << 14) -#define DSSR_VBK (1 << 11) -#define DSSR_RINT (1 << 9) -#define DSSR_HBK (1 << 8) -#define DSSR_ADC(n) (1 << ((n)-1)) - -#define DSRCR 0x0000c -#define D2SRCR 0x3000c -#define DSRCR_TVCL (1 << 15) -#define DSRCR_FRCL (1 << 14) -#define DSRCR_VBCL (1 << 11) -#define DSRCR_RICL (1 << 9) -#define DSRCR_HBCL (1 << 8) -#define DSRCR_ADCL(n) (1 << ((n)-1)) -#define DSRCR_MASK 0x0000cbff - -#define DIER 0x00010 -#define D2IER 0x30010 -#define DIER_TVE (1 << 15) -#define DIER_FRE (1 << 14) -#define DIER_VBE (1 << 11) -#define DIER_RIE (1 << 9) -#define DIER_HBE (1 << 8) -#define DIER_ADCE(n) (1 << ((n)-1)) - -#define CPCR 0x00014 -#define CPCR_CP4CE (1 << 19) -#define CPCR_CP3CE (1 << 18) -#define CPCR_CP2CE (1 << 17) -#define CPCR_CP1CE (1 << 16) - -#define DPPR 0x00018 -#define DPPR_DPE(n) (1 << ((n)*4-1)) -#define DPPR_DPS(n, p) (((p)-1) << DPPR_DPS_SHIFT(n)) -#define DPPR_DPS_SHIFT(n) (((n)-1)*4) -#define DPPR_BPP16 (DPPR_DPE(8) | DPPR_DPS(8, 1)) /* plane1 */ -#define DPPR_BPP32_P1 (DPPR_DPE(7) | DPPR_DPS(7, 1)) -#define DPPR_BPP32_P2 (DPPR_DPE(8) | DPPR_DPS(8, 2)) -#define DPPR_BPP32 (DPPR_BPP32_P1 | DPPR_BPP32_P2) /* plane1 & 2 */ - -#define DEFR 0x00020 -#define D2EFR 0x30020 -#define DEFR_CODE (0x7773 << 16) -#define DEFR_EXSL (1 << 12) -#define DEFR_EXVL (1 << 11) -#define DEFR_EXUP (1 << 5) -#define DEFR_VCUP (1 << 4) -#define DEFR_DEFE (1 << 0) - -#define DAPCR 0x00024 -#define DAPCR_CODE (0x7773 << 16) -#define DAPCR_AP2E (1 << 4) -#define DAPCR_AP1E (1 << 0) - -#define DCPCR 0x00028 -#define DCPCR_CODE (0x7773 << 16) -#define DCPCR_CA2B (1 << 13) -#define DCPCR_CD2F (1 << 12) -#define DCPCR_DC2E (1 << 8) -#define DCPCR_CAB (1 << 5) -#define DCPCR_CDF (1 << 4) -#define DCPCR_DCE (1 << 0) - -#define DEFR2 0x00034 -#define D2EFR2 0x30034 -#define DEFR2_CODE (0x7775 << 16) -#define DEFR2_DEFE2G (1 << 0) - -#define DEFR3 0x00038 -#define D2EFR3 0x30038 -#define DEFR3_CODE (0x7776 << 16) -#define DEFR3_EVDA (1 << 14) -#define DEFR3_EVDM_1 (1 << 12) -#define DEFR3_EVDM_2 (2 << 12) -#define DEFR3_EVDM_3 (3 << 12) -#define DEFR3_VMSM2_EMA (1 << 6) -#define DEFR3_VMSM1_ENA (1 << 4) -#define DEFR3_DEFE3 (1 << 0) - -#define DEFR4 0x0003c -#define D2EFR4 0x3003c -#define DEFR4_CODE (0x7777 << 16) -#define DEFR4_LRUO (1 << 5) -#define DEFR4_SPCE (1 << 4) - -#define DVCSR 0x000d0 -#define DVCSR_VCnFB2_DSA0(n) (0 << ((n)*2+16)) -#define DVCSR_VCnFB2_DSA1(n) (1 << ((n)*2+16)) -#define DVCSR_VCnFB2_DSA2(n) (2 << ((n)*2+16)) -#define DVCSR_VCnFB2_INIT(n) (3 << ((n)*2+16)) -#define DVCSR_VCnFB2_MASK(n) (3 << ((n)*2+16)) -#define DVCSR_VCnFB_DSA0(n) (0 << ((n)*2)) -#define DVCSR_VCnFB_DSA1(n) (1 << ((n)*2)) -#define DVCSR_VCnFB_DSA2(n) (2 << ((n)*2)) -#define DVCSR_VCnFB_INIT(n) (3 << ((n)*2)) -#define DVCSR_VCnFB_MASK(n) (3 << ((n)*2)) - -#define DEFR5 0x000e0 -#define DEFR5_CODE (0x66 << 24) -#define DEFR5_YCRGB2_DIS (0 << 14) -#define DEFR5_YCRGB2_PRI1 (1 << 14) -#define DEFR5_YCRGB2_PRI2 (2 << 14) -#define DEFR5_YCRGB2_PRI3 (3 << 14) -#define DEFR5_YCRGB2_MASK (3 << 14) -#define DEFR5_YCRGB1_DIS (0 << 12) -#define DEFR5_YCRGB1_PRI1 (1 << 12) -#define DEFR5_YCRGB1_PRI2 (2 << 12) -#define DEFR5_YCRGB1_PRI3 (3 << 12) -#define DEFR5_YCRGB1_MASK (3 << 12) -#define DEFR5_DEFE5 (1 << 0) - -#define DDLTR 0x000e4 -#define DDLTR_CODE (0x7766 << 16) -#define DDLTR_DLAR2 (1 << 6) -#define DDLTR_DLAY2 (1 << 5) -#define DDLTR_DLAY1 (1 << 1) - -#define DEFR6 0x000e8 -#define DEFR6_CODE (0x7778 << 16) -#define DEFR6_ODPM22_D2SMR (0 << 10) -#define DEFR6_ODPM22_DISP (2 << 10) -#define DEFR6_ODPM22_CDE (3 << 10) -#define DEFR6_ODPM22_MASK (3 << 10) -#define DEFR6_ODPM12_DSMR (0 << 8) -#define DEFR6_ODPM12_DISP (2 << 8) -#define DEFR6_ODPM12_CDE (3 << 8) -#define DEFR6_ODPM12_MASK (3 << 8) -#define DEFR6_TCNE2 (1 << 6) -#define DEFR6_MLOS1 (1 << 2) -#define DEFR6_DEFAULT (DEFR6_CODE | DEFR6_TCNE2) - -/* ----------------------------------------------------------------------------- - * Display Timing Generation Registers - */ - -#define HDSR 0x00040 -#define HDER 0x00044 -#define VDSR 0x00048 -#define VDER 0x0004c -#define HCR 0x00050 -#define HSWR 0x00054 -#define VCR 0x00058 -#define VSPR 0x0005c -#define EQWR 0x00060 -#define SPWR 0x00064 -#define CLAMPSR 0x00070 -#define CLAMPWR 0x00074 -#define DESR 0x00078 -#define DEWR 0x0007c - -/* ----------------------------------------------------------------------------- - * Display Attribute Registers - */ - -#define CP1TR 0x00080 -#define CP2TR 0x00084 -#define CP3TR 0x00088 -#define CP4TR 0x0008c - -#define DOOR 0x00090 -#define DOOR_RGB(r, g, b) (((r) << 18) | ((g) << 10) | ((b) << 2)) -#define CDER 0x00094 -#define CDER_RGB(r, g, b) (((r) << 18) | ((g) << 10) | ((b) << 2)) -#define BPOR 0x00098 -#define BPOR_RGB(r, g, b) (((r) << 18) | ((g) << 10) | ((b) << 2)) - -#define RINTOFSR 0x0009c - -#define DSHPR 0x000c8 -#define DSHPR_CODE (0x7776 << 16) -#define DSHPR_PRIH (0xa << 4) -#define DSHPR_PRIL_BPP16 (0x8 << 0) -#define DSHPR_PRIL_BPP32 (0x9 << 0) - -/* ----------------------------------------------------------------------------- - * Display Plane Registers - */ - -#define PLANE_OFF 0x00100 - -#define PnMR 0x00100 /* plane 1 */ -#define PnMR_VISL_VIN0 (0 << 26) /* use Video Input 0 */ -#define PnMR_VISL_VIN1 (1 << 26) /* use Video Input 1 */ -#define PnMR_VISL_VIN2 (2 << 26) /* use Video Input 2 */ -#define PnMR_VISL_VIN3 (3 << 26) /* use Video Input 3 */ -#define PnMR_YCDF_YUYV (1 << 20) /* YUYV format */ -#define PnMR_TC_R (0 << 17) /* Tranparent color is PnTC1R */ -#define PnMR_TC_CP (1 << 17) /* Tranparent color is color palette */ -#define PnMR_WAE (1 << 16) /* Wrap around Enable */ -#define PnMR_SPIM_TP (0 << 12) /* Transparent Color */ -#define PnMR_SPIM_ALP (1 << 12) /* Alpha Blending */ -#define PnMR_SPIM_EOR (2 << 12) /* EOR */ -#define PnMR_SPIM_TP_OFF (1 << 14) /* No Transparent Color */ -#define PnMR_CPSL_CP1 (0 << 8) /* Color Palette selected 1 */ -#define PnMR_CPSL_CP2 (1 << 8) /* Color Palette selected 2 */ -#define PnMR_CPSL_CP3 (2 << 8) /* Color Palette selected 3 */ -#define PnMR_CPSL_CP4 (3 << 8) /* Color Palette selected 4 */ -#define PnMR_DC (1 << 7) /* Display Area Change */ -#define PnMR_BM_MD (0 << 4) /* Manual Display Change Mode */ -#define PnMR_BM_AR (1 << 4) /* Auto Rendering Mode */ -#define PnMR_BM_AD (2 << 4) /* Auto Display Change Mode */ -#define PnMR_BM_VC (3 << 4) /* Video Capture Mode */ -#define PnMR_DDDF_8BPP (0 << 0) /* 8bit */ -#define PnMR_DDDF_16BPP (1 << 0) /* 16bit or 32bit */ -#define PnMR_DDDF_ARGB (2 << 0) /* ARGB */ -#define PnMR_DDDF_YC (3 << 0) /* YC */ -#define PnMR_DDDF_MASK (3 << 0) - -#define PnMWR 0x00104 - -#define PnALPHAR 0x00108 -#define PnALPHAR_ABIT_1 (0 << 12) -#define PnALPHAR_ABIT_0 (1 << 12) -#define PnALPHAR_ABIT_X (2 << 12) - -#define PnDSXR 0x00110 -#define PnDSYR 0x00114 -#define PnDPXR 0x00118 -#define PnDPYR 0x0011c - -#define PnDSA0R 0x00120 -#define PnDSA1R 0x00124 -#define PnDSA2R 0x00128 -#define PnDSA_MASK 0xfffffff0 - -#define PnSPXR 0x00130 -#define PnSPYR 0x00134 -#define PnWASPR 0x00138 -#define PnWAMWR 0x0013c - -#define PnBTR 0x00140 - -#define PnTC1R 0x00144 -#define PnTC2R 0x00148 -#define PnTC3R 0x0014c -#define PnTC3R_CODE (0x66 << 24) - -#define PnMLR 0x00150 - -#define PnSWAPR 0x00180 -#define PnSWAPR_DIGN (1 << 4) -#define PnSWAPR_SPQW (1 << 3) -#define PnSWAPR_SPLW (1 << 2) -#define PnSWAPR_SPWD (1 << 1) -#define PnSWAPR_SPBY (1 << 0) - -#define PnDDCR 0x00184 -#define PnDDCR_CODE (0x7775 << 16) -#define PnDDCR_LRGB1 (1 << 11) -#define PnDDCR_LRGB0 (1 << 10) - -#define PnDDCR2 0x00188 -#define PnDDCR2_CODE (0x7776 << 16) -#define PnDDCR2_NV21 (1 << 5) -#define PnDDCR2_Y420 (1 << 4) -#define PnDDCR2_DIVU (1 << 1) -#define PnDDCR2_DIVY (1 << 0) - -#define PnDDCR4 0x00190 -#define PnDDCR4_CODE (0x7766 << 16) -#define PnDDCR4_SDFS_RGB (0 << 4) -#define PnDDCR4_SDFS_YC (5 << 4) -#define PnDDCR4_SDFS_MASK (7 << 4) -#define PnDDCR4_EDF_NONE (0 << 0) -#define PnDDCR4_EDF_ARGB8888 (1 << 0) -#define PnDDCR4_EDF_RGB888 (2 << 0) -#define PnDDCR4_EDF_RGB666 (3 << 0) -#define PnDDCR4_EDF_MASK (7 << 0) - -#define APnMR 0x0a100 -#define APnMR_WAE (1 << 16) /* Wrap around Enable */ -#define APnMR_DC (1 << 7) /* Display Area Change */ -#define APnMR_BM_MD (0 << 4) /* Manual Display Change Mode */ -#define APnMR_BM_AD (2 << 4) /* Auto Display Change Mode */ - -#define APnMWR 0x0a104 -#define APnDSA0R 0x0a120 -#define APnDSA1R 0x0a124 -#define APnDSA2R 0x0a128 -#define APnMLR 0x0a150 - -/* ----------------------------------------------------------------------------- - * Display Capture Registers - */ - -#define DCMWR 0x0c104 -#define DC2MWR 0x0c204 -#define DCSAR 0x0c120 -#define DC2SAR 0x0c220 -#define DCMLR 0x0c150 -#define DC2MLR 0x0c250 - -/* ----------------------------------------------------------------------------- - * Color Palette Registers - */ - -#define CP1_000R 0x01000 -#define CP1_255R 0x013fc -#define CP2_000R 0x02000 -#define CP2_255R 0x023fc -#define CP3_000R 0x03000 -#define CP3_255R 0x033fc -#define CP4_000R 0x04000 -#define CP4_255R 0x043fc - -/* ----------------------------------------------------------------------------- - * External Synchronization Control Registers - */ - -#define ESCR 0x10000 -#define ESCR2 0x31000 -#define ESCR_DCLKOINV (1 << 25) -#define ESCR_DCLKSEL_DCLKIN (0 << 20) -#define ESCR_DCLKSEL_CLKS (1 << 20) -#define ESCR_DCLKSEL_MASK (1 << 20) -#define ESCR_DCLKDIS (1 << 16) -#define ESCR_SYNCSEL_OFF (0 << 8) -#define ESCR_SYNCSEL_EXVSYNC (2 << 8) -#define ESCR_SYNCSEL_EXHSYNC (3 << 8) -#define ESCR_FRQSEL_MASK (0x3f << 0) - -#define OTAR 0x10004 -#define OTAR2 0x31004 - -/* ----------------------------------------------------------------------------- - * Dual Display Output Control Registers - */ - -#define DORCR 0x11000 -#define DORCR_PG2T (1 << 30) -#define DORCR_DK2S (1 << 28) -#define DORCR_PG2D_DS1 (0 << 24) -#define DORCR_PG2D_DS2 (1 << 24) -#define DORCR_PG2D_FIX0 (2 << 24) -#define DORCR_PG2D_DOOR (3 << 24) -#define DORCR_PG2D_MASK (3 << 24) -#define DORCR_DR1D (1 << 21) -#define DORCR_PG1D_DS1 (0 << 16) -#define DORCR_PG1D_DS2 (1 << 16) -#define DORCR_PG1D_FIX0 (2 << 16) -#define DORCR_PG1D_DOOR (3 << 16) -#define DORCR_PG1D_MASK (3 << 16) -#define DORCR_RGPV (1 << 4) -#define DORCR_DPRS (1 << 0) - -#define DPTSR 0x11004 -#define DPTSR_PnDK(n) (1 << ((n) + 16)) -#define DPTSR_PnTS(n) (1 << (n)) - -#define DAPTSR 0x11008 -#define DAPTSR_APnDK(n) (1 << ((n) + 16)) -#define DAPTSR_APnTS(n) (1 << (n)) - -#define DS1PR 0x11020 -#define DS2PR 0x11024 - -/* ----------------------------------------------------------------------------- - * YC-RGB Conversion Coefficient Registers - */ - -#define YNCR 0x11080 -#define YNOR 0x11084 -#define CRNOR 0x11088 -#define CBNOR 0x1108c -#define RCRCR 0x11090 -#define GCRCR 0x11094 -#define GCBCR 0x11098 -#define BCBCR 0x1109c - -#endif /* __RCAR_DU_REGS_H__ */ |