diff options
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_gt_regs.h | 76 |
1 files changed, 38 insertions, 38 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index 2c48de2076a6..d7f52a634c11 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -42,11 +42,6 @@ #define FORCEWAKE_ACK_GSC XE_REG(0xdf8) #define FORCEWAKE_ACK_GT_MTL XE_REG(0xdfc) -/* L3 Cache Control */ -#define XELP_LNCFCMOCS(i) XE_REG(0xb020 + (i) * 4) -#define XEHP_LNCFCMOCS(i) XE_REG_MCR(0xb020 + (i) * 4) -#define LNCFCMOCS_REG_COUNT 32 - #define MCFG_MCR_SELECTOR XE_REG(0xfd0) #define MTL_MCR_SELECTOR XE_REG(0xfd4) #define SF_MCR_SELECTOR XE_REG(0xfd8) @@ -102,6 +97,12 @@ #define CACHE_MODE_1 XE_REG(0x7004, XE_REG_OPTION_MASKED) #define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11) +#define COMMON_SLICE_CHICKEN1 XE_REG(0x7010) + +#define HIZ_CHICKEN XE_REG(0x7018, XE_REG_OPTION_MASKED) +#define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14) +#define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE REG_BIT(13) + #define XEHP_PSS_MODE2 XE_REG_MCR(0x703c, XE_REG_OPTION_MASKED) #define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) @@ -109,12 +110,6 @@ #define FLSH_IGNORES_PSD REG_BIT(10) #define FD_END_COLLECT REG_BIT(5) -#define HIZ_CHICKEN XE_REG(0x7018, XE_REG_OPTION_MASKED) -#define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14) -#define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE REG_BIT(13) - -#define COMMON_SLICE_CHICKEN1 XE_REG(0x7010) - #define COMMON_SLICE_CHICKEN4 XE_REG(0x7300, XE_REG_OPTION_MASKED) #define DISABLE_TDC_LOAD_BALANCING_CALC REG_BIT(6) @@ -149,6 +144,11 @@ #define GSCPSMI_BASE XE_REG(0x880c) +/* Fuse readout registers for GT */ +#define XEHP_FUSE4 XE_REG(0x9114) +#define CCS_EN_MASK REG_GENMASK(19, 16) +#define GT_L3_EXC_MASK REG_GENMASK(6, 4) + #define MIRROR_FUSE3 XE_REG(0x9118) #define XE2_NODE_ENABLE_MASK REG_GENMASK(31, 16) #define L3BANK_PAIR_COUNT 4 @@ -157,18 +157,14 @@ #define MAX_MSLICES 4 #define MEML3_EN_MASK REG_GENMASK(3, 0) -/* Fuse readout registers for GT */ -#define XEHP_FUSE4 XE_REG(0x9114) -#define CCS_EN_MASK REG_GENMASK(19, 16) -#define GT_L3_EXC_MASK REG_GENMASK(6, 4) +#define XELP_EU_ENABLE XE_REG(0x9134) /* "_DISABLE" on Xe_LP */ +#define XELP_EU_MASK REG_GENMASK(7, 0) +#define XELP_GT_GEOMETRY_DSS_ENABLE XE_REG(0x913c) #define GT_VEBOX_VDBOX_DISABLE XE_REG(0x9140) #define GT_VEBOX_DISABLE_MASK REG_GENMASK(19, 16) #define GT_VDBOX_DISABLE_MASK REG_GENMASK(7, 0) -#define XELP_EU_ENABLE XE_REG(0x9134) /* "_DISABLE" on Xe_LP */ -#define XELP_EU_MASK REG_GENMASK(7, 0) -#define XELP_GT_GEOMETRY_DSS_ENABLE XE_REG(0x913c) #define XEHP_GT_COMPUTE_DSS_ENABLE XE_REG(0x9144) #define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT XE_REG(0x9148) #define XE2_GT_COMPUTE_DSS_2 XE_REG(0x914c) @@ -284,6 +280,11 @@ #define XEHPC_LNCFMISCCFGREG0 XE_REG_MCR(0xb01c, XE_REG_OPTION_MASKED) #define XEHPC_OVRLSCCC REG_BIT(0) +/* L3 Cache Control */ +#define XELP_LNCFCMOCS(i) XE_REG(0xb020 + (i) * 4) +#define XEHP_LNCFCMOCS(i) XE_REG_MCR(0xb020 + (i) * 4) +#define LNCFCMOCS_REG_COUNT 32 + #define XEHP_L3NODEARBCFG XE_REG_MCR(0xb0b4) #define XEHP_LNESPARE REG_BIT(19) @@ -360,13 +361,13 @@ #define PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8) #define DISABLE_DOP_GATING REG_BIT(0) +#define RT_CTRL XE_REG_MCR(0xe530) +#define DIS_NULL_QUERY REG_BIT(10) + #define XEHP_HDC_CHICKEN0 XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED) #define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11) #define DIS_ATOMIC_CHAINING_TYPED_WRITES REG_BIT(3) -#define RT_CTRL XE_REG_MCR(0xe530) -#define DIS_NULL_QUERY REG_BIT(10) - #define LSC_CHICKEN_BIT_0 XE_REG_MCR(0xe7c8) #define DISABLE_D8_D16_COASLESCE REG_BIT(30) #define TGM_WRITE_EOM_FORCE REG_BIT(17) @@ -408,6 +409,7 @@ #define FORCEWAKE_USER BIT(1) #define FORCEWAKE_KERNEL_FALLBACK BIT(15) +#define MTL_MEDIA_PERF_LIMIT_REASONS XE_REG(0x138030) #define MTL_MEDIA_MC6 XE_REG(0x138048) #define GT_CORE_STATUS XE_REG(0x138060) @@ -418,16 +420,30 @@ #define GT_GFX_RC6_LOCKED XE_REG(0x138104) #define GT_GFX_RC6 XE_REG(0x138108) +#define GT0_PERF_LIMIT_REASONS XE_REG(0x1381a8) +#define GT0_PERF_LIMIT_REASONS_MASK 0xde3 +#define PROCHOT_MASK REG_BIT(0) +#define THERMAL_LIMIT_MASK REG_BIT(1) +#define RATL_MASK REG_BIT(5) +#define VR_THERMALERT_MASK REG_BIT(6) +#define VR_TDC_MASK REG_BIT(7) +#define POWER_LIMIT_4_MASK REG_BIT(8) +#define POWER_LIMIT_1_MASK REG_BIT(10) +#define POWER_LIMIT_2_MASK REG_BIT(11) + #define GT_PERF_STATUS XE_REG(0x1381b4) #define VOLTAGE_MASK REG_GENMASK(10, 0) #define GT_INTR_DW(x) XE_REG(0x190018 + ((x) * 4)) +#define RENDER_COPY_INTR_ENABLE XE_REG(0x190030) +#define VCS_VECS_INTR_ENABLE XE_REG(0x190034) #define GUC_SG_INTR_ENABLE XE_REG(0x190038) #define ENGINE1_MASK REG_GENMASK(31, 16) #define ENGINE0_MASK REG_GENMASK(15, 0) - #define GPM_WGBOXPERF_INTR_ENABLE XE_REG(0x19003c) +#define GUNIT_GSC_INTR_ENABLE XE_REG(0x190044) +#define CCS_RSVD_INTR_ENABLE XE_REG(0x190048) #define INTR_IDENTITY_REG(x) XE_REG(0x190060 + ((x) * 4)) #define INTR_DATA_VALID REG_BIT(31) @@ -437,10 +453,6 @@ #define OTHER_GUC_INSTANCE 0 #define OTHER_GSC_INSTANCE 6 -#define RENDER_COPY_INTR_ENABLE XE_REG(0x190030) -#define VCS_VECS_INTR_ENABLE XE_REG(0x190034) -#define GUNIT_GSC_INTR_ENABLE XE_REG(0x190044) -#define CCS_RSVD_INTR_ENABLE XE_REG(0x190048) #define IIR_REG_SELECTOR(x) XE_REG(0x190070 + ((x) * 4)) #define RCS0_RSVD_INTR_MASK XE_REG(0x190090) #define BCS_RSVD_INTR_MASK XE_REG(0x1900a0) @@ -468,16 +480,4 @@ #define PVC_GT0_PLATFORM_ENERGY_STATUS XE_REG(0x28106c) #define PVC_GT0_PACKAGE_POWER_SKU XE_REG(0x281080) -#define GT0_PERF_LIMIT_REASONS XE_REG(0x1381a8) -#define GT0_PERF_LIMIT_REASONS_MASK 0xde3 -#define PROCHOT_MASK REG_BIT(0) -#define THERMAL_LIMIT_MASK REG_BIT(1) -#define RATL_MASK REG_BIT(5) -#define VR_THERMALERT_MASK REG_BIT(6) -#define VR_TDC_MASK REG_BIT(7) -#define POWER_LIMIT_4_MASK REG_BIT(8) -#define POWER_LIMIT_1_MASK REG_BIT(10) -#define POWER_LIMIT_2_MASK REG_BIT(11) -#define MTL_MEDIA_PERF_LIMIT_REASONS XE_REG(0x138030) - #endif |