diff options
Diffstat (limited to 'drivers/iio/adc')
60 files changed, 1272 insertions, 272 deletions
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 48ace7412874..7fe5930891e0 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -417,7 +417,6 @@ config DLN2_ADC config ENVELOPE_DETECTOR tristate "Envelope detector using a DAC and a comparator" - depends on OF help Say yes here to build support for an envelope detector using a DAC and a comparator. @@ -563,7 +562,7 @@ config LP8788_ADC config LPC18XX_ADC tristate "NXP LPC18xx ADC driver" depends on ARCH_LPC18XX || COMPILE_TEST - depends on OF && HAS_IOMEM + depends on HAS_IOMEM help Say yes here to build support for NXP LPC18XX ADC. @@ -823,6 +822,18 @@ config QCOM_PM8XXX_XOADC To compile this driver as a module, choose M here: the module will be called qcom-pm8xxx-xoadc. +config QCOM_SPMI_RRADC + tristate "Qualcomm SPMI RRADC" + depends on MFD_SPMI_PMIC + help + This is for the PMIC Round Robin ADC driver. + + This driver exposes the battery ID resistor, battery thermal, PMIC die + temperature, charger USB in and DC in voltage and current. + + To compile this driver as a module, choose M here: the module will + be called qcom-qpmi-rradc. + config QCOM_SPMI_IADC tristate "Qualcomm SPMI PMIC current ADC" depends on SPMI @@ -941,7 +952,6 @@ config SPEAR_ADC config SD_ADC_MODULATOR tristate "Generic sigma delta modulator" - depends on OF select IIO_BUFFER select IIO_TRIGGERED_BUFFER help @@ -1259,7 +1269,6 @@ config TWL6030_GPADC config VF610_ADC tristate "Freescale vf610 ADC driver" - depends on OF depends on HAS_IOMEM select IIO_BUFFER select IIO_TRIGGERED_BUFFER diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 39d806f6d457..1772a549a3c8 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -78,6 +78,7 @@ obj-$(CONFIG_NPCM_ADC) += npcm_adc.o obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o obj-$(CONFIG_QCOM_SPMI_ADC5) += qcom-spmi-adc5.o obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o +obj-$(CONFIG_QCOM_SPMI_RRADC) += qcom-spmi-rradc.o obj-$(CONFIG_QCOM_VADC_COMMON) += qcom-vadc-common.o obj-$(CONFIG_QCOM_SPMI_VADC) += qcom-spmi-vadc.o obj-$(CONFIG_QCOM_PM8XXX_XOADC) += qcom-pm8xxx-xoadc.o diff --git a/drivers/iio/adc/ad7266.c b/drivers/iio/adc/ad7266.c index f20d39f0bc01..468c2656d2be 100644 --- a/drivers/iio/adc/ad7266.c +++ b/drivers/iio/adc/ad7266.c @@ -37,7 +37,7 @@ struct ad7266_state { struct gpio_desc *gpios[3]; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. * The buffer needs to be large enough to hold two samples (4 bytes) and * the naturally aligned timestamp (8 bytes). @@ -45,7 +45,7 @@ struct ad7266_state { struct { __be16 sample[2]; s64 timestamp; - } data ____cacheline_aligned; + } data __aligned(IIO_DMA_MINALIGN); }; static int ad7266_wakeup(struct ad7266_state *st) diff --git a/drivers/iio/adc/ad7280a.c b/drivers/iio/adc/ad7280a.c index 3bdf3d9422f2..d4a4e15c8244 100644 --- a/drivers/iio/adc/ad7280a.c +++ b/drivers/iio/adc/ad7280a.c @@ -183,7 +183,7 @@ struct ad7280_state { unsigned char cb_mask[AD7280A_MAX_CHAIN]; struct mutex lock; /* protect sensor state */ - __be32 tx ____cacheline_aligned; + __be32 tx __aligned(IIO_DMA_MINALIGN); __be32 rx; }; diff --git a/drivers/iio/adc/ad7292.c b/drivers/iio/adc/ad7292.c index 3271a31afde1..92c68d467c50 100644 --- a/drivers/iio/adc/ad7292.c +++ b/drivers/iio/adc/ad7292.c @@ -80,7 +80,7 @@ struct ad7292_state { struct regulator *reg; unsigned short vref_mv; - __be16 d16 ____cacheline_aligned; + __be16 d16 __aligned(IIO_DMA_MINALIGN); u8 d8[2]; }; diff --git a/drivers/iio/adc/ad7298.c b/drivers/iio/adc/ad7298.c index 3f4e73f7d35a..c0430f71f592 100644 --- a/drivers/iio/adc/ad7298.c +++ b/drivers/iio/adc/ad7298.c @@ -49,7 +49,7 @@ struct ad7298_state { * DMA (thus cache coherency maintenance) requires the * transfer buffers to live in their own cache lines. */ - __be16 rx_buf[12] ____cacheline_aligned; + __be16 rx_buf[12] __aligned(IIO_DMA_MINALIGN); __be16 tx_buf[2]; }; diff --git a/drivers/iio/adc/ad7476.c b/drivers/iio/adc/ad7476.c index a1e8b32671cf..94776f696290 100644 --- a/drivers/iio/adc/ad7476.c +++ b/drivers/iio/adc/ad7476.c @@ -44,13 +44,12 @@ struct ad7476_state { struct spi_transfer xfer; struct spi_message msg; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. * Make the buffer large enough for one 16 bit sample and one 64 bit * aligned 64 bit timestamp. */ - unsigned char data[ALIGN(2, sizeof(s64)) + sizeof(s64)] - ____cacheline_aligned; + unsigned char data[ALIGN(2, sizeof(s64)) + sizeof(s64)] __aligned(IIO_DMA_MINALIGN); }; enum ad7476_supported_device_ids { diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index 3b193dc26438..ba24f99523e0 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -12,6 +12,7 @@ #include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/module.h> +#include <linux/property.h> #include <linux/regulator/consumer.h> #include <linux/sched.h> #include <linux/slab.h> diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index 4f82d7c9acfd..2dc4f599f9df 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -116,11 +116,11 @@ struct ad7606_state { struct completion completion; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. * 16 * 16-bit samples + 64-bit timestamp */ - unsigned short data[20] ____cacheline_aligned; + unsigned short data[20] __aligned(IIO_DMA_MINALIGN); __be16 d16[2]; }; diff --git a/drivers/iio/adc/ad7606_par.c b/drivers/iio/adc/ad7606_par.c index 8888e56b5e90..b912b4df9b56 100644 --- a/drivers/iio/adc/ad7606_par.c +++ b/drivers/iio/adc/ad7606_par.c @@ -5,6 +5,7 @@ * Copyright 2011 Analog Devices Inc. */ +#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/types.h> diff --git a/drivers/iio/adc/ad7766.c b/drivers/iio/adc/ad7766.c index 51ee9482e0df..3079a0872947 100644 --- a/drivers/iio/adc/ad7766.c +++ b/drivers/iio/adc/ad7766.c @@ -45,13 +45,12 @@ struct ad7766 { struct spi_message msg; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. * Make the buffer large enough for one 24 bit sample and one 64 bit * aligned 64 bit timestamp. */ - unsigned char data[ALIGN(3, sizeof(s64)) + sizeof(s64)] - ____cacheline_aligned; + unsigned char data[ALIGN(3, sizeof(s64)) + sizeof(s64)] __aligned(IIO_DMA_MINALIGN); }; /* diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index aa42ba759fa1..652db768ef37 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -163,7 +163,7 @@ struct ad7768_state { struct gpio_desc *gpio_sync_in; const char *labels[ARRAY_SIZE(ad7768_channels)]; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ union { @@ -173,7 +173,7 @@ struct ad7768_state { } scan; __be32 d32; u8 d8[2]; - } data ____cacheline_aligned; + } data __aligned(IIO_DMA_MINALIGN); }; static int ad7768_spi_reg_read(struct ad7768_state *st, unsigned int addr, @@ -620,7 +620,7 @@ static int ad7768_probe(struct spi_device *spi) indio_dev->num_channels = ARRAY_SIZE(ad7768_channels); indio_dev->name = spi_get_device_id(spi)->name; indio_dev->info = &ad7768_info; - indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_TRIGGERED; + indio_dev->modes = INDIO_DIRECT_MODE; ret = ad7768_setup(st); if (ret < 0) { diff --git a/drivers/iio/adc/ad7887.c b/drivers/iio/adc/ad7887.c index f64999714a4d..965bdc8aa696 100644 --- a/drivers/iio/adc/ad7887.c +++ b/drivers/iio/adc/ad7887.c @@ -66,13 +66,12 @@ struct ad7887_state { unsigned char tx_cmd_buf[4]; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. * Buffer needs to be large enough to hold two 16 bit samples and a * 64 bit aligned 64 bit timestamp. */ - unsigned char data[ALIGN(4, sizeof(s64)) + sizeof(s64)] - ____cacheline_aligned; + unsigned char data[ALIGN(4, sizeof(s64)) + sizeof(s64)] __aligned(IIO_DMA_MINALIGN); }; enum ad7887_supported_device_ids { diff --git a/drivers/iio/adc/ad7923.c b/drivers/iio/adc/ad7923.c index 069b561ee768..edad1f30121d 100644 --- a/drivers/iio/adc/ad7923.c +++ b/drivers/iio/adc/ad7923.c @@ -57,12 +57,12 @@ struct ad7923_state { unsigned int settings; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. * Ensure rx_buf can be directly used in iio_push_to_buffers_with_timetamp * Length = 8 channels + 4 extra for 8 byte timestamp */ - __be16 rx_buf[12] ____cacheline_aligned; + __be16 rx_buf[12] __aligned(IIO_DMA_MINALIGN); __be16 tx_buf[4]; }; diff --git a/drivers/iio/adc/ad7949.c b/drivers/iio/adc/ad7949.c index 44bb5fde83de..ed4c1656ca75 100644 --- a/drivers/iio/adc/ad7949.c +++ b/drivers/iio/adc/ad7949.c @@ -86,7 +86,7 @@ struct ad7949_adc_chip { u8 resolution; u16 cfg; unsigned int current_channel; - u16 buffer ____cacheline_aligned; + u16 buffer __aligned(IIO_DMA_MINALIGN); __be16 buf8b; }; diff --git a/drivers/iio/adc/ad9467.c b/drivers/iio/adc/ad9467.c index dbfc8517cb8a..5a5f33f7bc8f 100644 --- a/drivers/iio/adc/ad9467.c +++ b/drivers/iio/adc/ad9467.c @@ -474,3 +474,4 @@ module_spi_driver(ad9467_driver); MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); MODULE_DESCRIPTION("Analog Devices AD9467 ADC driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(IIO_ADI_AXI); diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c index a9e655e69eaa..e8a8ea4140f1 100644 --- a/drivers/iio/adc/adi-axi-adc.c +++ b/drivers/iio/adc/adi-axi-adc.c @@ -84,9 +84,10 @@ void *adi_axi_adc_conv_priv(struct adi_axi_adc_conv *conv) { struct adi_axi_adc_client *cl = conv_to_client(conv); - return (char *)cl + ALIGN(sizeof(struct adi_axi_adc_client), IIO_ALIGN); + return (char *)cl + ALIGN(sizeof(struct adi_axi_adc_client), + IIO_DMA_MINALIGN); } -EXPORT_SYMBOL_GPL(adi_axi_adc_conv_priv); +EXPORT_SYMBOL_NS_GPL(adi_axi_adc_conv_priv, IIO_ADI_AXI); static void adi_axi_adc_write(struct adi_axi_adc_state *st, unsigned int reg, @@ -169,9 +170,9 @@ static struct adi_axi_adc_conv *adi_axi_adc_conv_register(struct device *dev, struct adi_axi_adc_client *cl; size_t alloc_size; - alloc_size = ALIGN(sizeof(struct adi_axi_adc_client), IIO_ALIGN); + alloc_size = ALIGN(sizeof(struct adi_axi_adc_client), IIO_DMA_MINALIGN); if (sizeof_priv) - alloc_size += ALIGN(sizeof_priv, IIO_ALIGN); + alloc_size += ALIGN(sizeof_priv, IIO_DMA_MINALIGN); cl = kzalloc(alloc_size, GFP_KERNEL); if (!cl) @@ -224,7 +225,7 @@ struct adi_axi_adc_conv *devm_adi_axi_adc_conv_register(struct device *dev, return conv; } -EXPORT_SYMBOL_GPL(devm_adi_axi_adc_conv_register); +EXPORT_SYMBOL_NS_GPL(devm_adi_axi_adc_conv_register, IIO_ADI_AXI); static ssize_t in_voltage_scale_available_show(struct device *dev, struct device_attribute *attr, diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index b764823ce57e..fe3131c9593c 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -1752,7 +1752,7 @@ static int at91_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val) int ret; if (val > AT91_HWFIFO_MAX_SIZE) - return -EINVAL; + val = AT91_HWFIFO_MAX_SIZE; if (!st->selected_trig->hw_trig) { dev_dbg(&indio_dev->dev, "we need hw trigger for DMA\n"); diff --git a/drivers/iio/adc/berlin2-adc.c b/drivers/iio/adc/berlin2-adc.c index 03987d7e6b3d..3d2e8b4db61a 100644 --- a/drivers/iio/adc/berlin2-adc.c +++ b/drivers/iio/adc/berlin2-adc.c @@ -15,7 +15,9 @@ #include <linux/iio/machine.h> #include <linux/interrupt.h> #include <linux/kernel.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/mfd/syscon.h> diff --git a/drivers/iio/adc/hi8435.c b/drivers/iio/adc/hi8435.c index 8eb0140df133..771fa12bdc02 100644 --- a/drivers/iio/adc/hi8435.c +++ b/drivers/iio/adc/hi8435.c @@ -49,7 +49,7 @@ struct hi8435_priv { unsigned threshold_lo[2]; /* GND-Open and Supply-Open thresholds */ unsigned threshold_hi[2]; /* GND-Open and Supply-Open thresholds */ - u8 reg_buffer[3] ____cacheline_aligned; + u8 reg_buffer[3] __aligned(IIO_DMA_MINALIGN); }; static int hi8435_readb(struct hi8435_priv *priv, u8 reg, u8 *val) diff --git a/drivers/iio/adc/imx7d_adc.c b/drivers/iio/adc/imx7d_adc.c index 12f5b8e34c84..119217af2bde 100644 --- a/drivers/iio/adc/imx7d_adc.c +++ b/drivers/iio/adc/imx7d_adc.c @@ -11,6 +11,7 @@ #include <linux/interrupt.h> #include <linux/io.h> #include <linux/kernel.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/regulator/consumer.h> diff --git a/drivers/iio/adc/imx8qxp-adc.c b/drivers/iio/adc/imx8qxp-adc.c index 901dd8e1b32f..e8c9a69e10eb 100644 --- a/drivers/iio/adc/imx8qxp-adc.c +++ b/drivers/iio/adc/imx8qxp-adc.c @@ -19,6 +19,7 @@ #include <linux/interrupt.h> #include <linux/io.h> #include <linux/kernel.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> diff --git a/drivers/iio/adc/ina2xx-adc.c b/drivers/iio/adc/ina2xx-adc.c index abad16803849..240e6c420701 100644 --- a/drivers/iio/adc/ina2xx-adc.c +++ b/drivers/iio/adc/ina2xx-adc.c @@ -1038,12 +1038,18 @@ static int ina2xx_remove(struct i2c_client *client) { struct iio_dev *indio_dev = i2c_get_clientdata(client); struct ina2xx_chip_info *chip = iio_priv(indio_dev); + int ret; iio_device_unregister(indio_dev); /* Powerdown */ - return regmap_update_bits(chip->regmap, INA2XX_CONFIG, - INA2XX_MODE_MASK, 0); + ret = regmap_update_bits(chip->regmap, INA2XX_CONFIG, + INA2XX_MODE_MASK, 0); + if (ret) + dev_warn(&client->dev, "Failed to power down device (%pe)\n", + ERR_PTR(ret)); + + return 0; } static const struct i2c_device_id ina2xx_id[] = { diff --git a/drivers/iio/adc/ingenic-adc.c b/drivers/iio/adc/ingenic-adc.c index 2b3912c6ca6b..bf5c03c34f84 100644 --- a/drivers/iio/adc/ingenic-adc.c +++ b/drivers/iio/adc/ingenic-adc.c @@ -17,7 +17,9 @@ #include <linux/module.h> #include <linux/mod_devicetable.h> #include <linux/mutex.h> +#include <linux/of.h> #include <linux/platform_device.h> +#include <linux/property.h> #define JZ_ADC_REG_ENABLE 0x00 #define JZ_ADC_REG_CFG 0x04 diff --git a/drivers/iio/adc/intel_mrfld_adc.c b/drivers/iio/adc/intel_mrfld_adc.c index 616de0c3a049..7263ad76124d 100644 --- a/drivers/iio/adc/intel_mrfld_adc.c +++ b/drivers/iio/adc/intel_mrfld_adc.c @@ -15,6 +15,7 @@ #include <linux/interrupt.h> #include <linux/mfd/intel_soc_pmic.h> #include <linux/mfd/intel_soc_pmic_mrfld.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/mutex.h> #include <linux/platform_device.h> diff --git a/drivers/iio/adc/lpc18xx_adc.c b/drivers/iio/adc/lpc18xx_adc.c index ae9c9384f23e..42e6cd6fa6f7 100644 --- a/drivers/iio/adc/lpc18xx_adc.c +++ b/drivers/iio/adc/lpc18xx_adc.c @@ -17,10 +17,9 @@ #include <linux/iio/driver.h> #include <linux/io.h> #include <linux/iopoll.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/mutex.h> -#include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/regulator/consumer.h> diff --git a/drivers/iio/adc/ltc2496.c b/drivers/iio/adc/ltc2496.c index 5a55f79f2574..dfb3bb5997e5 100644 --- a/drivers/iio/adc/ltc2496.c +++ b/drivers/iio/adc/ltc2496.c @@ -24,10 +24,10 @@ struct ltc2496_driverdata { struct spi_device *spi; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ - unsigned char rxbuf[3] ____cacheline_aligned; + unsigned char rxbuf[3] __aligned(IIO_DMA_MINALIGN); unsigned char txbuf[3]; }; diff --git a/drivers/iio/adc/ltc2497.c b/drivers/iio/adc/ltc2497.c index 1adddf5a88a9..f7c786f37ceb 100644 --- a/drivers/iio/adc/ltc2497.c +++ b/drivers/iio/adc/ltc2497.c @@ -20,10 +20,10 @@ struct ltc2497_driverdata { struct ltc2497core_driverdata common_ddata; struct i2c_client *client; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ - __be32 buf ____cacheline_aligned; + __be32 buf __aligned(IIO_DMA_MINALIGN); }; static int ltc2497_result_and_measure(struct ltc2497core_driverdata *ddata, diff --git a/drivers/iio/adc/max1027.c b/drivers/iio/adc/max1027.c index 4daf1d576c4e..b725d012625c 100644 --- a/drivers/iio/adc/max1027.c +++ b/drivers/iio/adc/max1027.c @@ -272,7 +272,7 @@ struct max1027_state { struct mutex lock; struct completion complete; - u8 reg ____cacheline_aligned; + u8 reg __aligned(IIO_DMA_MINALIGN); }; static int max1027_wait_eoc(struct iio_dev *indio_dev) diff --git a/drivers/iio/adc/max11100.c b/drivers/iio/adc/max11100.c index eb1ce6a0315c..49e38dca8fe2 100644 --- a/drivers/iio/adc/max11100.c +++ b/drivers/iio/adc/max11100.c @@ -33,10 +33,10 @@ struct max11100_state { struct spi_device *spi; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ - u8 buffer[3] ____cacheline_aligned; + u8 buffer[3] __aligned(IIO_DMA_MINALIGN); }; static const struct iio_chan_spec max11100_channels[] = { diff --git a/drivers/iio/adc/max1118.c b/drivers/iio/adc/max1118.c index a41bc570be21..75ab57d9aef7 100644 --- a/drivers/iio/adc/max1118.c +++ b/drivers/iio/adc/max1118.c @@ -42,7 +42,7 @@ struct max1118 { s64 ts __aligned(8); } scan; - u8 data ____cacheline_aligned; + u8 data __aligned(IIO_DMA_MINALIGN); }; #define MAX1118_CHANNEL(ch) \ diff --git a/drivers/iio/adc/max1241.c b/drivers/iio/adc/max1241.c index a5afd84af58b..a815ad1f6913 100644 --- a/drivers/iio/adc/max1241.c +++ b/drivers/iio/adc/max1241.c @@ -26,7 +26,7 @@ struct max1241 { struct regulator *vref; struct gpio_desc *shutdown; - __be16 data ____cacheline_aligned; + __be16 data __aligned(IIO_DMA_MINALIGN); }; static const struct iio_chan_spec max1241_channels[] = { diff --git a/drivers/iio/adc/mcp320x.c b/drivers/iio/adc/mcp320x.c index b4c69acb33e3..f3b81798b3c9 100644 --- a/drivers/iio/adc/mcp320x.c +++ b/drivers/iio/adc/mcp320x.c @@ -92,7 +92,7 @@ struct mcp320x { struct mutex lock; const struct mcp320x_chip_info *chip_info; - u8 tx_buf ____cacheline_aligned; + u8 tx_buf __aligned(IIO_DMA_MINALIGN); u8 rx_buf[4]; }; diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c index 62cc6fb0ef85..c18be3c519af 100644 --- a/drivers/iio/adc/meson_saradc.c +++ b/drivers/iio/adc/meson_saradc.c @@ -322,22 +322,17 @@ static int meson_sar_adc_calib_val(struct iio_dev *indio_dev, int val) static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev) { struct meson_sar_adc_priv *priv = iio_priv(indio_dev); - int regval, timeout = 10000; + int val; /* * NOTE: we need a small delay before reading the status, otherwise * the sample engine may not have started internally (which would * seem to us that sampling is already finished). */ - do { - udelay(1); - regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); - } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--); - - if (timeout < 0) - return -ETIMEDOUT; - - return 0; + udelay(1); + return regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_REG0, val, + !FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, val), + 1, 10000); } static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev, @@ -345,6 +340,7 @@ static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev, int *val) { struct meson_sar_adc_priv *priv = iio_priv(indio_dev); + struct device *dev = indio_dev->dev.parent; int regval, fifo_chan, fifo_val, count; if (!wait_for_completion_timeout(&priv->done, @@ -353,16 +349,14 @@ static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev, count = meson_sar_adc_get_fifo_count(indio_dev); if (count != 1) { - dev_err(&indio_dev->dev, - "ADC FIFO has %d element(s) instead of one\n", count); + dev_err(dev, "ADC FIFO has %d element(s) instead of one\n", count); return -EINVAL; } regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val); fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval); if (fifo_chan != chan->address) { - dev_err(&indio_dev->dev, - "ADC FIFO entry belongs to channel %d instead of %lu\n", + dev_err(dev, "ADC FIFO entry belongs to channel %d instead of %lu\n", fifo_chan, chan->address); return -EINVAL; } @@ -490,7 +484,7 @@ static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev) static int meson_sar_adc_lock(struct iio_dev *indio_dev) { struct meson_sar_adc_priv *priv = iio_priv(indio_dev); - int val, timeout = 10000; + int val, ret; mutex_lock(&indio_dev->mlock); @@ -500,18 +494,18 @@ static int meson_sar_adc_lock(struct iio_dev *indio_dev) MESON_SAR_ADC_DELAY_KERNEL_BUSY, MESON_SAR_ADC_DELAY_KERNEL_BUSY); + udelay(1); + /* * wait until BL30 releases it's lock (so we can use the SAR * ADC) */ - do { - udelay(1); - regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val); - } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--); - - if (timeout < 0) { + ret = regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_DELAY, val, + !(val & MESON_SAR_ADC_DELAY_BL30_BUSY), + 1, 10000); + if (ret) { mutex_unlock(&indio_dev->mlock); - return -ETIMEDOUT; + return ret; } } @@ -550,6 +544,7 @@ static int meson_sar_adc_get_sample(struct iio_dev *indio_dev, int *val) { struct meson_sar_adc_priv *priv = iio_priv(indio_dev); + struct device *dev = indio_dev->dev.parent; int ret; if (chan->type == IIO_TEMP && !priv->temperature_sensor_calibrated) @@ -573,8 +568,7 @@ static int meson_sar_adc_get_sample(struct iio_dev *indio_dev, meson_sar_adc_unlock(indio_dev); if (ret) { - dev_warn(indio_dev->dev.parent, - "failed to read sample for channel %lu: %d\n", + dev_warn(dev, "failed to read sample for channel %lu: %d\n", chan->address, ret); return ret; } @@ -587,6 +581,7 @@ static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev, int *val, int *val2, long mask) { struct meson_sar_adc_priv *priv = iio_priv(indio_dev); + struct device *dev = indio_dev->dev.parent; int ret; switch (mask) { @@ -603,9 +598,7 @@ static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev, if (chan->type == IIO_VOLTAGE) { ret = regulator_get_voltage(priv->vref); if (ret < 0) { - dev_err(indio_dev->dev.parent, - "failed to get vref voltage: %d\n", - ret); + dev_err(dev, "failed to get vref voltage: %d\n", ret); return ret; } @@ -650,11 +643,11 @@ static int meson_sar_adc_clk_init(struct iio_dev *indio_dev, void __iomem *base) { struct meson_sar_adc_priv *priv = iio_priv(indio_dev); + struct device *dev = indio_dev->dev.parent; struct clk_init_data init; const char *clk_parents[1]; - init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div", - dev_name(indio_dev->dev.parent)); + init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#adc_div", dev_name(dev)); if (!init.name) return -ENOMEM; @@ -670,13 +663,11 @@ static int meson_sar_adc_clk_init(struct iio_dev *indio_dev, priv->clk_div.hw.init = &init; priv->clk_div.flags = 0; - priv->adc_div_clk = devm_clk_register(&indio_dev->dev, - &priv->clk_div.hw); + priv->adc_div_clk = devm_clk_register(dev, &priv->clk_div.hw); if (WARN_ON(IS_ERR(priv->adc_div_clk))) return PTR_ERR(priv->adc_div_clk); - init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en", - dev_name(indio_dev->dev.parent)); + init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#adc_en", dev_name(dev)); if (!init.name) return -ENOMEM; @@ -690,7 +681,7 @@ static int meson_sar_adc_clk_init(struct iio_dev *indio_dev, priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN); priv->clk_gate.hw.init = &init; - priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw); + priv->adc_clk = devm_clk_register(dev, &priv->clk_gate.hw); if (WARN_ON(IS_ERR(priv->adc_clk))) return PTR_ERR(priv->adc_clk); @@ -701,12 +692,12 @@ static int meson_sar_adc_temp_sensor_init(struct iio_dev *indio_dev) { struct meson_sar_adc_priv *priv = iio_priv(indio_dev); u8 *buf, trimming_bits, trimming_mask, upper_adc_val; + struct device *dev = indio_dev->dev.parent; struct nvmem_cell *temperature_calib; size_t read_len; int ret; - temperature_calib = devm_nvmem_cell_get(indio_dev->dev.parent, - "temperature_calib"); + temperature_calib = devm_nvmem_cell_get(dev, "temperature_calib"); if (IS_ERR(temperature_calib)) { ret = PTR_ERR(temperature_calib); @@ -717,30 +708,21 @@ static int meson_sar_adc_temp_sensor_init(struct iio_dev *indio_dev) if (ret == -ENODEV) return 0; - return dev_err_probe(indio_dev->dev.parent, ret, - "failed to get temperature_calib cell\n"); + return dev_err_probe(dev, ret, "failed to get temperature_calib cell\n"); } - priv->tsc_regmap = - syscon_regmap_lookup_by_phandle(indio_dev->dev.parent->of_node, - "amlogic,hhi-sysctrl"); - if (IS_ERR(priv->tsc_regmap)) { - dev_err(indio_dev->dev.parent, - "failed to get amlogic,hhi-sysctrl regmap\n"); - return PTR_ERR(priv->tsc_regmap); - } + priv->tsc_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "amlogic,hhi-sysctrl"); + if (IS_ERR(priv->tsc_regmap)) + return dev_err_probe(dev, PTR_ERR(priv->tsc_regmap), + "failed to get amlogic,hhi-sysctrl regmap\n"); read_len = MESON_SAR_ADC_EFUSE_BYTES; buf = nvmem_cell_read(temperature_calib, &read_len); - if (IS_ERR(buf)) { - dev_err(indio_dev->dev.parent, - "failed to read temperature_calib cell\n"); - return PTR_ERR(buf); - } else if (read_len != MESON_SAR_ADC_EFUSE_BYTES) { + if (IS_ERR(buf)) + return dev_err_probe(dev, PTR_ERR(buf), "failed to read temperature_calib cell\n"); + if (read_len != MESON_SAR_ADC_EFUSE_BYTES) { kfree(buf); - dev_err(indio_dev->dev.parent, - "invalid read size of temperature_calib cell\n"); - return -EINVAL; + return dev_err_probe(dev, -EINVAL, "invalid read size of temperature_calib cell\n"); } trimming_bits = priv->param->temperature_trimming_bits; @@ -765,6 +747,7 @@ static int meson_sar_adc_temp_sensor_init(struct iio_dev *indio_dev) static int meson_sar_adc_init(struct iio_dev *indio_dev) { struct meson_sar_adc_priv *priv = iio_priv(indio_dev); + struct device *dev = indio_dev->dev.parent; int regval, i, ret; /* @@ -888,18 +871,12 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev) } ret = clk_set_parent(priv->adc_sel_clk, priv->clkin); - if (ret) { - dev_err(indio_dev->dev.parent, - "failed to set adc parent to clkin\n"); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "failed to set adc parent to clkin\n"); ret = clk_set_rate(priv->adc_clk, priv->param->clock_rate); - if (ret) { - dev_err(indio_dev->dev.parent, - "failed to set adc clock rate\n"); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "failed to set adc clock rate\n"); return 0; } @@ -922,6 +899,7 @@ static void meson_sar_adc_set_bandgap(struct iio_dev *indio_dev, bool on_off) static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev) { struct meson_sar_adc_priv *priv = iio_priv(indio_dev); + struct device *dev = indio_dev->dev.parent; int ret; u32 regval; @@ -931,14 +909,13 @@ static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev) ret = regulator_enable(priv->vref); if (ret < 0) { - dev_err(indio_dev->dev.parent, - "failed to enable vref regulator\n"); + dev_err(dev, "failed to enable vref regulator\n"); goto err_vref; } ret = clk_prepare_enable(priv->core_clk); if (ret) { - dev_err(indio_dev->dev.parent, "failed to enable core clk\n"); + dev_err(dev, "failed to enable core clk\n"); goto err_core_clk; } @@ -956,7 +933,7 @@ static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev) ret = clk_prepare_enable(priv->adc_clk); if (ret) { - dev_err(indio_dev->dev.parent, "failed to enable adc clk\n"); + dev_err(dev, "failed to enable adc clk\n"); goto err_adc_clk; } @@ -1186,24 +1163,21 @@ static int meson_sar_adc_probe(struct platform_device *pdev) { const struct meson_sar_adc_data *match_data; struct meson_sar_adc_priv *priv; + struct device *dev = &pdev->dev; struct iio_dev *indio_dev; void __iomem *base; int irq, ret; - indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv)); - if (!indio_dev) { - dev_err(&pdev->dev, "failed allocating iio device\n"); - return -ENOMEM; - } + indio_dev = devm_iio_device_alloc(dev, sizeof(*priv)); + if (!indio_dev) + return dev_err_probe(dev, -ENOMEM, "failed allocating iio device\n"); priv = iio_priv(indio_dev); init_completion(&priv->done); - match_data = of_device_get_match_data(&pdev->dev); - if (!match_data) { - dev_err(&pdev->dev, "failed to get match data\n"); - return -ENODEV; - } + match_data = of_device_get_match_data(dev); + if (!match_data) + return dev_err_probe(dev, -ENODEV, "failed to get match data\n"); priv->param = match_data->param; @@ -1215,47 +1189,33 @@ static int meson_sar_adc_probe(struct platform_device *pdev) if (IS_ERR(base)) return PTR_ERR(base); - priv->regmap = devm_regmap_init_mmio(&pdev->dev, base, - priv->param->regmap_config); + priv->regmap = devm_regmap_init_mmio(dev, base, priv->param->regmap_config); if (IS_ERR(priv->regmap)) return PTR_ERR(priv->regmap); - irq = irq_of_parse_and_map(pdev->dev.of_node, 0); + irq = irq_of_parse_and_map(dev->of_node, 0); if (!irq) return -EINVAL; - ret = devm_request_irq(&pdev->dev, irq, meson_sar_adc_irq, IRQF_SHARED, - dev_name(&pdev->dev), indio_dev); + ret = devm_request_irq(dev, irq, meson_sar_adc_irq, IRQF_SHARED, dev_name(dev), indio_dev); if (ret) return ret; - priv->clkin = devm_clk_get(&pdev->dev, "clkin"); + priv->clkin = devm_clk_get(dev, "clkin"); if (IS_ERR(priv->clkin)) - return dev_err_probe(&pdev->dev, PTR_ERR(priv->clkin), - "failed to get clkin\n"); + return dev_err_probe(dev, PTR_ERR(priv->clkin), "failed to get clkin\n"); - priv->core_clk = devm_clk_get(&pdev->dev, "core"); + priv->core_clk = devm_clk_get(dev, "core"); if (IS_ERR(priv->core_clk)) - return dev_err_probe(&pdev->dev, PTR_ERR(priv->core_clk), - "failed to get core clk\n"); + return dev_err_probe(dev, PTR_ERR(priv->core_clk), "failed to get core clk\n"); - priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk"); - if (IS_ERR(priv->adc_clk)) { - if (PTR_ERR(priv->adc_clk) == -ENOENT) - priv->adc_clk = NULL; - else - return dev_err_probe(&pdev->dev, PTR_ERR(priv->adc_clk), - "failed to get adc clk\n"); - } + priv->adc_clk = devm_clk_get_optional(dev, "adc_clk"); + if (IS_ERR(priv->adc_clk)) + return dev_err_probe(dev, PTR_ERR(priv->adc_clk), "failed to get adc clk\n"); - priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel"); - if (IS_ERR(priv->adc_sel_clk)) { - if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) - priv->adc_sel_clk = NULL; - else - return dev_err_probe(&pdev->dev, PTR_ERR(priv->adc_sel_clk), - "failed to get adc_sel clk\n"); - } + priv->adc_sel_clk = devm_clk_get_optional(dev, "adc_sel"); + if (IS_ERR(priv->adc_sel_clk)) + return dev_err_probe(dev, PTR_ERR(priv->adc_sel_clk), "failed to get adc_sel clk\n"); /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */ if (!priv->adc_clk) { @@ -1264,10 +1224,9 @@ static int meson_sar_adc_probe(struct platform_device *pdev) return ret; } - priv->vref = devm_regulator_get(&pdev->dev, "vref"); + priv->vref = devm_regulator_get(dev, "vref"); if (IS_ERR(priv->vref)) - return dev_err_probe(&pdev->dev, PTR_ERR(priv->vref), - "failed to get vref regulator\n"); + return dev_err_probe(dev, PTR_ERR(priv->vref), "failed to get vref regulator\n"); priv->calibscale = MILLION; @@ -1297,7 +1256,7 @@ static int meson_sar_adc_probe(struct platform_device *pdev) ret = meson_sar_adc_calib(indio_dev); if (ret) - dev_warn(&pdev->dev, "calibration failed\n"); + dev_warn(dev, "calibration failed\n"); platform_set_drvdata(pdev, indio_dev); diff --git a/drivers/iio/adc/mp2629_adc.c b/drivers/iio/adc/mp2629_adc.c index aca084f1e78a..30a31f185d08 100644 --- a/drivers/iio/adc/mp2629_adc.c +++ b/drivers/iio/adc/mp2629_adc.c @@ -11,6 +11,7 @@ #include <linux/iio/iio.h> #include <linux/iio/machine.h> #include <linux/mfd/mp2629.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/mutex.h> #include <linux/platform_device.h> diff --git a/drivers/iio/adc/mt6360-adc.c b/drivers/iio/adc/mt6360-adc.c index 07c0e6768391..35260d9e4e47 100644 --- a/drivers/iio/adc/mt6360-adc.c +++ b/drivers/iio/adc/mt6360-adc.c @@ -5,6 +5,7 @@ #include <linux/irq.h> #include <linux/kernel.h> #include <linux/ktime.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/mutex.h> #include <linux/platform_device.h> diff --git a/drivers/iio/adc/nau7802.c b/drivers/iio/adc/nau7802.c index 976c235f3079..c1261ecd400c 100644 --- a/drivers/iio/adc/nau7802.c +++ b/drivers/iio/adc/nau7802.c @@ -8,10 +8,11 @@ #include <linux/delay.h> #include <linux/i2c.h> #include <linux/interrupt.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> +#include <linux/property.h> #include <linux/wait.h> #include <linux/log2.h> -#include <linux/of.h> #include <linux/iio/iio.h> #include <linux/iio/sysfs.h> @@ -407,21 +408,14 @@ static const struct iio_info nau7802_info = { .attrs = &nau7802_attribute_group, }; -static int nau7802_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int nau7802_probe(struct i2c_client *client) { struct iio_dev *indio_dev; struct nau7802_state *st; - struct device_node *np = client->dev.of_node; int i, ret; u8 data; u32 tmp = 0; - if (!client->dev.of_node) { - dev_err(&client->dev, "No device tree node available.\n"); - return -EINVAL; - } - indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st)); if (indio_dev == NULL) return -ENOMEM; @@ -457,7 +451,7 @@ static int nau7802_probe(struct i2c_client *client, if (!(ret & NAU7802_PUCTRL_PUR_BIT)) return ret; - of_property_read_u32(np, "nuvoton,vldo", &tmp); + device_property_read_u32(&client->dev, "nuvoton,vldo", &tmp); st->vref_mv = tmp; data = NAU7802_PUCTRL_PUD_BIT | NAU7802_PUCTRL_PUA_BIT | @@ -550,7 +544,7 @@ static const struct of_device_id nau7802_dt_ids[] = { MODULE_DEVICE_TABLE(of, nau7802_dt_ids); static struct i2c_driver nau7802_driver = { - .probe = nau7802_probe, + .probe_new = nau7802_probe, .id_table = nau7802_i2c_id, .driver = { .name = "nau7802", diff --git a/drivers/iio/adc/npcm_adc.c b/drivers/iio/adc/npcm_adc.c index f7bc0bb7f112..a242e7993476 100644 --- a/drivers/iio/adc/npcm_adc.c +++ b/drivers/iio/adc/npcm_adc.c @@ -8,6 +8,7 @@ #include <linux/iio/iio.h> #include <linux/interrupt.h> #include <linux/kernel.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/regmap.h> diff --git a/drivers/iio/adc/qcom-spmi-rradc.c b/drivers/iio/adc/qcom-spmi-rradc.c new file mode 100644 index 000000000000..56a713766954 --- /dev/null +++ b/drivers/iio/adc/qcom-spmi-rradc.c @@ -0,0 +1,1022 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Linaro Limited. + * Author: Caleb Connolly <caleb.connolly@linaro.org> + * + * This driver is for the Round Robin ADC found in the pmi8998 and pm660 PMICs. + */ + +#include <linux/bitfield.h> +#include <linux/delay.h> +#include <linux/kernel.h> +#include <linux/math64.h> +#include <linux/module.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> +#include <linux/property.h> +#include <linux/regmap.h> +#include <linux/spmi.h> +#include <linux/types.h> +#include <linux/units.h> + +#include <asm/unaligned.h> + +#include <linux/iio/iio.h> +#include <linux/iio/types.h> + +#include <soc/qcom/qcom-spmi-pmic.h> + +#define DRIVER_NAME "qcom-spmi-rradc" + +#define RR_ADC_EN_CTL 0x46 +#define RR_ADC_SKIN_TEMP_LSB 0x50 +#define RR_ADC_SKIN_TEMP_MSB 0x51 +#define RR_ADC_CTL 0x52 +#define RR_ADC_CTL_CONTINUOUS_SEL BIT(3) +#define RR_ADC_LOG 0x53 +#define RR_ADC_LOG_CLR_CTRL BIT(0) + +#define RR_ADC_FAKE_BATT_LOW_LSB 0x58 +#define RR_ADC_FAKE_BATT_LOW_MSB 0x59 +#define RR_ADC_FAKE_BATT_HIGH_LSB 0x5A +#define RR_ADC_FAKE_BATT_HIGH_MSB 0x5B + +#define RR_ADC_BATT_ID_CTRL 0x60 +#define RR_ADC_BATT_ID_CTRL_CHANNEL_CONV BIT(0) +#define RR_ADC_BATT_ID_TRIGGER 0x61 +#define RR_ADC_BATT_ID_STS 0x62 +#define RR_ADC_BATT_ID_CFG 0x63 +#define BATT_ID_SETTLE_MASK GENMASK(7, 5) +#define RR_ADC_BATT_ID_5_LSB 0x66 +#define RR_ADC_BATT_ID_5_MSB 0x67 +#define RR_ADC_BATT_ID_15_LSB 0x68 +#define RR_ADC_BATT_ID_15_MSB 0x69 +#define RR_ADC_BATT_ID_150_LSB 0x6A +#define RR_ADC_BATT_ID_150_MSB 0x6B + +#define RR_ADC_BATT_THERM_CTRL 0x70 +#define RR_ADC_BATT_THERM_TRIGGER 0x71 +#define RR_ADC_BATT_THERM_STS 0x72 +#define RR_ADC_BATT_THERM_CFG 0x73 +#define RR_ADC_BATT_THERM_LSB 0x74 +#define RR_ADC_BATT_THERM_MSB 0x75 +#define RR_ADC_BATT_THERM_FREQ 0x76 + +#define RR_ADC_AUX_THERM_CTRL 0x80 +#define RR_ADC_AUX_THERM_TRIGGER 0x81 +#define RR_ADC_AUX_THERM_STS 0x82 +#define RR_ADC_AUX_THERM_CFG 0x83 +#define RR_ADC_AUX_THERM_LSB 0x84 +#define RR_ADC_AUX_THERM_MSB 0x85 + +#define RR_ADC_SKIN_HOT 0x86 +#define RR_ADC_SKIN_TOO_HOT 0x87 + +#define RR_ADC_AUX_THERM_C1 0x88 +#define RR_ADC_AUX_THERM_C2 0x89 +#define RR_ADC_AUX_THERM_C3 0x8A +#define RR_ADC_AUX_THERM_HALF_RANGE 0x8B + +#define RR_ADC_USB_IN_V_CTRL 0x90 +#define RR_ADC_USB_IN_V_TRIGGER 0x91 +#define RR_ADC_USB_IN_V_STS 0x92 +#define RR_ADC_USB_IN_V_LSB 0x94 +#define RR_ADC_USB_IN_V_MSB 0x95 +#define RR_ADC_USB_IN_I_CTRL 0x98 +#define RR_ADC_USB_IN_I_TRIGGER 0x99 +#define RR_ADC_USB_IN_I_STS 0x9A +#define RR_ADC_USB_IN_I_LSB 0x9C +#define RR_ADC_USB_IN_I_MSB 0x9D + +#define RR_ADC_DC_IN_V_CTRL 0xA0 +#define RR_ADC_DC_IN_V_TRIGGER 0xA1 +#define RR_ADC_DC_IN_V_STS 0xA2 +#define RR_ADC_DC_IN_V_LSB 0xA4 +#define RR_ADC_DC_IN_V_MSB 0xA5 +#define RR_ADC_DC_IN_I_CTRL 0xA8 +#define RR_ADC_DC_IN_I_TRIGGER 0xA9 +#define RR_ADC_DC_IN_I_STS 0xAA +#define RR_ADC_DC_IN_I_LSB 0xAC +#define RR_ADC_DC_IN_I_MSB 0xAD + +#define RR_ADC_PMI_DIE_TEMP_CTRL 0xB0 +#define RR_ADC_PMI_DIE_TEMP_TRIGGER 0xB1 +#define RR_ADC_PMI_DIE_TEMP_STS 0xB2 +#define RR_ADC_PMI_DIE_TEMP_CFG 0xB3 +#define RR_ADC_PMI_DIE_TEMP_LSB 0xB4 +#define RR_ADC_PMI_DIE_TEMP_MSB 0xB5 + +#define RR_ADC_CHARGER_TEMP_CTRL 0xB8 +#define RR_ADC_CHARGER_TEMP_TRIGGER 0xB9 +#define RR_ADC_CHARGER_TEMP_STS 0xBA +#define RR_ADC_CHARGER_TEMP_CFG 0xBB +#define RR_ADC_CHARGER_TEMP_LSB 0xBC +#define RR_ADC_CHARGER_TEMP_MSB 0xBD +#define RR_ADC_CHARGER_HOT 0xBE +#define RR_ADC_CHARGER_TOO_HOT 0xBF + +#define RR_ADC_GPIO_CTRL 0xC0 +#define RR_ADC_GPIO_TRIGGER 0xC1 +#define RR_ADC_GPIO_STS 0xC2 +#define RR_ADC_GPIO_LSB 0xC4 +#define RR_ADC_GPIO_MSB 0xC5 + +#define RR_ADC_ATEST_CTRL 0xC8 +#define RR_ADC_ATEST_TRIGGER 0xC9 +#define RR_ADC_ATEST_STS 0xCA +#define RR_ADC_ATEST_LSB 0xCC +#define RR_ADC_ATEST_MSB 0xCD +#define RR_ADC_SEC_ACCESS 0xD0 + +#define RR_ADC_PERPH_RESET_CTL2 0xD9 +#define RR_ADC_PERPH_RESET_CTL3 0xDA +#define RR_ADC_PERPH_RESET_CTL4 0xDB +#define RR_ADC_INT_TEST1 0xE0 +#define RR_ADC_INT_TEST_VAL 0xE1 + +#define RR_ADC_TM_TRIGGER_CTRLS 0xE2 +#define RR_ADC_TM_ADC_CTRLS 0xE3 +#define RR_ADC_TM_CNL_CTRL 0xE4 +#define RR_ADC_TM_BATT_ID_CTRL 0xE5 +#define RR_ADC_TM_THERM_CTRL 0xE6 +#define RR_ADC_TM_CONV_STS 0xE7 +#define RR_ADC_TM_ADC_READ_LSB 0xE8 +#define RR_ADC_TM_ADC_READ_MSB 0xE9 +#define RR_ADC_TM_ATEST_MUX_1 0xEA +#define RR_ADC_TM_ATEST_MUX_2 0xEB +#define RR_ADC_TM_REFERENCES 0xED +#define RR_ADC_TM_MISC_CTL 0xEE +#define RR_ADC_TM_RR_CTRL 0xEF + +#define RR_ADC_TRIGGER_EVERY_CYCLE BIT(7) +#define RR_ADC_TRIGGER_CTL BIT(0) + +#define RR_ADC_BATT_ID_RANGE 820 + +#define RR_ADC_BITS 10 +#define RR_ADC_CHAN_MSB (1 << RR_ADC_BITS) +#define RR_ADC_FS_VOLTAGE_MV 2500 + +/* BATT_THERM 0.25K/LSB */ +#define RR_ADC_BATT_THERM_LSB_K 4 + +#define RR_ADC_TEMP_FS_VOLTAGE_NUM 5000000 +#define RR_ADC_TEMP_FS_VOLTAGE_DEN 3 +#define RR_ADC_DIE_TEMP_OFFSET 601400 +#define RR_ADC_DIE_TEMP_SLOPE 2 +#define RR_ADC_DIE_TEMP_OFFSET_MILLI_DEGC 25000 + +#define RR_ADC_CHG_TEMP_GF_OFFSET_UV 1303168 +#define RR_ADC_CHG_TEMP_GF_SLOPE_UV_PER_C 3784 +#define RR_ADC_CHG_TEMP_SMIC_OFFSET_UV 1338433 +#define RR_ADC_CHG_TEMP_SMIC_SLOPE_UV_PER_C 3655 +#define RR_ADC_CHG_TEMP_660_GF_OFFSET_UV 1309001 +#define RR_ADC_CHG_TEMP_660_GF_SLOPE_UV_PER_C 3403 +#define RR_ADC_CHG_TEMP_660_SMIC_OFFSET_UV 1295898 +#define RR_ADC_CHG_TEMP_660_SMIC_SLOPE_UV_PER_C 3596 +#define RR_ADC_CHG_TEMP_660_MGNA_OFFSET_UV 1314779 +#define RR_ADC_CHG_TEMP_660_MGNA_SLOPE_UV_PER_C 3496 +#define RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC 25000 +#define RR_ADC_CHG_THRESHOLD_SCALE 4 + +#define RR_ADC_VOLT_INPUT_FACTOR 8 +#define RR_ADC_CURR_INPUT_FACTOR 2000 +#define RR_ADC_CURR_USBIN_INPUT_FACTOR_MIL 1886 +#define RR_ADC_CURR_USBIN_660_FACTOR_MIL 9 +#define RR_ADC_CURR_USBIN_660_UV_VAL 579500 + +#define RR_ADC_GPIO_FS_RANGE 5000 +#define RR_ADC_COHERENT_CHECK_RETRY 5 +#define RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN 16 + +#define RR_ADC_STS_CHANNEL_READING_MASK GENMASK(1, 0) +#define RR_ADC_STS_CHANNEL_STS BIT(1) + +#define RR_ADC_TP_REV_VERSION1 21 +#define RR_ADC_TP_REV_VERSION2 29 +#define RR_ADC_TP_REV_VERSION3 32 + +#define RRADC_BATT_ID_DELAY_MAX 8 + +enum rradc_channel_id { + RR_ADC_BATT_ID = 0, + RR_ADC_BATT_THERM, + RR_ADC_SKIN_TEMP, + RR_ADC_USBIN_I, + RR_ADC_USBIN_V, + RR_ADC_DCIN_I, + RR_ADC_DCIN_V, + RR_ADC_DIE_TEMP, + RR_ADC_CHG_TEMP, + RR_ADC_GPIO, + RR_ADC_CHAN_MAX +}; + +struct rradc_chip; + +/** + * struct rradc_channel - rradc channel data + * @label: channel label + * @lsb: Channel least significant byte + * @status: Channel status address + * @size: number of bytes to read + * @trigger_addr: Trigger address, trigger is only used on some channels + * @trigger_mask: Trigger mask + * @scale_fn: Post process callback for channels which can't be exposed + * as offset + scale. + */ +struct rradc_channel { + const char *label; + u8 lsb; + u8 status; + int size; + int trigger_addr; + int trigger_mask; + int (*scale_fn)(struct rradc_chip *chip, u16 adc_code, int *result); +}; + +struct rradc_chip { + struct device *dev; + const struct qcom_spmi_pmic *pmic; + /* + * Lock held while doing channel conversion + * involving multiple register read/writes + */ + struct mutex conversion_lock; + struct regmap *regmap; + u32 base; + int batt_id_delay; + u16 batt_id_data; +}; + +static const int batt_id_delays[] = { 0, 1, 4, 12, 20, 40, 60, 80 }; +static const struct rradc_channel rradc_chans[RR_ADC_CHAN_MAX]; +static const struct iio_chan_spec rradc_iio_chans[RR_ADC_CHAN_MAX]; + +static int rradc_read(struct rradc_chip *chip, u16 addr, __le16 *buf, int len) +{ + int ret, retry_cnt = 0; + __le16 data_check[RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN / 2]; + + if (len > RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN) { + dev_err(chip->dev, + "Can't read more than %d bytes, but asked to read %d bytes.\n", + RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN, len); + return -EINVAL; + } + + while (retry_cnt < RR_ADC_COHERENT_CHECK_RETRY) { + ret = regmap_bulk_read(chip->regmap, chip->base + addr, buf, + len); + if (ret < 0) { + dev_err(chip->dev, "rr_adc reg 0x%x failed :%d\n", addr, + ret); + return ret; + } + + ret = regmap_bulk_read(chip->regmap, chip->base + addr, + data_check, len); + if (ret < 0) { + dev_err(chip->dev, "rr_adc reg 0x%x failed :%d\n", addr, + ret); + return ret; + } + + if (memcmp(buf, data_check, len) != 0) { + retry_cnt++; + dev_dbg(chip->dev, + "coherent read error, retry_cnt:%d\n", + retry_cnt); + continue; + } + + break; + } + + if (retry_cnt == RR_ADC_COHERENT_CHECK_RETRY) + dev_err(chip->dev, "Retry exceeded for coherency check\n"); + + return ret; +} + +static int rradc_get_fab_coeff(struct rradc_chip *chip, int64_t *offset, + int64_t *slope) +{ + if (chip->pmic->subtype == PM660_SUBTYPE) { + switch (chip->pmic->fab_id) { + case PM660_FAB_ID_GF: + *offset = RR_ADC_CHG_TEMP_660_GF_OFFSET_UV; + *slope = RR_ADC_CHG_TEMP_660_GF_SLOPE_UV_PER_C; + return 0; + case PM660_FAB_ID_TSMC: + *offset = RR_ADC_CHG_TEMP_660_SMIC_OFFSET_UV; + *slope = RR_ADC_CHG_TEMP_660_SMIC_SLOPE_UV_PER_C; + return 0; + default: + *offset = RR_ADC_CHG_TEMP_660_MGNA_OFFSET_UV; + *slope = RR_ADC_CHG_TEMP_660_MGNA_SLOPE_UV_PER_C; + } + } else if (chip->pmic->subtype == PMI8998_SUBTYPE) { + switch (chip->pmic->fab_id) { + case PMI8998_FAB_ID_GF: + *offset = RR_ADC_CHG_TEMP_GF_OFFSET_UV; + *slope = RR_ADC_CHG_TEMP_GF_SLOPE_UV_PER_C; + return 0; + case PMI8998_FAB_ID_SMIC: + *offset = RR_ADC_CHG_TEMP_SMIC_OFFSET_UV; + *slope = RR_ADC_CHG_TEMP_SMIC_SLOPE_UV_PER_C; + return 0; + default: + return -EINVAL; + } + } + + return -EINVAL; +} + +/* + * These functions explicitly cast int64_t to int. + * They will never overflow, as the values are small enough. + */ +static int rradc_post_process_batt_id(struct rradc_chip *chip, u16 adc_code, + int *result_ohms) +{ + uint32_t current_value; + int64_t r_id; + + current_value = chip->batt_id_data; + r_id = ((int64_t)adc_code * RR_ADC_FS_VOLTAGE_MV); + r_id = div64_s64(r_id, (RR_ADC_CHAN_MSB * current_value)); + *result_ohms = (int)(r_id * MILLI); + + return 0; +} + +static int rradc_enable_continuous_mode(struct rradc_chip *chip) +{ + int ret; + + /* Clear channel log */ + ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_LOG, + RR_ADC_LOG_CLR_CTRL, RR_ADC_LOG_CLR_CTRL); + if (ret < 0) { + dev_err(chip->dev, "log ctrl update to clear failed:%d\n", ret); + return ret; + } + + ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_LOG, + RR_ADC_LOG_CLR_CTRL, 0); + if (ret < 0) { + dev_err(chip->dev, "log ctrl update to not clear failed:%d\n", + ret); + return ret; + } + + /* Switch to continuous mode */ + ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_CTL, + RR_ADC_CTL_CONTINUOUS_SEL, + RR_ADC_CTL_CONTINUOUS_SEL); + if (ret < 0) + dev_err(chip->dev, "Update to continuous mode failed:%d\n", + ret); + + return ret; +} + +static int rradc_disable_continuous_mode(struct rradc_chip *chip) +{ + int ret; + + /* Switch to non continuous mode */ + ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_CTL, + RR_ADC_CTL_CONTINUOUS_SEL, 0); + if (ret < 0) + dev_err(chip->dev, "Update to non-continuous mode failed:%d\n", + ret); + + return ret; +} + +static bool rradc_is_ready(struct rradc_chip *chip, + enum rradc_channel_id chan_address) +{ + const struct rradc_channel *chan = &rradc_chans[chan_address]; + int ret; + unsigned int status, mask; + + /* BATT_ID STS bit does not get set initially */ + switch (chan_address) { + case RR_ADC_BATT_ID: + mask = RR_ADC_STS_CHANNEL_STS; + break; + default: + mask = RR_ADC_STS_CHANNEL_READING_MASK; + break; + } + + ret = regmap_read(chip->regmap, chip->base + chan->status, &status); + if (ret < 0 || !(status & mask)) + return false; + + return true; +} + +static int rradc_read_status_in_cont_mode(struct rradc_chip *chip, + enum rradc_channel_id chan_address) +{ + const struct rradc_channel *chan = &rradc_chans[chan_address]; + const struct iio_chan_spec *iio_chan = &rradc_iio_chans[chan_address]; + int ret, i; + + if (chan->trigger_mask == 0) { + dev_err(chip->dev, "Channel doesn't have a trigger mask\n"); + return -EINVAL; + } + + ret = regmap_update_bits(chip->regmap, chip->base + chan->trigger_addr, + chan->trigger_mask, chan->trigger_mask); + if (ret < 0) { + dev_err(chip->dev, + "Failed to apply trigger for channel '%s' ret=%d\n", + iio_chan->extend_name, ret); + return ret; + } + + ret = rradc_enable_continuous_mode(chip); + if (ret < 0) { + dev_err(chip->dev, "Failed to switch to continuous mode\n"); + goto disable_trigger; + } + + /* + * The wait/sleep values were found through trial and error, + * this is mostly for the battery ID channel which takes some + * time to settle. + */ + for (i = 0; i < 5; i++) { + if (rradc_is_ready(chip, chan_address)) + break; + usleep_range(50000, 50000 + 500); + } + + if (i == 5) { + dev_err(chip->dev, "Channel '%s' is not ready\n", + iio_chan->extend_name); + ret = -ETIMEDOUT; + } + + rradc_disable_continuous_mode(chip); + +disable_trigger: + regmap_update_bits(chip->regmap, chip->base + chan->trigger_addr, + chan->trigger_mask, 0); + + return ret; +} + +static int rradc_prepare_batt_id_conversion(struct rradc_chip *chip, + enum rradc_channel_id chan_address, + u16 *data) +{ + int ret; + + ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL, + RR_ADC_BATT_ID_CTRL_CHANNEL_CONV, + RR_ADC_BATT_ID_CTRL_CHANNEL_CONV); + if (ret < 0) { + dev_err(chip->dev, "Enabling BATT ID channel failed:%d\n", ret); + return ret; + } + + ret = regmap_update_bits(chip->regmap, + chip->base + RR_ADC_BATT_ID_TRIGGER, + RR_ADC_TRIGGER_CTL, RR_ADC_TRIGGER_CTL); + if (ret < 0) { + dev_err(chip->dev, "BATT_ID trigger set failed:%d\n", ret); + goto out_disable_batt_id; + } + + ret = rradc_read_status_in_cont_mode(chip, chan_address); + + /* Reset registers back to default values */ + regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_TRIGGER, + RR_ADC_TRIGGER_CTL, 0); + +out_disable_batt_id: + regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL, + RR_ADC_BATT_ID_CTRL_CHANNEL_CONV, 0); + + return ret; +} + +static int rradc_do_conversion(struct rradc_chip *chip, + enum rradc_channel_id chan_address, u16 *data) +{ + const struct rradc_channel *chan = &rradc_chans[chan_address]; + const struct iio_chan_spec *iio_chan = &rradc_iio_chans[chan_address]; + int ret; + __le16 buf[3]; + + mutex_lock(&chip->conversion_lock); + + switch (chan_address) { + case RR_ADC_BATT_ID: + ret = rradc_prepare_batt_id_conversion(chip, chan_address, data); + if (ret < 0) { + dev_err(chip->dev, "Battery ID conversion failed:%d\n", + ret); + goto unlock_out; + } + break; + + case RR_ADC_USBIN_V: + case RR_ADC_DIE_TEMP: + ret = rradc_read_status_in_cont_mode(chip, chan_address); + if (ret < 0) { + dev_err(chip->dev, + "Error reading in continuous mode:%d\n", ret); + goto unlock_out; + } + break; + default: + if (!rradc_is_ready(chip, chan_address)) { + /* + * Usually this means the channel isn't attached, for example + * the in_voltage_usbin_v_input channel will not be ready if + * no USB cable is attached + */ + dev_dbg(chip->dev, "channel '%s' is not ready\n", + iio_chan->extend_name); + ret = -ENODATA; + goto unlock_out; + } + break; + } + + ret = rradc_read(chip, chan->lsb, buf, chan->size); + if (ret) { + dev_err(chip->dev, "read data failed\n"); + goto unlock_out; + } + + /* + * For the battery ID we read the register for every ID ADC and then + * see which one is actually connected. + */ + if (chan_address == RR_ADC_BATT_ID) { + u16 batt_id_150 = le16_to_cpu(buf[2]); + u16 batt_id_15 = le16_to_cpu(buf[1]); + u16 batt_id_5 = le16_to_cpu(buf[0]); + + if (!batt_id_150 && !batt_id_15 && !batt_id_5) { + dev_err(chip->dev, + "Invalid batt_id values with all zeros\n"); + ret = -EINVAL; + goto unlock_out; + } + + if (batt_id_150 <= RR_ADC_BATT_ID_RANGE) { + *data = batt_id_150; + chip->batt_id_data = 150; + } else if (batt_id_15 <= RR_ADC_BATT_ID_RANGE) { + *data = batt_id_15; + chip->batt_id_data = 15; + } else { + *data = batt_id_5; + chip->batt_id_data = 5; + } + } else { + /* + * All of the other channels are either 1 or 2 bytes. + * We can rely on the second byte being 0 for 1-byte channels. + */ + *data = le16_to_cpu(buf[0]); + } + +unlock_out: + mutex_unlock(&chip->conversion_lock); + + return ret; +} + +static int rradc_read_scale(struct rradc_chip *chip, int chan_address, int *val, + int *val2) +{ + int64_t fab_offset, fab_slope; + int ret; + + ret = rradc_get_fab_coeff(chip, &fab_offset, &fab_slope); + if (ret < 0) { + dev_err(chip->dev, "Unable to get fab id coefficients\n"); + return -EINVAL; + } + + switch (chan_address) { + case RR_ADC_SKIN_TEMP: + *val = MILLI; + *val2 = RR_ADC_BATT_THERM_LSB_K; + return IIO_VAL_FRACTIONAL; + case RR_ADC_USBIN_I: + *val = RR_ADC_CURR_USBIN_INPUT_FACTOR_MIL * + RR_ADC_FS_VOLTAGE_MV; + *val2 = RR_ADC_CHAN_MSB; + return IIO_VAL_FRACTIONAL; + case RR_ADC_DCIN_I: + *val = RR_ADC_CURR_INPUT_FACTOR * RR_ADC_FS_VOLTAGE_MV; + *val2 = RR_ADC_CHAN_MSB; + return IIO_VAL_FRACTIONAL; + case RR_ADC_USBIN_V: + case RR_ADC_DCIN_V: + *val = RR_ADC_VOLT_INPUT_FACTOR * RR_ADC_FS_VOLTAGE_MV * MILLI; + *val2 = RR_ADC_CHAN_MSB; + return IIO_VAL_FRACTIONAL; + case RR_ADC_GPIO: + *val = RR_ADC_GPIO_FS_RANGE; + *val2 = RR_ADC_CHAN_MSB; + return IIO_VAL_FRACTIONAL; + case RR_ADC_CHG_TEMP: + /* + * We divide val2 by MILLI instead of multiplying val + * to avoid an integer overflow. + */ + *val = -RR_ADC_TEMP_FS_VOLTAGE_NUM; + *val2 = div64_s64(RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB * + fab_slope, + MILLI); + + return IIO_VAL_FRACTIONAL; + case RR_ADC_DIE_TEMP: + *val = RR_ADC_TEMP_FS_VOLTAGE_NUM; + *val2 = RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB * + RR_ADC_DIE_TEMP_SLOPE; + + return IIO_VAL_FRACTIONAL; + default: + return -EINVAL; + } +} + +static int rradc_read_offset(struct rradc_chip *chip, int chan_address, int *val) +{ + int64_t fab_offset, fab_slope; + int64_t offset1, offset2; + int ret; + + switch (chan_address) { + case RR_ADC_SKIN_TEMP: + /* + * Offset from kelvin to degC, divided by the + * scale factor (250). We lose some precision here. + * 273150 / 250 = 1092.6 + */ + *val = div64_s64(ABSOLUTE_ZERO_MILLICELSIUS, + (MILLI / RR_ADC_BATT_THERM_LSB_K)); + return IIO_VAL_INT; + case RR_ADC_CHG_TEMP: + ret = rradc_get_fab_coeff(chip, &fab_offset, &fab_slope); + if (ret < 0) { + dev_err(chip->dev, + "Unable to get fab id coefficients\n"); + return -EINVAL; + } + offset1 = -(fab_offset * RR_ADC_TEMP_FS_VOLTAGE_DEN * + RR_ADC_CHAN_MSB); + offset1 += (int64_t)RR_ADC_TEMP_FS_VOLTAGE_NUM / 2ULL; + offset1 = div64_s64(offset1, + (int64_t)(RR_ADC_TEMP_FS_VOLTAGE_NUM)); + + offset2 = (int64_t)RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC * + RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB * + (int64_t)fab_slope; + offset2 += ((int64_t)MILLI * RR_ADC_TEMP_FS_VOLTAGE_NUM) / 2; + offset2 = div64_s64( + offset2, ((int64_t)MILLI * RR_ADC_TEMP_FS_VOLTAGE_NUM)); + + /* + * The -1 is to compensate for lost precision. + * It should actually be -0.7906976744186046. + * This works out to every value being off + * by about +0.091 degrees C after applying offset and scale. + */ + *val = (int)(offset1 - offset2 - 1); + return IIO_VAL_INT; + case RR_ADC_DIE_TEMP: + offset1 = -RR_ADC_DIE_TEMP_OFFSET * + (int64_t)RR_ADC_TEMP_FS_VOLTAGE_DEN * + (int64_t)RR_ADC_CHAN_MSB; + offset1 = div64_s64(offset1, RR_ADC_TEMP_FS_VOLTAGE_NUM); + + offset2 = -(int64_t)RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC * + RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB * + RR_ADC_DIE_TEMP_SLOPE; + offset2 = div64_s64(offset2, + ((int64_t)RR_ADC_TEMP_FS_VOLTAGE_NUM)); + + /* + * The result is -339, it should be -338.69789, this results + * in the calculated die temp being off by + * -0.004 - -0.0175 degrees C + */ + *val = (int)(offset1 - offset2); + return IIO_VAL_INT; + default: + break; + } + return -EINVAL; +} + +static int rradc_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan_spec, int *val, + int *val2, long mask) +{ + struct rradc_chip *chip = iio_priv(indio_dev); + const struct rradc_channel *chan; + int ret; + u16 adc_code; + + if (chan_spec->address >= RR_ADC_CHAN_MAX) { + dev_err(chip->dev, "Invalid channel index:%lu\n", + chan_spec->address); + return -EINVAL; + } + + switch (mask) { + case IIO_CHAN_INFO_SCALE: + return rradc_read_scale(chip, chan_spec->address, val, val2); + case IIO_CHAN_INFO_OFFSET: + return rradc_read_offset(chip, chan_spec->address, val); + case IIO_CHAN_INFO_RAW: + ret = rradc_do_conversion(chip, chan_spec->address, &adc_code); + if (ret < 0) + return ret; + + *val = adc_code; + return IIO_VAL_INT; + case IIO_CHAN_INFO_PROCESSED: + chan = &rradc_chans[chan_spec->address]; + if (!chan->scale_fn) + return -EINVAL; + ret = rradc_do_conversion(chip, chan_spec->address, &adc_code); + if (ret < 0) + return ret; + + *val = chan->scale_fn(chip, adc_code, val); + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int rradc_read_label(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, char *label) +{ + return snprintf(label, PAGE_SIZE, "%s\n", + rradc_chans[chan->address].label); +} + +static const struct iio_info rradc_info = { + .read_raw = rradc_read_raw, + .read_label = rradc_read_label, +}; + +static const struct rradc_channel rradc_chans[RR_ADC_CHAN_MAX] = { + { + .label = "batt_id", + .scale_fn = rradc_post_process_batt_id, + .lsb = RR_ADC_BATT_ID_5_LSB, + .status = RR_ADC_BATT_ID_STS, + .size = 6, + .trigger_addr = RR_ADC_BATT_ID_TRIGGER, + .trigger_mask = BIT(0), + }, { + .label = "batt", + .lsb = RR_ADC_BATT_THERM_LSB, + .status = RR_ADC_BATT_THERM_STS, + .size = 2, + .trigger_addr = RR_ADC_BATT_THERM_TRIGGER, + }, { + .label = "pmi8998_skin", + .lsb = RR_ADC_SKIN_TEMP_LSB, + .status = RR_ADC_AUX_THERM_STS, + .size = 2, + .trigger_addr = RR_ADC_AUX_THERM_TRIGGER, + }, { + .label = "usbin_i", + .lsb = RR_ADC_USB_IN_I_LSB, + .status = RR_ADC_USB_IN_I_STS, + .size = 2, + .trigger_addr = RR_ADC_USB_IN_I_TRIGGER, + }, { + .label = "usbin_v", + .lsb = RR_ADC_USB_IN_V_LSB, + .status = RR_ADC_USB_IN_V_STS, + .size = 2, + .trigger_addr = RR_ADC_USB_IN_V_TRIGGER, + .trigger_mask = BIT(7), + }, { + .label = "dcin_i", + .lsb = RR_ADC_DC_IN_I_LSB, + .status = RR_ADC_DC_IN_I_STS, + .size = 2, + .trigger_addr = RR_ADC_DC_IN_I_TRIGGER, + }, { + .label = "dcin_v", + .lsb = RR_ADC_DC_IN_V_LSB, + .status = RR_ADC_DC_IN_V_STS, + .size = 2, + .trigger_addr = RR_ADC_DC_IN_V_TRIGGER, + }, { + .label = "pmi8998_die", + .lsb = RR_ADC_PMI_DIE_TEMP_LSB, + .status = RR_ADC_PMI_DIE_TEMP_STS, + .size = 2, + .trigger_addr = RR_ADC_PMI_DIE_TEMP_TRIGGER, + .trigger_mask = RR_ADC_TRIGGER_EVERY_CYCLE, + }, { + .label = "chg", + .lsb = RR_ADC_CHARGER_TEMP_LSB, + .status = RR_ADC_CHARGER_TEMP_STS, + .size = 2, + .trigger_addr = RR_ADC_CHARGER_TEMP_TRIGGER, + }, { + .label = "gpio", + .lsb = RR_ADC_GPIO_LSB, + .status = RR_ADC_GPIO_STS, + .size = 2, + .trigger_addr = RR_ADC_GPIO_TRIGGER, + }, +}; + +static const struct iio_chan_spec rradc_iio_chans[RR_ADC_CHAN_MAX] = { + { + .type = IIO_RESISTANCE, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), + .address = RR_ADC_BATT_ID, + .channel = 0, + .indexed = 1, + }, { + .type = IIO_TEMP, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), + .address = RR_ADC_BATT_THERM, + .channel = 0, + .indexed = 1, + }, { + .type = IIO_TEMP, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_OFFSET), + .address = RR_ADC_SKIN_TEMP, + .channel = 1, + .indexed = 1, + }, { + .type = IIO_CURRENT, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + .address = RR_ADC_USBIN_I, + .channel = 0, + .indexed = 1, + }, { + .type = IIO_VOLTAGE, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + .address = RR_ADC_USBIN_V, + .channel = 0, + .indexed = 1, + }, { + .type = IIO_CURRENT, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + .address = RR_ADC_DCIN_I, + .channel = 1, + .indexed = 1, + }, { + .type = IIO_VOLTAGE, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + .address = RR_ADC_DCIN_V, + .channel = 1, + .indexed = 1, + }, { + .type = IIO_TEMP, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_OFFSET), + .address = RR_ADC_DIE_TEMP, + .channel = 2, + .indexed = 1, + }, { + .type = IIO_TEMP, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_OFFSET) | + BIT(IIO_CHAN_INFO_SCALE), + .address = RR_ADC_CHG_TEMP, + .channel = 3, + .indexed = 1, + }, { + .type = IIO_VOLTAGE, + .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | + BIT(IIO_CHAN_INFO_SCALE), + .address = RR_ADC_GPIO, + .channel = 2, + .indexed = 1, + }, +}; + +static int rradc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct iio_dev *indio_dev; + struct rradc_chip *chip; + int ret, i, batt_id_delay; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*chip)); + if (!indio_dev) + return -ENOMEM; + + chip = iio_priv(indio_dev); + chip->regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!chip->regmap) { + dev_err(dev, "Couldn't get parent's regmap\n"); + return -EINVAL; + } + + chip->dev = dev; + mutex_init(&chip->conversion_lock); + + ret = device_property_read_u32(dev, "reg", &chip->base); + if (ret < 0) { + dev_err(chip->dev, "Couldn't find reg address, ret = %d\n", + ret); + return ret; + } + + batt_id_delay = -1; + ret = device_property_read_u32(dev, "qcom,batt-id-delay-ms", + &batt_id_delay); + if (!ret) { + for (i = 0; i < RRADC_BATT_ID_DELAY_MAX; i++) { + if (batt_id_delay == batt_id_delays[i]) + break; + } + if (i == RRADC_BATT_ID_DELAY_MAX) + batt_id_delay = -1; + } + + if (batt_id_delay >= 0) { + batt_id_delay = FIELD_PREP(BATT_ID_SETTLE_MASK, batt_id_delay); + ret = regmap_update_bits(chip->regmap, + chip->base + RR_ADC_BATT_ID_CFG, + batt_id_delay, batt_id_delay); + if (ret < 0) { + dev_err(chip->dev, + "BATT_ID settling time config failed:%d\n", + ret); + } + } + + /* Get the PMIC revision, we need it to handle some varying coefficients */ + chip->pmic = qcom_pmic_get(chip->dev); + if (IS_ERR(chip->pmic)) { + dev_err(chip->dev, "Unable to get reference to PMIC device\n"); + return PTR_ERR(chip->pmic); + } + + switch (chip->pmic->subtype) { + case PMI8998_SUBTYPE: + indio_dev->name = "pmi8998-rradc"; + break; + case PM660_SUBTYPE: + indio_dev->name = "pm660-rradc"; + break; + default: + indio_dev->name = DRIVER_NAME; + break; + } + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->info = &rradc_info; + indio_dev->channels = rradc_iio_chans; + indio_dev->num_channels = ARRAY_SIZE(rradc_iio_chans); + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct of_device_id rradc_match_table[] = { + { .compatible = "qcom,pm660-rradc" }, + { .compatible = "qcom,pmi8998-rradc" }, + {} +}; +MODULE_DEVICE_TABLE(of, rradc_match_table); + +static struct platform_driver rradc_driver = { + .driver = { + .name = DRIVER_NAME, + .of_match_table = rradc_match_table, + }, + .probe = rradc_probe, +}; +module_platform_driver(rradc_driver); + +MODULE_DESCRIPTION("QCOM SPMI PMIC RR ADC driver"); +MODULE_AUTHOR("Caleb Connolly <caleb.connolly@linaro.org>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c index 5b09a93fdf34..0921ff2d9b3a 100644 --- a/drivers/iio/adc/rzg2l_adc.c +++ b/drivers/iio/adc/rzg2l_adc.c @@ -18,6 +18,7 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> +#include <linux/property.h> #include <linux/reset.h> #define DRIVER_NAME "rzg2l-adc" @@ -260,9 +261,6 @@ static int rzg2l_adc_read_label(struct iio_dev *iio_dev, const struct iio_chan_spec *chan, char *label) { - if (chan->channel >= RZG2L_ADC_MAX_CHANNELS) - return -EINVAL; - return sysfs_emit(label, "%s\n", rzg2l_adc_channel_name[chan->channel]); } diff --git a/drivers/iio/adc/sc27xx_adc.c b/drivers/iio/adc/sc27xx_adc.c index e9ff2d6a8a57..f8421cbba8fa 100644 --- a/drivers/iio/adc/sc27xx_adc.c +++ b/drivers/iio/adc/sc27xx_adc.c @@ -579,15 +579,14 @@ unlock_adc: return ret; } -static void sc27xx_adc_volt_ratio(struct sc27xx_adc_data *data, - int channel, int scale, - u32 *div_numerator, u32 *div_denominator) +static void sc27xx_adc_volt_ratio(struct sc27xx_adc_data *data, int channel, int scale, + struct u32_fract *fract) { u32 ratio; ratio = data->var_data->get_ratio(channel, scale); - *div_numerator = ratio >> SC27XX_RATIO_NUMERATOR_OFFSET; - *div_denominator = ratio & SC27XX_RATIO_DENOMINATOR_MASK; + fract->numerator = ratio >> SC27XX_RATIO_NUMERATOR_OFFSET; + fract->denominator = ratio & SC27XX_RATIO_DENOMINATOR_MASK; } static int adc_to_volt(struct sc27xx_adc_linear_graph *graph, @@ -615,7 +614,7 @@ static int sc27xx_adc_to_volt(struct sc27xx_adc_linear_graph *graph, static int sc27xx_adc_convert_volt(struct sc27xx_adc_data *data, int channel, int scale, int raw_adc) { - u32 numerator, denominator; + struct u32_fract fract; u32 volt; /* @@ -637,9 +636,9 @@ static int sc27xx_adc_convert_volt(struct sc27xx_adc_data *data, int channel, break; } - sc27xx_adc_volt_ratio(data, channel, scale, &numerator, &denominator); + sc27xx_adc_volt_ratio(data, channel, scale, &fract); - return DIV_ROUND_CLOSEST(volt * denominator, numerator); + return DIV_ROUND_CLOSEST(volt * fract.denominator, fract.numerator); } static int sc27xx_adc_read_processed(struct sc27xx_adc_data *data, diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-core.c index 3efb8c404ccc..1ce52af3fe8b 100644 --- a/drivers/iio/adc/stm32-adc-core.c +++ b/drivers/iio/adc/stm32-adc-core.c @@ -358,7 +358,7 @@ static void stm32_adc_irq_handler(struct irq_desc *desc) if ((status & priv->cfg->regs->eoc_msk[i] && stm32_adc_eoc_enabled(priv, i)) || (status & priv->cfg->regs->ovr_msk[i])) - generic_handle_irq(irq_find_mapping(priv->domain, i)); + generic_handle_domain_irq(priv->domain, i); } chained_irq_exit(chip, desc); diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c index 11ef873d6453..130e8dd6f0c8 100644 --- a/drivers/iio/adc/stm32-adc.c +++ b/drivers/iio/adc/stm32-adc.c @@ -876,6 +876,9 @@ static void stm32h7_adc_disable(struct iio_dev *indio_dev) int ret; u32 val; + if (!(stm32_adc_readl(adc, STM32H7_ADC_CR) & STM32H7_ADEN)) + return; + /* Disable ADC and wait until it's effectively disabled */ stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, @@ -1016,6 +1019,9 @@ static int stm32h7_adc_selfcalib(struct iio_dev *indio_dev) if (adc->cal.calibrated) return true; + /* ADC must be disabled for calibration */ + stm32h7_adc_disable(indio_dev); + /* * Select calibration mode: * - Offset calibration for single ended inputs diff --git a/drivers/iio/adc/stx104.c b/drivers/iio/adc/stx104.c index 55bd2dc514e9..7552351bfed9 100644 --- a/drivers/iio/adc/stx104.c +++ b/drivers/iio/adc/stx104.c @@ -51,7 +51,7 @@ MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base addresses"); */ struct stx104_iio { unsigned int chan_out_states[STX104_NUM_OUT_CHAN]; - unsigned int base; + void __iomem *base; }; /** @@ -64,7 +64,7 @@ struct stx104_iio { struct stx104_gpio { struct gpio_chip chip; spinlock_t lock; - unsigned int base; + void __iomem *base; unsigned int out_state; }; @@ -79,7 +79,7 @@ static int stx104_read_raw(struct iio_dev *indio_dev, switch (mask) { case IIO_CHAN_INFO_HARDWAREGAIN: /* get gain configuration */ - adc_config = inb(priv->base + 11); + adc_config = ioread8(priv->base + 11); gain = adc_config & 0x3; *val = 1 << gain; @@ -91,24 +91,24 @@ static int stx104_read_raw(struct iio_dev *indio_dev, } /* select ADC channel */ - outb(chan->channel | (chan->channel << 4), priv->base + 2); + iowrite8(chan->channel | (chan->channel << 4), priv->base + 2); /* trigger ADC sample capture and wait for completion */ - outb(0, priv->base); - while (inb(priv->base + 8) & BIT(7)); + iowrite8(0, priv->base); + while (ioread8(priv->base + 8) & BIT(7)); - *val = inw(priv->base); + *val = ioread16(priv->base); return IIO_VAL_INT; case IIO_CHAN_INFO_OFFSET: /* get ADC bipolar/unipolar configuration */ - adc_config = inb(priv->base + 11); + adc_config = ioread8(priv->base + 11); adbu = !(adc_config & BIT(2)); *val = -32768 * adbu; return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: /* get ADC bipolar/unipolar and gain configuration */ - adc_config = inb(priv->base + 11); + adc_config = ioread8(priv->base + 11); adbu = !(adc_config & BIT(2)); gain = adc_config & 0x3; @@ -130,16 +130,16 @@ static int stx104_write_raw(struct iio_dev *indio_dev, /* Only four gain states (x1, x2, x4, x8) */ switch (val) { case 1: - outb(0, priv->base + 11); + iowrite8(0, priv->base + 11); break; case 2: - outb(1, priv->base + 11); + iowrite8(1, priv->base + 11); break; case 4: - outb(2, priv->base + 11); + iowrite8(2, priv->base + 11); break; case 8: - outb(3, priv->base + 11); + iowrite8(3, priv->base + 11); break; default: return -EINVAL; @@ -153,7 +153,7 @@ static int stx104_write_raw(struct iio_dev *indio_dev, return -EINVAL; priv->chan_out_states[chan->channel] = val; - outw(val, priv->base + 4 + 2 * chan->channel); + iowrite16(val, priv->base + 4 + 2 * chan->channel); return 0; } @@ -222,7 +222,7 @@ static int stx104_gpio_get(struct gpio_chip *chip, unsigned int offset) if (offset >= 4) return -EINVAL; - return !!(inb(stx104gpio->base) & BIT(offset)); + return !!(ioread8(stx104gpio->base) & BIT(offset)); } static int stx104_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, @@ -230,7 +230,7 @@ static int stx104_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, { struct stx104_gpio *const stx104gpio = gpiochip_get_data(chip); - *bits = inb(stx104gpio->base); + *bits = ioread8(stx104gpio->base); return 0; } @@ -252,7 +252,7 @@ static void stx104_gpio_set(struct gpio_chip *chip, unsigned int offset, else stx104gpio->out_state &= ~mask; - outb(stx104gpio->out_state, stx104gpio->base); + iowrite8(stx104gpio->out_state, stx104gpio->base); spin_unlock_irqrestore(&stx104gpio->lock, flags); } @@ -279,7 +279,7 @@ static void stx104_gpio_set_multiple(struct gpio_chip *chip, stx104gpio->out_state &= ~*mask; stx104gpio->out_state |= *mask & *bits; - outb(stx104gpio->out_state, stx104gpio->base); + iowrite8(stx104gpio->out_state, stx104gpio->base); spin_unlock_irqrestore(&stx104gpio->lock, flags); } @@ -306,11 +306,16 @@ static int stx104_probe(struct device *dev, unsigned int id) return -EBUSY; } + priv = iio_priv(indio_dev); + priv->base = devm_ioport_map(dev, base[id], STX104_EXTENT); + if (!priv->base) + return -ENOMEM; + indio_dev->info = &stx104_info; indio_dev->modes = INDIO_DIRECT_MODE; /* determine if differential inputs */ - if (inb(base[id] + 8) & BIT(5)) { + if (ioread8(priv->base + 8) & BIT(5)) { indio_dev->num_channels = ARRAY_SIZE(stx104_channels_diff); indio_dev->channels = stx104_channels_diff; } else { @@ -320,18 +325,15 @@ static int stx104_probe(struct device *dev, unsigned int id) indio_dev->name = dev_name(dev); - priv = iio_priv(indio_dev); - priv->base = base[id]; - /* configure device for software trigger operation */ - outb(0, base[id] + 9); + iowrite8(0, priv->base + 9); /* initialize gain setting to x1 */ - outb(0, base[id] + 11); + iowrite8(0, priv->base + 11); /* initialize DAC output to 0V */ - outw(0, base[id] + 4); - outw(0, base[id] + 6); + iowrite16(0, priv->base + 4); + iowrite16(0, priv->base + 6); stx104gpio->chip.label = dev_name(dev); stx104gpio->chip.parent = dev; @@ -346,7 +348,7 @@ static int stx104_probe(struct device *dev, unsigned int id) stx104gpio->chip.get_multiple = stx104_gpio_get_multiple; stx104gpio->chip.set = stx104_gpio_set; stx104gpio->chip.set_multiple = stx104_gpio_set_multiple; - stx104gpio->base = base[id] + 3; + stx104gpio->base = priv->base + 3; stx104gpio->out_state = 0x0; spin_lock_init(&stx104gpio->lock); diff --git a/drivers/iio/adc/ti-adc0832.c b/drivers/iio/adc/ti-adc0832.c index fb5e72600b96..b11ce555ba3b 100644 --- a/drivers/iio/adc/ti-adc0832.c +++ b/drivers/iio/adc/ti-adc0832.c @@ -36,7 +36,7 @@ struct adc0832 { */ u8 data[24] __aligned(8); - u8 tx_buf[2] ____cacheline_aligned; + u8 tx_buf[2] __aligned(IIO_DMA_MINALIGN); u8 rx_buf[2]; }; diff --git a/drivers/iio/adc/ti-adc084s021.c b/drivers/iio/adc/ti-adc084s021.c index c9b5d9aec3dc..1f6e53832e06 100644 --- a/drivers/iio/adc/ti-adc084s021.c +++ b/drivers/iio/adc/ti-adc084s021.c @@ -32,10 +32,10 @@ struct adc084s021 { s64 ts __aligned(8); } scan; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache line. */ - u16 tx_buf[4] ____cacheline_aligned; + u16 tx_buf[4] __aligned(IIO_DMA_MINALIGN); __be16 rx_buf[5]; /* First 16-bits are trash */ }; diff --git a/drivers/iio/adc/ti-adc108s102.c b/drivers/iio/adc/ti-adc108s102.c index c8e48881c37f..c82a161630e1 100644 --- a/drivers/iio/adc/ti-adc108s102.c +++ b/drivers/iio/adc/ti-adc108s102.c @@ -77,8 +77,8 @@ struct adc108s102_state { * tx_buf: 8 channel read commands, plus 1 dummy command * rx_buf: 1 dummy response, 8 channel responses */ - __be16 rx_buf[9] ____cacheline_aligned; - __be16 tx_buf[9] ____cacheline_aligned; + __be16 rx_buf[9] __aligned(IIO_DMA_MINALIGN); + __be16 tx_buf[9] __aligned(IIO_DMA_MINALIGN); }; #define ADC108S102_V_CHAN(index) \ diff --git a/drivers/iio/adc/ti-adc12138.c b/drivers/iio/adc/ti-adc12138.c index 59d75d09604f..c0a72d72f3a9 100644 --- a/drivers/iio/adc/ti-adc12138.c +++ b/drivers/iio/adc/ti-adc12138.c @@ -55,7 +55,7 @@ struct adc12138 { */ __be16 data[20] __aligned(8); - u8 tx_buf[2] ____cacheline_aligned; + u8 tx_buf[2] __aligned(IIO_DMA_MINALIGN); u8 rx_buf[2]; }; diff --git a/drivers/iio/adc/ti-adc128s052.c b/drivers/iio/adc/ti-adc128s052.c index 8e7adec87755..622fd384983c 100644 --- a/drivers/iio/adc/ti-adc128s052.c +++ b/drivers/iio/adc/ti-adc128s052.c @@ -29,7 +29,7 @@ struct adc128 { struct regulator *reg; struct mutex lock; - u8 buffer[2] ____cacheline_aligned; + u8 buffer[2] __aligned(IIO_DMA_MINALIGN); }; static int adc128_adc_conversion(struct adc128 *adc, u8 channel) diff --git a/drivers/iio/adc/ti-adc161s626.c b/drivers/iio/adc/ti-adc161s626.c index 75ca7f1c8726..b789891dcf49 100644 --- a/drivers/iio/adc/ti-adc161s626.c +++ b/drivers/iio/adc/ti-adc161s626.c @@ -71,7 +71,7 @@ struct ti_adc_data { u8 read_size; u8 shift; - u8 buffer[16] ____cacheline_aligned; + u8 buffer[16] __aligned(IIO_DMA_MINALIGN); }; static int ti_adc_read_measurement(struct ti_adc_data *data, diff --git a/drivers/iio/adc/ti-ads1015.c b/drivers/iio/adc/ti-ads1015.c index 5544da80b636..e3dfc155fbe2 100644 --- a/drivers/iio/adc/ti-ads1015.c +++ b/drivers/iio/adc/ti-ads1015.c @@ -1098,6 +1098,7 @@ static int ads1015_remove(struct i2c_client *client) { struct iio_dev *indio_dev = i2c_get_clientdata(client); struct ads1015_data *data = iio_priv(indio_dev); + int ret; iio_device_unregister(indio_dev); @@ -1105,7 +1106,12 @@ static int ads1015_remove(struct i2c_client *client) pm_runtime_set_suspended(&client->dev); /* power down single shot mode */ - return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT); + ret = ads1015_set_conv_mode(data, ADS1015_SINGLESHOT); + if (ret) + dev_warn(&client->dev, "Failed to power down (%pe)\n", + ERR_PTR(ret)); + + return 0; } #ifdef CONFIG_PM diff --git a/drivers/iio/adc/ti-ads124s08.c b/drivers/iio/adc/ti-ads124s08.c index 767b3b634809..64833156c199 100644 --- a/drivers/iio/adc/ti-ads124s08.c +++ b/drivers/iio/adc/ti-ads124s08.c @@ -106,7 +106,7 @@ struct ads124s_private { * timestamp is maintained. */ u32 buffer[ADS124S08_MAX_CHANNELS + sizeof(s64)/sizeof(u32)] __aligned(8); - u8 data[5] ____cacheline_aligned; + u8 data[5] __aligned(IIO_DMA_MINALIGN); }; #define ADS124S08_CHAN(index) \ diff --git a/drivers/iio/adc/ti-ads131e08.c b/drivers/iio/adc/ti-ads131e08.c index 80a09817c119..32237cacc9a3 100644 --- a/drivers/iio/adc/ti-ads131e08.c +++ b/drivers/iio/adc/ti-ads131e08.c @@ -105,7 +105,7 @@ struct ads131e08_state { s64 ts __aligned(8); } tmp_buf; - u8 tx_buf[3] ____cacheline_aligned; + u8 tx_buf[3] __aligned(IIO_DMA_MINALIGN); /* * Add extra one padding byte to be able to access the last channel * value using u32 pointer diff --git a/drivers/iio/adc/ti-ads7950.c b/drivers/iio/adc/ti-ads7950.c index e3658b969c5b..2cc9a9bd9db6 100644 --- a/drivers/iio/adc/ti-ads7950.c +++ b/drivers/iio/adc/ti-ads7950.c @@ -102,11 +102,11 @@ struct ti_ads7950_state { unsigned int gpio_cmd_settings_bitmask; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ u16 rx_buf[TI_ADS7950_MAX_CHAN + 2 + TI_ADS7950_TIMESTAMP_SIZE] - ____cacheline_aligned; + __aligned(IIO_DMA_MINALIGN); u16 tx_buf[TI_ADS7950_MAX_CHAN + 2]; u16 single_tx; u16 single_rx; diff --git a/drivers/iio/adc/ti-ads8344.c b/drivers/iio/adc/ti-ads8344.c index c96d2a9ba924..bbd85cb47f81 100644 --- a/drivers/iio/adc/ti-ads8344.c +++ b/drivers/iio/adc/ti-ads8344.c @@ -28,7 +28,7 @@ struct ads8344 { */ struct mutex lock; - u8 tx_buf ____cacheline_aligned; + u8 tx_buf __aligned(IIO_DMA_MINALIGN); u8 rx_buf[3]; }; diff --git a/drivers/iio/adc/ti-ads8688.c b/drivers/iio/adc/ti-ads8688.c index 708cca0a63be..ef06a897421a 100644 --- a/drivers/iio/adc/ti-ads8688.c +++ b/drivers/iio/adc/ti-ads8688.c @@ -71,7 +71,7 @@ struct ads8688_state { union { __be32 d32; u8 d8[4]; - } data[2] ____cacheline_aligned; + } data[2] __aligned(IIO_DMA_MINALIGN); }; enum ads8688_id { diff --git a/drivers/iio/adc/ti-tlc4541.c b/drivers/iio/adc/ti-tlc4541.c index 2406eda9dfc6..30f629a553a1 100644 --- a/drivers/iio/adc/ti-tlc4541.c +++ b/drivers/iio/adc/ti-tlc4541.c @@ -37,12 +37,12 @@ struct tlc4541_state { struct spi_message scan_single_msg; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. * 2 bytes data + 6 bytes padding + 8 bytes timestamp when * call iio_push_to_buffers_with_timestamp. */ - __be16 rx_buf[8] ____cacheline_aligned; + __be16 rx_buf[8] __aligned(IIO_DMA_MINALIGN); }; struct tlc4541_chip_info { diff --git a/drivers/iio/adc/ti-tsc2046.c b/drivers/iio/adc/ti-tsc2046.c index 55b35570ad8b..0d9436a69cbf 100644 --- a/drivers/iio/adc/ti-tsc2046.c +++ b/drivers/iio/adc/ti-tsc2046.c @@ -776,7 +776,7 @@ static int tsc2046_adc_probe(struct spi_device *spi) priv->spi = spi; indio_dev->name = TI_TSC2046_NAME; - indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_TRIGGERED; + indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->channels = dcfg->channels; indio_dev->num_channels = dcfg->num_channels; indio_dev->info = &tsc2046_adc_info; diff --git a/drivers/iio/adc/vf610_adc.c b/drivers/iio/adc/vf610_adc.c index c84293efc129..c6b16cf6e367 100644 --- a/drivers/iio/adc/vf610_adc.c +++ b/drivers/iio/adc/vf610_adc.c @@ -5,7 +5,9 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ +#include <linux/mod_devicetable.h> #include <linux/module.h> +#include <linux/property.h> #include <linux/platform_device.h> #include <linux/interrupt.h> #include <linux/delay.h> @@ -14,10 +16,7 @@ #include <linux/io.h> #include <linux/clk.h> #include <linux/completion.h> -#include <linux/of.h> -#include <linux/of_irq.h> #include <linux/regulator/consumer.h> -#include <linux/of_platform.h> #include <linux/err.h> #include <linux/iio/iio.h> @@ -799,6 +798,7 @@ MODULE_DEVICE_TABLE(of, vf610_adc_match); static int vf610_adc_probe(struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct vf610_adc *info; struct iio_dev *indio_dev; int irq; @@ -846,13 +846,10 @@ static int vf610_adc_probe(struct platform_device *pdev) info->vref_uv = regulator_get_voltage(info->vref); - of_property_read_u32_array(pdev->dev.of_node, "fsl,adck-max-frequency", - info->max_adck_rate, 3); + device_property_read_u32_array(dev, "fsl,adck-max-frequency", info->max_adck_rate, 3); - ret = of_property_read_u32(pdev->dev.of_node, "min-sample-time", - &info->adc_feature.default_sample_time); - if (ret) - info->adc_feature.default_sample_time = DEFAULT_SAMPLE_TIME; + info->adc_feature.default_sample_time = DEFAULT_SAMPLE_TIME; + device_property_read_u32(dev, "min-sample-time", &info->adc_feature.default_sample_time); platform_set_drvdata(pdev, indio_dev); diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c index 823c8e5f9809..1b247722ba25 100644 --- a/drivers/iio/adc/xilinx-xadc-core.c +++ b/drivers/iio/adc/xilinx-xadc-core.c @@ -17,10 +17,11 @@ #include <linux/interrupt.h> #include <linux/io.h> #include <linux/kernel.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of.h> #include <linux/overflow.h> #include <linux/platform_device.h> +#include <linux/property.h> #include <linux/slab.h> #include <linux/sysfs.h> @@ -1182,14 +1183,13 @@ static const struct of_device_id xadc_of_match_table[] = { }; MODULE_DEVICE_TABLE(of, xadc_of_match_table); -static int xadc_parse_dt(struct iio_dev *indio_dev, struct device_node *np, - unsigned int *conf, int irq) +static int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq) { struct device *dev = indio_dev->dev.parent; struct xadc *xadc = iio_priv(indio_dev); const struct iio_chan_spec *channel_templates; struct iio_chan_spec *channels, *chan; - struct device_node *chan_node, *child; + struct fwnode_handle *chan_node, *child; unsigned int max_channels; unsigned int num_channels; const char *external_mux; @@ -1200,7 +1200,7 @@ static int xadc_parse_dt(struct iio_dev *indio_dev, struct device_node *np, *conf = 0; - ret = of_property_read_string(np, "xlnx,external-mux", &external_mux); + ret = device_property_read_string(dev, "xlnx,external-mux", &external_mux); if (ret < 0 || strcasecmp(external_mux, "none") == 0) xadc->external_mux_mode = XADC_EXTERNAL_MUX_NONE; else if (strcasecmp(external_mux, "single") == 0) @@ -1211,8 +1211,7 @@ static int xadc_parse_dt(struct iio_dev *indio_dev, struct device_node *np, return -EINVAL; if (xadc->external_mux_mode != XADC_EXTERNAL_MUX_NONE) { - ret = of_property_read_u32(np, "xlnx,external-mux-channel", - &ext_mux_chan); + ret = device_property_read_u32(dev, "xlnx,external-mux-channel", &ext_mux_chan); if (ret < 0) return ret; @@ -1247,33 +1246,31 @@ static int xadc_parse_dt(struct iio_dev *indio_dev, struct device_node *np, num_channels = 9; chan = &channels[9]; - chan_node = of_get_child_by_name(np, "xlnx,channels"); - if (chan_node) { - for_each_child_of_node(chan_node, child) { - if (num_channels >= max_channels) { - of_node_put(child); - break; - } + chan_node = device_get_named_child_node(dev, "xlnx,channels"); + fwnode_for_each_child_node(chan_node, child) { + if (num_channels >= max_channels) { + fwnode_handle_put(child); + break; + } - ret = of_property_read_u32(child, "reg", ®); - if (ret || reg > 16) - continue; + ret = fwnode_property_read_u32(child, "reg", ®); + if (ret || reg > 16) + continue; - if (of_property_read_bool(child, "xlnx,bipolar")) - chan->scan_type.sign = 's'; + if (fwnode_property_read_bool(child, "xlnx,bipolar")) + chan->scan_type.sign = 's'; - if (reg == 0) { - chan->scan_index = 11; - chan->address = XADC_REG_VPVN; - } else { - chan->scan_index = 15 + reg; - chan->address = XADC_REG_VAUX(reg - 1); - } - num_channels++; - chan++; + if (reg == 0) { + chan->scan_index = 11; + chan->address = XADC_REG_VPVN; + } else { + chan->scan_index = 15 + reg; + chan->address = XADC_REG_VAUX(reg - 1); } + num_channels++; + chan++; } - of_node_put(chan_node); + fwnode_handle_put(chan_node); /* No IRQ => no events */ if (irq <= 0) { @@ -1316,7 +1313,6 @@ static void xadc_cancel_delayed_work(void *data) static int xadc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - const struct of_device_id *id; const struct xadc_ops *ops; struct iio_dev *indio_dev; unsigned int bipolar_mask; @@ -1326,15 +1322,10 @@ static int xadc_probe(struct platform_device *pdev) int irq; int i; - if (!dev->of_node) - return -ENODEV; - - id = of_match_node(xadc_of_match_table, dev->of_node); - if (!id) + ops = device_get_match_data(dev); + if (!ops) return -EINVAL; - ops = id->data; - irq = platform_get_irq_optional(pdev, 0); if (irq < 0 && (irq != -ENXIO || !(ops->flags & XADC_FLAGS_IRQ_OPTIONAL))) @@ -1345,7 +1336,7 @@ static int xadc_probe(struct platform_device *pdev) return -ENOMEM; xadc = iio_priv(indio_dev); - xadc->ops = id->data; + xadc->ops = ops; init_completion(&xadc->completion); mutex_init(&xadc->mutex); spin_lock_init(&xadc->lock); @@ -1359,7 +1350,7 @@ static int xadc_probe(struct platform_device *pdev) indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->info = &xadc_info; - ret = xadc_parse_dt(indio_dev, dev->of_node, &conf0, irq); + ret = xadc_parse_dt(indio_dev, &conf0, irq); if (ret) return ret; |