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path: root/drivers/interconnect/qcom/sc7280.c
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Diffstat (limited to 'drivers/interconnect/qcom/sc7280.c')
-rw-r--r--drivers/interconnect/qcom/sc7280.c1066
1 files changed, 593 insertions, 473 deletions
diff --git a/drivers/interconnect/qcom/sc7280.c b/drivers/interconnect/qcom/sc7280.c
index 8d1b55c3705c..c4cb6443f2d4 100644
--- a/drivers/interconnect/qcom/sc7280.c
+++ b/drivers/interconnect/qcom/sc7280.c
@@ -1,1289 +1,1400 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*
*/
#include <linux/device.h>
#include <linux/interconnect.h>
#include <linux/interconnect-provider.h>
+#include <linux/mod_devicetable.h>
#include <linux/module.h>
-#include <linux/of_platform.h>
+#include <linux/platform_device.h>
#include <dt-bindings/interconnect/qcom,sc7280.h>
#include "bcm-voter.h"
#include "icc-rpmh.h"
-#include "sc7280.h"
+
+static struct qcom_icc_node qhm_qspi;
+static struct qcom_icc_node qhm_qup0;
+static struct qcom_icc_node qhm_qup1;
+static struct qcom_icc_node qnm_a1noc_cfg;
+static struct qcom_icc_node xm_sdc1;
+static struct qcom_icc_node xm_sdc2;
+static struct qcom_icc_node xm_sdc4;
+static struct qcom_icc_node xm_ufs_mem;
+static struct qcom_icc_node xm_usb2;
+static struct qcom_icc_node xm_usb3_0;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qnm_a2noc_cfg;
+static struct qcom_icc_node qnm_cnoc_datapath;
+static struct qcom_icc_node qxm_crypto;
+static struct qcom_icc_node qxm_ipa;
+static struct qcom_icc_node xm_pcie3_0;
+static struct qcom_icc_node xm_pcie3_1;
+static struct qcom_icc_node xm_qdss_etr;
+static struct qcom_icc_node qup0_core_master;
+static struct qcom_icc_node qup1_core_master;
+static struct qcom_icc_node qnm_cnoc3_cnoc2;
+static struct qcom_icc_node xm_qdss_dap;
+static struct qcom_icc_node qnm_cnoc2_cnoc3;
+static struct qcom_icc_node qnm_gemnoc_cnoc;
+static struct qcom_icc_node qnm_gemnoc_pcie;
+static struct qcom_icc_node qnm_cnoc_dc_noc;
+static struct qcom_icc_node alm_gpu_tcu;
+static struct qcom_icc_node alm_sys_tcu;
+static struct qcom_icc_node chm_apps;
+static struct qcom_icc_node qnm_cmpnoc;
+static struct qcom_icc_node qnm_gemnoc_cfg;
+static struct qcom_icc_node qnm_gpu;
+static struct qcom_icc_node qnm_mnoc_hf;
+static struct qcom_icc_node qnm_mnoc_sf;
+static struct qcom_icc_node qnm_pcie;
+static struct qcom_icc_node qnm_snoc_gc;
+static struct qcom_icc_node qnm_snoc_sf;
+static struct qcom_icc_node qhm_config_noc;
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node qnm_mnoc_cfg;
+static struct qcom_icc_node qnm_video0;
+static struct qcom_icc_node qnm_video_cpu;
+static struct qcom_icc_node qxm_camnoc_hf;
+static struct qcom_icc_node qxm_camnoc_icp;
+static struct qcom_icc_node qxm_camnoc_sf;
+static struct qcom_icc_node qxm_mdp0;
+static struct qcom_icc_node qhm_nsp_noc_config;
+static struct qcom_icc_node qxm_nsp;
+static struct qcom_icc_node qnm_aggre1_noc;
+static struct qcom_icc_node qnm_aggre2_noc;
+static struct qcom_icc_node qnm_snoc_cfg;
+static struct qcom_icc_node qxm_pimem;
+static struct qcom_icc_node xm_gic;
+static struct qcom_icc_node qns_a1noc_snoc;
+static struct qcom_icc_node srvc_aggre1_noc;
+static struct qcom_icc_node qns_a2noc_snoc;
+static struct qcom_icc_node qns_pcie_mem_noc;
+static struct qcom_icc_node srvc_aggre2_noc;
+static struct qcom_icc_node qup0_core_slave;
+static struct qcom_icc_node qup1_core_slave;
+static struct qcom_icc_node qhs_ahb2phy0;
+static struct qcom_icc_node qhs_ahb2phy1;
+static struct qcom_icc_node qhs_camera_cfg;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_compute_cfg;
+static struct qcom_icc_node qhs_cpr_cx;
+static struct qcom_icc_node qhs_cpr_mx;
+static struct qcom_icc_node qhs_crypto0_cfg;
+static struct qcom_icc_node qhs_cx_rdpm;
+static struct qcom_icc_node qhs_dcc_cfg;
+static struct qcom_icc_node qhs_display_cfg;
+static struct qcom_icc_node qhs_gpuss_cfg;
+static struct qcom_icc_node qhs_hwkm;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_ipa;
+static struct qcom_icc_node qhs_ipc_router;
+static struct qcom_icc_node qhs_lpass_cfg;
+static struct qcom_icc_node qhs_mss_cfg;
+static struct qcom_icc_node qhs_mx_rdpm;
+static struct qcom_icc_node qhs_pcie0_cfg;
+static struct qcom_icc_node qhs_pcie1_cfg;
+static struct qcom_icc_node qhs_pdm;
+static struct qcom_icc_node qhs_pimem_cfg;
+static struct qcom_icc_node qhs_pka_wrapper_cfg;
+static struct qcom_icc_node qhs_pmu_wrapper_cfg;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qspi;
+static struct qcom_icc_node qhs_qup0;
+static struct qcom_icc_node qhs_qup1;
+static struct qcom_icc_node qhs_sdc1;
+static struct qcom_icc_node qhs_sdc2;
+static struct qcom_icc_node qhs_sdc4;
+static struct qcom_icc_node qhs_security;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm;
+static struct qcom_icc_node qhs_ufs_mem_cfg;
+static struct qcom_icc_node qhs_usb2;
+static struct qcom_icc_node qhs_usb3_0;
+static struct qcom_icc_node qhs_venus_cfg;
+static struct qcom_icc_node qhs_vsense_ctrl_cfg;
+static struct qcom_icc_node qns_a1_noc_cfg;
+static struct qcom_icc_node qns_a2_noc_cfg;
+static struct qcom_icc_node qns_cnoc2_cnoc3;
+static struct qcom_icc_node qns_mnoc_cfg;
+static struct qcom_icc_node qns_snoc_cfg;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_apss;
+static struct qcom_icc_node qns_cnoc3_cnoc2;
+static struct qcom_icc_node qns_cnoc_a2noc;
+static struct qcom_icc_node qns_ddrss_cfg;
+static struct qcom_icc_node qxs_boot_imem;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node qxs_pimem;
+static struct qcom_icc_node xs_pcie_0;
+static struct qcom_icc_node xs_pcie_1;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
+static struct qcom_icc_node qhs_llcc;
+static struct qcom_icc_node qns_gemnoc;
+static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg;
+static struct qcom_icc_node qhs_modem_ms_mpu_cfg;
+static struct qcom_icc_node qns_gem_noc_cnoc;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node qns_pcie;
+static struct qcom_icc_node srvc_even_gemnoc;
+static struct qcom_icc_node srvc_odd_gemnoc;
+static struct qcom_icc_node srvc_sys_gemnoc;
+static struct qcom_icc_node qhs_lpass_core;
+static struct qcom_icc_node qhs_lpass_lpi;
+static struct qcom_icc_node qhs_lpass_mpu;
+static struct qcom_icc_node qhs_lpass_top;
+static struct qcom_icc_node srvc_niu_aml_noc;
+static struct qcom_icc_node srvc_niu_lpass_agnoc;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qns_mem_noc_hf;
+static struct qcom_icc_node qns_mem_noc_sf;
+static struct qcom_icc_node srvc_mnoc;
+static struct qcom_icc_node qns_nsp_gemnoc;
+static struct qcom_icc_node service_nsp_noc;
+static struct qcom_icc_node qns_gemnoc_gc;
+static struct qcom_icc_node qns_gemnoc_sf;
+static struct qcom_icc_node srvc_snoc;
static struct qcom_icc_node qhm_qspi = {
.name = "qhm_qspi",
- .id = SC7280_MASTER_QSPI_0,
.channels = 1,
.buswidth = 4,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x7000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ },
.num_links = 1,
- .links = { SC7280_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node qhm_qup0 = {
.name = "qhm_qup0",
- .id = SC7280_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x11000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ },
.num_links = 1,
- .links = { SC7280_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
- .id = SC7280_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x8000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ },
.num_links = 1,
- .links = { SC7280_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node qnm_a1noc_cfg = {
.name = "qnm_a1noc_cfg",
- .id = SC7280_MASTER_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SC7280_SLAVE_SERVICE_A1NOC },
+ .link_nodes = { &srvc_aggre1_noc },
};
static struct qcom_icc_node xm_sdc1 = {
.name = "xm_sdc1",
- .id = SC7280_MASTER_SDCC_1,
.channels = 1,
.buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0xc000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ },
.num_links = 1,
- .links = { SC7280_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node xm_sdc2 = {
.name = "xm_sdc2",
- .id = SC7280_MASTER_SDCC_2,
.channels = 1,
.buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0xe000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ },
.num_links = 1,
- .links = { SC7280_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node xm_sdc4 = {
.name = "xm_sdc4",
- .id = SC7280_MASTER_SDCC_4,
.channels = 1,
.buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x9000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ },
.num_links = 1,
- .links = { SC7280_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
- .id = SC7280_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0xa000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ },
.num_links = 1,
- .links = { SC7280_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node xm_usb2 = {
.name = "xm_usb2",
- .id = SC7280_MASTER_USB2,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SC7280_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
- .id = SC7280_MASTER_USB3_0,
.channels = 1,
.buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0xb000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ },
.num_links = 1,
- .links = { SC7280_SLAVE_A1NOC_SNOC },
+ .link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = SC7280_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x18000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ },
.num_links = 1,
- .links = { SC7280_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_node qnm_a2noc_cfg = {
.name = "qnm_a2noc_cfg",
- .id = SC7280_MASTER_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SC7280_SLAVE_SERVICE_A2NOC },
+ .link_nodes = { &srvc_aggre2_noc },
};
static struct qcom_icc_node qnm_cnoc_datapath = {
.name = "qnm_cnoc_datapath",
- .id = SC7280_MASTER_CNOC_A2NOC,
.channels = 1,
.buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x1c000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ },
.num_links = 1,
- .links = { SC7280_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
- .id = SC7280_MASTER_CRYPTO,
.channels = 1,
.buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x1d000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ },
.num_links = 1,
- .links = { SC7280_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
- .id = SC7280_MASTER_IPA,
.channels = 1,
.buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x10000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ },
.num_links = 1,
- .links = { SC7280_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_node xm_pcie3_0 = {
.name = "xm_pcie3_0",
- .id = SC7280_MASTER_PCIE_0,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_mem_noc },
};
static struct qcom_icc_node xm_pcie3_1 = {
.name = "xm_pcie3_1",
- .id = SC7280_MASTER_PCIE_1,
.channels = 1,
.buswidth = 8,
- .links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC },
+ .num_links = 1,
+ .link_nodes = { &qns_pcie_mem_noc },
};
static struct qcom_icc_node xm_qdss_etr = {
.name = "xm_qdss_etr",
- .id = SC7280_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x15000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ },
.num_links = 1,
- .links = { SC7280_SLAVE_A2NOC_SNOC },
+ .link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
- .id = SC7280_MASTER_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SC7280_SLAVE_QUP_CORE_0 },
+ .link_nodes = { &qup0_core_slave },
};
static struct qcom_icc_node qup1_core_master = {
.name = "qup1_core_master",
- .id = SC7280_MASTER_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SC7280_SLAVE_QUP_CORE_1 },
+ .link_nodes = { &qup1_core_slave },
};
static struct qcom_icc_node qnm_cnoc3_cnoc2 = {
.name = "qnm_cnoc3_cnoc2",
- .id = SC7280_MASTER_CNOC3_CNOC2,
.channels = 1,
.buswidth = 8,
.num_links = 44,
- .links = { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH,
- SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL,
- SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG,
- SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG,
- SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG,
- SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG,
- SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG,
- SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG,
- SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS,
- SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG,
- SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM,
- SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG,
- SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG,
- SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0,
- SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1,
- SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4,
- SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR,
- SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG,
- SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0,
- SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG,
- SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG,
- SC7280_SLAVE_CNOC_MNOC_CFG, SC7280_SLAVE_SNOC_CFG },
+ .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
+ &qhs_camera_cfg, &qhs_clk_ctl,
+ &qhs_compute_cfg, &qhs_cpr_cx,
+ &qhs_cpr_mx, &qhs_crypto0_cfg,
+ &qhs_cx_rdpm, &qhs_dcc_cfg,
+ &qhs_display_cfg, &qhs_gpuss_cfg,
+ &qhs_hwkm, &qhs_imem_cfg,
+ &qhs_ipa, &qhs_ipc_router,
+ &qhs_lpass_cfg, &qhs_mss_cfg,
+ &qhs_mx_rdpm, &qhs_pcie0_cfg,
+ &qhs_pcie1_cfg, &qhs_pdm,
+ &qhs_pimem_cfg, &qhs_pka_wrapper_cfg,
+ &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg,
+ &qhs_qspi, &qhs_qup0,
+ &qhs_qup1, &qhs_sdc1,
+ &qhs_sdc2, &qhs_sdc4,
+ &qhs_security, &qhs_tcsr,
+ &qhs_tlmm, &qhs_ufs_mem_cfg,
+ &qhs_usb2, &qhs_usb3_0,
+ &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
+ &qns_a1_noc_cfg, &qns_a2_noc_cfg,
+ &qns_mnoc_cfg, &qns_snoc_cfg },
};
static struct qcom_icc_node xm_qdss_dap = {
.name = "xm_qdss_dap",
- .id = SC7280_MASTER_QDSS_DAP,
.channels = 1,
.buswidth = 8,
.num_links = 45,
- .links = { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH,
- SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL,
- SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG,
- SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG,
- SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG,
- SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG,
- SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG,
- SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG,
- SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS,
- SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG,
- SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM,
- SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG,
- SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG,
- SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0,
- SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1,
- SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4,
- SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR,
- SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG,
- SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0,
- SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG,
- SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG,
- SC7280_SLAVE_CNOC2_CNOC3, SC7280_SLAVE_CNOC_MNOC_CFG,
- SC7280_SLAVE_SNOC_CFG },
+ .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
+ &qhs_camera_cfg, &qhs_clk_ctl,
+ &qhs_compute_cfg, &qhs_cpr_cx,
+ &qhs_cpr_mx, &qhs_crypto0_cfg,
+ &qhs_cx_rdpm, &qhs_dcc_cfg,
+ &qhs_display_cfg, &qhs_gpuss_cfg,
+ &qhs_hwkm, &qhs_imem_cfg,
+ &qhs_ipa, &qhs_ipc_router,
+ &qhs_lpass_cfg, &qhs_mss_cfg,
+ &qhs_mx_rdpm, &qhs_pcie0_cfg,
+ &qhs_pcie1_cfg, &qhs_pdm,
+ &qhs_pimem_cfg, &qhs_pka_wrapper_cfg,
+ &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg,
+ &qhs_qspi, &qhs_qup0,
+ &qhs_qup1, &qhs_sdc1,
+ &qhs_sdc2, &qhs_sdc4,
+ &qhs_security, &qhs_tcsr,
+ &qhs_tlmm, &qhs_ufs_mem_cfg,
+ &qhs_usb2, &qhs_usb3_0,
+ &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
+ &qns_a1_noc_cfg, &qns_a2_noc_cfg,
+ &qns_cnoc2_cnoc3, &qns_mnoc_cfg,
+ &qns_snoc_cfg },
};
static struct qcom_icc_node qnm_cnoc2_cnoc3 = {
.name = "qnm_cnoc2_cnoc3",
- .id = SC7280_MASTER_CNOC2_CNOC3,
.channels = 1,
.buswidth = 8,
.num_links = 9,
- .links = { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS,
- SC7280_SLAVE_CNOC_A2NOC, SC7280_SLAVE_DDRSS_CFG,
- SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM,
- SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM,
- SC7280_SLAVE_TCU },
+ .link_nodes = { &qhs_aoss, &qhs_apss,
+ &qns_cnoc_a2noc, &qns_ddrss_cfg,
+ &qxs_boot_imem, &qxs_imem,
+ &qxs_pimem, &xs_qdss_stm,
+ &xs_sys_tcu_cfg },
};
static struct qcom_icc_node qnm_gemnoc_cnoc = {
.name = "qnm_gemnoc_cnoc",
- .id = SC7280_MASTER_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
.num_links = 9,
- .links = { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS,
- SC7280_SLAVE_CNOC3_CNOC2, SC7280_SLAVE_DDRSS_CFG,
- SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM,
- SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM,
- SC7280_SLAVE_TCU },
+ .link_nodes = { &qhs_aoss, &qhs_apss,
+ &qns_cnoc3_cnoc2, &qns_ddrss_cfg,
+ &qxs_boot_imem, &qxs_imem,
+ &qxs_pimem, &xs_qdss_stm,
+ &xs_sys_tcu_cfg },
};
static struct qcom_icc_node qnm_gemnoc_pcie = {
.name = "qnm_gemnoc_pcie",
- .id = SC7280_MASTER_GEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 2,
- .links = { SC7280_SLAVE_PCIE_0, SC7280_SLAVE_PCIE_1 },
+ .link_nodes = { &xs_pcie_0, &xs_pcie_1 },
};
static struct qcom_icc_node qnm_cnoc_dc_noc = {
.name = "qnm_cnoc_dc_noc",
- .id = SC7280_MASTER_CNOC_DC_NOC,
.channels = 1,
.buswidth = 4,
.num_links = 2,
- .links = { SC7280_SLAVE_LLCC_CFG, SC7280_SLAVE_GEM_NOC_CFG },
+ .link_nodes = { &qhs_llcc, &qns_gemnoc },
};
static struct qcom_icc_node alm_gpu_tcu = {
.name = "alm_gpu_tcu",
- .id = SC7280_MASTER_GPU_TCU,
.channels = 1,
.buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0xd7000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ },
.num_links = 2,
- .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
- .id = SC7280_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0xd6000 },
+ .prio = 6,
+ .urg_fwd = 0,
+ },
.num_links = 2,
- .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_node chm_apps = {
.name = "chm_apps",
- .id = SC7280_MASTER_APPSS_PROC,
.channels = 1,
.buswidth = 32,
.num_links = 3,
- .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC,
- SC7280_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
};
static struct qcom_icc_node qnm_cmpnoc = {
.name = "qnm_cmpnoc",
- .id = SC7280_MASTER_COMPUTE_NOC,
.channels = 2,
.buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x21000, 0x61000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ },
.num_links = 2,
- .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_node qnm_gemnoc_cfg = {
.name = "qnm_gemnoc_cfg",
- .id = SC7280_MASTER_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 5,
- .links = { SC7280_SLAVE_MSS_PROC_MS_MPU_CFG, SC7280_SLAVE_MCDMA_MS_MPU_CFG,
- SC7280_SLAVE_SERVICE_GEM_NOC_1, SC7280_SLAVE_SERVICE_GEM_NOC_2,
- SC7280_SLAVE_SERVICE_GEM_NOC },
+ .link_nodes = { &qhs_mdsp_ms_mpu_cfg, &qhs_modem_ms_mpu_cfg,
+ &srvc_even_gemnoc, &srvc_odd_gemnoc,
+ &srvc_sys_gemnoc },
};
static struct qcom_icc_node qnm_gpu = {
.name = "qnm_gpu",
- .id = SC7280_MASTER_GFX3D,
.channels = 2,
.buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x22000, 0x62000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ },
.num_links = 2,
- .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
- .id = SC7280_MASTER_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x23000, 0x63000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ },
.num_links = 1,
- .links = { SC7280_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc },
};
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
- .id = SC7280_MASTER_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0xcf000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ },
.num_links = 2,
- .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
- .id = SC7280_MASTER_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
.num_links = 2,
- .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
- .id = SC7280_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0xd3000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ },
.num_links = 1,
- .links = { SC7280_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
- .id = SC7280_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0xd4000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ },
.num_links = 3,
- .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC,
- SC7280_SLAVE_MEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
};
static struct qcom_icc_node qhm_config_noc = {
.name = "qhm_config_noc",
- .id = SC7280_MASTER_CNOC_LPASS_AG_NOC,
.channels = 1,
.buswidth = 4,
.num_links = 6,
- .links = { SC7280_SLAVE_LPASS_CORE_CFG, SC7280_SLAVE_LPASS_LPI_CFG,
- SC7280_SLAVE_LPASS_MPU_CFG, SC7280_SLAVE_LPASS_TOP_CFG,
- SC7280_SLAVE_SERVICES_LPASS_AML_NOC, SC7280_SLAVE_SERVICE_LPASS_AG_NOC },
+ .link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi,
+ &qhs_lpass_mpu, &qhs_lpass_top,
+ &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = SC7280_MASTER_LLCC,
.channels = 2,
.buswidth = 4,
.num_links = 1,
- .links = { SC7280_SLAVE_EBI1 },
+ .link_nodes = { &ebi },
};
static struct qcom_icc_node qnm_mnoc_cfg = {
.name = "qnm_mnoc_cfg",
- .id = SC7280_MASTER_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SC7280_SLAVE_SERVICE_MNOC },
+ .link_nodes = { &srvc_mnoc },
};
static struct qcom_icc_node qnm_video0 = {
.name = "qnm_video0",
- .id = SC7280_MASTER_VIDEO_P0,
.channels = 1,
.buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x14000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ },
.num_links = 1,
- .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_node qnm_video_cpu = {
.name = "qnm_video_cpu",
- .id = SC7280_MASTER_VIDEO_PROC,
.channels = 1,
.buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x15000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ },
.num_links = 1,
- .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_node qxm_camnoc_hf = {
.name = "qxm_camnoc_hf",
- .id = SC7280_MASTER_CAMNOC_HF,
.channels = 2,
.buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x10000, 0x10180 },
+ .prio = 0,
+ .urg_fwd = 1,
+ },
.num_links = 1,
- .links = { SC7280_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf },
};
static struct qcom_icc_node qxm_camnoc_icp = {
.name = "qxm_camnoc_icp",
- .id = SC7280_MASTER_CAMNOC_ICP,
.channels = 1,
.buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x11000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ },
.num_links = 1,
- .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_node qxm_camnoc_sf = {
.name = "qxm_camnoc_sf",
- .id = SC7280_MASTER_CAMNOC_SF,
.channels = 1,
.buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x12000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ },
.num_links = 1,
- .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_node qxm_mdp0 = {
.name = "qxm_mdp0",
- .id = SC7280_MASTER_MDP0,
.channels = 1,
.buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x16000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ },
.num_links = 1,
- .links = { SC7280_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf },
};
static struct qcom_icc_node qhm_nsp_noc_config = {
.name = "qhm_nsp_noc_config",
- .id = SC7280_MASTER_CDSP_NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SC7280_SLAVE_SERVICE_NSP_NOC },
+ .link_nodes = { &service_nsp_noc },
};
static struct qcom_icc_node qxm_nsp = {
.name = "qxm_nsp",
- .id = SC7280_MASTER_CDSP_PROC,
.channels = 2,
.buswidth = 32,
.num_links = 1,
- .links = { SC7280_SLAVE_CDSP_MEM_NOC },
+ .link_nodes = { &qns_nsp_gemnoc },
};
static struct qcom_icc_node qnm_aggre1_noc = {
.name = "qnm_aggre1_noc",
- .id = SC7280_MASTER_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
- .links = { SC7280_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_node qnm_aggre2_noc = {
.name = "qnm_aggre2_noc",
- .id = SC7280_MASTER_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
- .links = { SC7280_SLAVE_SNOC_GEM_NOC_SF },
+ .link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_node qnm_snoc_cfg = {
.name = "qnm_snoc_cfg",
- .id = SC7280_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SC7280_SLAVE_SERVICE_SNOC },
+ .link_nodes = { &srvc_snoc },
};
static struct qcom_icc_node qxm_pimem = {
.name = "qxm_pimem",
- .id = SC7280_MASTER_PIMEM,
.channels = 1,
.buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x8000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ },
.num_links = 1,
- .links = { SC7280_SLAVE_SNOC_GEM_NOC_GC },
+ .link_nodes = { &qns_gemnoc_gc },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
- .id = SC7280_MASTER_GIC,
.channels = 1,
.buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0xa000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ },
.num_links = 1,
- .links = { SC7280_SLAVE_SNOC_GEM_NOC_GC },
+ .link_nodes = { &qns_gemnoc_gc },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
- .id = SC7280_SLAVE_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
- .links = { SC7280_MASTER_A1NOC_SNOC },
+ .link_nodes = { &qnm_aggre1_noc },
};
static struct qcom_icc_node srvc_aggre1_noc = {
.name = "srvc_aggre1_noc",
- .id = SC7280_SLAVE_SERVICE_A1NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qns_a2noc_snoc = {
.name = "qns_a2noc_snoc",
- .id = SC7280_SLAVE_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
- .links = { SC7280_MASTER_A2NOC_SNOC },
+ .link_nodes = { &qnm_aggre2_noc },
};
static struct qcom_icc_node qns_pcie_mem_noc = {
.name = "qns_pcie_mem_noc",
- .id = SC7280_SLAVE_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
- .links = { SC7280_MASTER_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qnm_pcie },
};
static struct qcom_icc_node srvc_aggre2_noc = {
.name = "srvc_aggre2_noc",
- .id = SC7280_SLAVE_SERVICE_A2NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
- .id = SC7280_SLAVE_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qup1_core_slave = {
.name = "qup1_core_slave",
- .id = SC7280_SLAVE_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_ahb2phy0 = {
.name = "qhs_ahb2phy0",
- .id = SC7280_SLAVE_AHB2PHY_SOUTH,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_ahb2phy1 = {
.name = "qhs_ahb2phy1",
- .id = SC7280_SLAVE_AHB2PHY_NORTH,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_camera_cfg = {
.name = "qhs_camera_cfg",
- .id = SC7280_SLAVE_CAMERA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = SC7280_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_compute_cfg = {
.name = "qhs_compute_cfg",
- .id = SC7280_SLAVE_CDSP_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SC7280_MASTER_CDSP_NOC_CFG },
+ .link_nodes = { &qhm_nsp_noc_config },
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
- .id = SC7280_SLAVE_RBCPR_CX_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_cpr_mx = {
.name = "qhs_cpr_mx",
- .id = SC7280_SLAVE_RBCPR_MX_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
- .id = SC7280_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_cx_rdpm = {
.name = "qhs_cx_rdpm",
- .id = SC7280_SLAVE_CX_RDPM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_dcc_cfg = {
.name = "qhs_dcc_cfg",
- .id = SC7280_SLAVE_DCC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_display_cfg = {
.name = "qhs_display_cfg",
- .id = SC7280_SLAVE_DISPLAY_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_gpuss_cfg = {
.name = "qhs_gpuss_cfg",
- .id = SC7280_SLAVE_GFX3D_CFG,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
};
static struct qcom_icc_node qhs_hwkm = {
.name = "qhs_hwkm",
- .id = SC7280_SLAVE_HWKM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = SC7280_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
- .id = SC7280_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_ipc_router = {
.name = "qhs_ipc_router",
- .id = SC7280_SLAVE_IPC_ROUTER_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_lpass_cfg = {
.name = "qhs_lpass_cfg",
- .id = SC7280_SLAVE_LPASS,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SC7280_MASTER_CNOC_LPASS_AG_NOC },
+ .link_nodes = { &qhm_config_noc },
};
static struct qcom_icc_node qhs_mss_cfg = {
.name = "qhs_mss_cfg",
- .id = SC7280_SLAVE_CNOC_MSS,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_mx_rdpm = {
.name = "qhs_mx_rdpm",
- .id = SC7280_SLAVE_MX_RDPM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_pcie0_cfg = {
.name = "qhs_pcie0_cfg",
- .id = SC7280_SLAVE_PCIE_0_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_pcie1_cfg = {
.name = "qhs_pcie1_cfg",
- .id = SC7280_SLAVE_PCIE_1_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
- .id = SC7280_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_pimem_cfg = {
.name = "qhs_pimem_cfg",
- .id = SC7280_SLAVE_PIMEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_pka_wrapper_cfg = {
.name = "qhs_pka_wrapper_cfg",
- .id = SC7280_SLAVE_PKA_WRAPPER_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_pmu_wrapper_cfg = {
.name = "qhs_pmu_wrapper_cfg",
- .id = SC7280_SLAVE_PMU_WRAPPER_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = SC7280_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_qspi = {
.name = "qhs_qspi",
- .id = SC7280_SLAVE_QSPI_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_qup0 = {
.name = "qhs_qup0",
- .id = SC7280_SLAVE_QUP_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_qup1 = {
.name = "qhs_qup1",
- .id = SC7280_SLAVE_QUP_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_sdc1 = {
.name = "qhs_sdc1",
- .id = SC7280_SLAVE_SDCC_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_sdc2 = {
.name = "qhs_sdc2",
- .id = SC7280_SLAVE_SDCC_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_sdc4 = {
.name = "qhs_sdc4",
- .id = SC7280_SLAVE_SDCC_4,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_security = {
.name = "qhs_security",
- .id = SC7280_SLAVE_SECURITY,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = SC7280_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
- .id = SC7280_SLAVE_TLMM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_ufs_mem_cfg = {
.name = "qhs_ufs_mem_cfg",
- .id = SC7280_SLAVE_UFS_MEM_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_usb2 = {
.name = "qhs_usb2",
- .id = SC7280_SLAVE_USB2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_usb3_0 = {
.name = "qhs_usb3_0",
- .id = SC7280_SLAVE_USB3_0,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_venus_cfg = {
.name = "qhs_venus_cfg",
- .id = SC7280_SLAVE_VENUS_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
.name = "qhs_vsense_ctrl_cfg",
- .id = SC7280_SLAVE_VSENSE_CTRL_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qns_a1_noc_cfg = {
.name = "qns_a1_noc_cfg",
- .id = SC7280_SLAVE_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SC7280_MASTER_A1NOC_CFG },
+ .link_nodes = { &qnm_a1noc_cfg },
};
static struct qcom_icc_node qns_a2_noc_cfg = {
.name = "qns_a2_noc_cfg",
- .id = SC7280_SLAVE_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SC7280_MASTER_A2NOC_CFG },
+ .link_nodes = { &qnm_a2noc_cfg },
};
static struct qcom_icc_node qns_cnoc2_cnoc3 = {
.name = "qns_cnoc2_cnoc3",
- .id = SC7280_SLAVE_CNOC2_CNOC3,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SC7280_MASTER_CNOC2_CNOC3 },
+ .link_nodes = { &qnm_cnoc2_cnoc3 },
};
static struct qcom_icc_node qns_mnoc_cfg = {
.name = "qns_mnoc_cfg",
- .id = SC7280_SLAVE_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SC7280_MASTER_CNOC_MNOC_CFG },
+ .link_nodes = { &qnm_mnoc_cfg },
};
static struct qcom_icc_node qns_snoc_cfg = {
.name = "qns_snoc_cfg",
- .id = SC7280_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SC7280_MASTER_SNOC_CFG },
+ .link_nodes = { &qnm_snoc_cfg },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = SC7280_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
- .id = SC7280_SLAVE_APPSS,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
};
static struct qcom_icc_node qns_cnoc3_cnoc2 = {
.name = "qns_cnoc3_cnoc2",
- .id = SC7280_SLAVE_CNOC3_CNOC2,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SC7280_MASTER_CNOC3_CNOC2 },
+ .link_nodes = { &qnm_cnoc3_cnoc2 },
};
static struct qcom_icc_node qns_cnoc_a2noc = {
.name = "qns_cnoc_a2noc",
- .id = SC7280_SLAVE_CNOC_A2NOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SC7280_MASTER_CNOC_A2NOC },
+ .link_nodes = { &qnm_cnoc_datapath },
};
static struct qcom_icc_node qns_ddrss_cfg = {
.name = "qns_ddrss_cfg",
- .id = SC7280_SLAVE_DDRSS_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SC7280_MASTER_CNOC_DC_NOC },
+ .link_nodes = { &qnm_cnoc_dc_noc },
};
static struct qcom_icc_node qxs_boot_imem = {
.name = "qxs_boot_imem",
- .id = SC7280_SLAVE_BOOT_IMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = SC7280_SLAVE_IMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
};
static struct qcom_icc_node qxs_pimem = {
.name = "qxs_pimem",
- .id = SC7280_SLAVE_PIMEM,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
};
static struct qcom_icc_node xs_pcie_0 = {
.name = "xs_pcie_0",
- .id = SC7280_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
};
static struct qcom_icc_node xs_pcie_1 = {
.name = "xs_pcie_1",
- .id = SC7280_SLAVE_PCIE_1,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = SC7280_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = SC7280_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
- .num_links = 0,
};
static struct qcom_icc_node qhs_llcc = {
.name = "qhs_llcc",
- .id = SC7280_SLAVE_LLCC_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qns_gemnoc = {
.name = "qns_gemnoc",
- .id = SC7280_SLAVE_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SC7280_MASTER_GEM_NOC_CFG },
+ .link_nodes = { &qnm_gemnoc_cfg },
};
static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
.name = "qhs_mdsp_ms_mpu_cfg",
- .id = SC7280_SLAVE_MSS_PROC_MS_MPU_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_modem_ms_mpu_cfg = {
.name = "qhs_modem_ms_mpu_cfg",
- .id = SC7280_SLAVE_MCDMA_MS_MPU_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qns_gem_noc_cnoc = {
.name = "qns_gem_noc_cnoc",
- .id = SC7280_SLAVE_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
- .links = { SC7280_MASTER_GEM_NOC_CNOC },
+ .link_nodes = { &qnm_gemnoc_cnoc },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = SC7280_SLAVE_LLCC,
.channels = 2,
.buswidth = 16,
.num_links = 1,
- .links = { SC7280_MASTER_LLCC },
+ .link_nodes = { &llcc_mc },
};
static struct qcom_icc_node qns_pcie = {
.name = "qns_pcie",
- .id = SC7280_SLAVE_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SC7280_MASTER_GEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qnm_gemnoc_pcie },
};
static struct qcom_icc_node srvc_even_gemnoc = {
.name = "srvc_even_gemnoc",
- .id = SC7280_SLAVE_SERVICE_GEM_NOC_1,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node srvc_odd_gemnoc = {
.name = "srvc_odd_gemnoc",
- .id = SC7280_SLAVE_SERVICE_GEM_NOC_2,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node srvc_sys_gemnoc = {
.name = "srvc_sys_gemnoc",
- .id = SC7280_SLAVE_SERVICE_GEM_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_lpass_core = {
.name = "qhs_lpass_core",
- .id = SC7280_SLAVE_LPASS_CORE_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_lpass_lpi = {
.name = "qhs_lpass_lpi",
- .id = SC7280_SLAVE_LPASS_LPI_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_lpass_mpu = {
.name = "qhs_lpass_mpu",
- .id = SC7280_SLAVE_LPASS_MPU_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qhs_lpass_top = {
.name = "qhs_lpass_top",
- .id = SC7280_SLAVE_LPASS_TOP_CFG,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node srvc_niu_aml_noc = {
.name = "srvc_niu_aml_noc",
- .id = SC7280_SLAVE_SERVICES_LPASS_AML_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node srvc_niu_lpass_agnoc = {
.name = "srvc_niu_lpass_agnoc",
- .id = SC7280_SLAVE_SERVICE_LPASS_AG_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = SC7280_SLAVE_EBI1,
.channels = 2,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qns_mem_noc_hf = {
.name = "qns_mem_noc_hf",
- .id = SC7280_SLAVE_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
.num_links = 1,
- .links = { SC7280_MASTER_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_hf },
};
static struct qcom_icc_node qns_mem_noc_sf = {
.name = "qns_mem_noc_sf",
- .id = SC7280_SLAVE_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SC7280_MASTER_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_sf },
};
static struct qcom_icc_node srvc_mnoc = {
.name = "srvc_mnoc",
- .id = SC7280_SLAVE_SERVICE_MNOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qns_nsp_gemnoc = {
.name = "qns_nsp_gemnoc",
- .id = SC7280_SLAVE_CDSP_MEM_NOC,
.channels = 2,
.buswidth = 32,
.num_links = 1,
- .links = { SC7280_MASTER_COMPUTE_NOC },
+ .link_nodes = { &qnm_cmpnoc },
};
static struct qcom_icc_node service_nsp_noc = {
.name = "service_nsp_noc",
- .id = SC7280_SLAVE_SERVICE_NSP_NOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_node qns_gemnoc_gc = {
.name = "qns_gemnoc_gc",
- .id = SC7280_SLAVE_SNOC_GEM_NOC_GC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SC7280_MASTER_SNOC_GC_MEM_NOC },
+ .link_nodes = { &qnm_snoc_gc },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
- .id = SC7280_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 16,
.num_links = 1,
- .links = { SC7280_MASTER_SNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_snoc_sf },
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
- .id = SC7280_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
- .num_links = 0,
};
static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
+ .enable_mask = BIT(3),
.num_nodes = 1,
.nodes = { &ebi },
};
@@ -1476,13 +1587,13 @@ static struct qcom_icc_bcm bcm_sn14 = {
.nodes = { &qns_pcie_mem_noc },
};
-static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
+static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
&bcm_sn5,
&bcm_sn6,
&bcm_sn14,
};
-static struct qcom_icc_node *aggre1_noc_nodes[] = {
+static struct qcom_icc_node * const aggre1_noc_nodes[] = {
[MASTER_QSPI_0] = &qhm_qspi,
[MASTER_QUP_0] = &qhm_qup0,
[MASTER_QUP_1] = &qhm_qup1,
@@ -1500,18 +1611,36 @@ static struct qcom_icc_node *aggre1_noc_nodes[] = {
[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
};
-static struct qcom_icc_desc sc7280_aggre1_noc = {
+static const struct regmap_config sc7280_aggre1_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x1c080,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc sc7280_aggre1_noc = {
+ .config = &sc7280_aggre1_noc_regmap_config,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
+ .qos_requires_clocks = true,
};
-static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
+static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
&bcm_ce0,
};
-static struct qcom_icc_node *aggre2_noc_nodes[] = {
+static const struct regmap_config sc7280_aggre2_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x2b080,
+ .fast_io = true,
+};
+
+static struct qcom_icc_node * const aggre2_noc_nodes[] = {
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
[MASTER_A2NOC_CFG] = &qnm_a2noc_cfg,
[MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath,
@@ -1522,38 +1651,40 @@ static struct qcom_icc_node *aggre2_noc_nodes[] = {
[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
};
-static struct qcom_icc_desc sc7280_aggre2_noc = {
+static const struct qcom_icc_desc sc7280_aggre2_noc = {
+ .config = &sc7280_aggre2_noc_regmap_config,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
+ .qos_requires_clocks = true,
};
-static struct qcom_icc_bcm *clk_virt_bcms[] = {
+static struct qcom_icc_bcm * const clk_virt_bcms[] = {
&bcm_qup0,
&bcm_qup1,
};
-static struct qcom_icc_node *clk_virt_nodes[] = {
+static struct qcom_icc_node * const clk_virt_nodes[] = {
[MASTER_QUP_CORE_0] = &qup0_core_master,
[MASTER_QUP_CORE_1] = &qup1_core_master,
[SLAVE_QUP_CORE_0] = &qup0_core_slave,
[SLAVE_QUP_CORE_1] = &qup1_core_slave,
};
-static struct qcom_icc_desc sc7280_clk_virt = {
+static const struct qcom_icc_desc sc7280_clk_virt = {
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
.num_bcms = ARRAY_SIZE(clk_virt_bcms),
};
-static struct qcom_icc_bcm *cnoc2_bcms[] = {
+static struct qcom_icc_bcm * const cnoc2_bcms[] = {
&bcm_cn1,
&bcm_cn2,
};
-static struct qcom_icc_node *cnoc2_nodes[] = {
+static struct qcom_icc_node * const cnoc2_nodes[] = {
[MASTER_CNOC3_CNOC2] = &qnm_cnoc3_cnoc2,
[MASTER_QDSS_DAP] = &xm_qdss_dap,
[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
@@ -1603,21 +1734,30 @@ static struct qcom_icc_node *cnoc2_nodes[] = {
[SLAVE_SNOC_CFG] = &qns_snoc_cfg,
};
-static struct qcom_icc_desc sc7280_cnoc2 = {
+static const struct regmap_config sc7280_cnoc2_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x1000,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc sc7280_cnoc2 = {
+ .config = &sc7280_cnoc2_regmap_config,
.nodes = cnoc2_nodes,
.num_nodes = ARRAY_SIZE(cnoc2_nodes),
.bcms = cnoc2_bcms,
.num_bcms = ARRAY_SIZE(cnoc2_bcms),
};
-static struct qcom_icc_bcm *cnoc3_bcms[] = {
+static struct qcom_icc_bcm * const cnoc3_bcms[] = {
&bcm_cn0,
&bcm_cn1,
&bcm_sn3,
&bcm_sn4,
};
-static struct qcom_icc_node *cnoc3_nodes[] = {
+static struct qcom_icc_node * const cnoc3_nodes[] = {
[MASTER_CNOC2_CNOC3] = &qnm_cnoc2_cnoc3,
[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
@@ -1635,37 +1775,55 @@ static struct qcom_icc_node *cnoc3_nodes[] = {
[SLAVE_TCU] = &xs_sys_tcu_cfg,
};
-static struct qcom_icc_desc sc7280_cnoc3 = {
+static const struct regmap_config sc7280_cnoc3_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x1000,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc sc7280_cnoc3 = {
+ .config = &sc7280_cnoc3_regmap_config,
.nodes = cnoc3_nodes,
.num_nodes = ARRAY_SIZE(cnoc3_nodes),
.bcms = cnoc3_bcms,
.num_bcms = ARRAY_SIZE(cnoc3_bcms),
};
-static struct qcom_icc_bcm *dc_noc_bcms[] = {
+static struct qcom_icc_bcm * const dc_noc_bcms[] = {
};
-static struct qcom_icc_node *dc_noc_nodes[] = {
+static struct qcom_icc_node * const dc_noc_nodes[] = {
[MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
[SLAVE_LLCC_CFG] = &qhs_llcc,
[SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
};
-static struct qcom_icc_desc sc7280_dc_noc = {
+static const struct regmap_config sc7280_dc_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x5080,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc sc7280_dc_noc = {
+ .config = &sc7280_dc_noc_regmap_config,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
.num_bcms = ARRAY_SIZE(dc_noc_bcms),
};
-static struct qcom_icc_bcm *gem_noc_bcms[] = {
+static struct qcom_icc_bcm * const gem_noc_bcms[] = {
&bcm_sh0,
&bcm_sh2,
&bcm_sh3,
&bcm_sh4,
};
-static struct qcom_icc_node *gem_noc_nodes[] = {
+static struct qcom_icc_node * const gem_noc_nodes[] = {
[MASTER_GPU_TCU] = &alm_gpu_tcu,
[MASTER_SYS_TCU] = &alm_sys_tcu,
[MASTER_APPSS_PROC] = &chm_apps,
@@ -1687,17 +1845,26 @@ static struct qcom_icc_node *gem_noc_nodes[] = {
[SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
};
-static struct qcom_icc_desc sc7280_gem_noc = {
+static const struct regmap_config sc7280_gem_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xe2200,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc sc7280_gem_noc = {
+ .config = &sc7280_gem_noc_regmap_config,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
};
-static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = {
+static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
};
-static struct qcom_icc_node *lpass_ag_noc_nodes[] = {
+static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
[MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
[SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
[SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
@@ -1707,38 +1874,56 @@ static struct qcom_icc_node *lpass_ag_noc_nodes[] = {
[SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
};
-static struct qcom_icc_desc sc7280_lpass_ag_noc = {
+static const struct regmap_config sc7280_lpass_ag_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xf080,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc sc7280_lpass_ag_noc = {
+ .config = &sc7280_lpass_ag_noc_regmap_config,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
.num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
};
-static struct qcom_icc_bcm *mc_virt_bcms[] = {
+static struct qcom_icc_bcm * const mc_virt_bcms[] = {
&bcm_acv,
&bcm_mc0,
};
-static struct qcom_icc_node *mc_virt_nodes[] = {
+static struct qcom_icc_node * const mc_virt_nodes[] = {
[MASTER_LLCC] = &llcc_mc,
[SLAVE_EBI1] = &ebi,
};
-static struct qcom_icc_desc sc7280_mc_virt = {
+static const struct regmap_config sc7280_mc_virt_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x4,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc sc7280_mc_virt = {
+ .config = &sc7280_mc_virt_regmap_config,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
};
-static struct qcom_icc_bcm *mmss_noc_bcms[] = {
+static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
&bcm_mm0,
&bcm_mm1,
&bcm_mm4,
&bcm_mm5,
};
-static struct qcom_icc_node *mmss_noc_nodes[] = {
+static struct qcom_icc_node * const mmss_noc_nodes[] = {
[MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg,
[MASTER_VIDEO_P0] = &qnm_video0,
[MASTER_VIDEO_PROC] = &qnm_video_cpu,
@@ -1751,40 +1936,58 @@ static struct qcom_icc_node *mmss_noc_nodes[] = {
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
};
-static struct qcom_icc_desc sc7280_mmss_noc = {
+static const struct regmap_config sc7280_mmss_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x1e080,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc sc7280_mmss_noc = {
+ .config = &sc7280_mmss_noc_regmap_config,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
};
-static struct qcom_icc_bcm *nsp_noc_bcms[] = {
+static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
&bcm_co0,
&bcm_co3,
};
-static struct qcom_icc_node *nsp_noc_nodes[] = {
+static struct qcom_icc_node * const nsp_noc_nodes[] = {
[MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
[MASTER_CDSP_PROC] = &qxm_nsp,
[SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
[SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
};
-static struct qcom_icc_desc sc7280_nsp_noc = {
+static const struct regmap_config sc7280_nsp_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x10000,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc sc7280_nsp_noc = {
+ .config = &sc7280_nsp_noc_regmap_config,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
.bcms = nsp_noc_bcms,
.num_bcms = ARRAY_SIZE(nsp_noc_bcms),
};
-static struct qcom_icc_bcm *system_noc_bcms[] = {
+static struct qcom_icc_bcm * const system_noc_bcms[] = {
&bcm_sn0,
&bcm_sn2,
&bcm_sn7,
&bcm_sn8,
};
-static struct qcom_icc_node *system_noc_nodes[] = {
+static struct qcom_icc_node * const system_noc_nodes[] = {
[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
[MASTER_SNOC_CFG] = &qnm_snoc_cfg,
@@ -1795,105 +1998,22 @@ static struct qcom_icc_node *system_noc_nodes[] = {
[SLAVE_SERVICE_SNOC] = &srvc_snoc,
};
-static struct qcom_icc_desc sc7280_system_noc = {
+static const struct regmap_config sc7280_system_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x15480,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc sc7280_system_noc = {
+ .config = &sc7280_system_noc_regmap_config,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
.num_bcms = ARRAY_SIZE(system_noc_bcms),
};
-static int qnoc_probe(struct platform_device *pdev)
-{
- const struct qcom_icc_desc *desc;
- struct icc_onecell_data *data;
- struct icc_provider *provider;
- struct qcom_icc_node **qnodes;
- struct qcom_icc_provider *qp;
- struct icc_node *node;
- size_t num_nodes, i;
- int ret;
-
- desc = device_get_match_data(&pdev->dev);
- if (!desc)
- return -EINVAL;
-
- qnodes = desc->nodes;
- num_nodes = desc->num_nodes;
-
- qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
- if (!qp)
- return -ENOMEM;
-
- data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
- if (!data)
- return -ENOMEM;
-
- provider = &qp->provider;
- provider->dev = &pdev->dev;
- provider->set = qcom_icc_set;
- provider->pre_aggregate = qcom_icc_pre_aggregate;
- provider->aggregate = qcom_icc_aggregate;
- provider->xlate_extended = qcom_icc_xlate_extended;
- INIT_LIST_HEAD(&provider->nodes);
- provider->data = data;
-
- qp->dev = &pdev->dev;
- qp->bcms = desc->bcms;
- qp->num_bcms = desc->num_bcms;
-
- qp->voter = of_bcm_voter_get(qp->dev, NULL);
- if (IS_ERR(qp->voter))
- return PTR_ERR(qp->voter);
-
- ret = icc_provider_add(provider);
- if (ret) {
- dev_err(&pdev->dev, "error adding interconnect provider\n");
- return ret;
- }
-
- for (i = 0; i < qp->num_bcms; i++)
- qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
-
- for (i = 0; i < num_nodes; i++) {
- size_t j;
-
- if (!qnodes[i])
- continue;
-
- node = icc_node_create(qnodes[i]->id);
- if (IS_ERR(node)) {
- ret = PTR_ERR(node);
- goto err;
- }
-
- node->name = qnodes[i]->name;
- node->data = qnodes[i];
- icc_node_add(node, provider);
-
- for (j = 0; j < qnodes[i]->num_links; j++)
- icc_link_create(node, qnodes[i]->links[j]);
-
- data->nodes[i] = node;
- }
- data->num_nodes = num_nodes;
-
- platform_set_drvdata(pdev, qp);
-
- return 0;
-err:
- icc_nodes_remove(provider);
- icc_provider_del(provider);
- return ret;
-}
-
-static int qnoc_remove(struct platform_device *pdev)
-{
- struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
-
- icc_nodes_remove(&qp->provider);
- return icc_provider_del(&qp->provider);
-}
-
static const struct of_device_id qnoc_of_match[] = {
{ .compatible = "qcom,sc7280-aggre1-noc",
.data = &sc7280_aggre1_noc},
@@ -1924,8 +2044,8 @@ static const struct of_device_id qnoc_of_match[] = {
MODULE_DEVICE_TABLE(of, qnoc_of_match);
static struct platform_driver qnoc_driver = {
- .probe = qnoc_probe,
- .remove = qnoc_remove,
+ .probe = qcom_icc_rpmh_probe,
+ .remove = qcom_icc_rpmh_remove,
.driver = {
.name = "qnoc-sc7280",
.of_match_table = qnoc_of_match,
generated by cgit (git 2.34.1) at 2025-12-25 04:52:10 +0000