diff options
Diffstat (limited to 'drivers/interconnect')
75 files changed, 20187 insertions, 9384 deletions
diff --git a/drivers/interconnect/core.c b/drivers/interconnect/core.c index 7e9b996b47c8..6cc979b26151 100644 --- a/drivers/interconnect/core.c +++ b/drivers/interconnect/core.c @@ -20,6 +20,8 @@ #include "internal.h" +#define ICC_DYN_ID_START 100000 + #define CREATE_TRACE_POINTS #include "trace.h" @@ -383,7 +385,7 @@ struct icc_node_data *of_icc_get_from_provider(const struct of_phandle_args *spe mutex_lock(&icc_lock); list_for_each_entry(provider, &icc_providers, provider_list) { - if (provider->dev->of_node == spec->np) { + if (device_match_of_node(provider->dev, spec->np)) { if (provider->xlate_extended) { data = provider->xlate_extended(spec, provider->data); if (!IS_ERR(data)) { @@ -808,7 +810,7 @@ void icc_put(struct icc_path *path) mutex_unlock(&icc_bw_lock); mutex_unlock(&icc_lock); - kfree_const(path->name); + kfree(path->name); kfree(path); } EXPORT_SYMBOL_GPL(icc_put); @@ -817,6 +819,9 @@ static struct icc_node *icc_node_create_nolock(int id) { struct icc_node *node; + if (id >= ICC_DYN_ID_START) + return ERR_PTR(-EINVAL); + /* check if node already exists */ node = node_find(id); if (node) @@ -826,7 +831,12 @@ static struct icc_node *icc_node_create_nolock(int id) if (!node) return ERR_PTR(-ENOMEM); - id = idr_alloc(&icc_idr, node, id, id + 1, GFP_KERNEL); + /* dynamic id allocation */ + if (id == ICC_ALLOC_DYN_ID) + id = idr_alloc(&icc_idr, node, ICC_DYN_ID_START, 0, GFP_KERNEL); + else + id = idr_alloc(&icc_idr, node, id, id + 1, GFP_KERNEL); + if (id < 0) { WARN(1, "%s: couldn't get idr\n", __func__); kfree(node); @@ -839,6 +849,25 @@ static struct icc_node *icc_node_create_nolock(int id) } /** + * icc_node_create_dyn() - create a node with dynamic id + * + * Return: icc_node pointer on success, or ERR_PTR() on error + */ +struct icc_node *icc_node_create_dyn(void) +{ + struct icc_node *node; + + mutex_lock(&icc_lock); + + node = icc_node_create_nolock(ICC_ALLOC_DYN_ID); + + mutex_unlock(&icc_lock); + + return node; +} +EXPORT_SYMBOL_GPL(icc_node_create_dyn); + +/** * icc_node_create() - create a node * @id: node id * @@ -880,11 +909,86 @@ void icc_node_destroy(int id) return; kfree(node->links); + if (node->id >= ICC_DYN_ID_START) + kfree(node->name); kfree(node); } EXPORT_SYMBOL_GPL(icc_node_destroy); /** + * icc_node_set_name() - set node name + * @node: node + * @provider: node provider + * @name: node name + * + * Return: 0 on success, or -ENOMEM on allocation failure + */ +int icc_node_set_name(struct icc_node *node, const struct icc_provider *provider, const char *name) +{ + if (node->id >= ICC_DYN_ID_START) { + node->name = kasprintf(GFP_KERNEL, "%s@%s", name, + dev_name(provider->dev)); + if (!node->name) + return -ENOMEM; + } else { + node->name = name; + } + + return 0; +} +EXPORT_SYMBOL_GPL(icc_node_set_name); + +/** + * icc_link_nodes() - create link between two nodes + * @src_node: source node + * @dst_node: destination node + * + * Create a link between two nodes. The nodes might belong to different + * interconnect providers and the @dst_node might not exist (if the + * provider driver has not probed yet). So just create the @dst_node + * and when the actual provider driver is probed, the rest of the node + * data is filled. + * + * Return: 0 on success, or an error code otherwise + */ +int icc_link_nodes(struct icc_node *src_node, struct icc_node **dst_node) +{ + struct icc_node **new; + int ret = 0; + + if (!src_node->provider) + return -EINVAL; + + mutex_lock(&icc_lock); + + if (!*dst_node) { + *dst_node = icc_node_create_nolock(ICC_ALLOC_DYN_ID); + + if (IS_ERR(*dst_node)) { + ret = PTR_ERR(*dst_node); + goto out; + } + } + + new = krealloc(src_node->links, + (src_node->num_links + 1) * sizeof(*src_node->links), + GFP_KERNEL); + if (!new) { + ret = -ENOMEM; + goto out; + } + + src_node->links = new; + src_node->links[src_node->num_links++] = *dst_node; + +out: + mutex_unlock(&icc_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(icc_link_nodes); + +/** * icc_link_create() - create a link between two nodes * @node: source node id * @dst_id: destination node id @@ -1081,7 +1185,7 @@ static int of_count_icc_providers(struct device_node *np) int count = 0; for_each_available_child_of_node(np, child) { - if (of_property_read_bool(child, "#interconnect-cells") && + if (of_property_present(child, "#interconnect-cells") && likely(!of_match_node(ignore_list, child))) count++; count += of_count_icc_providers(child); diff --git a/drivers/interconnect/debugfs-client.c b/drivers/interconnect/debugfs-client.c index bc3fd8a7b9eb..778deeb4a7e8 100644 --- a/drivers/interconnect/debugfs-client.c +++ b/drivers/interconnect/debugfs-client.c @@ -117,7 +117,12 @@ static int icc_commit_set(void *data, u64 val) mutex_lock(&debugfs_lock); - if (IS_ERR_OR_NULL(cur_path)) { + if (!cur_path) { + ret = -EINVAL; + goto out; + } + + if (IS_ERR(cur_path)) { ret = PTR_ERR(cur_path); goto out; } diff --git a/drivers/interconnect/icc-clk.c b/drivers/interconnect/icc-clk.c index b956e4050f38..93c030608d3e 100644 --- a/drivers/interconnect/icc-clk.c +++ b/drivers/interconnect/icc-clk.c @@ -116,6 +116,12 @@ struct icc_provider *icc_clk_register(struct device *dev, } node->name = devm_kasprintf(dev, GFP_KERNEL, "%s_master", data[i].name); + if (!node->name) { + icc_node_destroy(node->id); + ret = -ENOMEM; + goto err; + } + node->data = &qp->clocks[i]; icc_node_add(node, provider); /* link to the next node, slave */ @@ -129,6 +135,12 @@ struct icc_provider *icc_clk_register(struct device *dev, } node->name = devm_kasprintf(dev, GFP_KERNEL, "%s_slave", data[i].name); + if (!node->name) { + icc_node_destroy(node->id); + ret = -ENOMEM; + goto err; + } + /* no data for slave node */ icc_node_add(node, provider); onecell->nodes[j++] = node; diff --git a/drivers/interconnect/imx/imx8mm.c b/drivers/interconnect/imx/imx8mm.c index a36aaaf106ae..efed12d635c1 100644 --- a/drivers/interconnect/imx/imx8mm.c +++ b/drivers/interconnect/imx/imx8mm.c @@ -88,7 +88,7 @@ static int imx8mm_icc_probe(struct platform_device *pdev) static struct platform_driver imx8mm_icc_driver = { .probe = imx8mm_icc_probe, - .remove_new = imx_icc_unregister, + .remove = imx_icc_unregister, .driver = { .name = "imx8mm-interconnect", }, diff --git a/drivers/interconnect/imx/imx8mn.c b/drivers/interconnect/imx/imx8mn.c index 2a97c74e875b..535fae791f2e 100644 --- a/drivers/interconnect/imx/imx8mn.c +++ b/drivers/interconnect/imx/imx8mn.c @@ -77,7 +77,7 @@ static int imx8mn_icc_probe(struct platform_device *pdev) static struct platform_driver imx8mn_icc_driver = { .probe = imx8mn_icc_probe, - .remove_new = imx_icc_unregister, + .remove = imx_icc_unregister, .driver = { .name = "imx8mn-interconnect", }, diff --git a/drivers/interconnect/imx/imx8mp.c b/drivers/interconnect/imx/imx8mp.c index 86d4c1517b26..c5751ed18d51 100644 --- a/drivers/interconnect/imx/imx8mp.c +++ b/drivers/interconnect/imx/imx8mp.c @@ -241,7 +241,7 @@ static int imx8mp_icc_probe(struct platform_device *pdev) static struct platform_driver imx8mp_icc_driver = { .probe = imx8mp_icc_probe, - .remove_new = imx_icc_unregister, + .remove = imx_icc_unregister, .driver = { .name = "imx8mp-interconnect", }, diff --git a/drivers/interconnect/imx/imx8mq.c b/drivers/interconnect/imx/imx8mq.c index f817d24aeefb..6aa4f06b4676 100644 --- a/drivers/interconnect/imx/imx8mq.c +++ b/drivers/interconnect/imx/imx8mq.c @@ -87,7 +87,7 @@ static int imx8mq_icc_probe(struct platform_device *pdev) static struct platform_driver imx8mq_icc_driver = { .probe = imx8mq_icc_probe, - .remove_new = imx_icc_unregister, + .remove = imx_icc_unregister, .driver = { .name = "imx8mq-interconnect", .sync_state = icc_sync_state, diff --git a/drivers/interconnect/mediatek/mt8183.c b/drivers/interconnect/mediatek/mt8183.c index 24245085c7a9..c212e79334cf 100644 --- a/drivers/interconnect/mediatek/mt8183.c +++ b/drivers/interconnect/mediatek/mt8183.c @@ -133,7 +133,7 @@ static struct platform_driver mtk_emi_icc_mt8183_driver = { .sync_state = icc_sync_state, }, .probe = mtk_emi_icc_probe, - .remove_new = mtk_emi_icc_remove, + .remove = mtk_emi_icc_remove, }; module_platform_driver(mtk_emi_icc_mt8183_driver); diff --git a/drivers/interconnect/mediatek/mt8195.c b/drivers/interconnect/mediatek/mt8195.c index 710e14c5447c..3ca23469ab18 100644 --- a/drivers/interconnect/mediatek/mt8195.c +++ b/drivers/interconnect/mediatek/mt8195.c @@ -329,7 +329,7 @@ static struct platform_driver mtk_emi_icc_mt8195_driver = { .sync_state = icc_sync_state, }, .probe = mtk_emi_icc_probe, - .remove_new = mtk_emi_icc_remove, + .remove = mtk_emi_icc_remove, }; module_platform_driver(mtk_emi_icc_mt8195_driver); diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig index de96d4661340..bb1cb8a640c1 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -8,6 +8,24 @@ config INTERCONNECT_QCOM config INTERCONNECT_QCOM_BCM_VOTER tristate +config INTERCONNECT_QCOM_GLYMUR + tristate "Qualcomm GLYMUR interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on glymur-based + platforms. + +config INTERCONNECT_QCOM_KAANAPALI + tristate "Qualcomm KAANAPALI interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on kaanapali-based + platforms. + config INTERCONNECT_QCOM_MSM8909 tristate "Qualcomm MSM8909 interconnect driver" depends on INTERCONNECT_QCOM @@ -105,6 +123,26 @@ config INTERCONNECT_QCOM_QCS404 This is a driver for the Qualcomm Network-on-Chip on qcs404-based platforms. +config INTERCONNECT_QCOM_QCS615 + tristate "Qualcomm QCS615 interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on qcs615-based + platforms. + +config INTERCONNECT_QCOM_QCS8300 + tristate "Qualcomm QCS8300 interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Technologies, Inc. Network-on-Chip + on QCS8300-based platforms. The interconnect provider collects and + aggreagates the cosumer bandwidth requests to satisfy constraints + placed on Network-on-Chip performance states. + config INTERCONNECT_QCOM_QDU1000 tristate "Qualcomm QDU1000/QRU1000 interconnect driver" depends on INTERCONNECT_QCOM_RPMH_POSSIBLE @@ -137,6 +175,15 @@ config INTERCONNECT_QCOM_SA8775P This is a driver for the Qualcomm Network-on-Chip on sa8775p-based platforms. +config INTERCONNECT_QCOM_SAR2130P + tristate "Qualcomm SAR2130P interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on SAR2130P-based + platforms. + config INTERCONNECT_QCOM_SC7180 tristate "Qualcomm SC7180 interconnect driver" depends on INTERCONNECT_QCOM_RPMH_POSSIBLE @@ -254,6 +301,15 @@ config INTERCONNECT_QCOM_SM7150 This is a driver for the Qualcomm Network-on-Chip on sm7150-based platforms. +config INTERCONNECT_QCOM_MILOS + tristate "Qualcomm Milos interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on Milos-based + platforms. + config INTERCONNECT_QCOM_SM8150 tristate "Qualcomm SM8150 interconnect driver" depends on INTERCONNECT_QCOM_RPMH_POSSIBLE @@ -308,6 +364,15 @@ config INTERCONNECT_QCOM_SM8650 This is a driver for the Qualcomm Network-on-Chip on SM8650-based platforms. +config INTERCONNECT_QCOM_SM8750 + tristate "Qualcomm SM8750 interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on SM8750-based + platforms. + config INTERCONNECT_QCOM_X1E80100 tristate "Qualcomm X1E80100 interconnect driver" depends on INTERCONNECT_QCOM_RPMH_POSSIBLE diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile index bfeea8416fcf..6eedff043b41 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -4,6 +4,9 @@ obj-$(CONFIG_INTERCONNECT_QCOM) += interconnect_qcom.o interconnect_qcom-y := icc-common.o icc-bcm-voter-objs := bcm-voter.o +qnoc-glymur-objs := glymur.o +qnoc-kaanapali-objs := kaanapali.o +qnoc-milos-objs := milos.o qnoc-msm8909-objs := msm8909.o qnoc-msm8916-objs := msm8916.o qnoc-msm8937-objs := msm8937.o @@ -15,9 +18,12 @@ qnoc-msm8996-objs := msm8996.o icc-osm-l3-objs := osm-l3.o qnoc-qcm2290-objs := qcm2290.o qnoc-qcs404-objs := qcs404.o +qnoc-qcs615-objs := qcs615.o +qnoc-qcs8300-objs := qcs8300.o qnoc-qdu1000-objs := qdu1000.o icc-rpmh-obj := icc-rpmh.o qnoc-sa8775p-objs := sa8775p.o +qnoc-sar2130p-objs := sar2130p.o qnoc-sc7180-objs := sc7180.o qnoc-sc7280-objs := sc7280.o qnoc-sc8180x-objs := sc8180x.o @@ -37,10 +43,14 @@ qnoc-sm8350-objs := sm8350.o qnoc-sm8450-objs := sm8450.o qnoc-sm8550-objs := sm8550.o qnoc-sm8650-objs := sm8650.o +qnoc-sm8750-objs := sm8750.o qnoc-x1e80100-objs := x1e80100.o icc-smd-rpm-objs := smd-rpm.o icc-rpm.o icc-rpm-clocks.o obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o +obj-$(CONFIG_INTERCONNECT_QCOM_GLYMUR) += qnoc-glymur.o +obj-$(CONFIG_INTERCONNECT_QCOM_KAANAPALI) += qnoc-kaanapali.o +obj-$(CONFIG_INTERCONNECT_QCOM_MILOS) += qnoc-milos.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8909) += qnoc-msm8909.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) += qnoc-msm8916.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8937) += qnoc-msm8937.o @@ -52,9 +62,12 @@ obj-$(CONFIG_INTERCONNECT_QCOM_MSM8996) += qnoc-msm8996.o obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o obj-$(CONFIG_INTERCONNECT_QCOM_QCM2290) += qnoc-qcm2290.o obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o +obj-$(CONFIG_INTERCONNECT_QCOM_QCS615) += qnoc-qcs615.o +obj-$(CONFIG_INTERCONNECT_QCOM_QCS8300) += qnoc-qcs8300.o obj-$(CONFIG_INTERCONNECT_QCOM_QDU1000) += qnoc-qdu1000.o obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o obj-$(CONFIG_INTERCONNECT_QCOM_SA8775P) += qnoc-sa8775p.o +obj-$(CONFIG_INTERCONNECT_QCOM_SAR2130P) += qnoc-sar2130p.o obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o obj-$(CONFIG_INTERCONNECT_QCOM_SC7280) += qnoc-sc7280.o obj-$(CONFIG_INTERCONNECT_QCOM_SC8180X) += qnoc-sc8180x.o @@ -74,5 +87,6 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SM8350) += qnoc-sm8350.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8450) += qnoc-sm8450.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8550) += qnoc-sm8550.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8650) += qnoc-sm8650.o +obj-$(CONFIG_INTERCONNECT_QCOM_SM8750) += qnoc-sm8750.o obj-$(CONFIG_INTERCONNECT_QCOM_X1E80100) += qnoc-x1e80100.o obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o diff --git a/drivers/interconnect/qcom/glymur.c b/drivers/interconnect/qcom/glymur.c new file mode 100644 index 000000000000..e5c07795a6c6 --- /dev/null +++ b/drivers/interconnect/qcom/glymur.c @@ -0,0 +1,2522 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved. + * + */ + +#include <linux/device.h> +#include <linux/interconnect.h> +#include <linux/interconnect-provider.h> +#include <linux/module.h> +#include <linux/of_platform.h> +#include <dt-bindings/interconnect/qcom,glymur-rpmh.h> + +#include "bcm-voter.h" +#include "icc-rpmh.h" + +static struct qcom_icc_node qup0_core_slave = { + .name = "qup0_core_slave", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup1_core_slave = { + .name = "qup1_core_slave", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup2_core_slave = { + .name = "qup2_core_slave", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy0 = { + .name = "qhs_ahb2phy0", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy1 = { + .name = "qhs_ahb2phy1", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy2 = { + .name = "qhs_ahb2phy2", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy3 = { + .name = "qhs_ahb2phy3", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_av1_enc_cfg = { + .name = "qhs_av1_enc_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display_cfg = { + .name = "qhs_display_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie0_cfg = { + .name = "qhs_pcie0_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie1_cfg = { + .name = "qhs_pcie1_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie2_cfg = { + .name = "qhs_pcie2_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie3a_cfg = { + .name = "qhs_pcie3a_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie3b_cfg = { + .name = "qhs_pcie3b_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie4_cfg = { + .name = "qhs_pcie4_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie5_cfg = { + .name = "qhs_pcie5_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie6_cfg = { + .name = "qhs_pcie6_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie_rscc = { + .name = "qhs_pcie_rscc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qspi = { + .name = "qhs_qspi", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup0 = { + .name = "qhs_qup0", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup1 = { + .name = "qhs_qup1", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup2 = { + .name = "qhs_qup2", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .name = "qhs_sdc2", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc4 = { + .name = "qhs_sdc4", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_smmuv3_cfg = { + .name = "qhs_smmuv3_cfg", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm = { + .name = "qhs_tlmm", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb2_0_cfg = { + .name = "qhs_usb2_0_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_0_cfg = { + .name = "qhs_usb3_0_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_1_cfg = { + .name = "qhs_usb3_1_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_2_cfg = { + .name = "qhs_usb3_2_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_mp_cfg = { + .name = "qhs_usb3_mp_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb4_0_cfg = { + .name = "qhs_usb4_0_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb4_1_cfg = { + .name = "qhs_usb4_1_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb4_2_cfg = { + .name = "qhs_usb4_2_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qss_lpass_qtb_cfg = { + .name = "qss_lpass_qtb_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qss_nsp_qtb_cfg = { + .name = "qss_nsp_qtb_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipc_router = { + .name = "qhs_ipc_router", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_soccp = { + .name = "qhs_soccp", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tme_cfg = { + .name = "qhs_tme_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_apss = { + .name = "qns_apss", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_boot_imem = { + .name = "qxs_boot_imem", + .channels = 1, + .buswidth = 16, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .channels = 12, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_mnoc = { + .name = "srvc_mnoc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_nsinoc = { + .name = "srvc_nsinoc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_pcie_east_aggre_noc = { + .name = "srvc_pcie_east_aggre_noc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_hscnoc_pcie_east_ms_mpu_cfg = { + .name = "qhs_hscnoc_pcie_east_ms_mpu_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_pcie_east = { + .name = "srvc_pcie_east", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_pcie_0 = { + .name = "xs_pcie_0", + .channels = 1, + .buswidth = 16, +}; + +static struct qcom_icc_node xs_pcie_1 = { + .name = "xs_pcie_1", + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node xs_pcie_5 = { + .name = "xs_pcie_5", + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node srvc_pcie_west_aggre_noc = { + .name = "srvc_pcie_west_aggre_noc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_hscnoc_pcie_west_ms_mpu_cfg = { + .name = "qhs_hscnoc_pcie_west_ms_mpu_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_pcie_west = { + .name = "srvc_pcie_west", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_pcie_2 = { + .name = "xs_pcie_2", + .channels = 1, + .buswidth = 16, +}; + +static struct qcom_icc_node xs_pcie_3a = { + .name = "xs_pcie_3a", + .channels = 1, + .buswidth = 64, +}; + +static struct qcom_icc_node xs_pcie_3b = { + .name = "xs_pcie_3b", + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node xs_pcie_4 = { + .name = "xs_pcie_4", + .channels = 1, + .buswidth = 16, +}; + +static struct qcom_icc_node xs_pcie_6 = { + .name = "xs_pcie_6", + .channels = 1, + .buswidth = 16, +}; + +static struct qcom_icc_node qup0_core_master = { + .name = "qup0_core_master", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qup0_core_slave }, +}; + +static struct qcom_icc_node qup1_core_master = { + .name = "qup1_core_master", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qup1_core_slave }, +}; + +static struct qcom_icc_node qup2_core_master = { + .name = "qup2_core_master", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qup2_core_slave }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .channels = 12, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &ebi }, +}; + +static struct qcom_icc_node qsm_mnoc_cfg = { + .name = "qsm_mnoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &srvc_mnoc }, +}; + +static struct qcom_icc_node qsm_pcie_east_anoc_cfg = { + .name = "qsm_pcie_east_anoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &srvc_pcie_east_aggre_noc }, +}; + +static struct qcom_icc_node qnm_hscnoc_pcie_east = { + .name = "qnm_hscnoc_pcie_east", + .channels = 1, + .buswidth = 32, + .num_links = 3, + .link_nodes = { &xs_pcie_0, &xs_pcie_1, + &xs_pcie_5 }, +}; + +static struct qcom_icc_node qsm_cnoc_pcie_east_slave_cfg = { + .name = "qsm_cnoc_pcie_east_slave_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 2, + .link_nodes = { &qhs_hscnoc_pcie_east_ms_mpu_cfg, + &srvc_pcie_east }, +}; + +static struct qcom_icc_node qsm_pcie_west_anoc_cfg = { + .name = "qsm_pcie_west_anoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &srvc_pcie_west_aggre_noc }, +}; + +static struct qcom_icc_node qnm_hscnoc_pcie_west = { + .name = "qnm_hscnoc_pcie_west", + .channels = 1, + .buswidth = 32, + .num_links = 5, + .link_nodes = { &xs_pcie_2, &xs_pcie_3a, + &xs_pcie_3b, &xs_pcie_4, + &xs_pcie_6 }, +}; + +static struct qcom_icc_node qsm_cnoc_pcie_west_slave_cfg = { + .name = "qsm_cnoc_pcie_west_slave_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 2, + .link_nodes = { &qhs_hscnoc_pcie_west_ms_mpu_cfg, + &srvc_pcie_west }, +}; + +static struct qcom_icc_node qss_cnoc_pcie_slave_east_cfg = { + .name = "qss_cnoc_pcie_slave_east_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qsm_cnoc_pcie_east_slave_cfg }, +}; + +static struct qcom_icc_node qss_cnoc_pcie_slave_west_cfg = { + .name = "qss_cnoc_pcie_slave_west_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qsm_cnoc_pcie_west_slave_cfg }, +}; + +static struct qcom_icc_node qss_mnoc_cfg = { + .name = "qss_mnoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qsm_mnoc_cfg }, +}; + +static struct qcom_icc_node qss_pcie_east_anoc_cfg = { + .name = "qss_pcie_east_anoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qsm_pcie_east_anoc_cfg }, +}; + +static struct qcom_icc_node qss_pcie_west_anoc_cfg = { + .name = "qss_pcie_west_anoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qsm_pcie_west_anoc_cfg }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .channels = 12, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &llcc_mc }, +}; + +static struct qcom_icc_node qns_pcie_east = { + .name = "qns_pcie_east", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_hscnoc_pcie_east }, +}; + +static struct qcom_icc_node qns_pcie_west = { + .name = "qns_pcie_west", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_hscnoc_pcie_west }, +}; + +static struct qcom_icc_node qsm_cfg = { + .name = "qsm_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 51, + .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_ahb2phy2, &qhs_ahb2phy3, + &qhs_av1_enc_cfg, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_crypto0_cfg, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_imem_cfg, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_pcie2_cfg, + &qhs_pcie3a_cfg, &qhs_pcie3b_cfg, + &qhs_pcie4_cfg, &qhs_pcie5_cfg, + &qhs_pcie6_cfg, &qhs_pcie_rscc, + &qhs_pdm, &qhs_prng, + &qhs_qdss_cfg, &qhs_qspi, + &qhs_qup0, &qhs_qup1, + &qhs_qup2, &qhs_sdc2, + &qhs_sdc4, &qhs_smmuv3_cfg, + &qhs_tcsr, &qhs_tlmm, + &qhs_ufs_mem_cfg, &qhs_usb2_0_cfg, + &qhs_usb3_0_cfg, &qhs_usb3_1_cfg, + &qhs_usb3_2_cfg, &qhs_usb3_mp_cfg, + &qhs_usb4_0_cfg, &qhs_usb4_1_cfg, + &qhs_usb4_2_cfg, &qhs_venus_cfg, + &qss_cnoc_pcie_slave_east_cfg, &qss_cnoc_pcie_slave_west_cfg, + &qss_lpass_qtb_cfg, &qss_mnoc_cfg, + &qss_nsp_qtb_cfg, &qss_pcie_east_anoc_cfg, + &qss_pcie_west_anoc_cfg, &xs_qdss_stm, + &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x33000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = { &qns_llcc }, +}; + +static struct qcom_icc_node qss_cfg = { + .name = "qss_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qsm_cfg }, +}; + +static struct qcom_icc_node qnm_hscnoc_cnoc = { + .name = "qnm_hscnoc_cnoc", + .channels = 1, + .buswidth = 16, + .num_links = 8, + .link_nodes = { &qhs_aoss, &qhs_ipc_router, + &qhs_soccp, &qhs_tme_cfg, + &qns_apss, &qss_cfg, + &qxs_boot_imem, &qxs_imem }, +}; + +static struct qcom_icc_node qns_hscnoc_cnoc = { + .name = "qns_hscnoc_cnoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_hscnoc_cnoc }, +}; + +static struct qcom_icc_node alm_gpu_tcu = { + .name = "alm_gpu_tcu", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x933000 }, + .prio = 1, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 2, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node alm_pcie_qtc = { + .name = "alm_pcie_qtc", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x51f000 }, + .prio = 3, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 2, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node alm_sys_tcu = { + .name = "alm_sys_tcu", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x51f080 }, + .prio = 6, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 2, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node chm_apps = { + .name = "chm_apps", + .channels = 6, + .buswidth = 32, + .num_links = 4, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie_east, &qns_pcie_west }, +}; + +static struct qcom_icc_node qnm_aggre_noc_east = { + .name = "qnm_aggre_noc_east", + .channels = 1, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x934000 }, + .prio = 2, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 4, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie_east, &qns_pcie_west }, +}; + +static struct qcom_icc_node qnm_gpu = { + .name = "qnm_gpu", + .channels = 4, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 4, + .port_offsets = { 0x935000, 0x936000, 0x937000, 0x938000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 4, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie_east, &qns_pcie_west }, +}; + +static struct qcom_icc_node qnm_lpass = { + .name = "qnm_lpass", + .channels = 1, + .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x939000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 4, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie_east, &qns_pcie_west }, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .channels = 2, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0x721000, 0x721080 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 4, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie_east, &qns_pcie_west }, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .channels = 2, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0x721100, 0x721180 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 4, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie_east, &qns_pcie_west }, +}; + +static struct qcom_icc_node qnm_nsp_noc = { + .name = "qnm_nsp_noc", + .channels = 4, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 4, + .port_offsets = { 0x816000, 0x816080, 0x816100, 0x816180 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 4, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie_east, &qns_pcie_west }, +}; + +static struct qcom_icc_node qnm_pcie_east = { + .name = "qnm_pcie_east", + .channels = 1, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x93a000 }, + .prio = 2, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 2, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node qnm_pcie_west = { + .name = "qnm_pcie_west", + .channels = 1, + .buswidth = 64, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x721200 }, + .prio = 2, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 2, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .channels = 1, + .buswidth = 64, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x51f100 }, + .prio = 2, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 4, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie_east, &qns_pcie_west }, +}; + +static struct qcom_icc_node qxm_wlan_q6 = { + .name = "qxm_wlan_q6", + .channels = 1, + .buswidth = 8, + .num_links = 4, + .link_nodes = { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie_east, &qns_pcie_west }, +}; + +static struct qcom_icc_node qns_a4noc_hscnoc = { + .name = "qns_a4noc_hscnoc", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_aggre_noc_east }, +}; + +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { + .name = "qns_lpass_ag_noc_gemnoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_lpass }, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_mnoc_hf }, +}; + +static struct qcom_icc_node qns_mem_noc_sf = { + .name = "qns_mem_noc_sf", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_mnoc_sf }, +}; + +static struct qcom_icc_node qns_nsp_hscnoc = { + .name = "qns_nsp_hscnoc", + .channels = 4, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_nsp_noc }, +}; + +static struct qcom_icc_node qns_pcie_east_mem_noc = { + .name = "qns_pcie_east_mem_noc", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_pcie_east }, +}; + +static struct qcom_icc_node qns_pcie_west_mem_noc = { + .name = "qns_pcie_west_mem_noc", + .channels = 1, + .buswidth = 64, + .num_links = 1, + .link_nodes = { &qnm_pcie_west }, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .channels = 1, + .buswidth = 64, + .num_links = 1, + .link_nodes = { &qnm_snoc_sf }, +}; + +static struct qcom_icc_node xm_usb3_0 = { + .name = "xm_usb3_0", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xa000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a4noc_hscnoc }, +}; + +static struct qcom_icc_node xm_usb3_1 = { + .name = "xm_usb3_1", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xb000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a4noc_hscnoc }, +}; + +static struct qcom_icc_node xm_usb4_0 = { + .name = "xm_usb4_0", + .channels = 1, + .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xc000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a4noc_hscnoc }, +}; + +static struct qcom_icc_node xm_usb4_1 = { + .name = "xm_usb4_1", + .channels = 1, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xd000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a4noc_hscnoc }, +}; + +static struct qcom_icc_node qnm_lpiaon_noc = { + .name = "qnm_lpiaon_noc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_lpass_ag_noc_gemnoc }, +}; + +static struct qcom_icc_node qnm_av1_enc = { + .name = "qnm_av1_enc", + .channels = 1, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x30000 }, + .prio = 4, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_camnoc_hf = { + .name = "qnm_camnoc_hf", + .channels = 2, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0x29000, 0x2a000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qnm_camnoc_icp = { + .name = "qnm_camnoc_icp", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x2b000 }, + .prio = 4, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_camnoc_sf = { + .name = "qnm_camnoc_sf", + .channels = 2, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0x2c000, 0x2d000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_eva = { + .name = "qnm_eva", + .channels = 1, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x34000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_mdp = { + .name = "qnm_mdp", + .channels = 2, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0x2e000, 0x2f000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qnm_vapss_hcp = { + .name = "qnm_vapss_hcp", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video = { + .name = "qnm_video", + .channels = 4, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 4, + .port_offsets = { 0x31000, 0x32000, 0x37000, 0x38000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_cv_cpu = { + .name = "qnm_video_cv_cpu", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x33000 }, + .prio = 4, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_v_cpu = { + .name = "qnm_video_v_cpu", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x35000 }, + .prio = 4, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_nsp = { + .name = "qnm_nsp", + .channels = 4, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_nsp_hscnoc }, +}; + +static struct qcom_icc_node xm_pcie_0 = { + .name = "xm_pcie_0", + .channels = 1, + .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xb000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = { &qns_pcie_east_mem_noc }, +}; + +static struct qcom_icc_node xm_pcie_1 = { + .name = "xm_pcie_1", + .channels = 1, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xc000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = { &qns_pcie_east_mem_noc }, +}; + +static struct qcom_icc_node xm_pcie_5 = { + .name = "xm_pcie_5", + .channels = 1, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xd000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = { &qns_pcie_east_mem_noc }, +}; + +static struct qcom_icc_node xm_pcie_2 = { + .name = "xm_pcie_2", + .channels = 1, + .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xd000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = { &qns_pcie_west_mem_noc }, +}; + +static struct qcom_icc_node xm_pcie_3a = { + .name = "xm_pcie_3a", + .channels = 1, + .buswidth = 64, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xd200 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = { &qns_pcie_west_mem_noc }, +}; + +static struct qcom_icc_node xm_pcie_3b = { + .name = "xm_pcie_3b", + .channels = 1, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xd400 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = { &qns_pcie_west_mem_noc }, +}; + +static struct qcom_icc_node xm_pcie_4 = { + .name = "xm_pcie_4", + .channels = 1, + .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xd600 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = { &qns_pcie_west_mem_noc }, +}; + +static struct qcom_icc_node xm_pcie_6 = { + .name = "xm_pcie_6", + .channels = 1, + .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xd800 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = { &qns_pcie_west_mem_noc }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_aggre3_noc = { + .name = "qnm_aggre3_noc", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_nsi_noc = { + .name = "qnm_nsi_noc", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x1c000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_oobmss = { + .name = "qnm_oobmss", + .channels = 1, + .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x1b000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_node qns_a3noc_snoc = { + .name = "qns_a3noc_snoc", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_aggre3_noc }, +}; + +static struct qcom_icc_node qns_lpass_aggnoc = { + .name = "qns_lpass_aggnoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_lpiaon_noc }, +}; + +static struct qcom_icc_node qns_system_noc = { + .name = "qns_system_noc", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qnm_nsi_noc }, +}; + +static struct qcom_icc_node qns_oobmss_snoc = { + .name = "qns_oobmss_snoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_oobmss }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xb000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qxm_soccp = { + .name = "qxm_soccp", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xe000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_qdss_etr_0 = { + .name = "xm_qdss_etr_0", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xc000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_qdss_etr_1 = { + .name = "xm_qdss_etr_1", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xd000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .channels = 1, + .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xa000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node xm_usb3_2 = { + .name = "xm_usb3_2", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x8000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node xm_usb4_2 = { + .name = "xm_usb4_2", + .channels = 1, + .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x9000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qhm_qspi = { + .name = "qhm_qspi", + .channels = 1, + .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x10000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a3noc_snoc }, +}; + +static struct qcom_icc_node qhm_qup0 = { + .name = "qhm_qup0", + .channels = 1, + .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x11000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a3noc_snoc }, +}; + +static struct qcom_icc_node qhm_qup1 = { + .name = "qhm_qup1", + .channels = 1, + .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x12000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a3noc_snoc }, +}; + +static struct qcom_icc_node qhm_qup2 = { + .name = "qhm_qup2", + .channels = 1, + .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x13000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a3noc_snoc }, +}; + +static struct qcom_icc_node qxm_sp = { + .name = "qxm_sp", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a3noc_snoc }, +}; + +static struct qcom_icc_node xm_sdc2 = { + .name = "xm_sdc2", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x18000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a3noc_snoc }, +}; + +static struct qcom_icc_node xm_sdc4 = { + .name = "xm_sdc4", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x14000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a3noc_snoc }, +}; + +static struct qcom_icc_node xm_usb2_0 = { + .name = "xm_usb2_0", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x15000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a3noc_snoc }, +}; + +static struct qcom_icc_node xm_usb3_mp = { + .name = "xm_usb3_mp", + .channels = 1, + .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x16000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a3noc_snoc }, +}; + +static struct qcom_icc_node qnm_lpass_lpinoc = { + .name = "qnm_lpass_lpinoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_lpass_aggnoc }, +}; + +static struct qcom_icc_node xm_cpucp = { + .name = "xm_cpucp", + .channels = 1, + .buswidth = 8, + .num_links = 2, + .link_nodes = { &qns_system_noc, &srvc_nsinoc }, +}; + +static struct qcom_icc_node xm_mem_sp = { + .name = "xm_mem_sp", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_oobmss_snoc }, +}; + +static struct qcom_icc_node qns_lpi_aon_noc = { + .name = "qns_lpi_aon_noc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_lpass_lpinoc }, +}; + +static struct qcom_icc_node qnm_lpinoc_dsp_qns4m = { + .name = "qnm_lpinoc_dsp_qns4m", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_lpi_aon_noc }, +}; + +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .enable_mask = BIT(3), + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .keepalive = true, + .enable_mask = BIT(0), + .num_nodes = 60, + .nodes = { &qsm_cfg, &qhs_ahb2phy0, + &qhs_ahb2phy1, &qhs_ahb2phy2, + &qhs_ahb2phy3, &qhs_av1_enc_cfg, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_crypto0_cfg, &qhs_gpuss_cfg, + &qhs_imem_cfg, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_pcie2_cfg, + &qhs_pcie3a_cfg, &qhs_pcie3b_cfg, + &qhs_pcie4_cfg, &qhs_pcie5_cfg, + &qhs_pcie6_cfg, &qhs_pcie_rscc, + &qhs_pdm, &qhs_prng, + &qhs_qdss_cfg, &qhs_qspi, + &qhs_qup0, &qhs_qup1, + &qhs_qup2, &qhs_sdc2, + &qhs_sdc4, &qhs_smmuv3_cfg, + &qhs_tcsr, &qhs_tlmm, + &qhs_ufs_mem_cfg, &qhs_usb2_0_cfg, + &qhs_usb3_0_cfg, &qhs_usb3_1_cfg, + &qhs_usb3_2_cfg, &qhs_usb3_mp_cfg, + &qhs_usb4_0_cfg, &qhs_usb4_1_cfg, + &qhs_usb4_2_cfg, &qhs_venus_cfg, + &qss_cnoc_pcie_slave_east_cfg, &qss_cnoc_pcie_slave_west_cfg, + &qss_lpass_qtb_cfg, &qss_mnoc_cfg, + &qss_nsp_qtb_cfg, &qss_pcie_east_anoc_cfg, + &qss_pcie_west_anoc_cfg, &xs_qdss_stm, + &xs_sys_tcu_cfg, &qnm_hscnoc_cnoc, + &qhs_aoss, &qhs_ipc_router, + &qhs_soccp, &qhs_tme_cfg, + &qns_apss, &qss_cfg, + &qxs_boot_imem, &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_cn1 = { + .name = "CN1", + .num_nodes = 1, + .nodes = { &qhs_display_cfg }, +}; + +static struct qcom_icc_bcm bcm_co0 = { + .name = "CO0", + .enable_mask = BIT(0), + .num_nodes = 2, + .nodes = { &qnm_nsp, &qns_nsp_hscnoc }, +}; + +static struct qcom_icc_bcm bcm_lp0 = { + .name = "LP0", + .num_nodes = 2, + .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .enable_mask = BIT(0), + .num_nodes = 11, + .nodes = { &qnm_av1_enc, &qnm_camnoc_hf, + &qnm_camnoc_icp, &qnm_camnoc_sf, + &qnm_eva, &qnm_mdp, + &qnm_vapss_hcp, &qnm_video, + &qnm_video_cv_cpu, &qnm_video_v_cpu, + &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .vote_scale = 1, + .keepalive = true, + .num_nodes = 1, + .nodes = { &qup0_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup1 = { + .name = "QUP1", + .vote_scale = 1, + .keepalive = true, + .num_nodes = 1, + .nodes = { &qup1_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup2 = { + .name = "QUP2", + .vote_scale = 1, + .keepalive = true, + .num_nodes = 1, + .nodes = { &qup2_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh1 = { + .name = "SH1", + .enable_mask = BIT(0), + .num_nodes = 18, + .nodes = { &alm_gpu_tcu, &alm_pcie_qtc, + &alm_sys_tcu, &chm_apps, + &qnm_aggre_noc_east, &qnm_gpu, + &qnm_lpass, &qnm_mnoc_hf, + &qnm_mnoc_sf, &qnm_nsp_noc, + &qnm_pcie_east, &qnm_pcie_west, + &qnm_snoc_sf, &qxm_wlan_q6, + &xm_gic, &qns_hscnoc_cnoc, + &qns_pcie_east, &qns_pcie_west }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .enable_mask = BIT(0), + .num_nodes = 1, + .nodes = { &qnm_oobmss }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .num_nodes = 1, + .nodes = { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .num_nodes = 1, + .nodes = { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .num_nodes = 1, + .nodes = { &qnm_aggre3_noc }, +}; + +static struct qcom_icc_bcm bcm_sn5 = { + .name = "SN5", + .num_nodes = 1, + .nodes = { &qns_a4noc_hscnoc }, +}; + +static struct qcom_icc_bcm bcm_sn6 = { + .name = "SN6", + .num_nodes = 4, + .nodes = { &qns_pcie_east_mem_noc, &qnm_hscnoc_pcie_east, + &qns_pcie_west_mem_noc, &qnm_hscnoc_pcie_west }, +}; + +static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { + &bcm_ce0, +}; + +static struct qcom_icc_node * const aggre1_noc_nodes[] = { + [MASTER_CRYPTO] = &qxm_crypto, + [MASTER_SOCCP_PROC] = &qxm_soccp, + [MASTER_QDSS_ETR] = &xm_qdss_etr_0, + [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, + [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, +}; + +static const struct regmap_config glymur_aggre1_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x14400, + .fast_io = true, +}; + +static const struct qcom_icc_desc glymur_aggre1_noc = { + .config = &glymur_aggre1_noc_regmap_config, + .nodes = aggre1_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), + .bcms = aggre1_noc_bcms, + .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), +}; + +static struct qcom_icc_node * const aggre2_noc_nodes[] = { + [MASTER_UFS_MEM] = &xm_ufs_mem, + [MASTER_USB3_2] = &xm_usb3_2, + [MASTER_USB4_2] = &xm_usb4_2, + [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, +}; + +static const struct regmap_config glymur_aggre2_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x14400, + .fast_io = true, +}; + +static const struct qcom_icc_desc glymur_aggre2_noc = { + .config = &glymur_aggre2_noc_regmap_config, + .nodes = aggre2_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), + .qos_requires_clocks = true, +}; + +static struct qcom_icc_node * const aggre3_noc_nodes[] = { + [MASTER_QSPI_0] = &qhm_qspi, + [MASTER_QUP_0] = &qhm_qup0, + [MASTER_QUP_1] = &qhm_qup1, + [MASTER_QUP_2] = &qhm_qup2, + [MASTER_SP] = &qxm_sp, + [MASTER_SDCC_2] = &xm_sdc2, + [MASTER_SDCC_4] = &xm_sdc4, + [MASTER_USB2] = &xm_usb2_0, + [MASTER_USB3_MP] = &xm_usb3_mp, + [SLAVE_A3NOC_SNOC] = &qns_a3noc_snoc, +}; + +static const struct regmap_config glymur_aggre3_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1d400, + .fast_io = true, +}; + +static const struct qcom_icc_desc glymur_aggre3_noc = { + .config = &glymur_aggre3_noc_regmap_config, + .nodes = aggre3_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre3_noc_nodes), +}; + +static struct qcom_icc_bcm * const aggre4_noc_bcms[] = { + &bcm_sn5, +}; + +static struct qcom_icc_node * const aggre4_noc_nodes[] = { + [MASTER_USB3_0] = &xm_usb3_0, + [MASTER_USB3_1] = &xm_usb3_1, + [MASTER_USB4_0] = &xm_usb4_0, + [MASTER_USB4_1] = &xm_usb4_1, + [SLAVE_A4NOC_HSCNOC] = &qns_a4noc_hscnoc, +}; + +static const struct regmap_config glymur_aggre4_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x14400, + .fast_io = true, +}; + +static const struct qcom_icc_desc glymur_aggre4_noc = { + .config = &glymur_aggre4_noc_regmap_config, + .nodes = aggre4_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre4_noc_nodes), + .bcms = aggre4_noc_bcms, + .num_bcms = ARRAY_SIZE(aggre4_noc_bcms), + .qos_requires_clocks = true, +}; + +static struct qcom_icc_bcm * const clk_virt_bcms[] = { + &bcm_qup0, + &bcm_qup1, + &bcm_qup2, +}; + +static struct qcom_icc_node * const clk_virt_nodes[] = { + [MASTER_QUP_CORE_0] = &qup0_core_master, + [MASTER_QUP_CORE_1] = &qup1_core_master, + [MASTER_QUP_CORE_2] = &qup2_core_master, + [SLAVE_QUP_CORE_0] = &qup0_core_slave, + [SLAVE_QUP_CORE_1] = &qup1_core_slave, + [SLAVE_QUP_CORE_2] = &qup2_core_slave, +}; + +static const struct qcom_icc_desc glymur_clk_virt = { + .nodes = clk_virt_nodes, + .num_nodes = ARRAY_SIZE(clk_virt_nodes), + .bcms = clk_virt_bcms, + .num_bcms = ARRAY_SIZE(clk_virt_bcms), +}; + +static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = { + &bcm_cn0, + &bcm_cn1, +}; + +static struct qcom_icc_node * const cnoc_cfg_nodes[] = { + [MASTER_CNOC_CFG] = &qsm_cfg, + [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, + [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, + [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2, + [SLAVE_AHB2PHY_3] = &qhs_ahb2phy3, + [SLAVE_AV1_ENC_CFG] = &qhs_av1_enc_cfg, + [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, + [SLAVE_CLK_CTL] = &qhs_clk_ctl, + [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, + [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, + [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, + [SLAVE_IMEM_CFG] = &qhs_imem_cfg, + [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, + [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, + [SLAVE_PCIE_2_CFG] = &qhs_pcie2_cfg, + [SLAVE_PCIE_3A_CFG] = &qhs_pcie3a_cfg, + [SLAVE_PCIE_3B_CFG] = &qhs_pcie3b_cfg, + [SLAVE_PCIE_4_CFG] = &qhs_pcie4_cfg, + [SLAVE_PCIE_5_CFG] = &qhs_pcie5_cfg, + [SLAVE_PCIE_6_CFG] = &qhs_pcie6_cfg, + [SLAVE_PCIE_RSCC] = &qhs_pcie_rscc, + [SLAVE_PDM] = &qhs_pdm, + [SLAVE_PRNG] = &qhs_prng, + [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, + [SLAVE_QSPI_0] = &qhs_qspi, + [SLAVE_QUP_0] = &qhs_qup0, + [SLAVE_QUP_1] = &qhs_qup1, + [SLAVE_QUP_2] = &qhs_qup2, + [SLAVE_SDCC_2] = &qhs_sdc2, + [SLAVE_SDCC_4] = &qhs_sdc4, + [SLAVE_SMMUV3_CFG] = &qhs_smmuv3_cfg, + [SLAVE_TCSR] = &qhs_tcsr, + [SLAVE_TLMM] = &qhs_tlmm, + [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, + [SLAVE_USB2] = &qhs_usb2_0_cfg, + [SLAVE_USB3_0] = &qhs_usb3_0_cfg, + [SLAVE_USB3_1] = &qhs_usb3_1_cfg, + [SLAVE_USB3_2] = &qhs_usb3_2_cfg, + [SLAVE_USB3_MP] = &qhs_usb3_mp_cfg, + [SLAVE_USB4_0] = &qhs_usb4_0_cfg, + [SLAVE_USB4_1] = &qhs_usb4_1_cfg, + [SLAVE_USB4_2] = &qhs_usb4_2_cfg, + [SLAVE_VENUS_CFG] = &qhs_venus_cfg, + [SLAVE_CNOC_PCIE_SLAVE_EAST_CFG] = &qss_cnoc_pcie_slave_east_cfg, + [SLAVE_CNOC_PCIE_SLAVE_WEST_CFG] = &qss_cnoc_pcie_slave_west_cfg, + [SLAVE_LPASS_QTB_CFG] = &qss_lpass_qtb_cfg, + [SLAVE_CNOC_MNOC_CFG] = &qss_mnoc_cfg, + [SLAVE_NSP_QTB_CFG] = &qss_nsp_qtb_cfg, + [SLAVE_PCIE_EAST_ANOC_CFG] = &qss_pcie_east_anoc_cfg, + [SLAVE_PCIE_WEST_ANOC_CFG] = &qss_pcie_west_anoc_cfg, + [SLAVE_QDSS_STM] = &xs_qdss_stm, + [SLAVE_TCU] = &xs_sys_tcu_cfg, +}; + +static const struct regmap_config glymur_cnoc_cfg_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x6600, + .fast_io = true, +}; + +static const struct qcom_icc_desc glymur_cnoc_cfg = { + .config = &glymur_cnoc_cfg_regmap_config, + .nodes = cnoc_cfg_nodes, + .num_nodes = ARRAY_SIZE(cnoc_cfg_nodes), + .bcms = cnoc_cfg_bcms, + .num_bcms = ARRAY_SIZE(cnoc_cfg_bcms), +}; + +static struct qcom_icc_bcm * const cnoc_main_bcms[] = { + &bcm_cn0, +}; + +static struct qcom_icc_node * const cnoc_main_nodes[] = { + [MASTER_HSCNOC_CNOC] = &qnm_hscnoc_cnoc, + [SLAVE_AOSS] = &qhs_aoss, + [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, + [SLAVE_SOCCP] = &qhs_soccp, + [SLAVE_TME_CFG] = &qhs_tme_cfg, + [SLAVE_APPSS] = &qns_apss, + [SLAVE_CNOC_CFG] = &qss_cfg, + [SLAVE_BOOT_IMEM] = &qxs_boot_imem, + [SLAVE_IMEM] = &qxs_imem, +}; + +static const struct regmap_config glymur_cnoc_main_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x17080, + .fast_io = true, +}; + +static const struct qcom_icc_desc glymur_cnoc_main = { + .config = &glymur_cnoc_main_regmap_config, + .nodes = cnoc_main_nodes, + .num_nodes = ARRAY_SIZE(cnoc_main_nodes), + .bcms = cnoc_main_bcms, + .num_bcms = ARRAY_SIZE(cnoc_main_bcms), +}; + +static struct qcom_icc_bcm * const hscnoc_bcms[] = { + &bcm_sh0, + &bcm_sh1, +}; + +static struct qcom_icc_node * const hscnoc_nodes[] = { + [MASTER_GPU_TCU] = &alm_gpu_tcu, + [MASTER_PCIE_TCU] = &alm_pcie_qtc, + [MASTER_SYS_TCU] = &alm_sys_tcu, + [MASTER_APPSS_PROC] = &chm_apps, + [MASTER_AGGRE_NOC_EAST] = &qnm_aggre_noc_east, + [MASTER_GFX3D] = &qnm_gpu, + [MASTER_LPASS_GEM_NOC] = &qnm_lpass, + [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, + [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, + [MASTER_COMPUTE_NOC] = &qnm_nsp_noc, + [MASTER_PCIE_EAST] = &qnm_pcie_east, + [MASTER_PCIE_WEST] = &qnm_pcie_west, + [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, + [MASTER_WLAN_Q6] = &qxm_wlan_q6, + [MASTER_GIC] = &xm_gic, + [SLAVE_HSCNOC_CNOC] = &qns_hscnoc_cnoc, + [SLAVE_LLCC] = &qns_llcc, + [SLAVE_PCIE_EAST] = &qns_pcie_east, + [SLAVE_PCIE_WEST] = &qns_pcie_west, +}; + +static const struct regmap_config glymur_hscnoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x93a080, + .fast_io = true, +}; + +static const struct qcom_icc_desc glymur_hscnoc = { + .config = &glymur_hscnoc_regmap_config, + .nodes = hscnoc_nodes, + .num_nodes = ARRAY_SIZE(hscnoc_nodes), + .bcms = hscnoc_bcms, + .num_bcms = ARRAY_SIZE(hscnoc_bcms), +}; + +static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { + [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc, + [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc, +}; + +static const struct regmap_config glymur_lpass_ag_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xe080, + .fast_io = true, +}; + +static const struct qcom_icc_desc glymur_lpass_ag_noc = { + .config = &glymur_lpass_ag_noc_regmap_config, + .nodes = lpass_ag_noc_nodes, + .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), +}; + +static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = { + &bcm_lp0, +}; + +static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { + [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc, + [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc, +}; + +static const struct regmap_config glymur_lpass_lpiaon_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x19080, + .fast_io = true, +}; + +static const struct qcom_icc_desc glymur_lpass_lpiaon_noc = { + .config = &glymur_lpass_lpiaon_noc_regmap_config, + .nodes = lpass_lpiaon_noc_nodes, + .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), + .bcms = lpass_lpiaon_noc_bcms, + .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms), +}; + +static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { + [MASTER_LPASS_PROC] = &qnm_lpinoc_dsp_qns4m, + [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc, +}; + +static const struct regmap_config glymur_lpass_lpicx_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x44080, + .fast_io = true, +}; + +static const struct qcom_icc_desc glymur_lpass_lpicx_noc = { + .config = &glymur_lpass_lpicx_noc_regmap_config, + .nodes = lpass_lpicx_noc_nodes, + .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), +}; + +static struct qcom_icc_bcm * const mc_virt_bcms[] = { + &bcm_acv, + &bcm_mc0, +}; + +static struct qcom_icc_node * const mc_virt_nodes[] = { + [MASTER_LLCC] = &llcc_mc, + [SLAVE_EBI1] = &ebi, +}; + +static const struct qcom_icc_desc glymur_mc_virt = { + .nodes = mc_virt_nodes, + .num_nodes = ARRAY_SIZE(mc_virt_nodes), + .bcms = mc_virt_bcms, + .num_bcms = ARRAY_SIZE(mc_virt_bcms), +}; + +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { + &bcm_mm0, + &bcm_mm1, +}; + +static struct qcom_icc_node * const mmss_noc_nodes[] = { + [MASTER_AV1_ENC] = &qnm_av1_enc, + [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, + [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, + [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, + [MASTER_EVA] = &qnm_eva, + [MASTER_MDP] = &qnm_mdp, + [MASTER_CDSP_HCP] = &qnm_vapss_hcp, + [MASTER_VIDEO] = &qnm_video, + [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu, + [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, + [MASTER_CNOC_MNOC_CFG] = &qsm_mnoc_cfg, + [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, + [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, + [SLAVE_SERVICE_MNOC] = &srvc_mnoc, +}; + +static const struct regmap_config glymur_mmss_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x5b800, + .fast_io = true, +}; + +static const struct qcom_icc_desc glymur_mmss_noc = { + .config = &glymur_mmss_noc_regmap_config, + .nodes = mmss_noc_nodes, + .num_nodes = ARRAY_SIZE(mmss_noc_nodes), + .bcms = mmss_noc_bcms, + .num_bcms = ARRAY_SIZE(mmss_noc_bcms), +}; + +static struct qcom_icc_node * const nsinoc_nodes[] = { + [MASTER_CPUCP] = &xm_cpucp, + [SLAVE_NSINOC_SYSTEM_NOC] = &qns_system_noc, + [SLAVE_SERVICE_NSINOC] = &srvc_nsinoc, +}; + +static const struct regmap_config glymur_nsinoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x14080, + .fast_io = true, +}; + +static const struct qcom_icc_desc glymur_nsinoc = { + .config = &glymur_nsinoc_regmap_config, + .nodes = nsinoc_nodes, + .num_nodes = ARRAY_SIZE(nsinoc_nodes), +}; + +static struct qcom_icc_bcm * const nsp_noc_bcms[] = { + &bcm_co0, +}; + +static struct qcom_icc_node * const nsp_noc_nodes[] = { + [MASTER_CDSP_PROC] = &qnm_nsp, + [SLAVE_NSP0_HSC_NOC] = &qns_nsp_hscnoc, +}; + +static const struct regmap_config glymur_nsp_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x21280, + .fast_io = true, +}; + +static const struct qcom_icc_desc glymur_nsp_noc = { + .config = &glymur_nsp_noc_regmap_config, + .nodes = nsp_noc_nodes, + .num_nodes = ARRAY_SIZE(nsp_noc_nodes), + .bcms = nsp_noc_bcms, + .num_bcms = ARRAY_SIZE(nsp_noc_bcms), +}; + +static struct qcom_icc_node * const oobm_ss_noc_nodes[] = { + [MASTER_OOBMSS_SP_PROC] = &xm_mem_sp, + [SLAVE_OOBMSS_SNOC] = &qns_oobmss_snoc, +}; + +static const struct regmap_config glymur_oobm_ss_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1e080, + .fast_io = true, +}; + +static const struct qcom_icc_desc glymur_oobm_ss_noc = { + .config = &glymur_oobm_ss_noc_regmap_config, + .nodes = oobm_ss_noc_nodes, + .num_nodes = ARRAY_SIZE(oobm_ss_noc_nodes), +}; + +static struct qcom_icc_bcm * const pcie_east_anoc_bcms[] = { + &bcm_sn6, +}; + +static struct qcom_icc_node * const pcie_east_anoc_nodes[] = { + [MASTER_PCIE_EAST_ANOC_CFG] = &qsm_pcie_east_anoc_cfg, + [MASTER_PCIE_0] = &xm_pcie_0, + [MASTER_PCIE_1] = &xm_pcie_1, + [MASTER_PCIE_5] = &xm_pcie_5, + [SLAVE_PCIE_EAST_MEM_NOC] = &qns_pcie_east_mem_noc, + [SLAVE_SERVICE_PCIE_EAST_AGGRE_NOC] = &srvc_pcie_east_aggre_noc, +}; + +static const struct regmap_config glymur_pcie_east_anoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xf300, + .fast_io = true, +}; + +static const struct qcom_icc_desc glymur_pcie_east_anoc = { + .config = &glymur_pcie_east_anoc_regmap_config, + .nodes = pcie_east_anoc_nodes, + .num_nodes = ARRAY_SIZE(pcie_east_anoc_nodes), + .bcms = pcie_east_anoc_bcms, + .num_bcms = ARRAY_SIZE(pcie_east_anoc_bcms), + .qos_requires_clocks = true, +}; + +static struct qcom_icc_bcm * const pcie_east_slv_noc_bcms[] = { + &bcm_sn6, +}; + +static struct qcom_icc_node * const pcie_east_slv_noc_nodes[] = { + [MASTER_HSCNOC_PCIE_EAST] = &qnm_hscnoc_pcie_east, + [MASTER_CNOC_PCIE_EAST_SLAVE_CFG] = &qsm_cnoc_pcie_east_slave_cfg, + [SLAVE_HSCNOC_PCIE_EAST_MS_MPU_CFG] = &qhs_hscnoc_pcie_east_ms_mpu_cfg, + [SLAVE_SERVICE_PCIE_EAST] = &srvc_pcie_east, + [SLAVE_PCIE_0] = &xs_pcie_0, + [SLAVE_PCIE_1] = &xs_pcie_1, + [SLAVE_PCIE_5] = &xs_pcie_5, +}; + +static const struct regmap_config glymur_pcie_east_slv_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xe080, + .fast_io = true, +}; + +static const struct qcom_icc_desc glymur_pcie_east_slv_noc = { + .config = &glymur_pcie_east_slv_noc_regmap_config, + .nodes = pcie_east_slv_noc_nodes, + .num_nodes = ARRAY_SIZE(pcie_east_slv_noc_nodes), + .bcms = pcie_east_slv_noc_bcms, + .num_bcms = ARRAY_SIZE(pcie_east_slv_noc_bcms), +}; + +static struct qcom_icc_bcm * const pcie_west_anoc_bcms[] = { + &bcm_sn6, +}; + +static struct qcom_icc_node * const pcie_west_anoc_nodes[] = { + [MASTER_PCIE_WEST_ANOC_CFG] = &qsm_pcie_west_anoc_cfg, + [MASTER_PCIE_2] = &xm_pcie_2, + [MASTER_PCIE_3A] = &xm_pcie_3a, + [MASTER_PCIE_3B] = &xm_pcie_3b, + [MASTER_PCIE_4] = &xm_pcie_4, + [MASTER_PCIE_6] = &xm_pcie_6, + [SLAVE_PCIE_WEST_MEM_NOC] = &qns_pcie_west_mem_noc, + [SLAVE_SERVICE_PCIE_WEST_AGGRE_NOC] = &srvc_pcie_west_aggre_noc, +}; + +static const struct regmap_config glymur_pcie_west_anoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xf580, + .fast_io = true, +}; + +static const struct qcom_icc_desc glymur_pcie_west_anoc = { + .config = &glymur_pcie_west_anoc_regmap_config, + .nodes = pcie_west_anoc_nodes, + .num_nodes = ARRAY_SIZE(pcie_west_anoc_nodes), + .bcms = pcie_west_anoc_bcms, + .num_bcms = ARRAY_SIZE(pcie_west_anoc_bcms), + .qos_requires_clocks = true, +}; + +static struct qcom_icc_bcm * const pcie_west_slv_noc_bcms[] = { + &bcm_sn6, +}; + +static struct qcom_icc_node * const pcie_west_slv_noc_nodes[] = { + [MASTER_HSCNOC_PCIE_WEST] = &qnm_hscnoc_pcie_west, + [MASTER_CNOC_PCIE_WEST_SLAVE_CFG] = &qsm_cnoc_pcie_west_slave_cfg, + [SLAVE_HSCNOC_PCIE_WEST_MS_MPU_CFG] = &qhs_hscnoc_pcie_west_ms_mpu_cfg, + [SLAVE_SERVICE_PCIE_WEST] = &srvc_pcie_west, + [SLAVE_PCIE_2] = &xs_pcie_2, + [SLAVE_PCIE_3A] = &xs_pcie_3a, + [SLAVE_PCIE_3B] = &xs_pcie_3b, + [SLAVE_PCIE_4] = &xs_pcie_4, + [SLAVE_PCIE_6] = &xs_pcie_6, +}; + +static const struct regmap_config glymur_pcie_west_slv_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xf180, + .fast_io = true, +}; + +static const struct qcom_icc_desc glymur_pcie_west_slv_noc = { + .config = &glymur_pcie_west_slv_noc_regmap_config, + .nodes = pcie_west_slv_noc_nodes, + .num_nodes = ARRAY_SIZE(pcie_west_slv_noc_nodes), + .bcms = pcie_west_slv_noc_bcms, + .num_bcms = ARRAY_SIZE(pcie_west_slv_noc_bcms), +}; + +static struct qcom_icc_bcm * const system_noc_bcms[] = { + &bcm_sn0, + &bcm_sn1, + &bcm_sn2, + &bcm_sn3, + &bcm_sn4, +}; + +static struct qcom_icc_node * const system_noc_nodes[] = { + [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, + [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, + [MASTER_A3NOC_SNOC] = &qnm_aggre3_noc, + [MASTER_NSINOC_SNOC] = &qnm_nsi_noc, + [MASTER_OOBMSS] = &qnm_oobmss, + [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, +}; + +static const struct regmap_config glymur_system_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1c080, + .fast_io = true, +}; + +static const struct qcom_icc_desc glymur_system_noc = { + .config = &glymur_system_noc_regmap_config, + .nodes = system_noc_nodes, + .num_nodes = ARRAY_SIZE(system_noc_nodes), + .bcms = system_noc_bcms, + .num_bcms = ARRAY_SIZE(system_noc_bcms), +}; + +static const struct of_device_id qnoc_of_match[] = { + { .compatible = "qcom,glymur-aggre1-noc", .data = &glymur_aggre1_noc}, + { .compatible = "qcom,glymur-aggre2-noc", .data = &glymur_aggre2_noc}, + { .compatible = "qcom,glymur-aggre3-noc", .data = &glymur_aggre3_noc}, + { .compatible = "qcom,glymur-aggre4-noc", .data = &glymur_aggre4_noc}, + { .compatible = "qcom,glymur-clk-virt", .data = &glymur_clk_virt}, + { .compatible = "qcom,glymur-cnoc-cfg", .data = &glymur_cnoc_cfg}, + { .compatible = "qcom,glymur-cnoc-main", .data = &glymur_cnoc_main}, + { .compatible = "qcom,glymur-hscnoc", .data = &glymur_hscnoc}, + { .compatible = "qcom,glymur-lpass-ag-noc", .data = &glymur_lpass_ag_noc}, + { .compatible = "qcom,glymur-lpass-lpiaon-noc", .data = &glymur_lpass_lpiaon_noc}, + { .compatible = "qcom,glymur-lpass-lpicx-noc", .data = &glymur_lpass_lpicx_noc}, + { .compatible = "qcom,glymur-mc-virt", .data = &glymur_mc_virt}, + { .compatible = "qcom,glymur-mmss-noc", .data = &glymur_mmss_noc}, + { .compatible = "qcom,glymur-nsinoc", .data = &glymur_nsinoc}, + { .compatible = "qcom,glymur-nsp-noc", .data = &glymur_nsp_noc}, + { .compatible = "qcom,glymur-oobm-ss-noc", .data = &glymur_oobm_ss_noc}, + { .compatible = "qcom,glymur-pcie-east-anoc", .data = &glymur_pcie_east_anoc}, + { .compatible = "qcom,glymur-pcie-east-slv-noc", .data = &glymur_pcie_east_slv_noc}, + { .compatible = "qcom,glymur-pcie-west-anoc", .data = &glymur_pcie_west_anoc}, + { .compatible = "qcom,glymur-pcie-west-slv-noc", .data = &glymur_pcie_west_slv_noc}, + { .compatible = "qcom,glymur-system-noc", .data = &glymur_system_noc}, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver = { + .probe = qcom_icc_rpmh_probe, + .remove = qcom_icc_rpmh_remove, + .driver = { + .name = "qnoc-glymur", + .of_match_table = qnoc_of_match, + .sync_state = icc_sync_state, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION("GLYMUR NoC driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index a8ed435f696c..ea1042d38128 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -503,6 +503,7 @@ int qnoc_probe(struct platform_device *pdev) GFP_KERNEL); if (!data) return -ENOMEM; + data->num_nodes = num_nodes; qp->num_intf_clks = cd_num; for (i = 0; i < cd_num; i++) @@ -597,7 +598,6 @@ regmap_done: data->nodes[i] = node; } - data->num_nodes = num_nodes; clk_bulk_disable_unprepare(qp->num_intf_clks, qp->intf_clks); diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c index f49a8e0cb03c..3b445acefece 100644 --- a/drivers/interconnect/qcom/icc-rpmh.c +++ b/drivers/interconnect/qcom/icc-rpmh.c @@ -280,18 +280,26 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) if (!qn) continue; - node = icc_node_create(qn->id); + if (!qn->node) + qn->node = icc_node_create_dyn(); + + node = qn->node; if (IS_ERR(node)) { ret = PTR_ERR(node); goto err_remove_nodes; } - node->name = qn->name; + ret = icc_node_set_name(node, provider, qn->name); + if (ret) { + icc_node_destroy(node->id); + goto err_remove_nodes; + } + node->data = qn; icc_node_add(node, provider); for (j = 0; j < qn->num_links; j++) - icc_link_create(node, qn->links[j]); + icc_link_nodes(node, &qn->link_nodes[j]->node); data->nodes[i] = node; } @@ -300,18 +308,26 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) struct resource *res; void __iomem *base; - base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); - if (IS_ERR(base)) - goto skip_qos_config; - - qp->regmap = devm_regmap_init_mmio(dev, base, desc->config); - if (IS_ERR(qp->regmap)) { - dev_info(dev, "Skipping QoS, regmap failed; %ld\n", PTR_ERR(qp->regmap)); - goto skip_qos_config; + /* Try parent's regmap first */ + qp->regmap = dev_get_regmap(dev->parent, NULL); + if (!qp->regmap) { + base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(base)) + goto skip_qos_config; + + qp->regmap = devm_regmap_init_mmio(dev, base, desc->config); + if (IS_ERR(qp->regmap)) { + dev_info(dev, "Skipping QoS, regmap failed; %ld\n", + PTR_ERR(qp->regmap)); + goto skip_qos_config; + } } qp->num_clks = devm_clk_bulk_get_all(qp->dev, &qp->clks); - if (qp->num_clks < 0 || (!qp->num_clks && desc->qos_clks_required)) { + if (qp->num_clks == -EPROBE_DEFER) + return dev_err_probe(dev, qp->num_clks, "Failed to get QoS clocks\n"); + + if (qp->num_clks < 0 || (!qp->num_clks && desc->qos_requires_clocks)) { dev_info(dev, "Skipping QoS, failed to get clk: %d\n", qp->num_clks); goto skip_qos_config; } diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h index 14db89850fb3..09d8791402dc 100644 --- a/drivers/interconnect/qcom/icc-rpmh.h +++ b/drivers/interconnect/qcom/icc-rpmh.h @@ -53,7 +53,7 @@ struct bcm_db { u8 reserved; }; -#define MAX_PORTS 2 +#define MAX_PORTS 4 /** * struct qcom_icc_qosbox - Qualcomm specific QoS config @@ -81,8 +81,8 @@ struct qcom_icc_qosbox { /** * struct qcom_icc_node - Qualcomm specific interconnect nodes * @name: the node name used in debugfs - * @links: an array of nodes where we can go next while traversing - * @id: a unique node identifier + * @link_nodes: links associated with this node + * @node: icc_node associated with this node * @num_links: the total number of @links * @channels: num of channels at this node * @buswidth: width of the interconnect between a node and the bus @@ -94,8 +94,7 @@ struct qcom_icc_qosbox { */ struct qcom_icc_node { const char *name; - u16 links[MAX_LINKS]; - u16 id; + struct icc_node *node; u16 num_links; u16 channels; u16 buswidth; @@ -104,6 +103,7 @@ struct qcom_icc_node { struct qcom_icc_bcm *bcms[MAX_BCM_PER_NODE]; size_t num_bcms; const struct qcom_icc_qosbox *qosbox; + struct qcom_icc_node *link_nodes[]; }; /** @@ -153,7 +153,7 @@ struct qcom_icc_desc { size_t num_nodes; struct qcom_icc_bcm * const *bcms; size_t num_bcms; - bool qos_clks_required; + bool qos_requires_clocks; }; int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, diff --git a/drivers/interconnect/qcom/kaanapali.c b/drivers/interconnect/qcom/kaanapali.c new file mode 100644 index 000000000000..d6e7327bfd7f --- /dev/null +++ b/drivers/interconnect/qcom/kaanapali.c @@ -0,0 +1,1855 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + */ + +#include <linux/device.h> +#include <linux/interconnect.h> +#include <linux/interconnect-provider.h> +#include <linux/module.h> +#include <linux/of_platform.h> +#include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h> + +#include "bcm-voter.h" +#include "icc-rpmh.h" + +static struct qcom_icc_node qup0_core_slave = { + .name = "qup0_core_slave", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup1_core_slave = { + .name = "qup1_core_slave", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup2_core_slave = { + .name = "qup2_core_slave", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup3_core_slave = { + .name = "qup3_core_slave", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup4_core_slave = { + .name = "qup4_core_slave", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy0 = { + .name = "qhs_ahb2phy0", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy1 = { + .name = "qhs_ahb2phy1", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display_cfg = { + .name = "qhs_display_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_eva_cfg = { + .name = "qhs_eva_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_i2c = { + .name = "qhs_i2c", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_i3c_ibi0_cfg = { + .name = "qhs_i3c_ibi0_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_i3c_ibi1_cfg = { + .name = "qhs_i3c_ibi1_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipc_router = { + .name = "qhs_ipc_router", + .channels = 4, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mss_cfg = { + .name = "qhs_mss_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie_cfg = { + .name = "qhs_pcie_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qspi = { + .name = "qhs_qspi", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup1 = { + .name = "qhs_qup1", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup2 = { + .name = "qhs_qup2", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup3 = { + .name = "qhs_qup3", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup4 = { + .name = "qhs_qup4", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .name = "qhs_sdc2", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc4 = { + .name = "qhs_sdc4", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_spss_cfg = { + .name = "qhs_spss_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm = { + .name = "qhs_tlmm", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3 = { + .name = "qhs_usb3", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .name = "qhs_vsense_ctrl_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipc_router_fence = { + .name = "qhs_ipc_router_fence", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_soccp = { + .name = "qhs_soccp", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tme_cfg = { + .name = "qhs_tme_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_apss = { + .name = "qns_apss", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qss_ddrss_cfg = { + .name = "qss_ddrss_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qxs_boot_imem = { + .name = "qxs_boot_imem", + .channels = 1, + .buswidth = 16, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_pcie = { + .name = "xs_pcie", + .channels = 1, + .buswidth = 16, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .channels = 4, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_mnoc = { + .name = "srvc_mnoc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_pcie_aggre_noc = { + .name = "srvc_pcie_aggre_noc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup0_core_master = { + .name = "qup0_core_master", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qup0_core_slave }, +}; + +static struct qcom_icc_node qup1_core_master = { + .name = "qup1_core_master", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qup1_core_slave }, +}; + +static struct qcom_icc_node qup2_core_master = { + .name = "qup2_core_master", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qup2_core_slave }, +}; + +static struct qcom_icc_node qup3_core_master = { + .name = "qup3_core_master", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qup3_core_slave }, +}; + +static struct qcom_icc_node qup4_core_master = { + .name = "qup4_core_master", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qup4_core_slave }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie = { + .name = "qnm_gemnoc_pcie", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &xs_pcie }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .channels = 4, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &ebi }, +}; + +static struct qcom_icc_node qsm_mnoc_cfg = { + .name = "qsm_mnoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &srvc_mnoc }, +}; + +static struct qcom_icc_node qsm_pcie_anoc_cfg = { + .name = "qsm_pcie_anoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &srvc_pcie_aggre_noc }, +}; + +static struct qcom_icc_node qss_mnoc_cfg = { + .name = "qss_mnoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qsm_mnoc_cfg }, +}; + +static struct qcom_icc_node qss_pcie_anoc_cfg = { + .name = "qss_pcie_anoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qsm_pcie_anoc_cfg }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .channels = 4, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &llcc_mc }, +}; + +static struct qcom_icc_node qns_pcie = { + .name = "qns_pcie", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qnm_gemnoc_pcie }, +}; + +static struct qcom_icc_node qsm_cfg = { + .name = "qsm_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 35, + .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_crypto0_cfg, &qhs_display_cfg, + &qhs_eva_cfg, &qhs_gpuss_cfg, + &qhs_i2c, &qhs_i3c_ibi0_cfg, + &qhs_i3c_ibi1_cfg, &qhs_imem_cfg, + &qhs_ipc_router, &qhs_mss_cfg, + &qhs_pcie_cfg, &qhs_prng, + &qhs_qdss_cfg, &qhs_qspi, + &qhs_qup1, &qhs_qup2, + &qhs_qup3, &qhs_qup4, + &qhs_sdc2, &qhs_sdc4, + &qhs_spss_cfg, &qhs_tcsr, + &qhs_tlmm, &qhs_ufs_mem_cfg, + &qhs_usb3, &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, &qss_mnoc_cfg, + &qss_pcie_anoc_cfg, &xs_qdss_stm, + &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_node qnm_qpace = { + .name = "qnm_qpace", + .channels = 1, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x14e000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = { &qns_llcc }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x145000 }, + .prio = 4, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_llcc }, +}; + +static struct qcom_icc_node qss_cfg = { + .name = "qss_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qsm_cfg }, +}; + +static struct qcom_icc_node qnm_gemnoc_cnoc = { + .name = "qnm_gemnoc_cnoc", + .channels = 1, + .buswidth = 16, + .num_links = 10, + .link_nodes = { &qhs_aoss, &qhs_ipa, + &qhs_ipc_router_fence, &qhs_soccp, + &qhs_tme_cfg, &qns_apss, + &qss_cfg, &qss_ddrss_cfg, + &qxs_boot_imem, &qxs_imem }, +}; + +static struct qcom_icc_node qns_gem_noc_cnoc = { + .name = "qns_gem_noc_cnoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_gemnoc_cnoc }, +}; + +static struct qcom_icc_node alm_gpu_tcu = { + .name = "alm_gpu_tcu", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x13d000 }, + .prio = 1, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node alm_sys_tcu = { + .name = "alm_sys_tcu", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x13f000 }, + .prio = 6, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node chm_apps = { + .name = "chm_apps", + .channels = 4, + .buswidth = 32, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_gpu = { + .name = "qnm_gpu", + .channels = 2, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0x31000, 0xb1000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_lpass_gemnoc = { + .name = "qnm_lpass_gemnoc", + .channels = 1, + .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x141000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_mdsp = { + .name = "qnm_mdsp", + .channels = 1, + .buswidth = 16, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .channels = 2, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0x33000, 0xb3000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .channels = 2, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0x35000, 0xb5000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_nsp_gemnoc = { + .name = "qnm_nsp_gemnoc", + .channels = 2, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0x37000, 0xb7000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_pcie = { + .name = "qnm_pcie", + .channels = 1, + .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x143000 }, + .prio = 2, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .channels = 1, + .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x147000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_wlan_q6 = { + .name = "qnm_wlan_q6", + .channels = 1, + .buswidth = 8, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { + .name = "qns_lpass_ag_noc_gemnoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_lpass_gemnoc }, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_mnoc_hf }, +}; + +static struct qcom_icc_node qns_mem_noc_sf = { + .name = "qns_mem_noc_sf", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_mnoc_sf }, +}; + +static struct qcom_icc_node qns_nsp_gemnoc = { + .name = "qns_nsp_gemnoc", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_nsp_gemnoc }, +}; + +static struct qcom_icc_node qns_pcie_gemnoc = { + .name = "qns_pcie_gemnoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_pcie }, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_snoc_sf }, +}; + +static struct qcom_icc_node qnm_lpiaon_noc = { + .name = "qnm_lpiaon_noc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_lpass_ag_noc_gemnoc }, +}; + +static struct qcom_icc_node qnm_camnoc_hf = { + .name = "qnm_camnoc_hf", + .channels = 2, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0x2a000, 0x2b000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qnm_camnoc_nrt_icp_sf = { + .name = "qnm_camnoc_nrt_icp_sf", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x2c000 }, + .prio = 4, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_camnoc_rt_cdm_sf = { + .name = "qnm_camnoc_rt_cdm_sf", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x38000 }, + .prio = 2, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_camnoc_sf = { + .name = "qnm_camnoc_sf", + .channels = 2, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0x2d000, 0x2e000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_mdp = { + .name = "qnm_mdp", + .channels = 2, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0x2f000, 0x30000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qnm_mdss_dcp = { + .name = "qnm_mdss_dcp", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x39000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_vapss_hcp = { + .name = "qnm_vapss_hcp", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_cv_cpu = { + .name = "qnm_video_cv_cpu", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x34000 }, + .prio = 4, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_eva = { + .name = "qnm_video_eva", + .channels = 2, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0x35000, 0x36000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_mvp = { + .name = "qnm_video_mvp", + .channels = 2, + .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0x32000, 0x33000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, + }, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_v_cpu = { + .name = "qnm_video_v_cpu", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x37000 }, + .prio = 4, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_nsp = { + .name = "qnm_nsp", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_nsp_gemnoc }, +}; + +static struct qcom_icc_node xm_pcie = { + .name = "xm_pcie", + .channels = 1, + .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xb000 }, + .prio = 3, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_pcie_gemnoc }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_apss_noc = { + .name = "qnm_apss_noc", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x1e000 }, + .prio = 2, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_cnoc_data = { + .name = "qnm_cnoc_data", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x1f000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_node qns_lpass_aggnoc = { + .name = "qns_lpass_aggnoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_lpiaon_noc }, +}; + +static struct qcom_icc_node qhm_qspi = { + .name = "qhm_qspi", + .channels = 1, + .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xc000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .channels = 1, + .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x36000 }, + .prio = 2, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qxm_qup1 = { + .name = "qxm_qup1", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x11000 }, + .prio = 2, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_sdc4 = { + .name = "xm_sdc4", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xe000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .channels = 1, + .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xf000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_usb3 = { + .name = "xm_usb3", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x10000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qhm_qup2 = { + .name = "qhm_qup2", + .channels = 1, + .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x35000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qhm_qup3 = { + .name = "qhm_qup3", + .channels = 1, + .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x3c000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qhm_qup4 = { + .name = "qhm_qup4", + .channels = 1, + .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x3d000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x37000 }, + .prio = 2, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qxm_soccp = { + .name = "qxm_soccp", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x3b000 }, + .prio = 2, + .urg_fwd = 1, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qxm_sp = { + .name = "qxm_sp", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node xm_qdss_etr_0 = { + .name = "xm_qdss_etr_0", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x38000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node xm_qdss_etr_1 = { + .name = "xm_qdss_etr_1", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x39000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node xm_sdc2 = { + .name = "xm_sdc2", + .channels = 1, + .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x3a000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, + }, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qnm_lpass_lpinoc = { + .name = "qnm_lpass_lpinoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_lpass_aggnoc }, +}; + +static struct qcom_icc_node qns_lpi_aon_noc = { + .name = "qns_lpi_aon_noc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_lpass_lpinoc }, +}; + +static struct qcom_icc_node qnm_lpinoc_dsp_qns4m = { + .name = "qnm_lpinoc_dsp_qns4m", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_lpi_aon_noc }, +}; + +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .enable_mask = BIT(3), + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .enable_mask = BIT(0), + .keepalive = true, + .num_nodes = 43, + .nodes = { &qsm_cfg, &qhs_ahb2phy0, + &qhs_ahb2phy1, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_crypto0_cfg, + &qhs_eva_cfg, &qhs_gpuss_cfg, + &qhs_i3c_ibi0_cfg, &qhs_i3c_ibi1_cfg, + &qhs_imem_cfg, &qhs_ipc_router, + &qhs_mss_cfg, &qhs_pcie_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_sdc2, + &qhs_sdc4, &qhs_spss_cfg, + &qhs_tcsr, &qhs_tlmm, + &qhs_ufs_mem_cfg, &qhs_usb3, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qss_mnoc_cfg, &qss_pcie_anoc_cfg, + &xs_qdss_stm, &xs_sys_tcu_cfg, + &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, + &qhs_aoss, &qhs_ipa, + &qhs_ipc_router_fence, &qhs_soccp, + &qhs_tme_cfg, &qns_apss, + &qss_cfg, &qss_ddrss_cfg, + &qxs_boot_imem, &qxs_imem, + &xs_pcie }, +}; + +static struct qcom_icc_bcm bcm_cn1 = { + .name = "CN1", + .num_nodes = 6, + .nodes = { &qhs_display_cfg, &qhs_i2c, + &qhs_qup1, &qhs_qup2, + &qhs_qup3, &qhs_qup4 }, +}; + +static struct qcom_icc_bcm bcm_co0 = { + .name = "CO0", + .enable_mask = BIT(0), + .num_nodes = 2, + .nodes = { &qnm_nsp, &qns_nsp_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_lp0 = { + .name = "LP0", + .num_nodes = 2, + .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .enable_mask = BIT(0), + .num_nodes = 9, + .nodes = { &qnm_camnoc_hf, &qnm_camnoc_nrt_icp_sf, + &qnm_camnoc_rt_cdm_sf, &qnm_camnoc_sf, + &qnm_vapss_hcp, &qnm_video_cv_cpu, + &qnm_video_mvp, &qnm_video_v_cpu, + &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_qpc0 = { + .name = "QPC0", + .num_nodes = 1, + .nodes = { &qnm_qpace }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .keepalive = true, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup0_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup1 = { + .name = "QUP1", + .keepalive = true, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup1_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup2 = { + .name = "QUP2", + .keepalive = true, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup2_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup3 = { + .name = "QUP3", + .keepalive = true, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup3_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup4 = { + .name = "QUP4", + .keepalive = true, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup4_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh1 = { + .name = "SH1", + .enable_mask = BIT(0), + .num_nodes = 14, + .nodes = { &alm_gpu_tcu, &alm_sys_tcu, + &chm_apps, &qnm_gpu, + &qnm_mdsp, &qnm_mnoc_hf, + &qnm_mnoc_sf, &qnm_nsp_gemnoc, + &qnm_pcie, &qnm_snoc_sf, + &qnm_wlan_q6, &xm_gic, + &qns_gem_noc_cnoc, &qns_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .num_nodes = 1, + .nodes = { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .num_nodes = 1, + .nodes = { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .num_nodes = 1, + .nodes = { &qns_pcie_gemnoc }, +}; + +static struct qcom_icc_bcm * const aggre_noc_bcms[] = { + &bcm_ce0, +}; + +static struct qcom_icc_node * const aggre_noc_nodes[] = { + [MASTER_QSPI_0] = &qhm_qspi, + [MASTER_CRYPTO] = &qxm_crypto, + [MASTER_QUP_1] = &qxm_qup1, + [MASTER_SDCC_4] = &xm_sdc4, + [MASTER_UFS_MEM] = &xm_ufs_mem, + [MASTER_USB3] = &xm_usb3, + [MASTER_QUP_2] = &qhm_qup2, + [MASTER_QUP_3] = &qhm_qup3, + [MASTER_QUP_4] = &qhm_qup4, + [MASTER_IPA] = &qxm_ipa, + [MASTER_SOCCP_PROC] = &qxm_soccp, + [MASTER_SP] = &qxm_sp, + [MASTER_QDSS_ETR] = &xm_qdss_etr_0, + [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, + [MASTER_SDCC_2] = &xm_sdc2, + [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, + [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, +}; + +static const struct regmap_config kaanapali_aggre_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x42400, + .fast_io = true, +}; + +static const struct qcom_icc_desc kaanapali_aggre_noc = { + .config = &kaanapali_aggre_noc_regmap_config, + .nodes = aggre_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre_noc_nodes), + .bcms = aggre_noc_bcms, + .num_bcms = ARRAY_SIZE(aggre_noc_bcms), + .qos_requires_clocks = true, +}; + +static struct qcom_icc_bcm * const clk_virt_bcms[] = { + &bcm_qup0, + &bcm_qup1, + &bcm_qup2, + &bcm_qup3, + &bcm_qup4, +}; + +static struct qcom_icc_node * const clk_virt_nodes[] = { + [MASTER_QUP_CORE_0] = &qup0_core_master, + [MASTER_QUP_CORE_1] = &qup1_core_master, + [MASTER_QUP_CORE_2] = &qup2_core_master, + [MASTER_QUP_CORE_3] = &qup3_core_master, + [MASTER_QUP_CORE_4] = &qup4_core_master, + [SLAVE_QUP_CORE_0] = &qup0_core_slave, + [SLAVE_QUP_CORE_1] = &qup1_core_slave, + [SLAVE_QUP_CORE_2] = &qup2_core_slave, + [SLAVE_QUP_CORE_3] = &qup3_core_slave, + [SLAVE_QUP_CORE_4] = &qup4_core_slave, +}; + +static const struct qcom_icc_desc kaanapali_clk_virt = { + .nodes = clk_virt_nodes, + .num_nodes = ARRAY_SIZE(clk_virt_nodes), + .bcms = clk_virt_bcms, + .num_bcms = ARRAY_SIZE(clk_virt_bcms), +}; + +static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = { + &bcm_cn0, + &bcm_cn1, +}; + +static struct qcom_icc_node * const cnoc_cfg_nodes[] = { + [MASTER_CNOC_CFG] = &qsm_cfg, + [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, + [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, + [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, + [SLAVE_CLK_CTL] = &qhs_clk_ctl, + [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, + [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, + [SLAVE_EVA_CFG] = &qhs_eva_cfg, + [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, + [SLAVE_I2C] = &qhs_i2c, + [SLAVE_I3C_IBI0_CFG] = &qhs_i3c_ibi0_cfg, + [SLAVE_I3C_IBI1_CFG] = &qhs_i3c_ibi1_cfg, + [SLAVE_IMEM_CFG] = &qhs_imem_cfg, + [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, + [SLAVE_CNOC_MSS] = &qhs_mss_cfg, + [SLAVE_PCIE_CFG] = &qhs_pcie_cfg, + [SLAVE_PRNG] = &qhs_prng, + [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, + [SLAVE_QSPI_0] = &qhs_qspi, + [SLAVE_QUP_1] = &qhs_qup1, + [SLAVE_QUP_2] = &qhs_qup2, + [SLAVE_QUP_3] = &qhs_qup3, + [SLAVE_QUP_4] = &qhs_qup4, + [SLAVE_SDCC_2] = &qhs_sdc2, + [SLAVE_SDCC_4] = &qhs_sdc4, + [SLAVE_SPSS_CFG] = &qhs_spss_cfg, + [SLAVE_TCSR] = &qhs_tcsr, + [SLAVE_TLMM] = &qhs_tlmm, + [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, + [SLAVE_USB3] = &qhs_usb3, + [SLAVE_VENUS_CFG] = &qhs_venus_cfg, + [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, + [SLAVE_CNOC_MNOC_CFG] = &qss_mnoc_cfg, + [SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg, + [SLAVE_QDSS_STM] = &xs_qdss_stm, + [SLAVE_TCU] = &xs_sys_tcu_cfg, +}; + +static const struct regmap_config kaanapali_cnoc_cfg_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x6200, + .fast_io = true, +}; + +static const struct qcom_icc_desc kaanapali_cnoc_cfg = { + .config = &kaanapali_cnoc_cfg_regmap_config, + .nodes = cnoc_cfg_nodes, + .num_nodes = ARRAY_SIZE(cnoc_cfg_nodes), + .bcms = cnoc_cfg_bcms, + .num_bcms = ARRAY_SIZE(cnoc_cfg_bcms), +}; + +static struct qcom_icc_bcm * const cnoc_main_bcms[] = { + &bcm_cn0, +}; + +static struct qcom_icc_node * const cnoc_main_nodes[] = { + [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, + [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, + [SLAVE_AOSS] = &qhs_aoss, + [SLAVE_IPA_CFG] = &qhs_ipa, + [SLAVE_IPC_ROUTER_FENCE] = &qhs_ipc_router_fence, + [SLAVE_SOCCP] = &qhs_soccp, + [SLAVE_TME_CFG] = &qhs_tme_cfg, + [SLAVE_APPSS] = &qns_apss, + [SLAVE_CNOC_CFG] = &qss_cfg, + [SLAVE_DDRSS_CFG] = &qss_ddrss_cfg, + [SLAVE_BOOT_IMEM] = &qxs_boot_imem, + [SLAVE_IMEM] = &qxs_imem, + [SLAVE_PCIE_0] = &xs_pcie, +}; + +static const struct regmap_config kaanapali_cnoc_main_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1a080, + .fast_io = true, +}; + +static const struct qcom_icc_desc kaanapali_cnoc_main = { + .config = &kaanapali_cnoc_main_regmap_config, + .nodes = cnoc_main_nodes, + .num_nodes = ARRAY_SIZE(cnoc_main_nodes), + .bcms = cnoc_main_bcms, + .num_bcms = ARRAY_SIZE(cnoc_main_bcms), +}; + +static struct qcom_icc_bcm * const gem_noc_bcms[] = { + &bcm_qpc0, + &bcm_sh0, + &bcm_sh1, +}; + +static struct qcom_icc_node * const gem_noc_nodes[] = { + [MASTER_GPU_TCU] = &alm_gpu_tcu, + [MASTER_SYS_TCU] = &alm_sys_tcu, + [MASTER_APPSS_PROC] = &chm_apps, + [MASTER_GFX3D] = &qnm_gpu, + [MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc, + [MASTER_MSS_PROC] = &qnm_mdsp, + [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, + [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, + [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc, + [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, + [MASTER_QPACE] = &qnm_qpace, + [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, + [MASTER_WLAN_Q6] = &qnm_wlan_q6, + [MASTER_GIC] = &xm_gic, + [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, + [SLAVE_LLCC] = &qns_llcc, + [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, +}; + +static const struct regmap_config kaanapali_gem_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x153080, + .fast_io = true, +}; + +static const struct qcom_icc_desc kaanapali_gem_noc = { + .config = &kaanapali_gem_noc_regmap_config, + .nodes = gem_noc_nodes, + .num_nodes = ARRAY_SIZE(gem_noc_nodes), + .bcms = gem_noc_bcms, + .num_bcms = ARRAY_SIZE(gem_noc_bcms), +}; + +static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { + [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc, + [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc, +}; + +static const struct regmap_config kaanapali_lpass_ag_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xe080, + .fast_io = true, +}; + +static const struct qcom_icc_desc kaanapali_lpass_ag_noc = { + .config = &kaanapali_lpass_ag_noc_regmap_config, + .nodes = lpass_ag_noc_nodes, + .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), +}; + +static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = { + &bcm_lp0, +}; + +static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { + [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc, + [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc, +}; + +static const struct regmap_config kaanapali_lpass_lpiaon_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x19080, + .fast_io = true, +}; + +static const struct qcom_icc_desc kaanapali_lpass_lpiaon_noc = { + .config = &kaanapali_lpass_lpiaon_noc_regmap_config, + .nodes = lpass_lpiaon_noc_nodes, + .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), + .bcms = lpass_lpiaon_noc_bcms, + .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms), +}; + +static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { + [MASTER_LPASS_PROC] = &qnm_lpinoc_dsp_qns4m, + [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc, +}; + +static const struct regmap_config kaanapali_lpass_lpicx_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x44080, + .fast_io = true, +}; + +static const struct qcom_icc_desc kaanapali_lpass_lpicx_noc = { + .config = &kaanapali_lpass_lpicx_noc_regmap_config, + .nodes = lpass_lpicx_noc_nodes, + .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), +}; + +static struct qcom_icc_bcm * const mc_virt_bcms[] = { + &bcm_acv, + &bcm_mc0, +}; + +static struct qcom_icc_node * const mc_virt_nodes[] = { + [MASTER_LLCC] = &llcc_mc, + [SLAVE_EBI1] = &ebi, +}; + +static const struct qcom_icc_desc kaanapali_mc_virt = { + .nodes = mc_virt_nodes, + .num_nodes = ARRAY_SIZE(mc_virt_nodes), + .bcms = mc_virt_bcms, + .num_bcms = ARRAY_SIZE(mc_virt_bcms), +}; + +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { + &bcm_mm0, + &bcm_mm1, +}; + +static struct qcom_icc_node * const mmss_noc_nodes[] = { + [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, + [MASTER_CAMNOC_NRT_ICP_SF] = &qnm_camnoc_nrt_icp_sf, + [MASTER_CAMNOC_RT_CDM_SF] = &qnm_camnoc_rt_cdm_sf, + [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, + [MASTER_MDP] = &qnm_mdp, + [MASTER_MDSS_DCP] = &qnm_mdss_dcp, + [MASTER_CDSP_HCP] = &qnm_vapss_hcp, + [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu, + [MASTER_VIDEO_EVA] = &qnm_video_eva, + [MASTER_VIDEO_MVP] = &qnm_video_mvp, + [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, + [MASTER_CNOC_MNOC_CFG] = &qsm_mnoc_cfg, + [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, + [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, + [SLAVE_SERVICE_MNOC] = &srvc_mnoc, +}; + +static const struct regmap_config kaanapali_mmss_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x5b800, + .fast_io = true, +}; + +static const struct qcom_icc_desc kaanapali_mmss_noc = { + .config = &kaanapali_mmss_noc_regmap_config, + .nodes = mmss_noc_nodes, + .num_nodes = ARRAY_SIZE(mmss_noc_nodes), + .bcms = mmss_noc_bcms, + .num_bcms = ARRAY_SIZE(mmss_noc_bcms), +}; + +static struct qcom_icc_bcm * const nsp_noc_bcms[] = { + &bcm_co0, +}; + +static struct qcom_icc_node * const nsp_noc_nodes[] = { + [MASTER_CDSP_PROC] = &qnm_nsp, + [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, +}; + +static const struct regmap_config kaanapali_nsp_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x21280, + .fast_io = true, +}; + +static const struct qcom_icc_desc kaanapali_nsp_noc = { + .config = &kaanapali_nsp_noc_regmap_config, + .nodes = nsp_noc_nodes, + .num_nodes = ARRAY_SIZE(nsp_noc_nodes), + .bcms = nsp_noc_bcms, + .num_bcms = ARRAY_SIZE(nsp_noc_bcms), +}; + +static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { + &bcm_sn4, +}; + +static struct qcom_icc_node * const pcie_anoc_nodes[] = { + [MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg, + [MASTER_PCIE_0] = &xm_pcie, + [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc, + [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc, +}; + +static const struct regmap_config kaanapali_pcie_anoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x11400, + .fast_io = true, +}; + +static const struct qcom_icc_desc kaanapali_pcie_anoc = { + .config = &kaanapali_pcie_anoc_regmap_config, + .nodes = pcie_anoc_nodes, + .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), + .bcms = pcie_anoc_bcms, + .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), + .qos_requires_clocks = true, +}; + +static struct qcom_icc_bcm * const system_noc_bcms[] = { + &bcm_sn0, + &bcm_sn2, + &bcm_sn3, +}; + +static struct qcom_icc_node * const system_noc_nodes[] = { + [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, + [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, + [MASTER_APSS_NOC] = &qnm_apss_noc, + [MASTER_CNOC_SNOC] = &qnm_cnoc_data, + [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, +}; + +static const struct regmap_config kaanapali_system_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1f080, + .fast_io = true, +}; + +static const struct qcom_icc_desc kaanapali_system_noc = { + .config = &kaanapali_system_noc_regmap_config, + .nodes = system_noc_nodes, + .num_nodes = ARRAY_SIZE(system_noc_nodes), + .bcms = system_noc_bcms, + .num_bcms = ARRAY_SIZE(system_noc_bcms), +}; + +static const struct of_device_id qnoc_of_match[] = { + { .compatible = "qcom,kaanapali-aggre-noc", .data = &kaanapali_aggre_noc }, + { .compatible = "qcom,kaanapali-clk-virt", .data = &kaanapali_clk_virt }, + { .compatible = "qcom,kaanapali-cnoc-cfg", .data = &kaanapali_cnoc_cfg }, + { .compatible = "qcom,kaanapali-cnoc-main", .data = &kaanapali_cnoc_main }, + { .compatible = "qcom,kaanapali-gem-noc", .data = &kaanapali_gem_noc }, + { .compatible = "qcom,kaanapali-lpass-ag-noc", .data = &kaanapali_lpass_ag_noc }, + { .compatible = "qcom,kaanapali-lpass-lpiaon-noc", .data = &kaanapali_lpass_lpiaon_noc }, + { .compatible = "qcom,kaanapali-lpass-lpicx-noc", .data = &kaanapali_lpass_lpicx_noc }, + { .compatible = "qcom,kaanapali-mc-virt", .data = &kaanapali_mc_virt }, + { .compatible = "qcom,kaanapali-mmss-noc", .data = &kaanapali_mmss_noc }, + { .compatible = "qcom,kaanapali-nsp-noc", .data = &kaanapali_nsp_noc }, + { .compatible = "qcom,kaanapali-pcie-anoc", .data = &kaanapali_pcie_anoc }, + { .compatible = "qcom,kaanapali-system-noc", .data = &kaanapali_system_noc }, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver = { + .probe = qcom_icc_rpmh_probe, + .remove = qcom_icc_rpmh_remove, + .driver = { + .name = "qnoc-kaanapali", + .of_match_table = qnoc_of_match, + .sync_state = icc_sync_state, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION("Qualcomm Kaanapali NoC driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/interconnect/qcom/milos.c b/drivers/interconnect/qcom/milos.c new file mode 100644 index 000000000000..d010b106728a --- /dev/null +++ b/drivers/interconnect/qcom/milos.c @@ -0,0 +1,1919 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com> + */ + +#include <linux/device.h> +#include <linux/interconnect-provider.h> +#include <linux/interconnect.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <dt-bindings/interconnect/qcom,milos-rpmh.h> + +#include "bcm-voter.h" +#include "icc-common.h" +#include "icc-rpmh.h" + +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qsm_cfg; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_lpass_gemnoc; +static struct qcom_icc_node qnm_mdsp; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_nsp_gemnoc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_wlan_q6; +static struct qcom_icc_node qxm_lpass_dsp; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_mdp; +static struct qcom_icc_node qnm_video; +static struct qcom_icc_node qsm_hf_mnoc_cfg; +static struct qcom_icc_node qsm_sf_mnoc_cfg; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node qsm_pcie_anoc_cfg; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_apss_noc; +static struct qcom_icc_node qnm_cnoc_data; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mxa; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_mx_2_rdpm; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qhs_wlan_q6; +static struct qcom_icc_node qss_mnoc_hf_cfg; +static struct qcom_icc_node qss_mnoc_sf_cfg; +static struct qcom_icc_node qss_nsp_qtb_cfg; +static struct qcom_icc_node qss_pcie_anoc_cfg; +static struct qcom_icc_node qss_wlan_q6_throttle_cfg; +static struct qcom_icc_node srvc_cnoc_cfg; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qss_apss; +static struct qcom_icc_node qss_cfg; +static struct qcom_icc_node qss_ddrss_cfg; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_cnoc_main; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc_hf; +static struct qcom_icc_node srvc_mnoc_sf; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_pcie_aggre_noc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; + +static struct qcom_icc_qosbox qhm_qup1_qos = { + .num_ports = 1, + .port_offsets = { 0xc000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node qhm_qup1 = { + .name = "qhm_qup1", + .channels = 1, + .buswidth = 4, + .qosbox = &qhm_qup1_qos, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_qosbox xm_ufs_mem_qos = { + .num_ports = 1, + .port_offsets = { 0xf200 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .channels = 1, + .buswidth = 8, + .qosbox = &xm_ufs_mem_qos, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_qosbox xm_usb3_0_qos = { + .num_ports = 1, + .port_offsets = { 0x10000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node xm_usb3_0 = { + .name = "xm_usb3_0", + .channels = 1, + .buswidth = 8, + .qosbox = &xm_usb3_0_qos, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_qosbox qhm_qdss_bam_qos = { + .num_ports = 1, + .port_offsets = { 0x14000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .channels = 1, + .buswidth = 4, + .qosbox = &qhm_qdss_bam_qos, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_qosbox qhm_qspi_qos = { + .num_ports = 1, + .port_offsets = { 0x12000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node qhm_qspi = { + .name = "qhm_qspi", + .channels = 1, + .buswidth = 4, + .qosbox = &qhm_qspi_qos, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_qosbox qhm_qup0_qos = { + .num_ports = 1, + .port_offsets = { 0x13000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node qhm_qup0 = { + .name = "qhm_qup0", + .channels = 1, + .buswidth = 4, + .qosbox = &qhm_qup0_qos, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_qosbox qxm_crypto_qos = { + .num_ports = 1, + .port_offsets = { 0x15000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .channels = 1, + .buswidth = 8, + .qosbox = &qxm_crypto_qos, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_qosbox qxm_ipa_qos = { + .num_ports = 1, + .port_offsets = { 0x16000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .channels = 1, + .buswidth = 8, + .qosbox = &qxm_ipa_qos, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_qosbox xm_qdss_etr_0_qos = { + .num_ports = 1, + .port_offsets = { 0x17000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node xm_qdss_etr_0 = { + .name = "xm_qdss_etr_0", + .channels = 1, + .buswidth = 8, + .qosbox = &xm_qdss_etr_0_qos, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_qosbox xm_qdss_etr_1_qos = { + .num_ports = 1, + .port_offsets = { 0x18000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node xm_qdss_etr_1 = { + .name = "xm_qdss_etr_1", + .channels = 1, + .buswidth = 8, + .qosbox = &xm_qdss_etr_1_qos, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_qosbox xm_sdc1_qos = { + .num_ports = 1, + .port_offsets = { 0x1a000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node xm_sdc1 = { + .name = "xm_sdc1", + .channels = 1, + .buswidth = 8, + .qosbox = &xm_sdc1_qos, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_qosbox xm_sdc2_qos = { + .num_ports = 1, + .port_offsets = { 0x19000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node xm_sdc2 = { + .name = "xm_sdc2", + .channels = 1, + .buswidth = 8, + .qosbox = &xm_sdc2_qos, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qup0_core_master = { + .name = "qup0_core_master", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qup0_core_slave }, +}; + +static struct qcom_icc_node qup1_core_master = { + .name = "qup1_core_master", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qup1_core_slave }, +}; + +static struct qcom_icc_node qsm_cfg = { + .name = "qsm_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 35, + .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_cpr_cx, &qhs_cpr_mxa, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_gpuss_cfg, &qhs_imem_cfg, + &qhs_mss_cfg, &qhs_mx_2_rdpm, + &qhs_mx_rdpm, &qhs_pdm, + &qhs_qdss_cfg, &qhs_qspi, + &qhs_qup0, &qhs_qup1, + &qhs_sdc1, &qhs_sdc2, + &qhs_tcsr, &qhs_tlmm, + &qhs_ufs_mem_cfg, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qhs_wlan_q6, &qss_mnoc_hf_cfg, + &qss_mnoc_sf_cfg, &qss_nsp_qtb_cfg, + &qss_pcie_anoc_cfg, &qss_wlan_q6_throttle_cfg, + &srvc_cnoc_cfg, &xs_qdss_stm, + &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_node qnm_gemnoc_cnoc = { + .name = "qnm_gemnoc_cnoc", + .channels = 1, + .buswidth = 16, + .num_links = 14, + .link_nodes = { &qhs_aoss, &qhs_display_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_prng, &qhs_tme_cfg, + &qss_apss, &qss_cfg, + &qss_ddrss_cfg, &qxs_imem, + &qxs_pimem, &srvc_cnoc_main }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie = { + .name = "qnm_gemnoc_pcie", + .channels = 1, + .buswidth = 8, + .num_links = 2, + .link_nodes = { &xs_pcie_0, &xs_pcie_1 }, +}; + +static struct qcom_icc_qosbox alm_gpu_tcu_qos = { + .num_ports = 1, + .port_offsets = { 0xf1000 }, + .prio = 1, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node alm_gpu_tcu = { + .name = "alm_gpu_tcu", + .channels = 1, + .buswidth = 8, + .qosbox = &alm_gpu_tcu_qos, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_qosbox alm_sys_tcu_qos = { + .num_ports = 1, + .port_offsets = { 0xf3000 }, + .prio = 6, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node alm_sys_tcu = { + .name = "alm_sys_tcu", + .channels = 1, + .buswidth = 8, + .qosbox = &alm_sys_tcu_qos, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node chm_apps = { + .name = "chm_apps", + .channels = 3, + .buswidth = 32, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_qosbox qnm_gpu_qos = { + .num_ports = 2, + .port_offsets = { 0x31000, 0x71000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node qnm_gpu = { + .name = "qnm_gpu", + .channels = 2, + .buswidth = 32, + .qosbox = &qnm_gpu_qos, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = { + .num_ports = 1, + .port_offsets = { 0xf5000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, +}; + +static struct qcom_icc_node qnm_lpass_gemnoc = { + .name = "qnm_lpass_gemnoc", + .channels = 1, + .buswidth = 16, + .qosbox = &qnm_lpass_gemnoc_qos, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_mdsp = { + .name = "qnm_mdsp", + .channels = 1, + .buswidth = 16, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_qosbox qnm_mnoc_hf_qos = { + .num_ports = 2, + .port_offsets = { 0x33000, 0x73000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .channels = 2, + .buswidth = 32, + .qosbox = &qnm_mnoc_hf_qos, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_qosbox qnm_mnoc_sf_qos = { + .num_ports = 2, + .port_offsets = { 0x35000, 0x75000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .channels = 2, + .buswidth = 32, + .qosbox = &qnm_mnoc_sf_qos, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = { + .num_ports = 2, + .port_offsets = { 0x37000, 0x77000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node qnm_nsp_gemnoc = { + .name = "qnm_nsp_gemnoc", + .channels = 2, + .buswidth = 32, + .qosbox = &qnm_nsp_gemnoc_qos, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_qosbox qnm_pcie_qos = { + .num_ports = 1, + .port_offsets = { 0xf7000 }, + .prio = 2, + .urg_fwd = 1, + .prio_fwd_disable = 0, +}; + +static struct qcom_icc_node qnm_pcie = { + .name = "qnm_pcie", + .channels = 1, + .buswidth = 8, + .qosbox = &qnm_pcie_qos, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_qosbox qnm_snoc_gc_qos = { + .num_ports = 1, + .port_offsets = { 0xf9000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .channels = 1, + .buswidth = 8, + .qosbox = &qnm_snoc_gc_qos, + .num_links = 1, + .link_nodes = { &qns_llcc }, +}; + +static struct qcom_icc_qosbox qnm_snoc_sf_qos = { + .num_ports = 1, + .port_offsets = { 0xfb000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .channels = 1, + .buswidth = 16, + .qosbox = &qnm_snoc_sf_qos, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qxm_wlan_q6 = { + .name = "qxm_wlan_q6", + .channels = 1, + .buswidth = 8, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qxm_lpass_dsp = { + .name = "qxm_lpass_dsp", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_lpass_ag_noc_gemnoc }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .channels = 2, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &ebi }, +}; + +static struct qcom_icc_qosbox qnm_camnoc_hf_qos = { + .num_ports = 2, + .port_offsets = { 0xa8000, 0xa9000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, +}; + +static struct qcom_icc_node qnm_camnoc_hf = { + .name = "qnm_camnoc_hf", + .channels = 2, + .buswidth = 32, + .qosbox = &qnm_camnoc_hf_qos, + .num_links = 1, + .link_nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_qosbox qnm_camnoc_icp_qos = { + .num_ports = 1, + .port_offsets = { 0x2a000 }, + .prio = 5, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node qnm_camnoc_icp = { + .name = "qnm_camnoc_icp", + .channels = 1, + .buswidth = 8, + .qosbox = &qnm_camnoc_icp_qos, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_qosbox qnm_camnoc_sf_qos = { + .num_ports = 2, + .port_offsets = { 0x2b000, 0x2c000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, +}; + +static struct qcom_icc_node qnm_camnoc_sf = { + .name = "qnm_camnoc_sf", + .channels = 2, + .buswidth = 32, + .qosbox = &qnm_camnoc_sf_qos, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_qosbox qnm_mdp_qos = { + .num_ports = 1, + .port_offsets = { 0xad000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, +}; + +static struct qcom_icc_node qnm_mdp = { + .name = "qnm_mdp", + .channels = 1, + .buswidth = 32, + .qosbox = &qnm_mdp_qos, + .num_links = 1, + .link_nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_qosbox qnm_video_qos = { + .num_ports = 1, + .port_offsets = { 0x30000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, +}; + +static struct qcom_icc_node qnm_video = { + .name = "qnm_video", + .channels = 1, + .buswidth = 32, + .qosbox = &qnm_video_qos, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qsm_hf_mnoc_cfg = { + .name = "qsm_hf_mnoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &srvc_mnoc_hf }, +}; + +static struct qcom_icc_node qsm_sf_mnoc_cfg = { + .name = "qsm_sf_mnoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &srvc_mnoc_sf }, +}; + +static struct qcom_icc_node qxm_nsp = { + .name = "qxm_nsp", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_nsp_gemnoc }, +}; + +static struct qcom_icc_node qsm_pcie_anoc_cfg = { + .name = "qsm_pcie_anoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &srvc_pcie_aggre_noc }, +}; + +static struct qcom_icc_qosbox xm_pcie3_0_qos = { + .num_ports = 1, + .port_offsets = { 0xb000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node xm_pcie3_0 = { + .name = "xm_pcie3_0", + .channels = 1, + .buswidth = 8, + .qosbox = &xm_pcie3_0_qos, + .num_links = 1, + .link_nodes = { &qns_pcie_mem_noc }, +}; + +static struct qcom_icc_qosbox xm_pcie3_1_qos = { + .num_ports = 1, + .port_offsets = { 0xc000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node xm_pcie3_1 = { + .name = "xm_pcie3_1", + .channels = 1, + .buswidth = 8, + .qosbox = &xm_pcie3_1_qos, + .num_links = 1, + .link_nodes = { &qns_pcie_mem_noc }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_qosbox qnm_apss_noc_qos = { + .num_ports = 1, + .port_offsets = { 0x1c000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node qnm_apss_noc = { + .name = "qnm_apss_noc", + .channels = 1, + .buswidth = 4, + .qosbox = &qnm_apss_noc_qos, + .num_links = 1, + .link_nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_qosbox qnm_cnoc_data_qos = { + .num_ports = 1, + .port_offsets = { 0x1d000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node qnm_cnoc_data = { + .name = "qnm_cnoc_data", + .channels = 1, + .buswidth = 8, + .qosbox = &qnm_cnoc_data_qos, + .num_links = 1, + .link_nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_qosbox qxm_pimem_qos = { + .num_ports = 1, + .port_offsets = { 0x1e000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node qxm_pimem = { + .name = "qxm_pimem", + .channels = 1, + .buswidth = 8, + .qosbox = &qxm_pimem_qos, + .num_links = 1, + .link_nodes = { &qns_gemnoc_gc }, +}; + +static struct qcom_icc_qosbox xm_gic_qos = { + .num_ports = 1, + .port_offsets = { 0x1f000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .channels = 1, + .buswidth = 8, + .qosbox = &xm_gic_qos, + .num_links = 1, + .link_nodes = { &qns_gemnoc_gc }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_node qup0_core_slave = { + .name = "qup0_core_slave", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qup1_core_slave = { + .name = "qup1_core_slave", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ahb2phy0 = { + .name = "qhs_ahb2phy0", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ahb2phy1 = { + .name = "qhs_ahb2phy1", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_cpr_cx = { + .name = "qhs_cpr_cx", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_cpr_mxa = { + .name = "qhs_cpr_mxa", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_cx_rdpm = { + .name = "qhs_cx_rdpm", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_mss_cfg = { + .name = "qhs_mss_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_mx_2_rdpm = { + .name = "qhs_mx_2_rdpm", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_mx_rdpm = { + .name = "qhs_mx_rdpm", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qspi = { + .name = "qhs_qspi", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qup0 = { + .name = "qhs_qup0", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qup1 = { + .name = "qhs_qup1", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_sdc1 = { + .name = "qhs_sdc1", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .name = "qhs_sdc2", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_tlmm = { + .name = "qhs_tlmm", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_usb3_0 = { + .name = "qhs_usb3_0", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .name = "qhs_vsense_ctrl_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_wlan_q6 = { + .name = "qhs_wlan_q6", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qss_mnoc_hf_cfg = { + .name = "qss_mnoc_hf_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qsm_hf_mnoc_cfg }, +}; + +static struct qcom_icc_node qss_mnoc_sf_cfg = { + .name = "qss_mnoc_sf_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qsm_sf_mnoc_cfg }, +}; + +static struct qcom_icc_node qss_nsp_qtb_cfg = { + .name = "qss_nsp_qtb_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qss_pcie_anoc_cfg = { + .name = "qss_pcie_anoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qsm_pcie_anoc_cfg }, +}; + +static struct qcom_icc_node qss_wlan_q6_throttle_cfg = { + .name = "qss_wlan_q6_throttle_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node srvc_cnoc_cfg = { + .name = "srvc_cnoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_display_cfg = { + .name = "qhs_display_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ipc_router = { + .name = "qhs_ipc_router", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pcie0_cfg = { + .name = "qhs_pcie0_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pcie1_cfg = { + .name = "qhs_pcie1_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_tme_cfg = { + .name = "qhs_tme_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qss_apss = { + .name = "qss_apss", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qss_cfg = { + .name = "qss_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qsm_cfg }, +}; + +static struct qcom_icc_node qss_ddrss_cfg = { + .name = "qss_ddrss_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_node qxs_pimem = { + .name = "qxs_pimem", + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_node srvc_cnoc_main = { + .name = "srvc_cnoc_main", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node xs_pcie_0 = { + .name = "xs_pcie_0", + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_node xs_pcie_1 = { + .name = "xs_pcie_1", + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_node qns_gem_noc_cnoc = { + .name = "qns_gem_noc_cnoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_gemnoc_cnoc }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .channels = 2, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &llcc_mc }, +}; + +static struct qcom_icc_node qns_pcie = { + .name = "qns_pcie", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qnm_gemnoc_pcie }, +}; + +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { + .name = "qns_lpass_ag_noc_gemnoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_lpass_gemnoc }, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .channels = 2, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_mnoc_hf }, +}; + +static struct qcom_icc_node qns_mem_noc_sf = { + .name = "qns_mem_noc_sf", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_mnoc_sf }, +}; + +static struct qcom_icc_node srvc_mnoc_hf = { + .name = "srvc_mnoc_hf", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node srvc_mnoc_sf = { + .name = "srvc_mnoc_sf", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qns_nsp_gemnoc = { + .name = "qns_nsp_gemnoc", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_nsp_gemnoc }, +}; + +static struct qcom_icc_node qns_pcie_mem_noc = { + .name = "qns_pcie_mem_noc", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qnm_pcie }, +}; + +static struct qcom_icc_node srvc_pcie_aggre_noc = { + .name = "srvc_pcie_aggre_noc", + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qns_gemnoc_gc = { + .name = "qns_gemnoc_gc", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qnm_snoc_gc }, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_snoc_sf }, +}; + +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .enable_mask = 0x1, + .num_nodes = 1, + .nodes = { &ebi, }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .enable_mask = 0x1, + .keepalive = true, + .num_nodes = 51, + .nodes = { &qsm_cfg, &qhs_ahb2phy0, + &qhs_ahb2phy1, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_cpr_cx, + &qhs_cpr_mxa, &qhs_crypto0_cfg, + &qhs_cx_rdpm, &qhs_gpuss_cfg, + &qhs_imem_cfg, &qhs_mss_cfg, + &qhs_mx_2_rdpm, &qhs_mx_rdpm, + &qhs_pdm, &qhs_qdss_cfg, + &qhs_qspi, &qhs_sdc1, + &qhs_sdc2, &qhs_tcsr, + &qhs_tlmm, &qhs_ufs_mem_cfg, + &qhs_usb3_0, &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, &qhs_wlan_q6, + &qss_mnoc_hf_cfg, &qss_mnoc_sf_cfg, + &qss_nsp_qtb_cfg, &qss_pcie_anoc_cfg, + &qss_wlan_q6_throttle_cfg, &srvc_cnoc_cfg, + &xs_qdss_stm, &xs_sys_tcu_cfg, + &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, + &qhs_aoss, &qhs_ipa, + &qhs_ipc_router, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_prng, + &qhs_tme_cfg, &qss_apss, + &qss_cfg, &qss_ddrss_cfg, + &qxs_imem, &qxs_pimem, + &srvc_cnoc_main, &xs_pcie_0, + &xs_pcie_1 }, +}; + +static struct qcom_icc_bcm bcm_cn1 = { + .name = "CN1", + .num_nodes = 3, + .nodes = { &qhs_qup0, &qhs_qup1, + &qhs_display_cfg }, +}; + +static struct qcom_icc_bcm bcm_co0 = { + .name = "CO0", + .enable_mask = 0x1, + .num_nodes = 2, + .nodes = { &qxm_nsp, &qns_nsp_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .enable_mask = 0x1, + .num_nodes = 4, + .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp, + &qnm_camnoc_sf, &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .keepalive = true, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup0_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup1 = { + .name = "QUP1", + .keepalive = true, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup1_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh1 = { + .name = "SH1", + .enable_mask = 0x1, + .num_nodes = 14, + .nodes = { &alm_gpu_tcu, &alm_sys_tcu, + &chm_apps, &qnm_gpu, + &qnm_mdsp, &qnm_mnoc_hf, + &qnm_mnoc_sf, &qnm_nsp_gemnoc, + &qnm_pcie, &qnm_snoc_gc, + &qnm_snoc_sf, &qxm_wlan_q6, + &qns_gem_noc_cnoc, &qns_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .num_nodes = 2, + .nodes = { &qns_gemnoc_gc, &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .enable_mask = 0x1, + .num_nodes = 1, + .nodes = { &qxm_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .num_nodes = 1, + .nodes = { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .num_nodes = 1, + .nodes = { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .num_nodes = 1, + .nodes = { &qns_pcie_mem_noc }, +}; + +static struct qcom_icc_node * const aggre1_noc_nodes[] = { + [MASTER_QUP_1] = &qhm_qup1, + [MASTER_UFS_MEM] = &xm_ufs_mem, + [MASTER_USB3_0] = &xm_usb3_0, + [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, +}; + +static const struct regmap_config milos_aggre1_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x16400, + .fast_io = true, +}; + +static const struct qcom_icc_desc milos_aggre1_noc = { + .config = &milos_aggre1_noc_regmap_config, + .nodes = aggre1_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), +}; + +static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { + &bcm_ce0, +}; + +static struct qcom_icc_node * const aggre2_noc_nodes[] = { + [MASTER_QDSS_BAM] = &qhm_qdss_bam, + [MASTER_QSPI_0] = &qhm_qspi, + [MASTER_QUP_0] = &qhm_qup0, + [MASTER_CRYPTO] = &qxm_crypto, + [MASTER_IPA] = &qxm_ipa, + [MASTER_QDSS_ETR] = &xm_qdss_etr_0, + [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, + [MASTER_SDCC_1] = &xm_sdc1, + [MASTER_SDCC_2] = &xm_sdc2, + [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, +}; + +static const struct regmap_config milos_aggre2_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1f400, + .fast_io = true, +}; + +static const struct qcom_icc_desc milos_aggre2_noc = { + .config = &milos_aggre2_noc_regmap_config, + .nodes = aggre2_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), + .bcms = aggre2_noc_bcms, + .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), +}; + +static struct qcom_icc_bcm * const clk_virt_bcms[] = { + &bcm_qup0, + &bcm_qup1, +}; + +static struct qcom_icc_node * const clk_virt_nodes[] = { + [MASTER_QUP_CORE_0] = &qup0_core_master, + [MASTER_QUP_CORE_1] = &qup1_core_master, + [SLAVE_QUP_CORE_0] = &qup0_core_slave, + [SLAVE_QUP_CORE_1] = &qup1_core_slave, +}; + +static const struct qcom_icc_desc milos_clk_virt = { + .nodes = clk_virt_nodes, + .num_nodes = ARRAY_SIZE(clk_virt_nodes), + .bcms = clk_virt_bcms, + .num_bcms = ARRAY_SIZE(clk_virt_bcms), +}; + +static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = { + &bcm_cn0, + &bcm_cn1, +}; + +static struct qcom_icc_node * const cnoc_cfg_nodes[] = { + [MASTER_CNOC_CFG] = &qsm_cfg, + [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, + [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, + [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, + [SLAVE_CLK_CTL] = &qhs_clk_ctl, + [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, + [SLAVE_RBCPR_MXA_CFG] = &qhs_cpr_mxa, + [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, + [SLAVE_CX_RDPM] = &qhs_cx_rdpm, + [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, + [SLAVE_IMEM_CFG] = &qhs_imem_cfg, + [SLAVE_CNOC_MSS] = &qhs_mss_cfg, + [SLAVE_MX_2_RDPM] = &qhs_mx_2_rdpm, + [SLAVE_MX_RDPM] = &qhs_mx_rdpm, + [SLAVE_PDM] = &qhs_pdm, + [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, + [SLAVE_QSPI_0] = &qhs_qspi, + [SLAVE_QUP_0] = &qhs_qup0, + [SLAVE_QUP_1] = &qhs_qup1, + [SLAVE_SDC1] = &qhs_sdc1, + [SLAVE_SDCC_2] = &qhs_sdc2, + [SLAVE_TCSR] = &qhs_tcsr, + [SLAVE_TLMM] = &qhs_tlmm, + [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, + [SLAVE_USB3_0] = &qhs_usb3_0, + [SLAVE_VENUS_CFG] = &qhs_venus_cfg, + [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, + [SLAVE_WLAN] = &qhs_wlan_q6, + [SLAVE_CNOC_MNOC_HF_CFG] = &qss_mnoc_hf_cfg, + [SLAVE_CNOC_MNOC_SF_CFG] = &qss_mnoc_sf_cfg, + [SLAVE_NSP_QTB_CFG] = &qss_nsp_qtb_cfg, + [SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg, + [SLAVE_WLAN_Q6_THROTTLE_CFG] = &qss_wlan_q6_throttle_cfg, + [SLAVE_SERVICE_CNOC_CFG] = &srvc_cnoc_cfg, + [SLAVE_QDSS_STM] = &xs_qdss_stm, + [SLAVE_TCU] = &xs_sys_tcu_cfg, +}; + +static const struct regmap_config milos_cnoc_cfg_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x6e00, + .fast_io = true, +}; + +static const struct qcom_icc_desc milos_cnoc_cfg = { + .config = &milos_cnoc_cfg_regmap_config, + .nodes = cnoc_cfg_nodes, + .num_nodes = ARRAY_SIZE(cnoc_cfg_nodes), + .bcms = cnoc_cfg_bcms, + .num_bcms = ARRAY_SIZE(cnoc_cfg_bcms), +}; + +static struct qcom_icc_bcm * const cnoc_main_bcms[] = { + &bcm_cn0, + &bcm_cn1, +}; + +static struct qcom_icc_node * const cnoc_main_nodes[] = { + [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, + [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, + [SLAVE_AOSS] = &qhs_aoss, + [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, + [SLAVE_IPA_CFG] = &qhs_ipa, + [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, + [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, + [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, + [SLAVE_PRNG] = &qhs_prng, + [SLAVE_TME_CFG] = &qhs_tme_cfg, + [SLAVE_APPSS] = &qss_apss, + [SLAVE_CNOC_CFG] = &qss_cfg, + [SLAVE_DDRSS_CFG] = &qss_ddrss_cfg, + [SLAVE_IMEM] = &qxs_imem, + [SLAVE_PIMEM] = &qxs_pimem, + [SLAVE_SERVICE_CNOC] = &srvc_cnoc_main, + [SLAVE_PCIE_0] = &xs_pcie_0, + [SLAVE_PCIE_1] = &xs_pcie_1, +}; + +static const struct regmap_config milos_cnoc_main_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x14400, + .fast_io = true, +}; + +static const struct qcom_icc_desc milos_cnoc_main = { + .config = &milos_cnoc_main_regmap_config, + .nodes = cnoc_main_nodes, + .num_nodes = ARRAY_SIZE(cnoc_main_nodes), + .bcms = cnoc_main_bcms, + .num_bcms = ARRAY_SIZE(cnoc_main_bcms), +}; + +static struct qcom_icc_bcm * const gem_noc_bcms[] = { + &bcm_sh0, + &bcm_sh1, +}; + +static struct qcom_icc_node * const gem_noc_nodes[] = { + [MASTER_GPU_TCU] = &alm_gpu_tcu, + [MASTER_SYS_TCU] = &alm_sys_tcu, + [MASTER_APPSS_PROC] = &chm_apps, + [MASTER_GFX3D] = &qnm_gpu, + [MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc, + [MASTER_MSS_PROC] = &qnm_mdsp, + [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, + [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, + [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc, + [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, + [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, + [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, + [MASTER_WLAN_Q6] = &qxm_wlan_q6, + [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, + [SLAVE_LLCC] = &qns_llcc, + [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, +}; + +static const struct regmap_config milos_gem_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xff080, + .fast_io = true, +}; + +static const struct qcom_icc_desc milos_gem_noc = { + .config = &milos_gem_noc_regmap_config, + .nodes = gem_noc_nodes, + .num_nodes = ARRAY_SIZE(gem_noc_nodes), + .bcms = gem_noc_bcms, + .num_bcms = ARRAY_SIZE(gem_noc_bcms), +}; + +static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { + [MASTER_LPASS_PROC] = &qxm_lpass_dsp, + [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc, +}; + +static const struct regmap_config milos_lpass_ag_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x17200, + .fast_io = true, +}; + +static const struct qcom_icc_desc milos_lpass_ag_noc = { + .config = &milos_lpass_ag_noc_regmap_config, + .nodes = lpass_ag_noc_nodes, + .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), +}; + +static struct qcom_icc_bcm * const mc_virt_bcms[] = { + &bcm_acv, + &bcm_mc0, +}; + +static struct qcom_icc_node * const mc_virt_nodes[] = { + [MASTER_LLCC] = &llcc_mc, + [SLAVE_EBI1] = &ebi, +}; + +static const struct qcom_icc_desc milos_mc_virt = { + .nodes = mc_virt_nodes, + .num_nodes = ARRAY_SIZE(mc_virt_nodes), + .bcms = mc_virt_bcms, + .num_bcms = ARRAY_SIZE(mc_virt_bcms), +}; + +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { + &bcm_mm0, + &bcm_mm1, +}; + +static struct qcom_icc_node * const mmss_noc_nodes[] = { + [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, + [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, + [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, + [MASTER_MDP] = &qnm_mdp, + [MASTER_VIDEO] = &qnm_video, + [MASTER_CNOC_MNOC_HF_CFG] = &qsm_hf_mnoc_cfg, + [MASTER_CNOC_MNOC_SF_CFG] = &qsm_sf_mnoc_cfg, + [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, + [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, + [SLAVE_SERVICE_MNOC_HF] = &srvc_mnoc_hf, + [SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf, +}; + +static const struct regmap_config milos_mmss_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xdb800, + .fast_io = true, +}; + +static const struct qcom_icc_desc milos_mmss_noc = { + .config = &milos_mmss_noc_regmap_config, + .nodes = mmss_noc_nodes, + .num_nodes = ARRAY_SIZE(mmss_noc_nodes), + .bcms = mmss_noc_bcms, + .num_bcms = ARRAY_SIZE(mmss_noc_bcms), +}; + +static struct qcom_icc_bcm * const nsp_noc_bcms[] = { + &bcm_co0, +}; + +static struct qcom_icc_node * const nsp_noc_nodes[] = { + [MASTER_CDSP_PROC] = &qxm_nsp, + [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, +}; + +static const struct regmap_config milos_nsp_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xe080, + .fast_io = true, +}; + +static const struct qcom_icc_desc milos_nsp_noc = { + .config = &milos_nsp_noc_regmap_config, + .nodes = nsp_noc_nodes, + .num_nodes = ARRAY_SIZE(nsp_noc_nodes), + .bcms = nsp_noc_bcms, + .num_bcms = ARRAY_SIZE(nsp_noc_bcms), +}; + +static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { + &bcm_sn4, +}; + +static struct qcom_icc_node * const pcie_anoc_nodes[] = { + [MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg, + [MASTER_PCIE_0] = &xm_pcie3_0, + [MASTER_PCIE_1] = &xm_pcie3_1, + [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, + [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc, +}; + +static const struct regmap_config milos_pcie_anoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x12400, + .fast_io = true, +}; + +static const struct qcom_icc_desc milos_pcie_anoc = { + .config = &milos_pcie_anoc_regmap_config, + .nodes = pcie_anoc_nodes, + .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), + .bcms = pcie_anoc_bcms, + .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), +}; + +static struct qcom_icc_bcm * const system_noc_bcms[] = { + &bcm_sn0, + &bcm_sn1, + &bcm_sn2, + &bcm_sn3, +}; + +static struct qcom_icc_node * const system_noc_nodes[] = { + [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, + [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, + [MASTER_APSS_NOC] = &qnm_apss_noc, + [MASTER_CNOC_SNOC] = &qnm_cnoc_data, + [MASTER_PIMEM] = &qxm_pimem, + [MASTER_GIC] = &xm_gic, + [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, + [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, +}; + +static const struct regmap_config milos_system_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x40000, + .fast_io = true, +}; + +static const struct qcom_icc_desc milos_system_noc = { + .config = &milos_system_noc_regmap_config, + .nodes = system_noc_nodes, + .num_nodes = ARRAY_SIZE(system_noc_nodes), + .bcms = system_noc_bcms, + .num_bcms = ARRAY_SIZE(system_noc_bcms), +}; + +static const struct of_device_id qnoc_of_match[] = { + { .compatible = "qcom,milos-aggre1-noc", .data = &milos_aggre1_noc }, + { .compatible = "qcom,milos-aggre2-noc", .data = &milos_aggre2_noc }, + { .compatible = "qcom,milos-clk-virt", .data = &milos_clk_virt }, + { .compatible = "qcom,milos-cnoc-cfg", .data = &milos_cnoc_cfg }, + { .compatible = "qcom,milos-cnoc-main", .data = &milos_cnoc_main }, + { .compatible = "qcom,milos-gem-noc", .data = &milos_gem_noc }, + { .compatible = "qcom,milos-lpass-ag-noc", .data = &milos_lpass_ag_noc }, + { .compatible = "qcom,milos-mc-virt", .data = &milos_mc_virt }, + { .compatible = "qcom,milos-mmss-noc", .data = &milos_mmss_noc }, + { .compatible = "qcom,milos-nsp-noc", .data = &milos_nsp_noc }, + { .compatible = "qcom,milos-pcie-anoc", .data = &milos_pcie_anoc }, + { .compatible = "qcom,milos-system-noc", .data = &milos_system_noc }, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver = { + .probe = qcom_icc_rpmh_probe, + .remove = qcom_icc_rpmh_remove, + .driver = { + .name = "qnoc-milos", + .of_match_table = qnoc_of_match, + .sync_state = icc_sync_state, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION("Milos NoC driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/interconnect/qcom/msm8909.c b/drivers/interconnect/qcom/msm8909.c index 0d0cd7282f5b..dd656ce7b64d 100644 --- a/drivers/interconnect/qcom/msm8909.c +++ b/drivers/interconnect/qcom/msm8909.c @@ -1316,7 +1316,7 @@ MODULE_DEVICE_TABLE(of, msm8909_noc_of_match); static struct platform_driver msm8909_noc_driver = { .probe = qnoc_probe, - .remove_new = qnoc_remove, + .remove = qnoc_remove, .driver = { .name = "qnoc-msm8909", .of_match_table = msm8909_noc_of_match, diff --git a/drivers/interconnect/qcom/msm8916.c b/drivers/interconnect/qcom/msm8916.c index 499b1a9ac413..35148880b3e8 100644 --- a/drivers/interconnect/qcom/msm8916.c +++ b/drivers/interconnect/qcom/msm8916.c @@ -1344,7 +1344,7 @@ MODULE_DEVICE_TABLE(of, msm8916_noc_of_match); static struct platform_driver msm8916_noc_driver = { .probe = qnoc_probe, - .remove_new = qnoc_remove, + .remove = qnoc_remove, .driver = { .name = "qnoc-msm8916", .of_match_table = msm8916_noc_of_match, diff --git a/drivers/interconnect/qcom/msm8937.c b/drivers/interconnect/qcom/msm8937.c index 052b14c28ef8..58533d00266b 100644 --- a/drivers/interconnect/qcom/msm8937.c +++ b/drivers/interconnect/qcom/msm8937.c @@ -1175,7 +1175,7 @@ static struct qcom_icc_node slv_lpass = { .qos.qos_mode = NOC_QOS_MODE_INVALID, }; -static struct qcom_icc_node *msm8937_bimc_nodes[] = { +static struct qcom_icc_node * const msm8937_bimc_nodes[] = { [MAS_APPS_PROC] = &mas_apps_proc, [MAS_OXILI] = &mas_oxili, [MAS_SNOC_BIMC_0] = &mas_snoc_bimc_0, @@ -1204,7 +1204,7 @@ static const struct qcom_icc_desc msm8937_bimc = { .ab_coeff = 154, }; -static struct qcom_icc_node *msm8937_pcnoc_nodes[] = { +static struct qcom_icc_node * const msm8937_pcnoc_nodes[] = { [MAS_SPDM] = &mas_spdm, [MAS_BLSP_1] = &mas_blsp_1, [MAS_BLSP_2] = &mas_blsp_2, @@ -1268,7 +1268,7 @@ static const struct qcom_icc_desc msm8937_pcnoc = { .regmap_cfg = &msm8937_pcnoc_regmap_config, }; -static struct qcom_icc_node *msm8937_snoc_nodes[] = { +static struct qcom_icc_node * const msm8937_snoc_nodes[] = { [MAS_QDSS_BAM] = &mas_qdss_bam, [MAS_BIMC_SNOC] = &mas_bimc_snoc, [MAS_PCNOC_SNOC] = &mas_pcnoc_snoc, @@ -1304,7 +1304,7 @@ static const struct qcom_icc_desc msm8937_snoc = { .qos_offset = 0x7000, }; -static struct qcom_icc_node *msm8937_snoc_mm_nodes[] = { +static struct qcom_icc_node * const msm8937_snoc_mm_nodes[] = { [MAS_JPEG] = &mas_jpeg, [MAS_MDP] = &mas_mdp, [MAS_VENUS] = &mas_venus, @@ -1337,7 +1337,7 @@ MODULE_DEVICE_TABLE(of, msm8937_noc_of_match); static struct platform_driver msm8937_noc_driver = { .probe = qnoc_probe, - .remove_new = qnoc_remove, + .remove = qnoc_remove, .driver = { .name = "qnoc-msm8937", .of_match_table = msm8937_noc_of_match, diff --git a/drivers/interconnect/qcom/msm8939.c b/drivers/interconnect/qcom/msm8939.c index 8ff2c23b1ca0..b52c5ac1175c 100644 --- a/drivers/interconnect/qcom/msm8939.c +++ b/drivers/interconnect/qcom/msm8939.c @@ -1421,7 +1421,7 @@ MODULE_DEVICE_TABLE(of, msm8939_noc_of_match); static struct platform_driver msm8939_noc_driver = { .probe = qnoc_probe, - .remove_new = qnoc_remove, + .remove = qnoc_remove, .driver = { .name = "qnoc-msm8939", .of_match_table = msm8939_noc_of_match, diff --git a/drivers/interconnect/qcom/msm8953.c b/drivers/interconnect/qcom/msm8953.c index 62f8c0774b3e..be2b1a606612 100644 --- a/drivers/interconnect/qcom/msm8953.c +++ b/drivers/interconnect/qcom/msm8953.c @@ -1310,7 +1310,7 @@ static const struct of_device_id msm8953_noc_of_match[] = { static struct platform_driver msm8953_noc_driver = { .probe = qnoc_probe, - .remove_new = qnoc_remove, + .remove = qnoc_remove, .driver = { .name = "qnoc-msm8953", .of_match_table = msm8953_noc_of_match, diff --git a/drivers/interconnect/qcom/msm8974.c b/drivers/interconnect/qcom/msm8974.c index 241076b5f36b..469fc48ebfe9 100644 --- a/drivers/interconnect/qcom/msm8974.c +++ b/drivers/interconnect/qcom/msm8974.c @@ -762,7 +762,7 @@ MODULE_DEVICE_TABLE(of, msm8974_noc_of_match); static struct platform_driver msm8974_noc_driver = { .probe = msm8974_icc_probe, - .remove_new = msm8974_icc_remove, + .remove = msm8974_icc_remove, .driver = { .name = "qnoc-msm8974", .of_match_table = msm8974_noc_of_match, diff --git a/drivers/interconnect/qcom/msm8976.c b/drivers/interconnect/qcom/msm8976.c index ab963def77c3..4e2ac7ebe742 100644 --- a/drivers/interconnect/qcom/msm8976.c +++ b/drivers/interconnect/qcom/msm8976.c @@ -1427,7 +1427,7 @@ MODULE_DEVICE_TABLE(of, msm8976_noc_of_match); static struct platform_driver msm8976_noc_driver = { .probe = qnoc_probe, - .remove_new = qnoc_remove, + .remove = qnoc_remove, .driver = { .name = "qnoc-msm8976", .of_match_table = msm8976_noc_of_match, diff --git a/drivers/interconnect/qcom/msm8996.c b/drivers/interconnect/qcom/msm8996.c index 788131400cd1..84cfafb22aa1 100644 --- a/drivers/interconnect/qcom/msm8996.c +++ b/drivers/interconnect/qcom/msm8996.c @@ -552,6 +552,7 @@ static struct qcom_icc_node mas_venus_vmem = { static const u16 mas_snoc_pnoc_links[] = { MSM8996_SLAVE_BLSP_1, MSM8996_SLAVE_BLSP_2, + MSM8996_SLAVE_USB_HS, MSM8996_SLAVE_SDCC_1, MSM8996_SLAVE_SDCC_2, MSM8996_SLAVE_SDCC_4, @@ -2108,7 +2109,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qnoc_probe, - .remove_new = qnoc_remove, + .remove = qnoc_remove, .driver = { .name = "qnoc-msm8996", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index 61a8695a9adc..b33f00da1880 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include <linux/args.h> @@ -32,8 +33,6 @@ #define EPSS_REG_FREQ_LUT 0x100 #define EPSS_REG_PERF_STATE 0x320 -#define OSM_L3_MAX_LINKS 1 - #define to_osm_l3_provider(_provider) \ container_of(_provider, struct qcom_osm_l3_icc_provider, provider) @@ -48,16 +47,10 @@ struct qcom_osm_l3_icc_provider { /** * struct qcom_osm_l3_node - Qualcomm specific interconnect nodes * @name: the node name used in debugfs - * @links: an array of nodes where we can go next while traversing - * @id: a unique node identifier - * @num_links: the total number of @links * @buswidth: width of the interconnect between a node and the bus */ struct qcom_osm_l3_node { const char *name; - u16 links[OSM_L3_MAX_LINKS]; - u16 id; - u16 num_links; u16 buswidth; }; @@ -69,30 +62,22 @@ struct qcom_osm_l3_desc { unsigned int reg_perf_state; }; -enum { - OSM_L3_MASTER_NODE = 10000, - OSM_L3_SLAVE_NODE, -}; - -#define DEFINE_QNODE(_name, _id, _buswidth, ...) \ +#define DEFINE_QNODE(_name, _buswidth) \ static const struct qcom_osm_l3_node _name = { \ .name = #_name, \ - .id = _id, \ .buswidth = _buswidth, \ - .num_links = COUNT_ARGS(__VA_ARGS__), \ - .links = { __VA_ARGS__ }, \ } -DEFINE_QNODE(osm_l3_master, OSM_L3_MASTER_NODE, 16, OSM_L3_SLAVE_NODE); -DEFINE_QNODE(osm_l3_slave, OSM_L3_SLAVE_NODE, 16); +DEFINE_QNODE(osm_l3_slave, 16); +DEFINE_QNODE(osm_l3_master, 16); static const struct qcom_osm_l3_node * const osm_l3_nodes[] = { [MASTER_OSM_L3_APPS] = &osm_l3_master, [SLAVE_OSM_L3] = &osm_l3_slave, }; -DEFINE_QNODE(epss_l3_master, OSM_L3_MASTER_NODE, 32, OSM_L3_SLAVE_NODE); -DEFINE_QNODE(epss_l3_slave, OSM_L3_SLAVE_NODE, 32); +DEFINE_QNODE(epss_l3_slave, 32); +DEFINE_QNODE(epss_l3_master, 32); static const struct qcom_osm_l3_node * const epss_l3_nodes[] = { [MASTER_EPSS_L3_APPS] = &epss_l3_master, @@ -242,26 +227,31 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) icc_provider_init(provider); + /* Create nodes */ for (i = 0; i < num_nodes; i++) { - size_t j; + node = icc_node_create_dyn(); - node = icc_node_create(qnodes[i]->id); if (IS_ERR(node)) { ret = PTR_ERR(node); goto err; } - node->name = qnodes[i]->name; + ret = icc_node_set_name(node, provider, qnodes[i]->name); + if (ret) { + icc_node_destroy(node->id); + goto err; + } + /* Cast away const and add it back in qcom_osm_l3_set() */ node->data = (void *)qnodes[i]; icc_node_add(node, provider); - for (j = 0; j < qnodes[i]->num_links; j++) - icc_link_create(node, qnodes[i]->links[j]); - data->nodes[i] = node; } + /* Create link */ + icc_link_nodes(data->nodes[MASTER_OSM_L3_APPS], &data->nodes[SLAVE_OSM_L3]); + ret = icc_provider_register(provider); if (ret) goto err; @@ -278,6 +268,7 @@ err: static const struct of_device_id osm_l3_of_match[] = { { .compatible = "qcom,epss-l3", .data = &epss_l3_l3_vote }, { .compatible = "qcom,osm-l3", .data = &osm_l3 }, + { .compatible = "qcom,sa8775p-epss-l3", .data = &epss_l3_perf_state }, { .compatible = "qcom,sc7180-osm-l3", .data = &osm_l3 }, { .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3_perf_state }, { .compatible = "qcom,sdm845-osm-l3", .data = &osm_l3 }, @@ -290,7 +281,7 @@ MODULE_DEVICE_TABLE(of, osm_l3_of_match); static struct platform_driver osm_l3_driver = { .probe = qcom_osm_l3_probe, - .remove_new = qcom_osm_l3_remove, + .remove = qcom_osm_l3_remove, .driver = { .name = "osm-l3", .of_match_table = osm_l3_of_match, diff --git a/drivers/interconnect/qcom/qcm2290.c b/drivers/interconnect/qcom/qcm2290.c index ccbdc6202c07..e120bc1395f3 100644 --- a/drivers/interconnect/qcom/qcm2290.c +++ b/drivers/interconnect/qcom/qcm2290.c @@ -1367,7 +1367,7 @@ MODULE_DEVICE_TABLE(of, qcm2290_noc_of_match); static struct platform_driver qcm2290_noc_driver = { .probe = qnoc_probe, - .remove_new = qnoc_remove, + .remove = qnoc_remove, .driver = { .name = "qnoc-qcm2290", .of_match_table = qcm2290_noc_of_match, diff --git a/drivers/interconnect/qcom/qcs404.c b/drivers/interconnect/qcom/qcs404.c index 63e9ff223ac4..ceac7a698769 100644 --- a/drivers/interconnect/qcom/qcs404.c +++ b/drivers/interconnect/qcom/qcs404.c @@ -1204,7 +1204,7 @@ MODULE_DEVICE_TABLE(of, qcs404_noc_of_match); static struct platform_driver qcs404_noc_driver = { .probe = qnoc_probe, - .remove_new = qnoc_remove, + .remove = qnoc_remove, .driver = { .name = "qnoc-qcs404", .of_match_table = qcs404_noc_of_match, diff --git a/drivers/interconnect/qcom/qcs615.c b/drivers/interconnect/qcom/qcs615.c new file mode 100644 index 000000000000..797956eb6ff5 --- /dev/null +++ b/drivers/interconnect/qcom/qcs615.c @@ -0,0 +1,1472 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + * + */ + +#include <linux/device.h> +#include <linux/interconnect.h> +#include <linux/interconnect-provider.h> +#include <linux/module.h> +#include <linux/of_platform.h> +#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h> + +#include "bcm-voter.h" +#include "icc-rpmh.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_emac_avb; +static struct qcom_icc_node xm_pcie; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb2; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_hf1_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qhm_spdm; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc; +static struct qcom_icc_node acm_apps; +static struct qcom_icc_node acm_gpu_tcu; +static struct qcom_icc_node acm_sys_tcu; +static struct qcom_icc_node qhm_gemnoc_cfg; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qxm_camnoc_hf0; +static struct qcom_icc_node qxm_camnoc_hf1; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qxm_venus0; +static struct qcom_icc_node qxm_venus_arm9; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_gemnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node qnm_lpass_anoc; +static struct qcom_icc_node qnm_pcie_anoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_lpass_snoc; +static struct qcom_icc_node qns_pcie_snoc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_ahb2phy_east; +static struct qcom_icc_node qhs_ahb2phy_west; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_emac_avb_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_pcie_config; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spdm; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm_east; +static struct qcom_icc_node qhs_tlmm_south; +static struct qcom_icc_node qhs_tlmm_west; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb2; +static struct qcom_icc_node qhs_usb3; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_cnoc_a2noc; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_dc_noc_gemnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_gem_noc_snoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_sys_pcie; +static struct qcom_icc_node srvc_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns2_mem_noc; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qns_memnoc_gc; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_pcie; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; + +static struct qcom_icc_node qhm_a1noc_cfg = { + .name = "qhm_a1noc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &srvc_aggre2_noc }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qhm_qspi = { + .name = "qhm_qspi", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qhm_qup0 = { + .name = "qhm_qup0", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qhm_qup1 = { + .name = "qhm_qup1", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qnm_cnoc = { + .name = "qnm_cnoc", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_lpass_snoc }, +}; + +static struct qcom_icc_node xm_emac_avb = { + .name = "xm_emac_avb", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_pcie = { + .name = "xm_pcie", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_pcie_snoc }, +}; + +static struct qcom_icc_node xm_qdss_etr = { + .name = "xm_qdss_etr", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_sdc1 = { + .name = "xm_sdc1", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_sdc2 = { + .name = "xm_sdc2", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_usb2 = { + .name = "xm_usb2", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_usb3_0 = { + .name = "xm_usb3_0", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { + .name = "qxm_camnoc_hf0_uncomp", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_camnoc_uncomp }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { + .name = "qxm_camnoc_hf1_uncomp", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_camnoc_uncomp }, +}; + +static struct qcom_icc_node qxm_camnoc_sf_uncomp = { + .name = "qxm_camnoc_sf_uncomp", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_camnoc_uncomp }, +}; + +static struct qcom_icc_node qhm_spdm = { + .name = "qhm_spdm", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qns_cnoc_a2noc }, +}; + +static struct qcom_icc_node qnm_snoc = { + .name = "qnm_snoc", + .channels = 1, + .buswidth = 8, + .num_links = 39, + .link_nodes = { &qhs_a1_noc_cfg, &qhs_ahb2phy_east, + &qhs_ahb2phy_west, &qhs_aop, + &qhs_aoss, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_cpr_cx, + &qhs_cpr_mx, &qhs_crypto0_cfg, + &qhs_ddrss_cfg, &qhs_display_cfg, + &qhs_emac_avb_cfg, &qhs_glm, + &qhs_gpuss_cfg, &qhs_imem_cfg, + &qhs_ipa, &qhs_mnoc_cfg, + &qhs_pcie_config, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc1, + &qhs_sdc2, &qhs_snoc_cfg, + &qhs_spdm, &qhs_tcsr, + &qhs_tlmm_east, &qhs_tlmm_south, + &qhs_tlmm_west, &qhs_ufs_mem_cfg, + &qhs_usb2, &qhs_usb3, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &srvc_cnoc }, +}; + +static struct qcom_icc_node xm_qdss_dap = { + .name = "xm_qdss_dap", + .channels = 1, + .buswidth = 8, + .num_links = 40, + .link_nodes = { &qhs_a1_noc_cfg, &qhs_ahb2phy_east, + &qhs_ahb2phy_west, &qhs_aop, + &qhs_aoss, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_cpr_cx, + &qhs_cpr_mx, &qhs_crypto0_cfg, + &qhs_ddrss_cfg, &qhs_display_cfg, + &qhs_emac_avb_cfg, &qhs_glm, + &qhs_gpuss_cfg, &qhs_imem_cfg, + &qhs_ipa, &qhs_mnoc_cfg, + &qhs_pcie_config, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc1, + &qhs_sdc2, &qhs_snoc_cfg, + &qhs_spdm, &qhs_tcsr, + &qhs_tlmm_east, &qhs_tlmm_south, + &qhs_tlmm_west, &qhs_ufs_mem_cfg, + &qhs_usb2, &qhs_usb3, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qns_cnoc_a2noc, &srvc_cnoc }, +}; + +static struct qcom_icc_node qhm_cnoc = { + .name = "qhm_cnoc", + .channels = 1, + .buswidth = 4, + .num_links = 2, + .link_nodes = { &qhs_dc_noc_gemnoc, &qhs_llcc }, +}; + +static struct qcom_icc_node acm_apps = { + .name = "acm_apps", + .channels = 1, + .buswidth = 16, + .num_links = 3, + .link_nodes = { &qns_gem_noc_snoc, &qns_llcc, + &qns_sys_pcie }, +}; + +static struct qcom_icc_node acm_gpu_tcu = { + .name = "acm_gpu_tcu", + .channels = 1, + .buswidth = 8, + .num_links = 2, + .link_nodes = { &qns_gem_noc_snoc, &qns_llcc }, +}; + +static struct qcom_icc_node acm_sys_tcu = { + .name = "acm_sys_tcu", + .channels = 1, + .buswidth = 8, + .num_links = 2, + .link_nodes = { &qns_gem_noc_snoc, &qns_llcc }, +}; + +static struct qcom_icc_node qhm_gemnoc_cfg = { + .name = "qhm_gemnoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 2, + .link_nodes = { &qhs_mdsp_ms_mpu_cfg, &srvc_gemnoc }, +}; + +static struct qcom_icc_node qnm_gpu = { + .name = "qnm_gpu", + .channels = 2, + .buswidth = 32, + .num_links = 2, + .link_nodes = { &qns_gem_noc_snoc, &qns_llcc }, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_llcc }, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .channels = 1, + .buswidth = 32, + .num_links = 2, + .link_nodes = { &qns_gem_noc_snoc, &qns_llcc }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_llcc }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_llcc }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .channels = 2, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &ebi }, +}; + +static struct qcom_icc_node qhm_mnoc_cfg = { + .name = "qhm_mnoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &srvc_mnoc }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0 = { + .name = "qxm_camnoc_hf0", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1 = { + .name = "qxm_camnoc_hf1", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qxm_camnoc_sf = { + .name = "qxm_camnoc_sf", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns2_mem_noc }, +}; + +static struct qcom_icc_node qxm_mdp0 = { + .name = "qxm_mdp0", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qxm_rot = { + .name = "qxm_rot", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns2_mem_noc }, +}; + +static struct qcom_icc_node qxm_venus0 = { + .name = "qxm_venus0", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns2_mem_noc }, +}; + +static struct qcom_icc_node qxm_venus_arm9 = { + .name = "qxm_venus_arm9", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns2_mem_noc }, +}; + +static struct qcom_icc_node qhm_snoc_cfg = { + .name = "qhm_snoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &srvc_snoc }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .channels = 1, + .buswidth = 16, + .num_links = 8, + .link_nodes = { &qhs_apss, &qns_cnoc, + &qns_gemnoc_sf, &qxs_imem, + &qxs_pimem, &xs_pcie, + &xs_qdss_stm, &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_node qnm_gemnoc = { + .name = "qnm_gemnoc", + .channels = 1, + .buswidth = 8, + .num_links = 6, + .link_nodes = { &qhs_apss, &qns_cnoc, + &qxs_imem, &qxs_pimem, + &xs_qdss_stm, &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie = { + .name = "qnm_gemnoc_pcie", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &xs_pcie }, +}; + +static struct qcom_icc_node qnm_lpass_anoc = { + .name = "qnm_lpass_anoc", + .channels = 1, + .buswidth = 8, + .num_links = 7, + .link_nodes = { &qhs_apss, &qns_cnoc, + &qns_gemnoc_sf, &qxs_imem, + &qxs_pimem, &xs_pcie, + &xs_qdss_stm }, +}; + +static struct qcom_icc_node qnm_pcie_anoc = { + .name = "qnm_pcie_anoc", + .channels = 1, + .buswidth = 8, + .num_links = 5, + .link_nodes = { &qhs_apss, &qns_cnoc, + &qns_gemnoc_sf, &qxs_imem, + &xs_qdss_stm }, +}; + +static struct qcom_icc_node qxm_pimem = { + .name = "qxm_pimem", + .channels = 1, + .buswidth = 8, + .num_links = 2, + .link_nodes = { &qns_memnoc_gc, &qxs_imem }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .channels = 1, + .buswidth = 8, + .num_links = 2, + .link_nodes = { &qns_memnoc_gc, &qxs_imem }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_node qns_lpass_snoc = { + .name = "qns_lpass_snoc", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qnm_lpass_anoc }, +}; + +static struct qcom_icc_node qns_pcie_snoc = { + .name = "qns_pcie_snoc", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qnm_pcie_anoc }, +}; + +static struct qcom_icc_node srvc_aggre2_noc = { + .name = "srvc_aggre2_noc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_camnoc_uncomp = { + .name = "qns_camnoc_uncomp", + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node qhs_a1_noc_cfg = { + .name = "qhs_a1_noc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qhm_a1noc_cfg }, +}; + +static struct qcom_icc_node qhs_ahb2phy_east = { + .name = "qhs_ahb2phy_east", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy_west = { + .name = "qhs_ahb2phy_west", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aop = { + .name = "qhs_aop", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_cx = { + .name = "qhs_cpr_cx", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mx = { + .name = "qhs_cpr_mx", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ddrss_cfg = { + .name = "qhs_ddrss_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qhm_cnoc }, +}; + +static struct qcom_icc_node qhs_display_cfg = { + .name = "qhs_display_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_emac_avb_cfg = { + .name = "qhs_emac_avb_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_glm = { + .name = "qhs_glm", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mnoc_cfg = { + .name = "qhs_mnoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qhm_mnoc_cfg }, +}; + +static struct qcom_icc_node qhs_pcie_config = { + .name = "qhs_pcie_config", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg = { + .name = "qhs_pimem_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qspi = { + .name = "qhs_qspi", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup0 = { + .name = "qhs_qup0", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup1 = { + .name = "qhs_qup1", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc1 = { + .name = "qhs_sdc1", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .name = "qhs_sdc2", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg = { + .name = "qhs_snoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qhm_snoc_cfg }, +}; + +static struct qcom_icc_node qhs_spdm = { + .name = "qhs_spdm", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_east = { + .name = "qhs_tlmm_east", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_south = { + .name = "qhs_tlmm_south", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_west = { + .name = "qhs_tlmm_west", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb2 = { + .name = "qhs_usb2", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3 = { + .name = "qhs_usb3", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .name = "qhs_vsense_ctrl_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_cnoc_a2noc = { + .name = "qns_cnoc_a2noc", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qnm_cnoc }, +}; + +static struct qcom_icc_node srvc_cnoc = { + .name = "srvc_cnoc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dc_noc_gemnoc = { + .name = "qhs_dc_noc_gemnoc", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qhm_gemnoc_cfg }, +}; + +static struct qcom_icc_node qhs_llcc = { + .name = "qhs_llcc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { + .name = "qhs_mdsp_ms_mpu_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_gem_noc_snoc = { + .name = "qns_gem_noc_snoc", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qnm_gemnoc }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &llcc_mc }, +}; + +static struct qcom_icc_node qns_sys_pcie = { + .name = "qns_sys_pcie", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qnm_gemnoc_pcie }, +}; + +static struct qcom_icc_node srvc_gemnoc = { + .name = "srvc_gemnoc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .channels = 2, + .buswidth = 4, +}; + +static struct qcom_icc_node qns2_mem_noc = { + .name = "qns2_mem_noc", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_mnoc_sf }, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_mnoc_hf }, +}; + +static struct qcom_icc_node srvc_mnoc = { + .name = "srvc_mnoc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_apss = { + .name = "qhs_apss", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qns_cnoc = { + .name = "qns_cnoc", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qnm_snoc }, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_snoc_sf }, +}; + +static struct qcom_icc_node qns_memnoc_gc = { + .name = "qns_memnoc_gc", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qnm_snoc_gc }, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_pimem = { + .name = "qxs_pimem", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_pcie = { + .name = "xs_pcie", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .keepalive = true, + .num_nodes = 37, + .nodes = { &qhm_spdm, &qnm_snoc, + &qhs_a1_noc_cfg, &qhs_aop, + &qhs_aoss, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_cpr_cx, + &qhs_cpr_mx, &qhs_crypto0_cfg, + &qhs_ddrss_cfg, &qhs_display_cfg, + &qhs_emac_avb_cfg, &qhs_glm, + &qhs_gpuss_cfg, &qhs_imem_cfg, + &qhs_ipa, &qhs_mnoc_cfg, + &qhs_pcie_config, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qup0, &qhs_qup1, + &qhs_snoc_cfg, &qhs_spdm, + &qhs_tcsr, &qhs_tlmm_east, + &qhs_tlmm_south, &qhs_tlmm_west, + &qhs_ufs_mem_cfg, &qhs_usb2, + &qhs_usb3, &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, + &srvc_cnoc }, +}; + +static struct qcom_icc_bcm bcm_cn1 = { + .name = "CN1", + .num_nodes = 8, + .nodes = { &qhm_qspi, &xm_sdc1, + &xm_sdc2, &qhs_ahb2phy_east, + &qhs_ahb2phy_west, &qhs_qspi, + &qhs_sdc1, &qhs_sdc2 }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .num_nodes = 7, + .nodes = { &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, + &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, + &qxm_camnoc_hf1, &qxm_mdp0, + &qxm_rot }, +}; + +static struct qcom_icc_bcm bcm_mm2 = { + .name = "MM2", + .num_nodes = 2, + .nodes = { &qxm_camnoc_sf, &qns2_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_mm3 = { + .name = "MM3", + .num_nodes = 2, + .nodes = { &qxm_venus0, &qxm_venus_arm9 }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .keepalive = true, + .vote_scale = 1, + .num_nodes = 2, + .nodes = { &qhm_qup0, &qhm_qup1 }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh2 = { + .name = "SH2", + .num_nodes = 1, + .nodes = { &acm_apps }, +}; + +static struct qcom_icc_bcm bcm_sh3 = { + .name = "SH3", + .num_nodes = 1, + .nodes = { &qns_gem_noc_snoc }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .num_nodes = 1, + .nodes = { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .num_nodes = 1, + .nodes = { &qns_memnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .num_nodes = 2, + .nodes = { &srvc_aggre2_noc, &qns_cnoc }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .num_nodes = 1, + .nodes = { &qxs_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn5 = { + .name = "SN5", + .num_nodes = 1, + .nodes = { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn8 = { + .name = "SN8", + .num_nodes = 2, + .nodes = { &qnm_gemnoc_pcie, &xs_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn9 = { + .name = "SN9", + .num_nodes = 1, + .nodes = { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn12 = { + .name = "SN12", + .num_nodes = 2, + .nodes = { &qxm_pimem, &xm_gic }, +}; + +static struct qcom_icc_bcm bcm_sn13 = { + .name = "SN13", + .num_nodes = 1, + .nodes = { &qnm_lpass_anoc }, +}; + +static struct qcom_icc_bcm bcm_sn14 = { + .name = "SN14", + .num_nodes = 1, + .nodes = { &qns_pcie_snoc }, +}; + +static struct qcom_icc_bcm bcm_sn15 = { + .name = "SN15", + .num_nodes = 1, + .nodes = { &qnm_gemnoc }, +}; + +static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { + &bcm_ce0, + &bcm_cn1, + &bcm_qup0, + &bcm_sn3, + &bcm_sn14, +}; + +static struct qcom_icc_node * const aggre1_noc_nodes[] = { + [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, + [MASTER_QDSS_BAM] = &qhm_qdss_bam, + [MASTER_QSPI] = &qhm_qspi, + [MASTER_QUP_0] = &qhm_qup0, + [MASTER_BLSP_1] = &qhm_qup1, + [MASTER_CNOC_A2NOC] = &qnm_cnoc, + [MASTER_CRYPTO] = &qxm_crypto, + [MASTER_IPA] = &qxm_ipa, + [MASTER_EMAC_EVB] = &xm_emac_avb, + [MASTER_PCIE] = &xm_pcie, + [MASTER_QDSS_ETR] = &xm_qdss_etr, + [MASTER_SDCC_1] = &xm_sdc1, + [MASTER_SDCC_2] = &xm_sdc2, + [MASTER_UFS_MEM] = &xm_ufs_mem, + [MASTER_USB2] = &xm_usb2, + [MASTER_USB3_0] = &xm_usb3_0, + [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, + [SLAVE_LPASS_SNOC] = &qns_lpass_snoc, + [SLAVE_ANOC_PCIE_SNOC] = &qns_pcie_snoc, + [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, +}; + +static const struct qcom_icc_desc qcs615_aggre1_noc = { + .nodes = aggre1_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), + .bcms = aggre1_noc_bcms, + .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), +}; + +static struct qcom_icc_bcm * const camnoc_virt_bcms[] = { + &bcm_mm1, +}; + +static struct qcom_icc_node * const camnoc_virt_nodes[] = { + [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, + [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp, + [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, + [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, +}; + +static const struct qcom_icc_desc qcs615_camnoc_virt = { + .nodes = camnoc_virt_nodes, + .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), + .bcms = camnoc_virt_bcms, + .num_bcms = ARRAY_SIZE(camnoc_virt_bcms), +}; + +static struct qcom_icc_bcm * const config_noc_bcms[] = { + &bcm_cn0, + &bcm_cn1, +}; + +static struct qcom_icc_node * const config_noc_nodes[] = { + [MASTER_SPDM] = &qhm_spdm, + [MASTER_SNOC_CNOC] = &qnm_snoc, + [MASTER_QDSS_DAP] = &xm_qdss_dap, + [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, + [SLAVE_AHB2PHY_EAST] = &qhs_ahb2phy_east, + [SLAVE_AHB2PHY_WEST] = &qhs_ahb2phy_west, + [SLAVE_AOP] = &qhs_aop, + [SLAVE_AOSS] = &qhs_aoss, + [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, + [SLAVE_CLK_CTL] = &qhs_clk_ctl, + [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, + [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, + [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, + [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, + [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, + [SLAVE_EMAC_AVB_CFG] = &qhs_emac_avb_cfg, + [SLAVE_GLM] = &qhs_glm, + [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, + [SLAVE_IMEM_CFG] = &qhs_imem_cfg, + [SLAVE_IPA_CFG] = &qhs_ipa, + [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, + [SLAVE_PCIE_CFG] = &qhs_pcie_config, + [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, + [SLAVE_PRNG] = &qhs_prng, + [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, + [SLAVE_QSPI] = &qhs_qspi, + [SLAVE_QUP_0] = &qhs_qup0, + [SLAVE_QUP_1] = &qhs_qup1, + [SLAVE_SDCC_1] = &qhs_sdc1, + [SLAVE_SDCC_2] = &qhs_sdc2, + [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, + [SLAVE_SPDM_WRAPPER] = &qhs_spdm, + [SLAVE_TCSR] = &qhs_tcsr, + [SLAVE_TLMM_EAST] = &qhs_tlmm_east, + [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south, + [SLAVE_TLMM_WEST] = &qhs_tlmm_west, + [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, + [SLAVE_USB2] = &qhs_usb2, + [SLAVE_USB3] = &qhs_usb3, + [SLAVE_VENUS_CFG] = &qhs_venus_cfg, + [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, + [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc, + [SLAVE_SERVICE_CNOC] = &srvc_cnoc, +}; + +static const struct qcom_icc_desc qcs615_config_noc = { + .nodes = config_noc_nodes, + .num_nodes = ARRAY_SIZE(config_noc_nodes), + .bcms = config_noc_bcms, + .num_bcms = ARRAY_SIZE(config_noc_bcms), +}; + +static struct qcom_icc_node * const dc_noc_nodes[] = { + [MASTER_CNOC_DC_NOC] = &qhm_cnoc, + [SLAVE_DC_NOC_GEMNOC] = &qhs_dc_noc_gemnoc, + [SLAVE_LLCC_CFG] = &qhs_llcc, +}; + +static const struct qcom_icc_desc qcs615_dc_noc = { + .nodes = dc_noc_nodes, + .num_nodes = ARRAY_SIZE(dc_noc_nodes), +}; + +static struct qcom_icc_bcm * const gem_noc_bcms[] = { + &bcm_sh0, + &bcm_sh2, + &bcm_sh3, + &bcm_mm1, +}; + +static struct qcom_icc_node * const gem_noc_nodes[] = { + [MASTER_APPSS_PROC] = &acm_apps, + [MASTER_GPU_TCU] = &acm_gpu_tcu, + [MASTER_SYS_TCU] = &acm_sys_tcu, + [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg, + [MASTER_GFX3D] = &qnm_gpu, + [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, + [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, + [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, + [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, + [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, + [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc, + [SLAVE_LLCC] = &qns_llcc, + [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie, + [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, +}; + +static const struct qcom_icc_desc qcs615_gem_noc = { + .nodes = gem_noc_nodes, + .num_nodes = ARRAY_SIZE(gem_noc_nodes), + .bcms = gem_noc_bcms, + .num_bcms = ARRAY_SIZE(gem_noc_bcms), +}; + +static struct qcom_icc_bcm * const mc_virt_bcms[] = { + &bcm_acv, + &bcm_mc0, +}; + +static struct qcom_icc_node * const mc_virt_nodes[] = { + [MASTER_LLCC] = &llcc_mc, + [SLAVE_EBI1] = &ebi, +}; + +static const struct qcom_icc_desc qcs615_mc_virt = { + .nodes = mc_virt_nodes, + .num_nodes = ARRAY_SIZE(mc_virt_nodes), + .bcms = mc_virt_bcms, + .num_bcms = ARRAY_SIZE(mc_virt_bcms), +}; + +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { + &bcm_mm0, + &bcm_mm1, + &bcm_mm2, + &bcm_mm3, +}; + +static struct qcom_icc_node * const mmss_noc_nodes[] = { + [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, + [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0, + [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1, + [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, + [MASTER_MDP0] = &qxm_mdp0, + [MASTER_ROTATOR] = &qxm_rot, + [MASTER_VIDEO_P0] = &qxm_venus0, + [MASTER_VIDEO_PROC] = &qxm_venus_arm9, + [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc, + [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, + [SLAVE_SERVICE_MNOC] = &srvc_mnoc, +}; + +static const struct qcom_icc_desc qcs615_mmss_noc = { + .nodes = mmss_noc_nodes, + .num_nodes = ARRAY_SIZE(mmss_noc_nodes), + .bcms = mmss_noc_bcms, + .num_bcms = ARRAY_SIZE(mmss_noc_bcms), +}; + +static struct qcom_icc_bcm * const system_noc_bcms[] = { + &bcm_sn0, + &bcm_sn1, + &bcm_sn2, + &bcm_sn3, + &bcm_sn4, + &bcm_sn5, + &bcm_sn8, + &bcm_sn9, + &bcm_sn12, + &bcm_sn13, + &bcm_sn15, +}; + +static struct qcom_icc_node * const system_noc_nodes[] = { + [MASTER_SNOC_CFG] = &qhm_snoc_cfg, + [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, + [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc, + [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, + [MASTER_LPASS_ANOC] = &qnm_lpass_anoc, + [MASTER_ANOC_PCIE_SNOC] = &qnm_pcie_anoc, + [MASTER_PIMEM] = &qxm_pimem, + [MASTER_GIC] = &xm_gic, + [SLAVE_APPSS] = &qhs_apss, + [SLAVE_SNOC_CNOC] = &qns_cnoc, + [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, + [SLAVE_SNOC_MEM_NOC_GC] = &qns_memnoc_gc, + [SLAVE_IMEM] = &qxs_imem, + [SLAVE_PIMEM] = &qxs_pimem, + [SLAVE_SERVICE_SNOC] = &srvc_snoc, + [SLAVE_PCIE_0] = &xs_pcie, + [SLAVE_QDSS_STM] = &xs_qdss_stm, + [SLAVE_TCU] = &xs_sys_tcu_cfg, +}; + +static const struct qcom_icc_desc qcs615_system_noc = { + .nodes = system_noc_nodes, + .num_nodes = ARRAY_SIZE(system_noc_nodes), + .bcms = system_noc_bcms, + .num_bcms = ARRAY_SIZE(system_noc_bcms), +}; + +static const struct of_device_id qnoc_of_match[] = { + { .compatible = "qcom,qcs615-aggre1-noc", + .data = &qcs615_aggre1_noc}, + { .compatible = "qcom,qcs615-camnoc-virt", + .data = &qcs615_camnoc_virt}, + { .compatible = "qcom,qcs615-config-noc", + .data = &qcs615_config_noc}, + { .compatible = "qcom,qcs615-dc-noc", + .data = &qcs615_dc_noc}, + { .compatible = "qcom,qcs615-gem-noc", + .data = &qcs615_gem_noc}, + { .compatible = "qcom,qcs615-mc-virt", + .data = &qcs615_mc_virt}, + { .compatible = "qcom,qcs615-mmss-noc", + .data = &qcs615_mmss_noc}, + { .compatible = "qcom,qcs615-system-noc", + .data = &qcs615_system_noc}, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver = { + .probe = qcom_icc_rpmh_probe, + .remove = qcom_icc_rpmh_remove, + .driver = { + .name = "qnoc-qcs615", + .of_match_table = qnoc_of_match, + .sync_state = icc_sync_state, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION("qcs615 NoC driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/interconnect/qcom/qcs8300.c b/drivers/interconnect/qcom/qcs8300.c new file mode 100644 index 000000000000..70a377bbcf29 --- /dev/null +++ b/drivers/interconnect/qcom/qcs8300.c @@ -0,0 +1,2001 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + * + */ + +#include <linux/device.h> +#include <linux/interconnect.h> +#include <linux/interconnect-provider.h> +#include <linux/module.h> +#include <linux/of_platform.h> +#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h> + +#include "bcm-voter.h" +#include "icc-rpmh.h" + +static struct qcom_icc_node qxm_qup3; +static struct qcom_icc_node xm_emac_0; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb2_2; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qnm_cnoc_datapath; +static struct qcom_icc_node qxm_crypto_0; +static struct qcom_icc_node qxm_crypto_1; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup3_core_master; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node qnm_cnoc_dc_noc; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_pcie_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_cmpnoc0; +static struct qcom_icc_node qnm_gemnoc_cfg; +static struct qcom_icc_node qnm_gpdsp_sail; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qnm_sailss_md0; +static struct qcom_icc_node qxm_dsp0; +static struct qcom_icc_node qhm_config_noc; +static struct qcom_icc_node qxm_lpass_dsp; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_mdp0_0; +static struct qcom_icc_node qnm_mdp0_1; +static struct qcom_icc_node qnm_mnoc_hf_cfg; +static struct qcom_icc_node qnm_mnoc_sf_cfg; +static struct qcom_icc_node qnm_video0; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qnm_video_v_cpu; +static struct qcom_icc_node qhm_nsp_noc_config; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node qhm_gic; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_lpass_noc; +static struct qcom_icc_node qnm_snoc_cfg; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup3_core_slave; +static struct qcom_icc_node qhs_ahb2phy2; +static struct qcom_icc_node qhs_ahb2phy3; +static struct qcom_icc_node qhs_anoc_throttle_cfg; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qhs_boot_rom; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_camera_nrt_throttle_cfg; +static struct qcom_icc_node qhs_camera_rt_throttle_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute0_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_cpr_nspcx; +static struct qcom_icc_node qhs_cpr_nsphmx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_display0_cfg; +static struct qcom_icc_node qhs_display0_rt_throttle_cfg; +static struct qcom_icc_node qhs_emac0_cfg; +static struct qcom_icc_node qhs_gp_dsp0_cfg; +static struct qcom_icc_node qhs_gpdsp0_throttle_cfg; +static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_hwkm; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_lpass_cfg; +static struct qcom_icc_node qhs_lpass_throttle_cfg; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_mxc_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg; +static struct qcom_icc_node qhs_pcie_throttle_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_pke_wrapper_cfg; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qm_cfg; +static struct qcom_icc_node qhs_qm_mpu_cfg; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup3; +static struct qcom_icc_node qhs_sail_throttle_cfg; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_security; +static struct qcom_icc_node qhs_snoc_throttle_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_tsc_cfg; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb2_0; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_venus_cvp_throttle_cfg; +static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg; +static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qns_gpdsp_noc_cfg; +static struct qcom_icc_node qns_mnoc_hf_cfg; +static struct qcom_icc_node qns_mnoc_sf_cfg; +static struct qcom_icc_node qns_pcie_anoc_cfg; +static struct qcom_icc_node qns_snoc_cfg; +static struct qcom_icc_node qxs_boot_imem; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qns_gemnoc; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node srvc_even_gemnoc; +static struct qcom_icc_node srvc_odd_gemnoc; +static struct qcom_icc_node srvc_sys_gemnoc; +static struct qcom_icc_node srvc_sys_gemnoc_2; +static struct qcom_icc_node qns_gp_dsp_sail_noc; +static struct qcom_icc_node qhs_lpass_core; +static struct qcom_icc_node qhs_lpass_lpi; +static struct qcom_icc_node qhs_lpass_mpu; +static struct qcom_icc_node qhs_lpass_top; +static struct qcom_icc_node qns_sysnoc; +static struct qcom_icc_node srvc_niu_aml_noc; +static struct qcom_icc_node srvc_niu_lpass_agnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc_hf; +static struct qcom_icc_node srvc_mnoc_sf; +static struct qcom_icc_node qns_hcp; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node service_nsp_noc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node srvc_snoc; + +static struct qcom_icc_node qxm_qup3 = { + .name = "qxm_qup3", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_emac_0 = { + .name = "xm_emac_0", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_sdc1 = { + .name = "xm_sdc1", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_usb2_2 = { + .name = "xm_usb2_2", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_usb3_0 = { + .name = "xm_usb3_0", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qhm_qup0 = { + .name = "qhm_qup0", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qhm_qup1 = { + .name = "qhm_qup1", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qnm_cnoc_datapath = { + .name = "qnm_cnoc_datapath", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qxm_crypto_0 = { + .name = "qxm_crypto_0", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qxm_crypto_1 = { + .name = "qxm_crypto_1", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node xm_qdss_etr_0 = { + .name = "xm_qdss_etr_0", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node xm_qdss_etr_1 = { + .name = "xm_qdss_etr_1", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qup0_core_master = { + .name = "qup0_core_master", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qup0_core_slave }, +}; + +static struct qcom_icc_node qup1_core_master = { + .name = "qup1_core_master", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qup1_core_slave }, +}; + +static struct qcom_icc_node qup3_core_master = { + .name = "qup3_core_master", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qup3_core_slave }, +}; + +static struct qcom_icc_node qnm_gemnoc_cnoc = { + .name = "qnm_gemnoc_cnoc", + .channels = 1, + .buswidth = 16, + .num_links = 71, + .link_nodes = { &qhs_ahb2phy2, &qhs_ahb2phy3, + &qhs_anoc_throttle_cfg, &qhs_aoss, + &qhs_apss, &qhs_boot_rom, + &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, + &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, + &qhs_compute0_cfg, &qhs_cpr_cx, + &qhs_cpr_mmcx, &qhs_cpr_mx, + &qhs_cpr_nspcx, &qhs_cpr_nsphmx, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg, + &qhs_emac0_cfg, &qhs_gp_dsp0_cfg, + &qhs_gpdsp0_throttle_cfg, &qhs_gpu_tcu_throttle_cfg, + &qhs_gpuss_cfg, &qhs_hwkm, + &qhs_imem_cfg, &qhs_ipa, + &qhs_ipc_router, &qhs_lpass_cfg, + &qhs_lpass_throttle_cfg, &qhs_mx_rdpm, + &qhs_mxc_rdpm, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_pcie_tcu_throttle_cfg, + &qhs_pcie_throttle_cfg, &qhs_pdm, + &qhs_pimem_cfg, &qhs_pke_wrapper_cfg, + &qhs_qdss_cfg, &qhs_qm_cfg, + &qhs_qm_mpu_cfg, &qhs_qup0, + &qhs_qup1, &qhs_qup3, + &qhs_sail_throttle_cfg, &qhs_sdc1, + &qhs_security, &qhs_snoc_throttle_cfg, + &qhs_tcsr, &qhs_tlmm, + &qhs_tsc_cfg, &qhs_ufs_mem_cfg, + &qhs_usb2_0, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_venus_cvp_throttle_cfg, + &qhs_venus_v_cpu_throttle_cfg, + &qhs_venus_vcodec_throttle_cfg, + &qns_ddrss_cfg, &qns_gpdsp_noc_cfg, + &qns_mnoc_hf_cfg, &qns_mnoc_sf_cfg, + &qns_pcie_anoc_cfg, &qns_snoc_cfg, + &qxs_boot_imem, &qxs_imem, + &qxs_pimem, &xs_qdss_stm, + &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie = { + .name = "qnm_gemnoc_pcie", + .channels = 1, + .buswidth = 16, + .num_links = 2, + .link_nodes = { &xs_pcie_0, &xs_pcie_1 }, +}; + +static struct qcom_icc_node qnm_cnoc_dc_noc = { + .name = "qnm_cnoc_dc_noc", + .channels = 1, + .buswidth = 4, + .num_links = 2, + .link_nodes = { &qhs_llcc, &qns_gemnoc }, +}; + +static struct qcom_icc_node alm_gpu_tcu = { + .name = "alm_gpu_tcu", + .channels = 1, + .buswidth = 8, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node alm_pcie_tcu = { + .name = "alm_pcie_tcu", + .channels = 1, + .buswidth = 8, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node alm_sys_tcu = { + .name = "alm_sys_tcu", + .channels = 1, + .buswidth = 8, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node chm_apps = { + .name = "chm_apps", + .channels = 4, + .buswidth = 32, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_cmpnoc0 = { + .name = "qnm_cmpnoc0", + .channels = 2, + .buswidth = 32, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node qnm_gemnoc_cfg = { + .name = "qnm_gemnoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 4, + .link_nodes = { &srvc_even_gemnoc, &srvc_odd_gemnoc, + &srvc_sys_gemnoc, &srvc_sys_gemnoc_2 }, +}; + +static struct qcom_icc_node qnm_gpdsp_sail = { + .name = "qnm_gpdsp_sail", + .channels = 1, + .buswidth = 16, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node qnm_gpu = { + .name = "qnm_gpu", + .channels = 2, + .buswidth = 32, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .channels = 2, + .buswidth = 32, + .num_links = 2, + .link_nodes = { &qns_llcc, &qns_pcie }, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .channels = 2, + .buswidth = 32, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_pcie = { + .name = "qnm_pcie", + .channels = 1, + .buswidth = 32, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_llcc }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .channels = 1, + .buswidth = 16, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_sailss_md0 = { + .name = "qnm_sailss_md0", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_gp_dsp_sail_noc }, +}; + +static struct qcom_icc_node qxm_dsp0 = { + .name = "qxm_dsp0", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_gp_dsp_sail_noc }, +}; + +static struct qcom_icc_node qhm_config_noc = { + .name = "qhm_config_noc", + .channels = 1, + .buswidth = 4, + .num_links = 6, + .link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi, + &qhs_lpass_mpu, &qhs_lpass_top, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, +}; + +static struct qcom_icc_node qxm_lpass_dsp = { + .name = "qxm_lpass_dsp", + .channels = 1, + .buswidth = 8, + .num_links = 4, + .link_nodes = { &qhs_lpass_top, &qns_sysnoc, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .channels = 8, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &ebi }, +}; + +static struct qcom_icc_node qnm_camnoc_hf = { + .name = "qnm_camnoc_hf", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qnm_camnoc_icp = { + .name = "qnm_camnoc_icp", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_camnoc_sf = { + .name = "qnm_camnoc_sf", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_mdp0_0 = { + .name = "qnm_mdp0_0", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qnm_mdp0_1 = { + .name = "qnm_mdp0_1", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qnm_mnoc_hf_cfg = { + .name = "qnm_mnoc_hf_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &srvc_mnoc_hf }, +}; + +static struct qcom_icc_node qnm_mnoc_sf_cfg = { + .name = "qnm_mnoc_sf_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &srvc_mnoc_sf }, +}; + +static struct qcom_icc_node qnm_video0 = { + .name = "qnm_video0", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_cvp = { + .name = "qnm_video_cvp", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_v_cpu = { + .name = "qnm_video_v_cpu", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qhm_nsp_noc_config = { + .name = "qhm_nsp_noc_config", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &service_nsp_noc }, +}; + +static struct qcom_icc_node qxm_nsp = { + .name = "qxm_nsp", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_hcp, &qns_nsp_gemnoc }, +}; + +static struct qcom_icc_node xm_pcie3_0 = { + .name = "xm_pcie3_0", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_pcie_mem_noc }, +}; + +static struct qcom_icc_node xm_pcie3_1 = { + .name = "xm_pcie3_1", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_pcie_mem_noc }, +}; + +static struct qcom_icc_node qhm_gic = { + .name = "qhm_gic", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_lpass_noc = { + .name = "qnm_lpass_noc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_snoc_cfg = { + .name = "qnm_snoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &srvc_snoc }, +}; + +static struct qcom_icc_node qxm_pimem = { + .name = "qxm_pimem", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_gemnoc_gc }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_gemnoc_gc }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_node qup0_core_slave = { + .name = "qup0_core_slave", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup1_core_slave = { + .name = "qup1_core_slave", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup3_core_slave = { + .name = "qup3_core_slave", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy2 = { + .name = "qhs_ahb2phy2", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy3 = { + .name = "qhs_ahb2phy3", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_anoc_throttle_cfg = { + .name = "qhs_anoc_throttle_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_apss = { + .name = "qhs_apss", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_boot_rom = { + .name = "qhs_boot_rom", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = { + .name = "qhs_camera_nrt_throttle_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { + .name = "qhs_camera_rt_throttle_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_compute0_cfg = { + .name = "qhs_compute0_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qhm_nsp_noc_config }, +}; + +static struct qcom_icc_node qhs_cpr_cx = { + .name = "qhs_cpr_cx", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mmcx = { + .name = "qhs_cpr_mmcx", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mx = { + .name = "qhs_cpr_mx", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_nspcx = { + .name = "qhs_cpr_nspcx", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_nsphmx = { + .name = "qhs_cpr_nsphmx", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cx_rdpm = { + .name = "qhs_cx_rdpm", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display0_cfg = { + .name = "qhs_display0_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display0_rt_throttle_cfg = { + .name = "qhs_display0_rt_throttle_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_emac0_cfg = { + .name = "qhs_emac0_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gp_dsp0_cfg = { + .name = "qhs_gp_dsp0_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpdsp0_throttle_cfg = { + .name = "qhs_gpdsp0_throttle_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg = { + .name = "qhs_gpu_tcu_throttle_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_hwkm = { + .name = "qhs_hwkm", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipc_router = { + .name = "qhs_ipc_router", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_cfg = { + .name = "qhs_lpass_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qhm_config_noc }, +}; + +static struct qcom_icc_node qhs_lpass_throttle_cfg = { + .name = "qhs_lpass_throttle_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mx_rdpm = { + .name = "qhs_mx_rdpm", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mxc_rdpm = { + .name = "qhs_mxc_rdpm", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie0_cfg = { + .name = "qhs_pcie0_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie1_cfg = { + .name = "qhs_pcie1_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg = { + .name = "qhs_pcie_tcu_throttle_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie_throttle_cfg = { + .name = "qhs_pcie_throttle_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg = { + .name = "qhs_pimem_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pke_wrapper_cfg = { + .name = "qhs_pke_wrapper_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qm_cfg = { + .name = "qhs_qm_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qm_mpu_cfg = { + .name = "qhs_qm_mpu_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup0 = { + .name = "qhs_qup0", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup1 = { + .name = "qhs_qup1", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup3 = { + .name = "qhs_qup3", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sail_throttle_cfg = { + .name = "qhs_sail_throttle_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc1 = { + .name = "qhs_sdc1", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_security = { + .name = "qhs_security", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_snoc_throttle_cfg = { + .name = "qhs_snoc_throttle_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm = { + .name = "qhs_tlmm", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tsc_cfg = { + .name = "qhs_tsc_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb2_0 = { + .name = "qhs_usb2_0", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_0 = { + .name = "qhs_usb3_0", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = { + .name = "qhs_venus_cvp_throttle_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg = { + .name = "qhs_venus_v_cpu_throttle_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg = { + .name = "qhs_venus_vcodec_throttle_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_ddrss_cfg = { + .name = "qns_ddrss_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qnm_cnoc_dc_noc }, +}; + +static struct qcom_icc_node qns_gpdsp_noc_cfg = { + .name = "qns_gpdsp_noc_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_mnoc_hf_cfg = { + .name = "qns_mnoc_hf_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qnm_mnoc_hf_cfg }, +}; + +static struct qcom_icc_node qns_mnoc_sf_cfg = { + .name = "qns_mnoc_sf_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qnm_mnoc_sf_cfg }, +}; + +static struct qcom_icc_node qns_pcie_anoc_cfg = { + .name = "qns_pcie_anoc_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_snoc_cfg = { + .name = "qns_snoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qnm_snoc_cfg }, +}; + +static struct qcom_icc_node qxs_boot_imem = { + .name = "qxs_boot_imem", + .channels = 1, + .buswidth = 16, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_pimem = { + .name = "qxs_pimem", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_pcie_0 = { + .name = "xs_pcie_0", + .channels = 1, + .buswidth = 16, +}; + +static struct qcom_icc_node xs_pcie_1 = { + .name = "xs_pcie_1", + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_llcc = { + .name = "qhs_llcc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_gemnoc = { + .name = "qns_gemnoc", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qnm_gemnoc_cfg }, +}; + +static struct qcom_icc_node qns_gem_noc_cnoc = { + .name = "qns_gem_noc_cnoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_gemnoc_cnoc }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .channels = 4, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &llcc_mc }, +}; + +static struct qcom_icc_node qns_pcie = { + .name = "qns_pcie", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_gemnoc_pcie }, +}; + +static struct qcom_icc_node srvc_even_gemnoc = { + .name = "srvc_even_gemnoc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_odd_gemnoc = { + .name = "srvc_odd_gemnoc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_sys_gemnoc = { + .name = "srvc_sys_gemnoc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_sys_gemnoc_2 = { + .name = "srvc_sys_gemnoc_2", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_gp_dsp_sail_noc = { + .name = "qns_gp_dsp_sail_noc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_gpdsp_sail }, +}; + +static struct qcom_icc_node qhs_lpass_core = { + .name = "qhs_lpass_core", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_lpi = { + .name = "qhs_lpass_lpi", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_mpu = { + .name = "qhs_lpass_mpu", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_top = { + .name = "qhs_lpass_top", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_sysnoc = { + .name = "qns_sysnoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_lpass_noc }, +}; + +static struct qcom_icc_node srvc_niu_aml_noc = { + .name = "srvc_niu_aml_noc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_niu_lpass_agnoc = { + .name = "srvc_niu_lpass_agnoc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .channels = 8, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_mnoc_hf }, +}; + +static struct qcom_icc_node qns_mem_noc_sf = { + .name = "qns_mem_noc_sf", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_mnoc_sf }, +}; + +static struct qcom_icc_node srvc_mnoc_hf = { + .name = "srvc_mnoc_hf", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_mnoc_sf = { + .name = "srvc_mnoc_sf", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_hcp = { + .name = "qns_hcp", + .channels = 2, + .buswidth = 32, +}; + +static struct qcom_icc_node qns_nsp_gemnoc = { + .name = "qns_nsp_gemnoc", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_cmpnoc0 }, +}; + +static struct qcom_icc_node service_nsp_noc = { + .name = "service_nsp_noc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_pcie_mem_noc = { + .name = "qns_pcie_mem_noc", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_pcie }, +}; + +static struct qcom_icc_node qns_gemnoc_gc = { + .name = "qns_gemnoc_gc", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qnm_snoc_gc }, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_snoc_sf }, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .enable_mask = BIT(3), + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .num_nodes = 2, + .nodes = { &qxm_crypto_0, &qxm_crypto_1 }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .keepalive = true, + .num_nodes = 2, + .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie }, +}; + +static struct qcom_icc_bcm bcm_cn1 = { + .name = "CN1", + .num_nodes = 66, + .nodes = { &qhs_ahb2phy2, &qhs_ahb2phy3, + &qhs_anoc_throttle_cfg, &qhs_aoss, + &qhs_apss, &qhs_boot_rom, + &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, + &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, + &qhs_compute0_cfg, &qhs_cpr_cx, + &qhs_cpr_mmcx, &qhs_cpr_mx, + &qhs_cpr_nspcx, &qhs_cpr_nsphmx, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg, + &qhs_emac0_cfg, &qhs_gp_dsp0_cfg, + &qhs_gpdsp0_throttle_cfg, &qhs_gpu_tcu_throttle_cfg, + &qhs_gpuss_cfg, &qhs_hwkm, + &qhs_imem_cfg, &qhs_ipa, + &qhs_ipc_router, &qhs_lpass_cfg, + &qhs_lpass_throttle_cfg, &qhs_mx_rdpm, + &qhs_mxc_rdpm, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_pcie_tcu_throttle_cfg, + &qhs_pcie_throttle_cfg, &qhs_pdm, + &qhs_pimem_cfg, &qhs_pke_wrapper_cfg, + &qhs_qdss_cfg, &qhs_qm_cfg, + &qhs_qm_mpu_cfg, &qhs_sail_throttle_cfg, + &qhs_sdc1, &qhs_security, + &qhs_snoc_throttle_cfg, &qhs_tcsr, + &qhs_tlmm, &qhs_tsc_cfg, + &qhs_ufs_mem_cfg, &qhs_usb2_0, + &qhs_usb3_0, &qhs_venus_cfg, + &qhs_venus_cvp_throttle_cfg, &qhs_venus_v_cpu_throttle_cfg, + &qhs_venus_vcodec_throttle_cfg, &qns_ddrss_cfg, + &qns_gpdsp_noc_cfg, &qns_mnoc_hf_cfg, + &qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg, + &qns_snoc_cfg, &qxs_boot_imem, + &qxs_imem, &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_bcm bcm_cn2 = { + .name = "CN2", + .num_nodes = 3, + .nodes = { &qhs_qup0, &qhs_qup1, + &qhs_qup3 }, +}; + +static struct qcom_icc_bcm bcm_cn3 = { + .name = "CN3", + .num_nodes = 2, + .nodes = { &xs_pcie_0, &xs_pcie_1 }, +}; + +static struct qcom_icc_bcm bcm_gna0 = { + .name = "GNA0", + .num_nodes = 1, + .nodes = { &qxm_dsp0 }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .keepalive = true, + .num_nodes = 4, + .nodes = { &qnm_camnoc_hf, &qnm_mdp0_0, + &qnm_mdp0_1, &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .num_nodes = 6, + .nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf, + &qnm_video0, &qnm_video_cvp, + &qnm_video_v_cpu, &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_nsa0 = { + .name = "NSA0", + .num_nodes = 2, + .nodes = { &qns_hcp, &qns_nsp_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_nsa1 = { + .name = "NSA1", + .num_nodes = 1, + .nodes = { &qxm_nsp }, +}; + +static struct qcom_icc_bcm bcm_pci0 = { + .name = "PCI0", + .num_nodes = 1, + .nodes = { &qns_pcie_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .vote_scale = 1, + .keepalive = true, + .num_nodes = 1, + .nodes = { &qup0_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup1 = { + .name = "QUP1", + .vote_scale = 1, + .keepalive = true, + .num_nodes = 1, + .nodes = { &qup1_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup2 = { + .name = "QUP2", + .vote_scale = 1, + .keepalive = true, + .num_nodes = 1, + .nodes = { &qup3_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh2 = { + .name = "SH2", + .num_nodes = 1, + .nodes = { &chm_apps }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .num_nodes = 1, + .nodes = { &qns_gemnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .num_nodes = 1, + .nodes = { &qxs_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .num_nodes = 2, + .nodes = { &qns_a1noc_snoc, &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .num_nodes = 2, + .nodes = { &qns_a2noc_snoc, &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn9 = { + .name = "SN9", + .num_nodes = 2, + .nodes = { &qns_sysnoc, &qnm_lpass_noc }, +}; + +static struct qcom_icc_bcm bcm_sn10 = { + .name = "SN10", + .num_nodes = 1, + .nodes = { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { + &bcm_sn3, +}; + +static struct qcom_icc_node * const aggre1_noc_nodes[] = { + [MASTER_QUP_3] = &qxm_qup3, + [MASTER_EMAC] = &xm_emac_0, + [MASTER_SDC] = &xm_sdc1, + [MASTER_UFS_MEM] = &xm_ufs_mem, + [MASTER_USB2] = &xm_usb2_2, + [MASTER_USB3_0] = &xm_usb3_0, + [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, +}; + +static const struct qcom_icc_desc qcs8300_aggre1_noc = { + .nodes = aggre1_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), + .bcms = aggre1_noc_bcms, + .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), +}; + +static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { + &bcm_ce0, + &bcm_sn4, +}; + +static struct qcom_icc_node * const aggre2_noc_nodes[] = { + [MASTER_QDSS_BAM] = &qhm_qdss_bam, + [MASTER_QUP_0] = &qhm_qup0, + [MASTER_QUP_1] = &qhm_qup1, + [MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath, + [MASTER_CRYPTO_CORE0] = &qxm_crypto_0, + [MASTER_CRYPTO_CORE1] = &qxm_crypto_1, + [MASTER_IPA] = &qxm_ipa, + [MASTER_QDSS_ETR_0] = &xm_qdss_etr_0, + [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, + [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, +}; + +static const struct qcom_icc_desc qcs8300_aggre2_noc = { + .nodes = aggre2_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), + .bcms = aggre2_noc_bcms, + .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), +}; + +static struct qcom_icc_bcm * const clk_virt_bcms[] = { + &bcm_qup0, + &bcm_qup1, + &bcm_qup2, +}; + +static struct qcom_icc_node * const clk_virt_nodes[] = { + [MASTER_QUP_CORE_0] = &qup0_core_master, + [MASTER_QUP_CORE_1] = &qup1_core_master, + [MASTER_QUP_CORE_3] = &qup3_core_master, + [SLAVE_QUP_CORE_0] = &qup0_core_slave, + [SLAVE_QUP_CORE_1] = &qup1_core_slave, + [SLAVE_QUP_CORE_3] = &qup3_core_slave, +}; + +static const struct qcom_icc_desc qcs8300_clk_virt = { + .nodes = clk_virt_nodes, + .num_nodes = ARRAY_SIZE(clk_virt_nodes), + .bcms = clk_virt_bcms, + .num_bcms = ARRAY_SIZE(clk_virt_bcms), +}; + +static struct qcom_icc_bcm * const config_noc_bcms[] = { + &bcm_cn0, + &bcm_cn1, + &bcm_cn2, + &bcm_cn3, + &bcm_sn2, + &bcm_sn10, +}; + +static struct qcom_icc_node * const config_noc_nodes[] = { + [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, + [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, + [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2, + [SLAVE_AHB2PHY_3] = &qhs_ahb2phy3, + [SLAVE_ANOC_THROTTLE_CFG] = &qhs_anoc_throttle_cfg, + [SLAVE_AOSS] = &qhs_aoss, + [SLAVE_APPSS] = &qhs_apss, + [SLAVE_BOOT_ROM] = &qhs_boot_rom, + [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, + [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg, + [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg, + [SLAVE_CLK_CTL] = &qhs_clk_ctl, + [SLAVE_CDSP_CFG] = &qhs_compute0_cfg, + [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, + [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, + [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, + [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx, + [SLAVE_CPR_NSPHMX] = &qhs_cpr_nsphmx, + [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, + [SLAVE_CX_RDPM] = &qhs_cx_rdpm, + [SLAVE_DISPLAY_CFG] = &qhs_display0_cfg, + [SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display0_rt_throttle_cfg, + [SLAVE_EMAC_CFG] = &qhs_emac0_cfg, + [SLAVE_GP_DSP0_CFG] = &qhs_gp_dsp0_cfg, + [SLAVE_GPDSP0_THROTTLE_CFG] = &qhs_gpdsp0_throttle_cfg, + [SLAVE_GPU_TCU_THROTTLE_CFG] = &qhs_gpu_tcu_throttle_cfg, + [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, + [SLAVE_HWKM] = &qhs_hwkm, + [SLAVE_IMEM_CFG] = &qhs_imem_cfg, + [SLAVE_IPA_CFG] = &qhs_ipa, + [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, + [SLAVE_LPASS] = &qhs_lpass_cfg, + [SLAVE_LPASS_THROTTLE_CFG] = &qhs_lpass_throttle_cfg, + [SLAVE_MX_RDPM] = &qhs_mx_rdpm, + [SLAVE_MXC_RDPM] = &qhs_mxc_rdpm, + [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, + [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, + [SLAVE_PCIE_TCU_THROTTLE_CFG] = &qhs_pcie_tcu_throttle_cfg, + [SLAVE_PCIE_THROTTLE_CFG] = &qhs_pcie_throttle_cfg, + [SLAVE_PDM] = &qhs_pdm, + [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, + [SLAVE_PKA_WRAPPER_CFG] = &qhs_pke_wrapper_cfg, + [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, + [SLAVE_QM_CFG] = &qhs_qm_cfg, + [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg, + [SLAVE_QUP_0] = &qhs_qup0, + [SLAVE_QUP_1] = &qhs_qup1, + [SLAVE_QUP_3] = &qhs_qup3, + [SLAVE_SAIL_THROTTLE_CFG] = &qhs_sail_throttle_cfg, + [SLAVE_SDC1] = &qhs_sdc1, + [SLAVE_SECURITY] = &qhs_security, + [SLAVE_SNOC_THROTTLE_CFG] = &qhs_snoc_throttle_cfg, + [SLAVE_TCSR] = &qhs_tcsr, + [SLAVE_TLMM] = &qhs_tlmm, + [SLAVE_TSC_CFG] = &qhs_tsc_cfg, + [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, + [SLAVE_USB2] = &qhs_usb2_0, + [SLAVE_USB3_0] = &qhs_usb3_0, + [SLAVE_VENUS_CFG] = &qhs_venus_cfg, + [SLAVE_VENUS_CVP_THROTTLE_CFG] = &qhs_venus_cvp_throttle_cfg, + [SLAVE_VENUS_V_CPU_THROTTLE_CFG] = &qhs_venus_v_cpu_throttle_cfg, + [SLAVE_VENUS_VCODEC_THROTTLE_CFG] = &qhs_venus_vcodec_throttle_cfg, + [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, + [SLAVE_GPDSP_NOC_CFG] = &qns_gpdsp_noc_cfg, + [SLAVE_CNOC_MNOC_HF_CFG] = &qns_mnoc_hf_cfg, + [SLAVE_CNOC_MNOC_SF_CFG] = &qns_mnoc_sf_cfg, + [SLAVE_PCIE_ANOC_CFG] = &qns_pcie_anoc_cfg, + [SLAVE_SNOC_CFG] = &qns_snoc_cfg, + [SLAVE_BOOT_IMEM] = &qxs_boot_imem, + [SLAVE_IMEM] = &qxs_imem, + [SLAVE_PIMEM] = &qxs_pimem, + [SLAVE_PCIE_0] = &xs_pcie_0, + [SLAVE_PCIE_1] = &xs_pcie_1, + [SLAVE_QDSS_STM] = &xs_qdss_stm, + [SLAVE_TCU] = &xs_sys_tcu_cfg, +}; + +static const struct qcom_icc_desc qcs8300_config_noc = { + .nodes = config_noc_nodes, + .num_nodes = ARRAY_SIZE(config_noc_nodes), + .bcms = config_noc_bcms, + .num_bcms = ARRAY_SIZE(config_noc_bcms), +}; + +static struct qcom_icc_node * const dc_noc_nodes[] = { + [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc, + [SLAVE_LLCC_CFG] = &qhs_llcc, + [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, +}; + +static const struct qcom_icc_desc qcs8300_dc_noc = { + .nodes = dc_noc_nodes, + .num_nodes = ARRAY_SIZE(dc_noc_nodes), +}; + +static struct qcom_icc_bcm * const gem_noc_bcms[] = { + &bcm_sh0, + &bcm_sh2, +}; + +static struct qcom_icc_node * const gem_noc_nodes[] = { + [MASTER_GPU_TCU] = &alm_gpu_tcu, + [MASTER_PCIE_TCU] = &alm_pcie_tcu, + [MASTER_SYS_TCU] = &alm_sys_tcu, + [MASTER_APPSS_PROC] = &chm_apps, + [MASTER_COMPUTE_NOC] = &qnm_cmpnoc0, + [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg, + [MASTER_GPDSP_SAIL] = &qnm_gpdsp_sail, + [MASTER_GFX3D] = &qnm_gpu, + [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, + [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, + [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, + [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, + [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, + [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, + [SLAVE_LLCC] = &qns_llcc, + [SLAVE_GEM_NOC_PCIE_CNOC] = &qns_pcie, + [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc, + [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc, + [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, + [SLAVE_SERVICE_GEM_NOC2] = &srvc_sys_gemnoc_2, +}; + +static const struct qcom_icc_desc qcs8300_gem_noc = { + .nodes = gem_noc_nodes, + .num_nodes = ARRAY_SIZE(gem_noc_nodes), + .bcms = gem_noc_bcms, + .num_bcms = ARRAY_SIZE(gem_noc_bcms), +}; + +static struct qcom_icc_bcm * const gpdsp_anoc_bcms[] = { + &bcm_gna0, +}; + +static struct qcom_icc_node * const gpdsp_anoc_nodes[] = { + [MASTER_SAILSS_MD0] = &qnm_sailss_md0, + [MASTER_DSP0] = &qxm_dsp0, + [SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc, +}; + +static const struct qcom_icc_desc qcs8300_gpdsp_anoc = { + .nodes = gpdsp_anoc_nodes, + .num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes), + .bcms = gpdsp_anoc_bcms, + .num_bcms = ARRAY_SIZE(gpdsp_anoc_bcms), +}; + +static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { + &bcm_sn9, +}; + +static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { + [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, + [MASTER_LPASS_PROC] = &qxm_lpass_dsp, + [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, + [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, + [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, + [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, + [SLAVE_LPASS_SNOC] = &qns_sysnoc, + [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, + [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, +}; + +static const struct qcom_icc_desc qcs8300_lpass_ag_noc = { + .nodes = lpass_ag_noc_nodes, + .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), + .bcms = lpass_ag_noc_bcms, + .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), +}; + +static struct qcom_icc_bcm * const mc_virt_bcms[] = { + &bcm_acv, + &bcm_mc0, +}; + +static struct qcom_icc_node * const mc_virt_nodes[] = { + [MASTER_LLCC] = &llcc_mc, + [SLAVE_EBI1] = &ebi, +}; + +static const struct qcom_icc_desc qcs8300_mc_virt = { + .nodes = mc_virt_nodes, + .num_nodes = ARRAY_SIZE(mc_virt_nodes), + .bcms = mc_virt_bcms, + .num_bcms = ARRAY_SIZE(mc_virt_bcms), +}; + +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { + &bcm_mm0, + &bcm_mm1, +}; + +static struct qcom_icc_node * const mmss_noc_nodes[] = { + [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, + [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, + [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, + [MASTER_MDP0] = &qnm_mdp0_0, + [MASTER_MDP1] = &qnm_mdp0_1, + [MASTER_CNOC_MNOC_HF_CFG] = &qnm_mnoc_hf_cfg, + [MASTER_CNOC_MNOC_SF_CFG] = &qnm_mnoc_sf_cfg, + [MASTER_VIDEO_P0] = &qnm_video0, + [MASTER_VIDEO_PROC] = &qnm_video_cvp, + [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, + [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, + [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, + [SLAVE_SERVICE_MNOC_HF] = &srvc_mnoc_hf, + [SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf, +}; + +static const struct qcom_icc_desc qcs8300_mmss_noc = { + .nodes = mmss_noc_nodes, + .num_nodes = ARRAY_SIZE(mmss_noc_nodes), + .bcms = mmss_noc_bcms, + .num_bcms = ARRAY_SIZE(mmss_noc_bcms), +}; + +static struct qcom_icc_bcm * const nspa_noc_bcms[] = { + &bcm_nsa0, + &bcm_nsa1, +}; + +static struct qcom_icc_node * const nspa_noc_nodes[] = { + [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, + [MASTER_CDSP_PROC] = &qxm_nsp, + [SLAVE_HCP_A] = &qns_hcp, + [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, + [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, +}; + +static const struct qcom_icc_desc qcs8300_nspa_noc = { + .nodes = nspa_noc_nodes, + .num_nodes = ARRAY_SIZE(nspa_noc_nodes), + .bcms = nspa_noc_bcms, + .num_bcms = ARRAY_SIZE(nspa_noc_bcms), +}; + +static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { + &bcm_pci0, +}; + +static struct qcom_icc_node * const pcie_anoc_nodes[] = { + [MASTER_PCIE_0] = &xm_pcie3_0, + [MASTER_PCIE_1] = &xm_pcie3_1, + [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, +}; + +static const struct qcom_icc_desc qcs8300_pcie_anoc = { + .nodes = pcie_anoc_nodes, + .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), + .bcms = pcie_anoc_bcms, + .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), +}; + +static struct qcom_icc_bcm * const system_noc_bcms[] = { + &bcm_sn0, + &bcm_sn1, + &bcm_sn3, + &bcm_sn4, + &bcm_sn9, +}; + +static struct qcom_icc_node * const system_noc_nodes[] = { + [MASTER_GIC_AHB] = &qhm_gic, + [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, + [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, + [MASTER_LPASS_ANOC] = &qnm_lpass_noc, + [MASTER_SNOC_CFG] = &qnm_snoc_cfg, + [MASTER_PIMEM] = &qxm_pimem, + [MASTER_GIC] = &xm_gic, + [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, + [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, + [SLAVE_SERVICE_SNOC] = &srvc_snoc, +}; + +static const struct qcom_icc_desc qcs8300_system_noc = { + .nodes = system_noc_nodes, + .num_nodes = ARRAY_SIZE(system_noc_nodes), + .bcms = system_noc_bcms, + .num_bcms = ARRAY_SIZE(system_noc_bcms), +}; + +static const struct of_device_id qnoc_of_match[] = { + { .compatible = "qcom,qcs8300-aggre1-noc", + .data = &qcs8300_aggre1_noc}, + { .compatible = "qcom,qcs8300-aggre2-noc", + .data = &qcs8300_aggre2_noc}, + { .compatible = "qcom,qcs8300-clk-virt", + .data = &qcs8300_clk_virt}, + { .compatible = "qcom,qcs8300-config-noc", + .data = &qcs8300_config_noc}, + { .compatible = "qcom,qcs8300-dc-noc", + .data = &qcs8300_dc_noc}, + { .compatible = "qcom,qcs8300-gem-noc", + .data = &qcs8300_gem_noc}, + { .compatible = "qcom,qcs8300-gpdsp-anoc", + .data = &qcs8300_gpdsp_anoc}, + { .compatible = "qcom,qcs8300-lpass-ag-noc", + .data = &qcs8300_lpass_ag_noc}, + { .compatible = "qcom,qcs8300-mc-virt", + .data = &qcs8300_mc_virt}, + { .compatible = "qcom,qcs8300-mmss-noc", + .data = &qcs8300_mmss_noc}, + { .compatible = "qcom,qcs8300-nspa-noc", + .data = &qcs8300_nspa_noc}, + { .compatible = "qcom,qcs8300-pcie-anoc", + .data = &qcs8300_pcie_anoc}, + { .compatible = "qcom,qcs8300-system-noc", + .data = &qcs8300_system_noc}, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver = { + .probe = qcom_icc_rpmh_probe, + .remove = qcom_icc_rpmh_remove, + .driver = { + .name = "qnoc-qcs8300", + .of_match_table = qnoc_of_match, + .sync_state = icc_sync_state, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION("QCS8300 NoC driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/interconnect/qcom/qdu1000.c b/drivers/interconnect/qcom/qdu1000.c index 9cb477d2bdfe..0006413241dc 100644 --- a/drivers/interconnect/qcom/qdu1000.c +++ b/drivers/interconnect/qcom/qdu1000.c @@ -15,756 +15,710 @@ #include "bcm-voter.h" #include "icc-common.h" #include "icc-rpmh.h" -#include "qdu1000.h" + +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_ecpri_dma; +static struct qcom_icc_node qnm_fec_2_gemnoc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_mdsp; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qhm_gic; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qpic; +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qhm_system_noc_cfg; +static struct qcom_icc_node qnm_aggre_noc; +static struct qcom_icc_node qnm_aggre_noc_gsi; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_modem_slave; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ecpri_gsi; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_ecpri_dma; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node xm_pcie; +static struct qcom_icc_node xm_qdss_etr0; +static struct qcom_icc_node xm_qdss_etr1; +static struct qcom_icc_node xm_sdc; +static struct qcom_icc_node xm_usb3; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_modem_slave; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qhs_ahb2phy0_south; +static struct qcom_icc_node qhs_ahb2phy1_north; +static struct qcom_icc_node qhs_ahb2phy2_east; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto_cfg; +static struct qcom_icc_node qhs_ecpri_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_pcie_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qpic; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_smbus_cfg; +static struct qcom_icc_node qhs_system_noc_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qhs_tsc_cfg; +static struct qcom_icc_node qhs_usb3; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_anoc_snoc_gsi; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qns_ecpri_gemnoc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qns_modem; +static struct qcom_icc_node qns_pcie_gemnoc; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_system_noc; +static struct qcom_icc_node xs_ethernet_ss; +static struct qcom_icc_node xs_pcie; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", - .id = QDU1000_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QDU1000_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { .name = "qup1_core_master", - .id = QDU1000_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QDU1000_SLAVE_QUP_CORE_1 }, + .link_nodes = { &qup1_core_slave }, }; static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", - .id = QDU1000_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", - .id = QDU1000_MASTER_APPSS_PROC, .channels = 1, .buswidth = 16, .num_links = 4, - .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC, - QDU1000_SLAVE_GEMNOC_MODEM_CNOC, QDU1000_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_modem_slave, &qns_pcie }, }; static struct qcom_icc_node qnm_ecpri_dma = { .name = "qnm_ecpri_dma", - .id = QDU1000_MASTER_GEMNOC_ECPRI_DMA, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_fec_2_gemnoc = { .name = "qnm_fec_2_gemnoc", - .id = QDU1000_MASTER_FEC_2_GEMNOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = QDU1000_MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 64, .num_links = 3, - .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC, - QDU1000_SLAVE_GEMNOC_MODEM_CNOC - }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_modem_slave }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = QDU1000_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = QDU1000_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 4, - .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC, - QDU1000_SLAVE_GEMNOC_MODEM_CNOC, QDU1000_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_modem_slave, &qns_pcie }, }; static struct qcom_icc_node qxm_mdsp = { .name = "qxm_mdsp", - .id = QDU1000_MASTER_MSS_PROC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC, - QDU1000_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = QDU1000_MASTER_LLCC, .channels = 8, .buswidth = 4, .num_links = 1, - .links = { QDU1000_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qhm_gic = { .name = "qhm_gic", - .id = QDU1000_MASTER_GIC_AHB, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = QDU1000_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qhm_qpic = { .name = "qhm_qpic", - .id = QDU1000_MASTER_QPIC, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QDU1000_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = QDU1000_MASTER_QSPI_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QDU1000_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", - .id = QDU1000_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QDU1000_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = QDU1000_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QDU1000_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_system_noc_cfg = { .name = "qhm_system_noc_cfg", - .id = QDU1000_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QDU1000_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_system_noc }, }; static struct qcom_icc_node qnm_aggre_noc = { .name = "qnm_aggre_noc", - .id = QDU1000_MASTER_ANOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre_noc_gsi = { .name = "qnm_aggre_noc_gsi", - .id = QDU1000_MASTER_ANOC_GSI, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", - .id = QDU1000_MASTER_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 36, - .links = { QDU1000_SLAVE_AHB2PHY_SOUTH, QDU1000_SLAVE_AHB2PHY_NORTH, - QDU1000_SLAVE_AHB2PHY_EAST, QDU1000_SLAVE_AOSS, - QDU1000_SLAVE_CLK_CTL, QDU1000_SLAVE_RBCPR_CX_CFG, - QDU1000_SLAVE_RBCPR_MX_CFG, QDU1000_SLAVE_CRYPTO_0_CFG, - QDU1000_SLAVE_ECPRI_CFG, QDU1000_SLAVE_IMEM_CFG, - QDU1000_SLAVE_IPC_ROUTER_CFG, QDU1000_SLAVE_CNOC_MSS, - QDU1000_SLAVE_PCIE_CFG, QDU1000_SLAVE_PDM, - QDU1000_SLAVE_PIMEM_CFG, QDU1000_SLAVE_PRNG, - QDU1000_SLAVE_QDSS_CFG, QDU1000_SLAVE_QPIC, - QDU1000_SLAVE_QSPI_0, QDU1000_SLAVE_QUP_0, - QDU1000_SLAVE_QUP_1, QDU1000_SLAVE_SDCC_2, - QDU1000_SLAVE_SMBUS_CFG, QDU1000_SLAVE_SNOC_CFG, - QDU1000_SLAVE_TCSR, QDU1000_SLAVE_TLMM, - QDU1000_SLAVE_TME_CFG, QDU1000_SLAVE_TSC_CFG, - QDU1000_SLAVE_USB3_0, QDU1000_SLAVE_VSENSE_CTRL_CFG, - QDU1000_SLAVE_DDRSS_CFG, QDU1000_SLAVE_IMEM, - QDU1000_SLAVE_PIMEM, QDU1000_SLAVE_ETHERNET_SS, - QDU1000_SLAVE_QDSS_STM, QDU1000_SLAVE_TCU - }, + .link_nodes = { &qhs_ahb2phy0_south, &qhs_ahb2phy1_north, + &qhs_ahb2phy2_east, &qhs_aoss, + &qhs_clk_ctl, &qhs_cpr_cx, + &qhs_cpr_mx, &qhs_crypto_cfg, + &qhs_ecpri_cfg, &qhs_imem_cfg, + &qhs_ipc_router, &qhs_mss_cfg, + &qhs_pcie_cfg, &qhs_pdm, + &qhs_pimem_cfg, &qhs_prng, + &qhs_qdss_cfg, &qhs_qpic, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc2, + &qhs_smbus_cfg, &qhs_system_noc_cfg, + &qhs_tcsr, &qhs_tlmm, + &qhs_tme_cfg, &qhs_tsc_cfg, + &qhs_usb3, &qhs_vsense_ctrl_cfg, + &qns_ddrss_cfg, &qxs_imem, + &qxs_pimem, &xs_ethernet_ss, + &xs_qdss_stm, &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc_modem_slave = { .name = "qnm_gemnoc_modem_slave", - .id = QDU1000_MASTER_GEMNOC_MODEM_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QDU1000_SLAVE_MODEM_OFFLINE }, + .link_nodes = { &qns_modem }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = QDU1000_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QDU1000_SLAVE_PCIE_0 }, + .link_nodes = { &xs_pcie }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = QDU1000_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qxm_ecpri_gsi = { .name = "qxm_ecpri_gsi", - .id = QDU1000_MASTER_ECPRI_GSI, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { QDU1000_SLAVE_ANOC_SNOC_GSI, QDU1000_SLAVE_PCIE_0 }, + .link_nodes = { &qns_anoc_snoc_gsi, &xs_pcie }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = QDU1000_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node xm_ecpri_dma = { .name = "xm_ecpri_dma", - .id = QDU1000_MASTER_SNOC_ECPRI_DMA, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { QDU1000_SLAVE_ECPRI_GEMNOC, QDU1000_SLAVE_PCIE_0 }, + .link_nodes = { &qns_ecpri_gemnoc, &xs_pcie }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = QDU1000_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node xm_pcie = { .name = "xm_pcie", - .id = QDU1000_MASTER_PCIE, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { QDU1000_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_gemnoc }, }; static struct qcom_icc_node xm_qdss_etr0 = { .name = "xm_qdss_etr0", - .id = QDU1000_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node xm_qdss_etr1 = { .name = "xm_qdss_etr1", - .id = QDU1000_MASTER_QDSS_ETR_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node xm_sdc = { .name = "xm_sdc", - .id = QDU1000_MASTER_SDCC_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3 = { .name = "xm_usb3", - .id = QDU1000_MASTER_USB3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", - .id = QDU1000_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup1_core_slave = { .name = "qup1_core_slave", - .id = QDU1000_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_gem_noc_cnoc = { .name = "qns_gem_noc_cnoc", - .id = QDU1000_SLAVE_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QDU1000_MASTER_GEM_NOC_CNOC }, + .link_nodes = { &qnm_gemnoc_cnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = QDU1000_SLAVE_LLCC, .channels = 8, .buswidth = 16, .num_links = 1, - .links = { QDU1000_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_modem_slave = { .name = "qns_modem_slave", - .id = QDU1000_SLAVE_GEMNOC_MODEM_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QDU1000_MASTER_GEMNOC_MODEM_CNOC }, + .link_nodes = { &qnm_gemnoc_modem_slave }, }; static struct qcom_icc_node qns_pcie = { .name = "qns_pcie", - .id = QDU1000_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QDU1000_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = QDU1000_SLAVE_EBI1, .channels = 8, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy0_south = { .name = "qhs_ahb2phy0_south", - .id = QDU1000_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy1_north = { .name = "qhs_ahb2phy1_north", - .id = QDU1000_SLAVE_AHB2PHY_NORTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy2_east = { .name = "qhs_ahb2phy2_east", - .id = QDU1000_SLAVE_AHB2PHY_EAST, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = QDU1000_SLAVE_AOSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = QDU1000_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = QDU1000_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mx = { .name = "qhs_cpr_mx", - .id = QDU1000_SLAVE_RBCPR_MX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_crypto_cfg = { .name = "qhs_crypto_cfg", - .id = QDU1000_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ecpri_cfg = { .name = "qhs_ecpri_cfg", - .id = QDU1000_SLAVE_ECPRI_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = QDU1000_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", - .id = QDU1000_SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", - .id = QDU1000_SLAVE_CNOC_MSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie_cfg = { .name = "qhs_pcie_cfg", - .id = QDU1000_SLAVE_PCIE_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = QDU1000_SLAVE_PDM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = QDU1000_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = QDU1000_SLAVE_PRNG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = QDU1000_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qpic = { .name = "qhs_qpic", - .id = QDU1000_SLAVE_QPIC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = QDU1000_SLAVE_QSPI_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", - .id = QDU1000_SLAVE_QUP_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = QDU1000_SLAVE_QUP_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = QDU1000_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_smbus_cfg = { .name = "qhs_smbus_cfg", - .id = QDU1000_SLAVE_SMBUS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_system_noc_cfg = { .name = "qhs_system_noc_cfg", - .id = QDU1000_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { QDU1000_MASTER_SNOC_CFG }, + .link_nodes = { &qhm_system_noc_cfg }, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = QDU1000_SLAVE_TCSR, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = QDU1000_SLAVE_TLMM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tme_cfg = { .name = "qhs_tme_cfg", - .id = QDU1000_SLAVE_TME_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tsc_cfg = { .name = "qhs_tsc_cfg", - .id = QDU1000_SLAVE_TSC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3 = { .name = "qhs_usb3", - .id = QDU1000_SLAVE_USB3_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = QDU1000_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = QDU1000_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_MASTER_ANOC_SNOC }, + .link_nodes = { &qnm_aggre_noc }, }; static struct qcom_icc_node qns_anoc_snoc_gsi = { .name = "qns_anoc_snoc_gsi", - .id = QDU1000_SLAVE_ANOC_SNOC_GSI, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_MASTER_ANOC_GSI }, + .link_nodes = { &qnm_aggre_noc_gsi }, }; static struct qcom_icc_node qns_ddrss_cfg = { .name = "qns_ddrss_cfg", - .id = QDU1000_SLAVE_DDRSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_ecpri_gemnoc = { .name = "qns_ecpri_gemnoc", - .id = QDU1000_SLAVE_ECPRI_GEMNOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { QDU1000_MASTER_GEMNOC_ECPRI_DMA }, + .link_nodes = { &qnm_ecpri_dma }, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = QDU1000_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { QDU1000_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = QDU1000_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { QDU1000_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node qns_modem = { .name = "qns_modem", - .id = QDU1000_SLAVE_MODEM_OFFLINE, .channels = 1, .buswidth = 32, - .num_links = 0, }; static struct qcom_icc_node qns_pcie_gemnoc = { .name = "qns_pcie_gemnoc", - .id = QDU1000_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { QDU1000_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = QDU1000_SLAVE_IMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = QDU1000_SLAVE_PIMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node srvc_system_noc = { .name = "srvc_system_noc", - .id = QDU1000_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_ethernet_ss = { .name = "xs_ethernet_ss", - .id = QDU1000_SLAVE_ETHERNET_SS, .channels = 1, .buswidth = 32, - .num_links = 0, }; static struct qcom_icc_node xs_pcie = { .name = "xs_pcie", - .id = QDU1000_SLAVE_PCIE_0, .channels = 1, .buswidth = 64, - .num_links = 0, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = QDU1000_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = QDU1000_SLAVE_TCU, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_bcm bcm_acv = { @@ -1046,7 +1000,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qnoc_probe, - .remove_new = qcom_icc_rpmh_remove, + .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-qdu1000", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/qdu1000.h b/drivers/interconnect/qcom/qdu1000.h deleted file mode 100644 index e75a6419df23..000000000000 --- a/drivers/interconnect/qcom/qdu1000.h +++ /dev/null @@ -1,95 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_QDU1000_H -#define __DRIVERS_INTERCONNECT_QCOM_QDU1000_H - -#define QDU1000_MASTER_SYS_TCU 0 -#define QDU1000_MASTER_APPSS_PROC 1 -#define QDU1000_MASTER_LLCC 2 -#define QDU1000_MASTER_GIC_AHB 3 -#define QDU1000_MASTER_QDSS_BAM 4 -#define QDU1000_MASTER_QPIC 5 -#define QDU1000_MASTER_QSPI_0 6 -#define QDU1000_MASTER_QUP_0 7 -#define QDU1000_MASTER_QUP_1 8 -#define QDU1000_MASTER_SNOC_CFG 9 -#define QDU1000_MASTER_ANOC_SNOC 10 -#define QDU1000_MASTER_ANOC_GSI 11 -#define QDU1000_MASTER_GEMNOC_ECPRI_DMA 12 -#define QDU1000_MASTER_FEC_2_GEMNOC 13 -#define QDU1000_MASTER_GEM_NOC_CNOC 14 -#define QDU1000_MASTER_GEMNOC_MODEM_CNOC 15 -#define QDU1000_MASTER_GEM_NOC_PCIE_SNOC 16 -#define QDU1000_MASTER_ANOC_PCIE_GEM_NOC 17 -#define QDU1000_MASTER_SNOC_GC_MEM_NOC 18 -#define QDU1000_MASTER_SNOC_SF_MEM_NOC 19 -#define QDU1000_MASTER_QUP_CORE_0 20 -#define QDU1000_MASTER_QUP_CORE_1 21 -#define QDU1000_MASTER_CRYPTO 22 -#define QDU1000_MASTER_ECPRI_GSI 23 -#define QDU1000_MASTER_MSS_PROC 24 -#define QDU1000_MASTER_PIMEM 25 -#define QDU1000_MASTER_SNOC_ECPRI_DMA 26 -#define QDU1000_MASTER_GIC 27 -#define QDU1000_MASTER_PCIE 28 -#define QDU1000_MASTER_QDSS_ETR 29 -#define QDU1000_MASTER_QDSS_ETR_1 30 -#define QDU1000_MASTER_SDCC_1 31 -#define QDU1000_MASTER_USB3 32 -#define QDU1000_SLAVE_EBI1 512 -#define QDU1000_SLAVE_AHB2PHY_SOUTH 513 -#define QDU1000_SLAVE_AHB2PHY_NORTH 514 -#define QDU1000_SLAVE_AHB2PHY_EAST 515 -#define QDU1000_SLAVE_AOSS 516 -#define QDU1000_SLAVE_CLK_CTL 517 -#define QDU1000_SLAVE_RBCPR_CX_CFG 518 -#define QDU1000_SLAVE_RBCPR_MX_CFG 519 -#define QDU1000_SLAVE_CRYPTO_0_CFG 520 -#define QDU1000_SLAVE_ECPRI_CFG 521 -#define QDU1000_SLAVE_IMEM_CFG 522 -#define QDU1000_SLAVE_IPC_ROUTER_CFG 523 -#define QDU1000_SLAVE_CNOC_MSS 524 -#define QDU1000_SLAVE_PCIE_CFG 525 -#define QDU1000_SLAVE_PDM 526 -#define QDU1000_SLAVE_PIMEM_CFG 527 -#define QDU1000_SLAVE_PRNG 528 -#define QDU1000_SLAVE_QDSS_CFG 529 -#define QDU1000_SLAVE_QPIC 530 -#define QDU1000_SLAVE_QSPI_0 531 -#define QDU1000_SLAVE_QUP_0 532 -#define QDU1000_SLAVE_QUP_1 533 -#define QDU1000_SLAVE_SDCC_2 534 -#define QDU1000_SLAVE_SMBUS_CFG 535 -#define QDU1000_SLAVE_SNOC_CFG 536 -#define QDU1000_SLAVE_TCSR 537 -#define QDU1000_SLAVE_TLMM 538 -#define QDU1000_SLAVE_TME_CFG 539 -#define QDU1000_SLAVE_TSC_CFG 540 -#define QDU1000_SLAVE_USB3_0 541 -#define QDU1000_SLAVE_VSENSE_CTRL_CFG 542 -#define QDU1000_SLAVE_A1NOC_SNOC 543 -#define QDU1000_SLAVE_ANOC_SNOC_GSI 544 -#define QDU1000_SLAVE_DDRSS_CFG 545 -#define QDU1000_SLAVE_ECPRI_GEMNOC 546 -#define QDU1000_SLAVE_GEM_NOC_CNOC 547 -#define QDU1000_SLAVE_SNOC_GEM_NOC_GC 548 -#define QDU1000_SLAVE_SNOC_GEM_NOC_SF 549 -#define QDU1000_SLAVE_LLCC 550 -#define QDU1000_SLAVE_MODEM_OFFLINE 551 -#define QDU1000_SLAVE_GEMNOC_MODEM_CNOC 552 -#define QDU1000_SLAVE_MEM_NOC_PCIE_SNOC 553 -#define QDU1000_SLAVE_ANOC_PCIE_GEM_NOC 554 -#define QDU1000_SLAVE_QUP_CORE_0 555 -#define QDU1000_SLAVE_QUP_CORE_1 556 -#define QDU1000_SLAVE_IMEM 557 -#define QDU1000_SLAVE_PIMEM 558 -#define QDU1000_SLAVE_SERVICE_SNOC 559 -#define QDU1000_SLAVE_ETHERNET_SS 560 -#define QDU1000_SLAVE_PCIE_0 561 -#define QDU1000_SLAVE_QDSS_STM 562 -#define QDU1000_SLAVE_TCU 563 - -#endif diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qcom/sa8775p.c index a729775c2aa4..6a49abc96efe 100644 --- a/drivers/interconnect/qcom/sa8775p.c +++ b/drivers/interconnect/qcom/sa8775p.c @@ -15,1859 +15,1916 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#define SA8775P_MASTER_GPU_TCU 0 -#define SA8775P_MASTER_PCIE_TCU 1 -#define SA8775P_MASTER_SYS_TCU 2 -#define SA8775P_MASTER_APPSS_PROC 3 -#define SA8775P_MASTER_LLCC 4 -#define SA8775P_MASTER_CNOC_LPASS_AG_NOC 5 -#define SA8775P_MASTER_GIC_AHB 6 -#define SA8775P_MASTER_CDSP_NOC_CFG 7 -#define SA8775P_MASTER_CDSPB_NOC_CFG 8 -#define SA8775P_MASTER_QDSS_BAM 9 -#define SA8775P_MASTER_QUP_0 10 -#define SA8775P_MASTER_QUP_1 11 -#define SA8775P_MASTER_QUP_2 12 -#define SA8775P_MASTER_A1NOC_SNOC 13 -#define SA8775P_MASTER_A2NOC_SNOC 14 -#define SA8775P_MASTER_CAMNOC_HF 15 -#define SA8775P_MASTER_CAMNOC_ICP 16 -#define SA8775P_MASTER_CAMNOC_SF 17 -#define SA8775P_MASTER_COMPUTE_NOC 18 -#define SA8775P_MASTER_COMPUTE_NOC_1 19 -#define SA8775P_MASTER_CNOC_A2NOC 20 -#define SA8775P_MASTER_CNOC_DC_NOC 21 -#define SA8775P_MASTER_GEM_NOC_CFG 22 -#define SA8775P_MASTER_GEM_NOC_CNOC 23 -#define SA8775P_MASTER_GEM_NOC_PCIE_SNOC 24 -#define SA8775P_MASTER_GPDSP_SAIL 25 -#define SA8775P_MASTER_GFX3D 26 -#define SA8775P_MASTER_LPASS_ANOC 27 -#define SA8775P_MASTER_MDP0 28 -#define SA8775P_MASTER_MDP1 29 -#define SA8775P_MASTER_MDP_CORE1_0 30 -#define SA8775P_MASTER_MDP_CORE1_1 31 -#define SA8775P_MASTER_MNOC_HF_MEM_NOC 32 -#define SA8775P_MASTER_CNOC_MNOC_HF_CFG 33 -#define SA8775P_MASTER_MNOC_SF_MEM_NOC 34 -#define SA8775P_MASTER_CNOC_MNOC_SF_CFG 35 -#define SA8775P_MASTER_ANOC_PCIE_GEM_NOC 36 -#define SA8775P_MASTER_SNOC_CFG 37 -#define SA8775P_MASTER_SNOC_GC_MEM_NOC 38 -#define SA8775P_MASTER_SNOC_SF_MEM_NOC 39 -#define SA8775P_MASTER_VIDEO_P0 40 -#define SA8775P_MASTER_VIDEO_P1 41 -#define SA8775P_MASTER_VIDEO_PROC 42 -#define SA8775P_MASTER_VIDEO_V_PROC 43 -#define SA8775P_MASTER_QUP_CORE_0 44 -#define SA8775P_MASTER_QUP_CORE_1 45 -#define SA8775P_MASTER_QUP_CORE_2 46 -#define SA8775P_MASTER_QUP_CORE_3 47 -#define SA8775P_MASTER_CRYPTO_CORE0 48 -#define SA8775P_MASTER_CRYPTO_CORE1 49 -#define SA8775P_MASTER_DSP0 50 -#define SA8775P_MASTER_DSP1 51 -#define SA8775P_MASTER_IPA 52 -#define SA8775P_MASTER_LPASS_PROC 53 -#define SA8775P_MASTER_CDSP_PROC 54 -#define SA8775P_MASTER_CDSP_PROC_B 55 -#define SA8775P_MASTER_PIMEM 56 -#define SA8775P_MASTER_QUP_3 57 -#define SA8775P_MASTER_EMAC 58 -#define SA8775P_MASTER_EMAC_1 59 -#define SA8775P_MASTER_GIC 60 -#define SA8775P_MASTER_PCIE_0 61 -#define SA8775P_MASTER_PCIE_1 62 -#define SA8775P_MASTER_QDSS_ETR_0 63 -#define SA8775P_MASTER_QDSS_ETR_1 64 -#define SA8775P_MASTER_SDC 65 -#define SA8775P_MASTER_UFS_CARD 66 -#define SA8775P_MASTER_UFS_MEM 67 -#define SA8775P_MASTER_USB2 68 -#define SA8775P_MASTER_USB3_0 69 -#define SA8775P_MASTER_USB3_1 70 -#define SA8775P_SLAVE_EBI1 512 -#define SA8775P_SLAVE_AHB2PHY_0 513 -#define SA8775P_SLAVE_AHB2PHY_1 514 -#define SA8775P_SLAVE_AHB2PHY_2 515 -#define SA8775P_SLAVE_AHB2PHY_3 516 -#define SA8775P_SLAVE_ANOC_THROTTLE_CFG 517 -#define SA8775P_SLAVE_AOSS 518 -#define SA8775P_SLAVE_APPSS 519 -#define SA8775P_SLAVE_BOOT_ROM 520 -#define SA8775P_SLAVE_CAMERA_CFG 521 -#define SA8775P_SLAVE_CAMERA_NRT_THROTTLE_CFG 522 -#define SA8775P_SLAVE_CAMERA_RT_THROTTLE_CFG 523 -#define SA8775P_SLAVE_CLK_CTL 524 -#define SA8775P_SLAVE_CDSP_CFG 525 -#define SA8775P_SLAVE_CDSP1_CFG 526 -#define SA8775P_SLAVE_RBCPR_CX_CFG 527 -#define SA8775P_SLAVE_RBCPR_MMCX_CFG 528 -#define SA8775P_SLAVE_RBCPR_MX_CFG 529 -#define SA8775P_SLAVE_CPR_NSPCX 530 -#define SA8775P_SLAVE_CRYPTO_0_CFG 531 -#define SA8775P_SLAVE_CX_RDPM 532 -#define SA8775P_SLAVE_DISPLAY_CFG 533 -#define SA8775P_SLAVE_DISPLAY_RT_THROTTLE_CFG 534 -#define SA8775P_SLAVE_DISPLAY1_CFG 535 -#define SA8775P_SLAVE_DISPLAY1_RT_THROTTLE_CFG 536 -#define SA8775P_SLAVE_EMAC_CFG 537 -#define SA8775P_SLAVE_EMAC1_CFG 538 -#define SA8775P_SLAVE_GP_DSP0_CFG 539 -#define SA8775P_SLAVE_GP_DSP1_CFG 540 -#define SA8775P_SLAVE_GPDSP0_THROTTLE_CFG 541 -#define SA8775P_SLAVE_GPDSP1_THROTTLE_CFG 542 -#define SA8775P_SLAVE_GPU_TCU_THROTTLE_CFG 543 -#define SA8775P_SLAVE_GFX3D_CFG 544 -#define SA8775P_SLAVE_HWKM 545 -#define SA8775P_SLAVE_IMEM_CFG 546 -#define SA8775P_SLAVE_IPA_CFG 547 -#define SA8775P_SLAVE_IPC_ROUTER_CFG 548 -#define SA8775P_SLAVE_LLCC_CFG 549 -#define SA8775P_SLAVE_LPASS 550 -#define SA8775P_SLAVE_LPASS_CORE_CFG 551 -#define SA8775P_SLAVE_LPASS_LPI_CFG 552 -#define SA8775P_SLAVE_LPASS_MPU_CFG 553 -#define SA8775P_SLAVE_LPASS_THROTTLE_CFG 554 -#define SA8775P_SLAVE_LPASS_TOP_CFG 555 -#define SA8775P_SLAVE_MX_RDPM 556 -#define SA8775P_SLAVE_MXC_RDPM 557 -#define SA8775P_SLAVE_PCIE_0_CFG 558 -#define SA8775P_SLAVE_PCIE_1_CFG 559 -#define SA8775P_SLAVE_PCIE_RSC_CFG 560 -#define SA8775P_SLAVE_PCIE_TCU_THROTTLE_CFG 561 -#define SA8775P_SLAVE_PCIE_THROTTLE_CFG 562 -#define SA8775P_SLAVE_PDM 563 -#define SA8775P_SLAVE_PIMEM_CFG 564 -#define SA8775P_SLAVE_PKA_WRAPPER_CFG 565 -#define SA8775P_SLAVE_QDSS_CFG 566 -#define SA8775P_SLAVE_QM_CFG 567 -#define SA8775P_SLAVE_QM_MPU_CFG 568 -#define SA8775P_SLAVE_QUP_0 569 -#define SA8775P_SLAVE_QUP_1 570 -#define SA8775P_SLAVE_QUP_2 571 -#define SA8775P_SLAVE_QUP_3 572 -#define SA8775P_SLAVE_SAIL_THROTTLE_CFG 573 -#define SA8775P_SLAVE_SDC1 574 -#define SA8775P_SLAVE_SECURITY 575 -#define SA8775P_SLAVE_SNOC_THROTTLE_CFG 576 -#define SA8775P_SLAVE_TCSR 577 -#define SA8775P_SLAVE_TLMM 578 -#define SA8775P_SLAVE_TSC_CFG 579 -#define SA8775P_SLAVE_UFS_CARD_CFG 580 -#define SA8775P_SLAVE_UFS_MEM_CFG 581 -#define SA8775P_SLAVE_USB2 582 -#define SA8775P_SLAVE_USB3_0 583 -#define SA8775P_SLAVE_USB3_1 584 -#define SA8775P_SLAVE_VENUS_CFG 585 -#define SA8775P_SLAVE_VENUS_CVP_THROTTLE_CFG 586 -#define SA8775P_SLAVE_VENUS_V_CPU_THROTTLE_CFG 587 -#define SA8775P_SLAVE_VENUS_VCODEC_THROTTLE_CFG 588 -#define SA8775P_SLAVE_A1NOC_SNOC 589 -#define SA8775P_SLAVE_A2NOC_SNOC 590 -#define SA8775P_SLAVE_DDRSS_CFG 591 -#define SA8775P_SLAVE_GEM_NOC_CNOC 592 -#define SA8775P_SLAVE_GEM_NOC_CFG 593 -#define SA8775P_SLAVE_SNOC_GEM_NOC_GC 594 -#define SA8775P_SLAVE_SNOC_GEM_NOC_SF 595 -#define SA8775P_SLAVE_GP_DSP_SAIL_NOC 596 -#define SA8775P_SLAVE_GPDSP_NOC_CFG 597 -#define SA8775P_SLAVE_HCP_A 598 -#define SA8775P_SLAVE_LLCC 599 -#define SA8775P_SLAVE_MNOC_HF_MEM_NOC 600 -#define SA8775P_SLAVE_MNOC_SF_MEM_NOC 601 -#define SA8775P_SLAVE_CNOC_MNOC_HF_CFG 602 -#define SA8775P_SLAVE_CNOC_MNOC_SF_CFG 603 -#define SA8775P_SLAVE_CDSP_MEM_NOC 604 -#define SA8775P_SLAVE_CDSPB_MEM_NOC 605 -#define SA8775P_SLAVE_HCP_B 606 -#define SA8775P_SLAVE_GEM_NOC_PCIE_CNOC 607 -#define SA8775P_SLAVE_PCIE_ANOC_CFG 608 -#define SA8775P_SLAVE_ANOC_PCIE_GEM_NOC 609 -#define SA8775P_SLAVE_SNOC_CFG 610 -#define SA8775P_SLAVE_LPASS_SNOC 611 -#define SA8775P_SLAVE_QUP_CORE_0 612 -#define SA8775P_SLAVE_QUP_CORE_1 613 -#define SA8775P_SLAVE_QUP_CORE_2 614 -#define SA8775P_SLAVE_QUP_CORE_3 615 -#define SA8775P_SLAVE_BOOT_IMEM 616 -#define SA8775P_SLAVE_IMEM 617 -#define SA8775P_SLAVE_PIMEM 618 -#define SA8775P_SLAVE_SERVICE_NSP_NOC 619 -#define SA8775P_SLAVE_SERVICE_NSPB_NOC 620 -#define SA8775P_SLAVE_SERVICE_GEM_NOC_1 621 -#define SA8775P_SLAVE_SERVICE_MNOC_HF 622 -#define SA8775P_SLAVE_SERVICE_MNOC_SF 623 -#define SA8775P_SLAVE_SERVICES_LPASS_AML_NOC 624 -#define SA8775P_SLAVE_SERVICE_LPASS_AG_NOC 625 -#define SA8775P_SLAVE_SERVICE_GEM_NOC_2 626 -#define SA8775P_SLAVE_SERVICE_SNOC 627 -#define SA8775P_SLAVE_SERVICE_GEM_NOC 628 -#define SA8775P_SLAVE_SERVICE_GEM_NOC2 629 -#define SA8775P_SLAVE_PCIE_0 630 -#define SA8775P_SLAVE_PCIE_1 631 -#define SA8775P_SLAVE_QDSS_STM 632 -#define SA8775P_SLAVE_TCU 633 +static struct qcom_icc_node qxm_qup3; +static struct qcom_icc_node xm_emac_0; +static struct qcom_icc_node xm_emac_1; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb2_2; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node xm_usb3_1; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qnm_cnoc_datapath; +static struct qcom_icc_node qxm_crypto_0; +static struct qcom_icc_node qxm_crypto_1; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node xm_ufs_card; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup2_core_master; +static struct qcom_icc_node qup3_core_master; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup2_core_slave; +static struct qcom_icc_node qup3_core_slave; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_ahb2phy2; +static struct qcom_icc_node qhs_ahb2phy3; +static struct qcom_icc_node qhs_anoc_throttle_cfg; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qhs_boot_rom; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_camera_nrt_throttle_cfg; +static struct qcom_icc_node qhs_camera_rt_throttle_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute0_cfg; +static struct qcom_icc_node qhs_compute1_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_cpr_nspcx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_display0_cfg; +static struct qcom_icc_node qhs_display0_rt_throttle_cfg; +static struct qcom_icc_node qhs_display1_cfg; +static struct qcom_icc_node qhs_display1_rt_throttle_cfg; +static struct qcom_icc_node qhs_emac0_cfg; +static struct qcom_icc_node qhs_emac1_cfg; +static struct qcom_icc_node qhs_gp_dsp0_cfg; +static struct qcom_icc_node qhs_gp_dsp1_cfg; +static struct qcom_icc_node qhs_gpdsp0_throttle_cfg; +static struct qcom_icc_node qhs_gpdsp1_throttle_cfg; +static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_hwkm; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_lpass_cfg; +static struct qcom_icc_node qhs_lpass_throttle_cfg; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_mxc_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pcie_rsc_cfg; +static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg; +static struct qcom_icc_node qhs_pcie_throttle_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_pke_wrapper_cfg; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qm_cfg; +static struct qcom_icc_node qhs_qm_mpu_cfg; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_qup3; +static struct qcom_icc_node qhs_sail_throttle_cfg; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_security; +static struct qcom_icc_node qhs_snoc_throttle_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_tsc_cfg; +static struct qcom_icc_node qhs_ufs_card_cfg; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb2_0; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_usb3_1; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_venus_cvp_throttle_cfg; +static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg; +static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qns_gpdsp_noc_cfg; +static struct qcom_icc_node qns_mnoc_hf_cfg; +static struct qcom_icc_node qns_mnoc_sf_cfg; +static struct qcom_icc_node qns_pcie_anoc_cfg; +static struct qcom_icc_node qns_snoc_cfg; +static struct qcom_icc_node qxs_boot_imem; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qnm_cnoc_dc_noc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qns_gemnoc; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_pcie_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_cmpnoc0; +static struct qcom_icc_node qnm_cmpnoc1; +static struct qcom_icc_node qnm_gemnoc_cfg; +static struct qcom_icc_node qnm_gpdsp_sail; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node srvc_even_gemnoc; +static struct qcom_icc_node srvc_odd_gemnoc; +static struct qcom_icc_node srvc_sys_gemnoc; +static struct qcom_icc_node srvc_sys_gemnoc_2; +static struct qcom_icc_node qxm_dsp0; +static struct qcom_icc_node qxm_dsp1; +static struct qcom_icc_node qns_gp_dsp_sail_noc; +static struct qcom_icc_node qhm_config_noc; +static struct qcom_icc_node qxm_lpass_dsp; +static struct qcom_icc_node qhs_lpass_core; +static struct qcom_icc_node qhs_lpass_lpi; +static struct qcom_icc_node qhs_lpass_mpu; +static struct qcom_icc_node qhs_lpass_top; +static struct qcom_icc_node qns_sysnoc; +static struct qcom_icc_node srvc_niu_aml_noc; +static struct qcom_icc_node srvc_niu_lpass_agnoc; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_mdp0_0; +static struct qcom_icc_node qnm_mdp0_1; +static struct qcom_icc_node qnm_mdp1_0; +static struct qcom_icc_node qnm_mdp1_1; +static struct qcom_icc_node qnm_mnoc_hf_cfg; +static struct qcom_icc_node qnm_mnoc_sf_cfg; +static struct qcom_icc_node qnm_video0; +static struct qcom_icc_node qnm_video1; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qnm_video_v_cpu; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc_hf; +static struct qcom_icc_node srvc_mnoc_sf; +static struct qcom_icc_node qhm_nsp_noc_config; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node qns_hcp; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node service_nsp_noc; +static struct qcom_icc_node qhm_nspb_noc_config; +static struct qcom_icc_node qxm_nspb; +static struct qcom_icc_node qns_nspb_gemnoc; +static struct qcom_icc_node qns_nspb_hcp; +static struct qcom_icc_node service_nspb_noc; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node qhm_gic; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_lpass_noc; +static struct qcom_icc_node qnm_snoc_cfg; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node srvc_snoc; static struct qcom_icc_node qxm_qup3 = { .name = "qxm_qup3", - .id = SA8775P_MASTER_QUP_3, .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x11000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, - .links = { SA8775P_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_emac_0 = { .name = "xm_emac_0", - .id = SA8775P_MASTER_EMAC, .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x12000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, - .links = { SA8775P_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_emac_1 = { .name = "xm_emac_1", - .id = SA8775P_MASTER_EMAC_1, .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x13000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, - .links = { SA8775P_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc1 = { .name = "xm_sdc1", - .id = SA8775P_MASTER_SDC, .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x14000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, - .links = { SA8775P_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SA8775P_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x15000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, - .links = { SA8775P_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb2_2 = { .name = "xm_usb2_2", - .id = SA8775P_MASTER_USB2, .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x16000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, - .links = { SA8775P_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SA8775P_MASTER_USB3_0, .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x17000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, - .links = { SA8775P_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_1 = { .name = "xm_usb3_1", - .id = SA8775P_MASTER_USB3_1, .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x18000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, - .links = { SA8775P_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SA8775P_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x14000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, - .links = { SA8775P_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", - .id = SA8775P_MASTER_QUP_0, .channels = 1, .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x17000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, - .links = { SA8775P_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = SA8775P_MASTER_QUP_1, .channels = 1, .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x12000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, - .links = { SA8775P_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", - .id = SA8775P_MASTER_QUP_2, .channels = 1, .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x15000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, - .links = { SA8775P_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_cnoc_datapath = { .name = "qnm_cnoc_datapath", - .id = SA8775P_MASTER_CNOC_A2NOC, .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x16000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, - .links = { SA8775P_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto_0 = { .name = "qxm_crypto_0", - .id = SA8775P_MASTER_CRYPTO_CORE0, .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x18000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, - .links = { SA8775P_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto_1 = { .name = "qxm_crypto_1", - .id = SA8775P_MASTER_CRYPTO_CORE1, .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x1a000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, - .links = { SA8775P_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SA8775P_MASTER_IPA, .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x11000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, - .links = { SA8775P_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr_0 = { .name = "xm_qdss_etr_0", - .id = SA8775P_MASTER_QDSS_ETR_0, .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x13000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, - .links = { SA8775P_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr_1 = { .name = "xm_qdss_etr_1", - .id = SA8775P_MASTER_QDSS_ETR_1, .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x19000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, - .links = { SA8775P_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_ufs_card = { .name = "xm_ufs_card", - .id = SA8775P_MASTER_UFS_CARD, .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x1b000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, - .links = { SA8775P_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", - .id = SA8775P_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SA8775P_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { .name = "qup1_core_master", - .id = SA8775P_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SA8775P_SLAVE_QUP_CORE_1 }, + .link_nodes = { &qup1_core_slave }, }; static struct qcom_icc_node qup2_core_master = { .name = "qup2_core_master", - .id = SA8775P_MASTER_QUP_CORE_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SA8775P_SLAVE_QUP_CORE_2 }, + .link_nodes = { &qup2_core_slave }, }; static struct qcom_icc_node qup3_core_master = { .name = "qup3_core_master", - .id = SA8775P_MASTER_QUP_CORE_3, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SA8775P_SLAVE_QUP_CORE_3 }, + .link_nodes = { &qup3_core_slave }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", - .id = SA8775P_MASTER_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 82, - .links = { SA8775P_SLAVE_AHB2PHY_0, - SA8775P_SLAVE_AHB2PHY_1, - SA8775P_SLAVE_AHB2PHY_2, - SA8775P_SLAVE_AHB2PHY_3, - SA8775P_SLAVE_ANOC_THROTTLE_CFG, - SA8775P_SLAVE_AOSS, - SA8775P_SLAVE_APPSS, - SA8775P_SLAVE_BOOT_ROM, - SA8775P_SLAVE_CAMERA_CFG, - SA8775P_SLAVE_CAMERA_NRT_THROTTLE_CFG, - SA8775P_SLAVE_CAMERA_RT_THROTTLE_CFG, - SA8775P_SLAVE_CLK_CTL, - SA8775P_SLAVE_CDSP_CFG, - SA8775P_SLAVE_CDSP1_CFG, - SA8775P_SLAVE_RBCPR_CX_CFG, - SA8775P_SLAVE_RBCPR_MMCX_CFG, - SA8775P_SLAVE_RBCPR_MX_CFG, - SA8775P_SLAVE_CPR_NSPCX, - SA8775P_SLAVE_CRYPTO_0_CFG, - SA8775P_SLAVE_CX_RDPM, - SA8775P_SLAVE_DISPLAY_CFG, - SA8775P_SLAVE_DISPLAY_RT_THROTTLE_CFG, - SA8775P_SLAVE_DISPLAY1_CFG, - SA8775P_SLAVE_DISPLAY1_RT_THROTTLE_CFG, - SA8775P_SLAVE_EMAC_CFG, - SA8775P_SLAVE_EMAC1_CFG, - SA8775P_SLAVE_GP_DSP0_CFG, - SA8775P_SLAVE_GP_DSP1_CFG, - SA8775P_SLAVE_GPDSP0_THROTTLE_CFG, - SA8775P_SLAVE_GPDSP1_THROTTLE_CFG, - SA8775P_SLAVE_GPU_TCU_THROTTLE_CFG, - SA8775P_SLAVE_GFX3D_CFG, - SA8775P_SLAVE_HWKM, - SA8775P_SLAVE_IMEM_CFG, - SA8775P_SLAVE_IPA_CFG, - SA8775P_SLAVE_IPC_ROUTER_CFG, - SA8775P_SLAVE_LPASS, - SA8775P_SLAVE_LPASS_THROTTLE_CFG, - SA8775P_SLAVE_MX_RDPM, - SA8775P_SLAVE_MXC_RDPM, - SA8775P_SLAVE_PCIE_0_CFG, - SA8775P_SLAVE_PCIE_1_CFG, - SA8775P_SLAVE_PCIE_RSC_CFG, - SA8775P_SLAVE_PCIE_TCU_THROTTLE_CFG, - SA8775P_SLAVE_PCIE_THROTTLE_CFG, - SA8775P_SLAVE_PDM, - SA8775P_SLAVE_PIMEM_CFG, - SA8775P_SLAVE_PKA_WRAPPER_CFG, - SA8775P_SLAVE_QDSS_CFG, - SA8775P_SLAVE_QM_CFG, - SA8775P_SLAVE_QM_MPU_CFG, - SA8775P_SLAVE_QUP_0, - SA8775P_SLAVE_QUP_1, - SA8775P_SLAVE_QUP_2, - SA8775P_SLAVE_QUP_3, - SA8775P_SLAVE_SAIL_THROTTLE_CFG, - SA8775P_SLAVE_SDC1, - SA8775P_SLAVE_SECURITY, - SA8775P_SLAVE_SNOC_THROTTLE_CFG, - SA8775P_SLAVE_TCSR, - SA8775P_SLAVE_TLMM, - SA8775P_SLAVE_TSC_CFG, - SA8775P_SLAVE_UFS_CARD_CFG, - SA8775P_SLAVE_UFS_MEM_CFG, - SA8775P_SLAVE_USB2, - SA8775P_SLAVE_USB3_0, - SA8775P_SLAVE_USB3_1, - SA8775P_SLAVE_VENUS_CFG, - SA8775P_SLAVE_VENUS_CVP_THROTTLE_CFG, - SA8775P_SLAVE_VENUS_V_CPU_THROTTLE_CFG, - SA8775P_SLAVE_VENUS_VCODEC_THROTTLE_CFG, - SA8775P_SLAVE_DDRSS_CFG, - SA8775P_SLAVE_GPDSP_NOC_CFG, - SA8775P_SLAVE_CNOC_MNOC_HF_CFG, - SA8775P_SLAVE_CNOC_MNOC_SF_CFG, - SA8775P_SLAVE_PCIE_ANOC_CFG, - SA8775P_SLAVE_SNOC_CFG, - SA8775P_SLAVE_BOOT_IMEM, - SA8775P_SLAVE_IMEM, - SA8775P_SLAVE_PIMEM, - SA8775P_SLAVE_QDSS_STM, - SA8775P_SLAVE_TCU - }, + .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_ahb2phy2, &qhs_ahb2phy3, + &qhs_anoc_throttle_cfg, &qhs_aoss, + &qhs_apss, &qhs_boot_rom, + &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, + &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, + &qhs_compute0_cfg, &qhs_compute1_cfg, + &qhs_cpr_cx, &qhs_cpr_mmcx, + &qhs_cpr_mx, &qhs_cpr_nspcx, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg, + &qhs_display1_cfg, &qhs_display1_rt_throttle_cfg, + &qhs_emac0_cfg, &qhs_emac1_cfg, + &qhs_gp_dsp0_cfg, &qhs_gp_dsp1_cfg, + &qhs_gpdsp0_throttle_cfg, &qhs_gpdsp1_throttle_cfg, + &qhs_gpu_tcu_throttle_cfg, &qhs_gpuss_cfg, + &qhs_hwkm, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_lpass_cfg, &qhs_lpass_throttle_cfg, + &qhs_mx_rdpm, &qhs_mxc_rdpm, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pcie_rsc_cfg, &qhs_pcie_tcu_throttle_cfg, + &qhs_pcie_throttle_cfg, &qhs_pdm, + &qhs_pimem_cfg, &qhs_pke_wrapper_cfg, + &qhs_qdss_cfg, &qhs_qm_cfg, + &qhs_qm_mpu_cfg, &qhs_qup0, + &qhs_qup1, &qhs_qup2, + &qhs_qup3, &qhs_sail_throttle_cfg, + &qhs_sdc1, &qhs_security, + &qhs_snoc_throttle_cfg, &qhs_tcsr, + &qhs_tlmm, &qhs_tsc_cfg, + &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, + &qhs_usb2_0, &qhs_usb3_0, + &qhs_usb3_1, &qhs_venus_cfg, + &qhs_venus_cvp_throttle_cfg, &qhs_venus_v_cpu_throttle_cfg, + &qhs_venus_vcodec_throttle_cfg, &qns_ddrss_cfg, + &qns_gpdsp_noc_cfg, &qns_mnoc_hf_cfg, + &qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg, + &qns_snoc_cfg, &qxs_boot_imem, + &qxs_imem, &qxs_pimem, + &xs_qdss_stm, &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = SA8775P_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SA8775P_SLAVE_PCIE_0, - SA8775P_SLAVE_PCIE_1 - }, + .link_nodes = { &xs_pcie_0, &xs_pcie_1 }, }; static struct qcom_icc_node qnm_cnoc_dc_noc = { .name = "qnm_cnoc_dc_noc", - .id = SA8775P_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SA8775P_SLAVE_LLCC_CFG, - SA8775P_SLAVE_GEM_NOC_CFG - }, + .link_nodes = { &qhs_llcc, &qns_gemnoc }, }; static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", - .id = SA8775P_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, - .num_links = 2, - .links = { SA8775P_SLAVE_GEM_NOC_CNOC, - SA8775P_SLAVE_LLCC + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xb4000 }, + .prio_fwd_disable = 1, + .prio = 1, + .urg_fwd = 0, }, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node alm_pcie_tcu = { .name = "alm_pcie_tcu", - .id = SA8775P_MASTER_PCIE_TCU, .channels = 1, .buswidth = 8, - .num_links = 2, - .links = { SA8775P_SLAVE_GEM_NOC_CNOC, - SA8775P_SLAVE_LLCC + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xb5000 }, + .prio_fwd_disable = 1, + .prio = 3, + .urg_fwd = 0, }, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", - .id = SA8775P_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, - .num_links = 2, - .links = { SA8775P_SLAVE_GEM_NOC_CNOC, - SA8775P_SLAVE_LLCC + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xb6000 }, + .prio_fwd_disable = 1, + .prio = 6, + .urg_fwd = 0, }, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", - .id = SA8775P_MASTER_APPSS_PROC, .channels = 4, .buswidth = 32, .num_links = 3, - .links = { SA8775P_SLAVE_GEM_NOC_CNOC, - SA8775P_SLAVE_LLCC, - SA8775P_SLAVE_GEM_NOC_PCIE_CNOC - }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_cmpnoc0 = { .name = "qnm_cmpnoc0", - .id = SA8775P_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, - .num_links = 2, - .links = { SA8775P_SLAVE_GEM_NOC_CNOC, - SA8775P_SLAVE_LLCC + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0xf3000, 0xf4000 }, + .prio_fwd_disable = 1, + .prio = 0, + .urg_fwd = 0, }, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_cmpnoc1 = { .name = "qnm_cmpnoc1", - .id = SA8775P_MASTER_COMPUTE_NOC_1, .channels = 2, .buswidth = 32, - .num_links = 2, - .links = { SA8775P_SLAVE_GEM_NOC_CNOC, - SA8775P_SLAVE_LLCC + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0xf5000, 0xf6000 }, + .prio_fwd_disable = 1, + .prio = 0, + .urg_fwd = 0, }, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_gemnoc_cfg = { .name = "qnm_gemnoc_cfg", - .id = SA8775P_MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 4, - .links = { SA8775P_SLAVE_SERVICE_GEM_NOC_1, - SA8775P_SLAVE_SERVICE_GEM_NOC_2, - SA8775P_SLAVE_SERVICE_GEM_NOC, - SA8775P_SLAVE_SERVICE_GEM_NOC2 - }, + .link_nodes = { &srvc_even_gemnoc, &srvc_odd_gemnoc, + &srvc_sys_gemnoc, &srvc_sys_gemnoc_2 }, }; static struct qcom_icc_node qnm_gpdsp_sail = { .name = "qnm_gpdsp_sail", - .id = SA8775P_MASTER_GPDSP_SAIL, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SA8775P_SLAVE_GEM_NOC_CNOC, - SA8775P_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", - .id = SA8775P_MASTER_GFX3D, .channels = 2, .buswidth = 32, - .num_links = 2, - .links = { SA8775P_SLAVE_GEM_NOC_CNOC, - SA8775P_SLAVE_LLCC + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0xed000, 0xee000 }, + .prio_fwd_disable = 1, + .prio = 0, + .urg_fwd = 0, }, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SA8775P_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, - .num_links = 2, - .links = { SA8775P_SLAVE_LLCC, - SA8775P_SLAVE_GEM_NOC_PCIE_CNOC + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0xef000, 0xf0000 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, }, + .num_links = 2, + .link_nodes = { &qns_llcc, &qns_pcie }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SA8775P_MASTER_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, - .num_links = 3, - .links = { SA8775P_SLAVE_GEM_NOC_CNOC, - SA8775P_SLAVE_LLCC, - SA8775P_SLAVE_GEM_NOC_PCIE_CNOC + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 2, + .port_offsets = { 0xf1000, 0xf2000 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, }, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = SA8775P_MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 32, - .num_links = 2, - .links = { SA8775P_SLAVE_GEM_NOC_CNOC, - SA8775P_SLAVE_LLCC + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xb8000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, }, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SA8775P_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xb9000 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, - .links = { SA8775P_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SA8775P_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xba000 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 3, - .links = { SA8775P_SLAVE_GEM_NOC_CNOC, - SA8775P_SLAVE_LLCC, - SA8775P_SLAVE_GEM_NOC_PCIE_CNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qxm_dsp0 = { .name = "qxm_dsp0", - .id = SA8775P_MASTER_DSP0, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SA8775P_SLAVE_GP_DSP_SAIL_NOC }, + .link_nodes = { &qns_gp_dsp_sail_noc }, }; static struct qcom_icc_node qxm_dsp1 = { .name = "qxm_dsp1", - .id = SA8775P_MASTER_DSP1, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SA8775P_SLAVE_GP_DSP_SAIL_NOC }, + .link_nodes = { &qns_gp_dsp_sail_noc }, }; static struct qcom_icc_node qhm_config_noc = { .name = "qhm_config_noc", - .id = SA8775P_MASTER_CNOC_LPASS_AG_NOC, .channels = 1, .buswidth = 4, .num_links = 6, - .links = { SA8775P_SLAVE_LPASS_CORE_CFG, - SA8775P_SLAVE_LPASS_LPI_CFG, - SA8775P_SLAVE_LPASS_MPU_CFG, - SA8775P_SLAVE_LPASS_TOP_CFG, - SA8775P_SLAVE_SERVICES_LPASS_AML_NOC, - SA8775P_SLAVE_SERVICE_LPASS_AG_NOC - }, + .link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi, + &qhs_lpass_mpu, &qhs_lpass_top, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; static struct qcom_icc_node qxm_lpass_dsp = { .name = "qxm_lpass_dsp", - .id = SA8775P_MASTER_LPASS_PROC, .channels = 1, .buswidth = 8, .num_links = 4, - .links = { SA8775P_SLAVE_LPASS_TOP_CFG, - SA8775P_SLAVE_LPASS_SNOC, - SA8775P_SLAVE_SERVICES_LPASS_AML_NOC, - SA8775P_SLAVE_SERVICE_LPASS_AG_NOC - }, + .link_nodes = { &qhs_lpass_top, &qns_sysnoc, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SA8775P_MASTER_LLCC, .channels = 8, .buswidth = 4, .num_links = 1, - .links = { SA8775P_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qnm_camnoc_hf = { .name = "qnm_camnoc_hf", - .id = SA8775P_MASTER_CAMNOC_HF, .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xa000 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, - .links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_camnoc_icp = { .name = "qnm_camnoc_icp", - .id = SA8775P_MASTER_CAMNOC_ICP, .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x2a000 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, - .links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_camnoc_sf = { .name = "qnm_camnoc_sf", - .id = SA8775P_MASTER_CAMNOC_SF, .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x2a080 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, - .links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_mdp0_0 = { .name = "qnm_mdp0_0", - .id = SA8775P_MASTER_MDP0, .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xa080 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, - .links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_mdp0_1 = { .name = "qnm_mdp0_1", - .id = SA8775P_MASTER_MDP1, .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xa180 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, - .links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_mdp1_0 = { .name = "qnm_mdp1_0", - .id = SA8775P_MASTER_MDP_CORE1_0, .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xa100 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, - .links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_mdp1_1 = { .name = "qnm_mdp1_1", - .id = SA8775P_MASTER_MDP_CORE1_1, .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xa200 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, - .links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_mnoc_hf_cfg = { .name = "qnm_mnoc_hf_cfg", - .id = SA8775P_MASTER_CNOC_MNOC_HF_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SA8775P_SLAVE_SERVICE_MNOC_HF }, + .link_nodes = { &srvc_mnoc_hf }, }; static struct qcom_icc_node qnm_mnoc_sf_cfg = { .name = "qnm_mnoc_sf_cfg", - .id = SA8775P_MASTER_CNOC_MNOC_SF_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SA8775P_SLAVE_SERVICE_MNOC_SF }, + .link_nodes = { &srvc_mnoc_sf }, }; static struct qcom_icc_node qnm_video0 = { .name = "qnm_video0", - .id = SA8775P_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x2a100 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, - .links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video1 = { .name = "qnm_video1", - .id = SA8775P_MASTER_VIDEO_P1, .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x2a180 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, - .links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_cvp = { .name = "qnm_video_cvp", - .id = SA8775P_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x2a200 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, - .links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_v_cpu = { .name = "qnm_video_v_cpu", - .id = SA8775P_MASTER_VIDEO_V_PROC, .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x2a280 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, - .links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qhm_nsp_noc_config = { .name = "qhm_nsp_noc_config", - .id = SA8775P_MASTER_CDSP_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SA8775P_SLAVE_SERVICE_NSP_NOC }, + .link_nodes = { &service_nsp_noc }, }; static struct qcom_icc_node qxm_nsp = { .name = "qxm_nsp", - .id = SA8775P_MASTER_CDSP_PROC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SA8775P_SLAVE_HCP_A, SLAVE_CDSP_MEM_NOC }, + .link_nodes = { &qns_hcp, &qns_nsp_gemnoc }, }; static struct qcom_icc_node qhm_nspb_noc_config = { .name = "qhm_nspb_noc_config", - .id = SA8775P_MASTER_CDSPB_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SA8775P_SLAVE_SERVICE_NSPB_NOC }, + .link_nodes = { &service_nspb_noc }, }; static struct qcom_icc_node qxm_nspb = { .name = "qxm_nspb", - .id = SA8775P_MASTER_CDSP_PROC_B, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SA8775P_SLAVE_HCP_B, SLAVE_CDSPB_MEM_NOC }, + .link_nodes = { &qns_nspb_hcp, &qns_nspb_gemnoc }, }; static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", - .id = SA8775P_MASTER_PCIE_0, .channels = 1, .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xb000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, - .links = { SA8775P_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", - .id = SA8775P_MASTER_PCIE_1, .channels = 1, .buswidth = 32, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0xc000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, - .links = { SA8775P_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node qhm_gic = { .name = "qhm_gic", - .id = SA8775P_MASTER_GIC_AHB, .channels = 1, .buswidth = 4, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x14000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, - .links = { SA8775P_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SA8775P_MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SA8775P_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SA8775P_MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SA8775P_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_lpass_noc = { .name = "qnm_lpass_noc", - .id = SA8775P_MASTER_LPASS_ANOC, .channels = 1, .buswidth = 16, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x12000 }, + .prio_fwd_disable = 0, + .prio = 0, + .urg_fwd = 1, + }, .num_links = 1, - .links = { SA8775P_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_snoc_cfg = { .name = "qnm_snoc_cfg", - .id = SA8775P_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SA8775P_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = SA8775P_MASTER_PIMEM, .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x13000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, - .links = { SA8775P_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SA8775P_MASTER_GIC, .channels = 1, .buswidth = 8, + .qosbox = &(const struct qcom_icc_qosbox) { + .num_ports = 1, + .port_offsets = { 0x15000 }, + .prio_fwd_disable = 1, + .prio = 2, + .urg_fwd = 0, + }, .num_links = 1, - .links = { SA8775P_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SA8775P_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SA8775P_MASTER_A1NOC_SNOC }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SA8775P_SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SA8775P_MASTER_A2NOC_SNOC }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", - .id = SA8775P_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qup1_core_slave = { .name = "qup1_core_slave", - .id = SA8775P_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qup2_core_slave = { .name = "qup2_core_slave", - .id = SA8775P_SLAVE_QUP_CORE_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qup3_core_slave = { .name = "qup3_core_slave", - .id = SA8775P_SLAVE_QUP_CORE_3, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", - .id = SA8775P_SLAVE_AHB2PHY_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ahb2phy1 = { .name = "qhs_ahb2phy1", - .id = SA8775P_SLAVE_AHB2PHY_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ahb2phy2 = { .name = "qhs_ahb2phy2", - .id = SA8775P_SLAVE_AHB2PHY_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ahb2phy3 = { .name = "qhs_ahb2phy3", - .id = SA8775P_SLAVE_AHB2PHY_3, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_anoc_throttle_cfg = { .name = "qhs_anoc_throttle_cfg", - .id = SA8775P_SLAVE_ANOC_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SA8775P_SLAVE_AOSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SA8775P_SLAVE_APPSS, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_boot_rom = { .name = "qhs_boot_rom", - .id = SA8775P_SLAVE_BOOT_ROM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SA8775P_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = { .name = "qhs_camera_nrt_throttle_cfg", - .id = SA8775P_SLAVE_CAMERA_NRT_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { .name = "qhs_camera_rt_throttle_cfg", - .id = SA8775P_SLAVE_CAMERA_RT_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SA8775P_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_compute0_cfg = { .name = "qhs_compute0_cfg", - .id = SA8775P_SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SA8775P_MASTER_CDSP_NOC_CFG }, + .link_nodes = { &qhm_nsp_noc_config }, }; static struct qcom_icc_node qhs_compute1_cfg = { .name = "qhs_compute1_cfg", - .id = SA8775P_SLAVE_CDSP1_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SA8775P_MASTER_CDSPB_NOC_CFG }, + .link_nodes = { &qhm_nspb_noc_config }, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SA8775P_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_mmcx = { .name = "qhs_cpr_mmcx", - .id = SA8775P_SLAVE_RBCPR_MMCX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_mx = { .name = "qhs_cpr_mx", - .id = SA8775P_SLAVE_RBCPR_MX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_nspcx = { .name = "qhs_cpr_nspcx", - .id = SA8775P_SLAVE_CPR_NSPCX, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SA8775P_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cx_rdpm = { .name = "qhs_cx_rdpm", - .id = SA8775P_SLAVE_CX_RDPM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_display0_cfg = { .name = "qhs_display0_cfg", - .id = SA8775P_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_display0_rt_throttle_cfg = { .name = "qhs_display0_rt_throttle_cfg", - .id = SA8775P_SLAVE_DISPLAY_RT_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_display1_cfg = { .name = "qhs_display1_cfg", - .id = SA8775P_SLAVE_DISPLAY1_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_display1_rt_throttle_cfg = { .name = "qhs_display1_rt_throttle_cfg", - .id = SA8775P_SLAVE_DISPLAY1_RT_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_emac0_cfg = { .name = "qhs_emac0_cfg", - .id = SA8775P_SLAVE_EMAC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_emac1_cfg = { .name = "qhs_emac1_cfg", - .id = SA8775P_SLAVE_EMAC1_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gp_dsp0_cfg = { .name = "qhs_gp_dsp0_cfg", - .id = SA8775P_SLAVE_GP_DSP0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gp_dsp1_cfg = { .name = "qhs_gp_dsp1_cfg", - .id = SA8775P_SLAVE_GP_DSP1_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gpdsp0_throttle_cfg = { .name = "qhs_gpdsp0_throttle_cfg", - .id = SA8775P_SLAVE_GPDSP0_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gpdsp1_throttle_cfg = { .name = "qhs_gpdsp1_throttle_cfg", - .id = SA8775P_SLAVE_GPDSP1_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg = { .name = "qhs_gpu_tcu_throttle_cfg", - .id = SA8775P_SLAVE_GPU_TCU_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SA8775P_SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_hwkm = { .name = "qhs_hwkm", - .id = SA8775P_SLAVE_HWKM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SA8775P_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SA8775P_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", - .id = SA8775P_SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_cfg = { .name = "qhs_lpass_cfg", - .id = SA8775P_SLAVE_LPASS, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SA8775P_MASTER_CNOC_LPASS_AG_NOC }, + .link_nodes = { &qhm_config_noc }, }; static struct qcom_icc_node qhs_lpass_throttle_cfg = { .name = "qhs_lpass_throttle_cfg", - .id = SA8775P_SLAVE_LPASS_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mx_rdpm = { .name = "qhs_mx_rdpm", - .id = SA8775P_SLAVE_MX_RDPM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mxc_rdpm = { .name = "qhs_mxc_rdpm", - .id = SA8775P_SLAVE_MXC_RDPM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = SA8775P_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie1_cfg = { .name = "qhs_pcie1_cfg", - .id = SA8775P_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie_rsc_cfg = { .name = "qhs_pcie_rsc_cfg", - .id = SA8775P_SLAVE_PCIE_RSC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg = { .name = "qhs_pcie_tcu_throttle_cfg", - .id = SA8775P_SLAVE_PCIE_TCU_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie_throttle_cfg = { .name = "qhs_pcie_throttle_cfg", - .id = SA8775P_SLAVE_PCIE_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SA8775P_SLAVE_PDM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SA8775P_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pke_wrapper_cfg = { .name = "qhs_pke_wrapper_cfg", - .id = SA8775P_SLAVE_PKA_WRAPPER_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SA8775P_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qm_cfg = { .name = "qhs_qm_cfg", - .id = SA8775P_SLAVE_QM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qm_mpu_cfg = { .name = "qhs_qm_mpu_cfg", - .id = SA8775P_SLAVE_QM_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", - .id = SA8775P_SLAVE_QUP_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = SA8775P_SLAVE_QUP_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup2 = { .name = "qhs_qup2", - .id = SA8775P_SLAVE_QUP_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup3 = { .name = "qhs_qup3", - .id = SA8775P_SLAVE_QUP_3, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sail_throttle_cfg = { .name = "qhs_sail_throttle_cfg", - .id = SA8775P_SLAVE_SAIL_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc1 = { .name = "qhs_sdc1", - .id = SA8775P_SLAVE_SDC1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_security = { .name = "qhs_security", - .id = SA8775P_SLAVE_SECURITY, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_snoc_throttle_cfg = { .name = "qhs_snoc_throttle_cfg", - .id = SA8775P_SLAVE_SNOC_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SA8775P_SLAVE_TCSR, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = SA8775P_SLAVE_TLMM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tsc_cfg = { .name = "qhs_tsc_cfg", - .id = SA8775P_SLAVE_TSC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_card_cfg = { .name = "qhs_ufs_card_cfg", - .id = SA8775P_SLAVE_UFS_CARD_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SA8775P_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb2_0 = { .name = "qhs_usb2_0", - .id = SA8775P_SLAVE_USB2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SA8775P_SLAVE_USB3_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_1 = { .name = "qhs_usb3_1", - .id = SA8775P_SLAVE_USB3_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SA8775P_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = { .name = "qhs_venus_cvp_throttle_cfg", - .id = SA8775P_SLAVE_VENUS_CVP_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg = { .name = "qhs_venus_v_cpu_throttle_cfg", - .id = SA8775P_SLAVE_VENUS_V_CPU_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg = { .name = "qhs_venus_vcodec_throttle_cfg", - .id = SA8775P_SLAVE_VENUS_VCODEC_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_ddrss_cfg = { .name = "qns_ddrss_cfg", - .id = SA8775P_SLAVE_DDRSS_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SA8775P_MASTER_CNOC_DC_NOC }, + .link_nodes = { &qnm_cnoc_dc_noc }, }; static struct qcom_icc_node qns_gpdsp_noc_cfg = { .name = "qns_gpdsp_noc_cfg", - .id = SA8775P_SLAVE_GPDSP_NOC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_mnoc_hf_cfg = { .name = "qns_mnoc_hf_cfg", - .id = SA8775P_SLAVE_CNOC_MNOC_HF_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SA8775P_MASTER_CNOC_MNOC_HF_CFG }, + .link_nodes = { &qnm_mnoc_hf_cfg }, }; static struct qcom_icc_node qns_mnoc_sf_cfg = { .name = "qns_mnoc_sf_cfg", - .id = SA8775P_SLAVE_CNOC_MNOC_SF_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SA8775P_MASTER_CNOC_MNOC_SF_CFG }, + .link_nodes = { &qnm_mnoc_sf_cfg }, }; static struct qcom_icc_node qns_pcie_anoc_cfg = { .name = "qns_pcie_anoc_cfg", - .id = SA8775P_SLAVE_PCIE_ANOC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_snoc_cfg = { .name = "qns_snoc_cfg", - .id = SA8775P_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SA8775P_MASTER_SNOC_CFG }, + .link_nodes = { &qnm_snoc_cfg }, }; static struct qcom_icc_node qxs_boot_imem = { .name = "qxs_boot_imem", - .id = SA8775P_SLAVE_BOOT_IMEM, .channels = 1, .buswidth = 16, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SA8775P_SLAVE_IMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = SA8775P_SLAVE_PIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_pcie_0 = { .name = "xs_pcie_0", - .id = SA8775P_SLAVE_PCIE_0, .channels = 1, .buswidth = 16, }; static struct qcom_icc_node xs_pcie_1 = { .name = "xs_pcie_1", - .id = SA8775P_SLAVE_PCIE_1, .channels = 1, .buswidth = 32, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SA8775P_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SA8775P_SLAVE_TCU, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_llcc = { .name = "qhs_llcc", - .id = SA8775P_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_gemnoc = { .name = "qns_gemnoc", - .id = SA8775P_SLAVE_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SA8775P_MASTER_GEM_NOC_CFG }, + .link_nodes = { &qnm_gemnoc_cfg }, }; static struct qcom_icc_node qns_gem_noc_cnoc = { .name = "qns_gem_noc_cnoc", - .id = SA8775P_SLAVE_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SA8775P_MASTER_GEM_NOC_CNOC }, + .link_nodes = { &qnm_gemnoc_cnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SA8775P_SLAVE_LLCC, .channels = 6, .buswidth = 16, .num_links = 1, - .links = { SA8775P_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_pcie = { .name = "qns_pcie", - .id = SA8775P_SLAVE_GEM_NOC_PCIE_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SA8775P_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node srvc_even_gemnoc = { .name = "srvc_even_gemnoc", - .id = SA8775P_SLAVE_SERVICE_GEM_NOC_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_odd_gemnoc = { .name = "srvc_odd_gemnoc", - .id = SA8775P_SLAVE_SERVICE_GEM_NOC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_sys_gemnoc = { .name = "srvc_sys_gemnoc", - .id = SA8775P_SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_sys_gemnoc_2 = { .name = "srvc_sys_gemnoc_2", - .id = SA8775P_SLAVE_SERVICE_GEM_NOC2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_gp_dsp_sail_noc = { .name = "qns_gp_dsp_sail_noc", - .id = SA8775P_SLAVE_GP_DSP_SAIL_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SA8775P_MASTER_GPDSP_SAIL }, + .link_nodes = { &qnm_gpdsp_sail }, }; static struct qcom_icc_node qhs_lpass_core = { .name = "qhs_lpass_core", - .id = SA8775P_SLAVE_LPASS_CORE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_lpi = { .name = "qhs_lpass_lpi", - .id = SA8775P_SLAVE_LPASS_LPI_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_mpu = { .name = "qhs_lpass_mpu", - .id = SA8775P_SLAVE_LPASS_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_top = { .name = "qhs_lpass_top", - .id = SA8775P_SLAVE_LPASS_TOP_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_sysnoc = { .name = "qns_sysnoc", - .id = SA8775P_SLAVE_LPASS_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SA8775P_MASTER_LPASS_ANOC }, + .link_nodes = { &qnm_lpass_noc }, }; static struct qcom_icc_node srvc_niu_aml_noc = { .name = "srvc_niu_aml_noc", - .id = SA8775P_SLAVE_SERVICES_LPASS_AML_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_niu_lpass_agnoc = { .name = "srvc_niu_lpass_agnoc", - .id = SA8775P_SLAVE_SERVICE_LPASS_AG_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SA8775P_SLAVE_EBI1, .channels = 8, .buswidth = 4, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SA8775P_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SA8775P_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", - .id = SA8775P_SLAVE_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SA8775P_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc_hf = { .name = "srvc_mnoc_hf", - .id = SA8775P_SLAVE_SERVICE_MNOC_HF, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_mnoc_sf = { .name = "srvc_mnoc_sf", - .id = SA8775P_SLAVE_SERVICE_MNOC_SF, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_hcp = { .name = "qns_hcp", - .id = SA8775P_SLAVE_HCP_A, .channels = 2, .buswidth = 32, }; static struct qcom_icc_node qns_nsp_gemnoc = { .name = "qns_nsp_gemnoc", - .id = SA8775P_SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SA8775P_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_cmpnoc0 }, }; static struct qcom_icc_node service_nsp_noc = { .name = "service_nsp_noc", - .id = SA8775P_SLAVE_SERVICE_NSP_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_nspb_gemnoc = { .name = "qns_nspb_gemnoc", - .id = SA8775P_SLAVE_CDSPB_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SA8775P_MASTER_COMPUTE_NOC_1 }, + .link_nodes = { &qnm_cmpnoc1 }, }; static struct qcom_icc_node qns_nspb_hcp = { .name = "qns_nspb_hcp", - .id = SA8775P_SLAVE_HCP_B, .channels = 2, .buswidth = 32, }; static struct qcom_icc_node service_nspb_noc = { .name = "service_nspb_noc", - .id = SA8775P_SLAVE_SERVICE_NSPB_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_pcie_mem_noc = { .name = "qns_pcie_mem_noc", - .id = SA8775P_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SA8775P_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = SA8775P_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SA8775P_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SA8775P_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SA8775P_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SA8775P_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, }; @@ -2108,11 +2165,21 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, }; +static const struct regmap_config sa8775p_aggre1_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x18080, + .fast_io = true, +}; + static const struct qcom_icc_desc sa8775p_aggre1_noc = { + .config = &sa8775p_aggre1_noc_regmap_config, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), + .qos_requires_clocks = true, }; static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { @@ -2135,11 +2202,21 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, }; +static const struct regmap_config sa8775p_aggre2_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1b080, + .fast_io = true, +}; + static const struct qcom_icc_desc sa8775p_aggre2_noc = { + .config = &sa8775p_aggre2_noc_regmap_config, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), + .qos_requires_clocks = true, }; static struct qcom_icc_bcm * const clk_virt_bcms[] = { @@ -2264,7 +2341,16 @@ static struct qcom_icc_node * const config_noc_nodes[] = { [SLAVE_TCU] = &xs_sys_tcu_cfg, }; +static const struct regmap_config sa8775p_config_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x13080, + .fast_io = true, +}; + static const struct qcom_icc_desc sa8775p_config_noc = { + .config = &sa8775p_config_noc_regmap_config, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -2280,7 +2366,16 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, }; +static const struct regmap_config sa8775p_dc_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x5080, + .fast_io = true, +}; + static const struct qcom_icc_desc sa8775p_dc_noc = { + .config = &sa8775p_dc_noc_regmap_config, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, @@ -2316,7 +2411,16 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { [SLAVE_SERVICE_GEM_NOC2] = &srvc_sys_gemnoc_2, }; +static const struct regmap_config sa8775p_gem_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xf6080, + .fast_io = true, +}; + static const struct qcom_icc_desc sa8775p_gem_noc = { + .config = &sa8775p_gem_noc_regmap_config, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -2334,7 +2438,16 @@ static struct qcom_icc_node * const gpdsp_anoc_nodes[] = { [SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc, }; +static const struct regmap_config sa8775p_gpdsp_anoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xe080, + .fast_io = true, +}; + static const struct qcom_icc_desc sa8775p_gpdsp_anoc = { + .config = &sa8775p_gpdsp_anoc_regmap_config, .nodes = gpdsp_anoc_nodes, .num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes), .bcms = gpdsp_anoc_bcms, @@ -2357,7 +2470,16 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, }; +static const struct regmap_config sa8775p_lpass_ag_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x17200, + .fast_io = true, +}; + static const struct qcom_icc_desc sa8775p_lpass_ag_noc = { + .config = &sa8775p_lpass_ag_noc_regmap_config, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), .bcms = lpass_ag_noc_bcms, @@ -2406,7 +2528,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { [SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf, }; +static const struct regmap_config sa8775p_mmss_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x40000, + .fast_io = true, +}; + static const struct qcom_icc_desc sa8775p_mmss_noc = { + .config = &sa8775p_mmss_noc_regmap_config, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -2426,7 +2557,16 @@ static struct qcom_icc_node * const nspa_noc_nodes[] = { [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, }; +static const struct regmap_config sa8775p_nspa_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x16080, + .fast_io = true, +}; + static const struct qcom_icc_desc sa8775p_nspa_noc = { + .config = &sa8775p_nspa_noc_regmap_config, .nodes = nspa_noc_nodes, .num_nodes = ARRAY_SIZE(nspa_noc_nodes), .bcms = nspa_noc_bcms, @@ -2438,6 +2578,14 @@ static struct qcom_icc_bcm * const nspb_noc_bcms[] = { &bcm_nsb1, }; +static const struct regmap_config sa8775p_nspb_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x16080, + .fast_io = true, +}; + static struct qcom_icc_node * const nspb_noc_nodes[] = { [MASTER_CDSPB_NOC_CFG] = &qhm_nspb_noc_config, [MASTER_CDSP_PROC_B] = &qxm_nspb, @@ -2447,6 +2595,7 @@ static struct qcom_icc_node * const nspb_noc_nodes[] = { }; static const struct qcom_icc_desc sa8775p_nspb_noc = { + .config = &sa8775p_nspb_noc_regmap_config, .nodes = nspb_noc_nodes, .num_nodes = ARRAY_SIZE(nspb_noc_nodes), .bcms = nspb_noc_bcms, @@ -2463,7 +2612,16 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = { [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, }; +static const struct regmap_config sa8775p_pcie_anoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xc080, + .fast_io = true, +}; + static const struct qcom_icc_desc sa8775p_pcie_anoc = { + .config = &sa8775p_pcie_anoc_regmap_config, .nodes = pcie_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), .bcms = pcie_anoc_bcms, @@ -2491,7 +2649,16 @@ static struct qcom_icc_node * const system_noc_nodes[] = { [SLAVE_SERVICE_SNOC] = &srvc_snoc, }; +static const struct regmap_config sa8775p_system_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x15080, + .fast_io = true, +}; + static const struct qcom_icc_desc sa8775p_system_noc = { + .config = &sa8775p_system_noc_regmap_config, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, @@ -2519,7 +2686,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove_new = qcom_icc_rpmh_remove, + .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sa8775p", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sar2130p.c b/drivers/interconnect/qcom/sar2130p.c new file mode 100644 index 000000000000..34cb3fc1f995 --- /dev/null +++ b/drivers/interconnect/qcom/sar2130p.c @@ -0,0 +1,1758 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024, Linaro Ltd. + */ + +#include <linux/device.h> +#include <linux/interconnect.h> +#include <linux/interconnect-provider.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/sort.h> +#include <dt-bindings/interconnect/qcom,sar2130p-rpmh.h> + +#include "bcm-voter.h" +#include "icc-common.h" +#include "icc-rpmh.h" + +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_nsp_gemnoc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_wlan_q6; +static struct qcom_icc_node qhm_config_noc; +static struct qcom_icc_node qxm_lpass_dsp; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_lsr; +static struct qcom_icc_node qnm_mdp; +static struct qcom_icc_node qnm_mnoc_cfg; +static struct qcom_icc_node qnm_video; +static struct qcom_icc_node qnm_video_cv_cpu; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qnm_video_v_cpu; +static struct qcom_icc_node qhm_nsp_noc_config; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node qhm_gic; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_cnoc_datapath; +static struct qcom_icc_node qnm_lpass_noc; +static struct qcom_icc_node qnm_snoc_cfg; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mxa; +static struct qcom_icc_node qhs_cpr_mxc; +static struct qcom_icc_node qhs_cpr_nspcx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_lpass_cfg; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qhs_wlan_q6; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qns_mnoc_cfg; +static struct qcom_icc_node qns_snoc_cfg; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node qhs_lpass_core; +static struct qcom_icc_node qhs_lpass_lpi; +static struct qcom_icc_node qhs_lpass_mpu; +static struct qcom_icc_node qhs_lpass_top; +static struct qcom_icc_node qns_sysnoc; +static struct qcom_icc_node srvc_niu_aml_noc; +static struct qcom_icc_node srvc_niu_lpass_agnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node service_nsp_noc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node srvc_snoc; + +static const struct regmap_config icc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .fast_io = true, +}; + +static struct qcom_icc_node qup0_core_master = { + .name = "qup0_core_master", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qup0_core_slave }, +}; + +static struct qcom_icc_node qup1_core_master = { + .name = "qup1_core_master", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qup1_core_slave }, +}; + +static struct qcom_icc_node qnm_gemnoc_cnoc = { + .name = "qnm_gemnoc_cnoc", + .channels = 1, + .buswidth = 16, + .num_links = 43, + .link_nodes = { &qhs_ahb2phy0, &qhs_aoss, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_compute_cfg, &qhs_cpr_cx, + &qhs_cpr_mmcx, &qhs_cpr_mxa, + &qhs_cpr_mxc, &qhs_cpr_nspcx, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_imem_cfg, &qhs_ipc_router, + &qhs_lpass_cfg, &qhs_mx_rdpm, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pdm, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc1, + &qhs_tcsr, &qhs_tlmm, + &qhs_tme_cfg, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qhs_wlan_q6, &qns_ddrss_cfg, + &qns_mnoc_cfg, &qns_snoc_cfg, + &qxs_imem, &qxs_pimem, + &srvc_cnoc, &xs_qdss_stm, + &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie = { + .name = "qnm_gemnoc_pcie", + .channels = 1, + .buswidth = 8, + .num_links = 2, + .link_nodes = { &xs_pcie_0, &xs_pcie_1 }, +}; + +static struct qcom_icc_node xm_qdss_dap = { + .name = "xm_qdss_dap", + .channels = 1, + .buswidth = 8, + .num_links = 43, + .link_nodes = { &qhs_ahb2phy0, &qhs_aoss, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_compute_cfg, &qhs_cpr_cx, + &qhs_cpr_mmcx, &qhs_cpr_mxa, + &qhs_cpr_mxc, &qhs_cpr_nspcx, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_imem_cfg, &qhs_ipc_router, + &qhs_lpass_cfg, &qhs_mx_rdpm, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pdm, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc1, + &qhs_tcsr, &qhs_tlmm, + &qhs_tme_cfg, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qhs_wlan_q6, &qns_ddrss_cfg, + &qns_mnoc_cfg, &qns_snoc_cfg, + &qxs_imem, &qxs_pimem, + &srvc_cnoc, &xs_qdss_stm, + &xs_sys_tcu_cfg }, +}; + +static const struct qcom_icc_qosbox alm_gpu_tcu_qos = { + .num_ports = 1, + .port_offsets = { 0x9e000 }, + .prio = 1, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node alm_gpu_tcu = { + .name = "alm_gpu_tcu", + .channels = 1, + .buswidth = 8, + .qosbox = &alm_gpu_tcu_qos, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static const struct qcom_icc_qosbox alm_sys_tcu_qos = { + .num_ports = 1, + .port_offsets = { 0x9f000 }, + .prio = 6, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node alm_sys_tcu = { + .name = "alm_sys_tcu", + .channels = 1, + .buswidth = 8, + .qosbox = &alm_sys_tcu_qos, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node chm_apps = { + .name = "chm_apps", + .channels = 1, + .buswidth = 32, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static const struct qcom_icc_qosbox qnm_gpu_qos = { + .num_ports = 2, + .port_offsets = { 0xe000, 0x4e000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node qnm_gpu = { + .name = "qnm_gpu", + .channels = 2, + .buswidth = 32, + .qosbox = &qnm_gpu_qos, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static const struct qcom_icc_qosbox qnm_mnoc_hf_qos = { + .num_ports = 2, + .port_offsets = { 0xf000, 0x4f000 }, + .prio = 0, + .urg_fwd = 1, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .channels = 2, + .buswidth = 32, + .qosbox = &qnm_mnoc_hf_qos, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static const struct qcom_icc_qosbox qnm_mnoc_sf_qos = { + .num_ports = 1, + .port_offsets = { 0x9d000 }, + .prio = 0, + .urg_fwd = 1, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .channels = 1, + .buswidth = 32, + .qosbox = &qnm_mnoc_sf_qos, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static const struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = { + .num_ports = 2, + .port_offsets = { 0x10000, 0x50000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node qnm_nsp_gemnoc = { + .name = "qnm_nsp_gemnoc", + .channels = 2, + .buswidth = 32, + .qosbox = &qnm_nsp_gemnoc_qos, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static const struct qcom_icc_qosbox qnm_pcie_qos = { + .num_ports = 1, + .port_offsets = { 0xa2000 }, + .prio = 2, + .urg_fwd = 1, +}; + +static struct qcom_icc_node qnm_pcie = { + .name = "qnm_pcie", + .channels = 1, + .buswidth = 16, + .qosbox = &qnm_pcie_qos, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static const struct qcom_icc_qosbox qnm_snoc_gc_qos = { + .num_ports = 1, + .port_offsets = { 0xa0000 }, + .prio = 0, + .urg_fwd = 1, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .channels = 1, + .buswidth = 8, + .qosbox = &qnm_snoc_gc_qos, + .num_links = 1, + .link_nodes = { &qns_llcc }, +}; + +static const struct qcom_icc_qosbox qnm_snoc_sf_qos = { + .num_ports = 1, + .port_offsets = { 0xa1000 }, + .prio = 0, + .urg_fwd = 1, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .channels = 1, + .buswidth = 16, + .qosbox = &qnm_snoc_sf_qos, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qxm_wlan_q6 = { + .name = "qxm_wlan_q6", + .channels = 1, + .buswidth = 8, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qhm_config_noc = { + .name = "qhm_config_noc", + .channels = 1, + .buswidth = 4, + .num_links = 6, + .link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi, + &qhs_lpass_mpu, &qhs_lpass_top, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, +}; + +static struct qcom_icc_node qxm_lpass_dsp = { + .name = "qxm_lpass_dsp", + .channels = 1, + .buswidth = 8, + .num_links = 4, + .link_nodes = { &qhs_lpass_top, &qns_sysnoc, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &ebi }, +}; + +static const struct qcom_icc_qosbox qnm_camnoc_hf_qos = { + .num_ports = 1, + .port_offsets = { 0x1c000 }, + .prio = 0, + .urg_fwd = 1, +}; + +static struct qcom_icc_node qnm_camnoc_hf = { + .name = "qnm_camnoc_hf", + .channels = 1, + .buswidth = 32, + .qosbox = &qnm_camnoc_hf_qos, + .num_links = 1, + .link_nodes = { &qns_mem_noc_hf }, +}; + +static const struct qcom_icc_qosbox qnm_camnoc_icp_qos = { + .num_ports = 1, + .port_offsets = { 0x1c080 }, + .prio = 4, + .urg_fwd = 1, +}; + +static struct qcom_icc_node qnm_camnoc_icp = { + .name = "qnm_camnoc_icp", + .channels = 1, + .buswidth = 8, + .qosbox = &qnm_camnoc_icp_qos, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static const struct qcom_icc_qosbox qnm_camnoc_sf_qos = { + .num_ports = 1, + .port_offsets = { 0x1c100 }, + .prio = 0, + .urg_fwd = 1, +}; + +static struct qcom_icc_node qnm_camnoc_sf = { + .name = "qnm_camnoc_sf", + .channels = 1, + .buswidth = 32, + .qosbox = &qnm_camnoc_sf_qos, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static const struct qcom_icc_qosbox qnm_lsr_qos = { + .num_ports = 2, + .port_offsets = { 0x1f000, 0x1f080 }, + .prio = 3, + .urg_fwd = 1, +}; + +static struct qcom_icc_node qnm_lsr = { + .name = "qnm_lsr", + .channels = 2, + .buswidth = 32, + .qosbox = &qnm_lsr_qos, + .num_links = 1, + .link_nodes = { &qns_mem_noc_hf }, +}; + +static const struct qcom_icc_qosbox qnm_mdp_qos = { + .num_ports = 2, + .port_offsets = { 0x1d000, 0x1d080 }, + .prio = 0, + .urg_fwd = 1, +}; + +static struct qcom_icc_node qnm_mdp = { + .name = "qnm_mdp", + .channels = 2, + .buswidth = 32, + .qosbox = &qnm_mdp_qos, + .num_links = 1, + .link_nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qnm_mnoc_cfg = { + .name = "qnm_mnoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &srvc_mnoc }, +}; + +static const struct qcom_icc_qosbox qnm_video_qos = { + .num_ports = 2, + .port_offsets = { 0x1e000, 0x1e080 }, + .prio = 0, + .urg_fwd = 1, +}; + +static struct qcom_icc_node qnm_video = { + .name = "qnm_video", + .channels = 2, + .buswidth = 32, + .qosbox = &qnm_video_qos, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static const struct qcom_icc_qosbox qnm_video_cv_cpu_qos = { + .num_ports = 1, + .port_offsets = { 0x1e100 }, + .prio = 4, + .urg_fwd = 1, +}; + +static struct qcom_icc_node qnm_video_cv_cpu = { + .name = "qnm_video_cv_cpu", + .channels = 1, + .buswidth = 8, + .qosbox = &qnm_video_cv_cpu_qos, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static const struct qcom_icc_qosbox qnm_video_cvp_qos = { + .num_ports = 1, + .port_offsets = { 0x1e180 }, + .prio = 0, + .urg_fwd = 1, +}; + +static struct qcom_icc_node qnm_video_cvp = { + .name = "qnm_video_cvp", + .channels = 1, + .buswidth = 32, + .qosbox = &qnm_video_cvp_qos, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static const struct qcom_icc_qosbox qnm_video_v_cpu_qos = { + .num_ports = 1, + .port_offsets = { 0x1e200 }, + .prio = 4, + .urg_fwd = 1, +}; + +static struct qcom_icc_node qnm_video_v_cpu = { + .name = "qnm_video_v_cpu", + .channels = 1, + .buswidth = 8, + .qosbox = &qnm_video_v_cpu_qos, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qhm_nsp_noc_config = { + .name = "qhm_nsp_noc_config", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &service_nsp_noc }, +}; + +static struct qcom_icc_node qxm_nsp = { + .name = "qxm_nsp", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_nsp_gemnoc }, +}; + +static const struct qcom_icc_qosbox xm_pcie3_0_qos = { + .num_ports = 1, + .port_offsets = { 0x9000 }, + .prio = 3, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node xm_pcie3_0 = { + .name = "xm_pcie3_0", + .channels = 1, + .buswidth = 8, + .qosbox = &xm_pcie3_0_qos, + .num_links = 1, + .link_nodes = { &qns_pcie_mem_noc }, +}; + +static const struct qcom_icc_qosbox xm_pcie3_1_qos = { + .num_ports = 1, + .port_offsets = { 0xa000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node xm_pcie3_1 = { + .name = "xm_pcie3_1", + .channels = 1, + .buswidth = 8, + .qosbox = &xm_pcie3_1_qos, + .num_links = 1, + .link_nodes = { &qns_pcie_mem_noc }, +}; + +static const struct qcom_icc_qosbox qhm_gic_qos = { + .num_ports = 1, + .port_offsets = { 0x1d000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node qhm_gic = { + .name = "qhm_gic", + .channels = 1, + .buswidth = 4, + .qosbox = &qhm_gic_qos, + .num_links = 1, + .link_nodes = { &qns_gemnoc_sf }, +}; + +static const struct qcom_icc_qosbox qhm_qdss_bam_qos = { + .num_ports = 1, + .port_offsets = { 0x22000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .channels = 1, + .buswidth = 4, + .qosbox = &qhm_qdss_bam_qos, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static const struct qcom_icc_qosbox qhm_qspi_qos = { + .num_ports = 1, + .port_offsets = { 0x23000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node qhm_qspi = { + .name = "qhm_qspi", + .channels = 1, + .buswidth = 4, + .qosbox = &qhm_qspi_qos, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static const struct qcom_icc_qosbox qhm_qup0_qos = { + .num_ports = 1, + .port_offsets = { 0x24000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node qhm_qup0 = { + .name = "qhm_qup0", + .channels = 1, + .buswidth = 4, + .qosbox = &qhm_qup0_qos, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static const struct qcom_icc_qosbox qhm_qup1_qos = { + .num_ports = 1, + .port_offsets = { 0x25000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node qhm_qup1 = { + .name = "qhm_qup1", + .channels = 1, + .buswidth = 4, + .qosbox = &qhm_qup1_qos, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_gemnoc_sf }, +}; + +static const struct qcom_icc_qosbox qnm_cnoc_datapath_qos = { + .num_ports = 1, + .port_offsets = { 0x26000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node qnm_cnoc_datapath = { + .name = "qnm_cnoc_datapath", + .channels = 1, + .buswidth = 8, + .qosbox = &qnm_cnoc_datapath_qos, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static const struct qcom_icc_qosbox qnm_lpass_noc_qos = { + .num_ports = 1, + .port_offsets = { 0x1e000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node qnm_lpass_noc = { + .name = "qnm_lpass_noc", + .channels = 1, + .buswidth = 16, + .qosbox = &qnm_lpass_noc_qos, + .num_links = 1, + .link_nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_snoc_cfg = { + .name = "qnm_snoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &srvc_snoc }, +}; + +static const struct qcom_icc_qosbox qxm_crypto_qos = { + .num_ports = 1, + .port_offsets = { 0x27000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .channels = 1, + .buswidth = 8, + .qosbox = &qxm_crypto_qos, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static const struct qcom_icc_qosbox qxm_pimem_qos = { + .num_ports = 1, + .port_offsets = { 0x1f000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node qxm_pimem = { + .name = "qxm_pimem", + .channels = 1, + .buswidth = 8, + .qosbox = &qxm_pimem_qos, + .num_links = 1, + .link_nodes = { &qns_gemnoc_gc }, +}; + +static const struct qcom_icc_qosbox xm_gic_qos = { + .num_ports = 1, + .port_offsets = { 0x21000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .channels = 1, + .buswidth = 8, + .qosbox = &xm_gic_qos, + .num_links = 1, + .link_nodes = { &qns_gemnoc_gc }, +}; + +static const struct qcom_icc_qosbox xm_qdss_etr_0_qos = { + .num_ports = 1, + .port_offsets = { 0x1b000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node xm_qdss_etr_0 = { + .name = "xm_qdss_etr_0", + .channels = 1, + .buswidth = 8, + .qosbox = &xm_qdss_etr_0_qos, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static const struct qcom_icc_qosbox xm_qdss_etr_1_qos = { + .num_ports = 1, + .port_offsets = { 0x1c000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node xm_qdss_etr_1 = { + .name = "xm_qdss_etr_1", + .channels = 1, + .buswidth = 8, + .qosbox = &xm_qdss_etr_1_qos, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static const struct qcom_icc_qosbox xm_sdc1_qos = { + .num_ports = 1, + .port_offsets = { 0x29000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node xm_sdc1 = { + .name = "xm_sdc1", + .channels = 1, + .buswidth = 8, + .qosbox = &xm_sdc1_qos, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static const struct qcom_icc_qosbox xm_usb3_0_qos = { + .num_ports = 1, + .port_offsets = { 0x28000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node xm_usb3_0 = { + .name = "xm_usb3_0", + .channels = 1, + .buswidth = 8, + .qosbox = &xm_usb3_0_qos, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qup0_core_slave = { + .name = "qup0_core_slave", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup1_core_slave = { + .name = "qup1_core_slave", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy0 = { + .name = "qhs_ahb2phy0", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_compute_cfg = { + .name = "qhs_compute_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qhm_nsp_noc_config }, +}; + +static struct qcom_icc_node qhs_cpr_cx = { + .name = "qhs_cpr_cx", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mmcx = { + .name = "qhs_cpr_mmcx", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mxa = { + .name = "qhs_cpr_mxa", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mxc = { + .name = "qhs_cpr_mxc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_nspcx = { + .name = "qhs_cpr_nspcx", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cx_rdpm = { + .name = "qhs_cx_rdpm", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display_cfg = { + .name = "qhs_display_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipc_router = { + .name = "qhs_ipc_router", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_cfg = { + .name = "qhs_lpass_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qhm_config_noc }, +}; + +static struct qcom_icc_node qhs_mx_rdpm = { + .name = "qhs_mx_rdpm", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie0_cfg = { + .name = "qhs_pcie0_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie1_cfg = { + .name = "qhs_pcie1_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg = { + .name = "qhs_pimem_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qspi = { + .name = "qhs_qspi", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup0 = { + .name = "qhs_qup0", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup1 = { + .name = "qhs_qup1", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc1 = { + .name = "qhs_sdc1", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm = { + .name = "qhs_tlmm", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tme_cfg = { + .name = "qhs_tme_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_0 = { + .name = "qhs_usb3_0", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .name = "qhs_vsense_ctrl_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_wlan_q6 = { + .name = "qhs_wlan_q6", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_ddrss_cfg = { + .name = "qns_ddrss_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_mnoc_cfg = { + .name = "qns_mnoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qnm_mnoc_cfg }, +}; + +static struct qcom_icc_node qns_snoc_cfg = { + .name = "qns_snoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qnm_snoc_cfg }, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_pimem = { + .name = "qxs_pimem", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node srvc_cnoc = { + .name = "srvc_cnoc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_pcie_0 = { + .name = "xs_pcie_0", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_pcie_1 = { + .name = "xs_pcie_1", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qns_gem_noc_cnoc = { + .name = "qns_gem_noc_cnoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_gemnoc_cnoc }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .channels = 2, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &llcc_mc }, +}; + +static struct qcom_icc_node qns_pcie = { + .name = "qns_pcie", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qnm_gemnoc_pcie }, +}; + +static struct qcom_icc_node qhs_lpass_core = { + .name = "qhs_lpass_core", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_lpi = { + .name = "qhs_lpass_lpi", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_mpu = { + .name = "qhs_lpass_mpu", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_top = { + .name = "qhs_lpass_top", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_sysnoc = { + .name = "qns_sysnoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_lpass_noc }, +}; + +static struct qcom_icc_node srvc_niu_aml_noc = { + .name = "srvc_niu_aml_noc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_niu_lpass_agnoc = { + .name = "srvc_niu_lpass_agnoc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_mnoc_hf }, +}; + +static struct qcom_icc_node qns_mem_noc_sf = { + .name = "qns_mem_noc_sf", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_mnoc_sf }, +}; + +static struct qcom_icc_node srvc_mnoc = { + .name = "srvc_mnoc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_nsp_gemnoc = { + .name = "qns_nsp_gemnoc", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_nsp_gemnoc }, +}; + +static struct qcom_icc_node service_nsp_noc = { + .name = "service_nsp_noc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_pcie_mem_noc = { + .name = "qns_pcie_mem_noc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_pcie }, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_node qns_gemnoc_gc = { + .name = "qns_gemnoc_gc", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qnm_snoc_gc }, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_snoc_sf }, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .enable_mask = BIT(3), + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .enable_mask = BIT(0), + .keepalive = true, + .num_nodes = 48, + .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, + &xm_qdss_dap, &qhs_ahb2phy0, + &qhs_aoss, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_compute_cfg, + &qhs_cpr_cx, &qhs_cpr_mmcx, + &qhs_cpr_mxa, &qhs_cpr_mxc, + &qhs_cpr_nspcx, &qhs_crypto0_cfg, + &qhs_cx_rdpm, &qhs_display_cfg, + &qhs_gpuss_cfg, &qhs_imem_cfg, + &qhs_ipc_router, &qhs_lpass_cfg, + &qhs_mx_rdpm, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_pdm, + &qhs_pimem_cfg, &qhs_prng, + &qhs_qdss_cfg, &qhs_qspi, + &qhs_qup0, &qhs_qup1, + &qhs_sdc1, &qhs_tcsr, + &qhs_tlmm, &qhs_tme_cfg, + &qhs_usb3_0, &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, &qhs_wlan_q6, + &qns_ddrss_cfg, &qns_mnoc_cfg, + &qns_snoc_cfg, &qxs_imem, + &qxs_pimem, &srvc_cnoc, + &xs_pcie_0, &xs_pcie_1, + &xs_qdss_stm, &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_bcm bcm_co0 = { + .name = "CO0", + .enable_mask = BIT(0), + .num_nodes = 2, + .nodes = { &qxm_nsp, &qns_nsp_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .enable_mask = BIT(0), + .num_nodes = 11, + .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp, + &qnm_camnoc_sf, &qnm_lsr, + &qnm_mdp, &qnm_mnoc_cfg, + &qnm_video, &qnm_video_cv_cpu, + &qnm_video_cvp, &qnm_video_v_cpu, + &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .keepalive = true, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup0_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup1 = { + .name = "QUP1", + .keepalive = true, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup1_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh1 = { + .name = "SH1", + .enable_mask = BIT(0), + .num_nodes = 13, + .nodes = { &alm_gpu_tcu, &alm_sys_tcu, + &chm_apps, &qnm_gpu, + &qnm_mnoc_hf, &qnm_mnoc_sf, + &qnm_nsp_gemnoc, &qnm_pcie, + &qnm_snoc_gc, &qnm_snoc_sf, + &qxm_wlan_q6, &qns_gem_noc_cnoc, + &qns_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .enable_mask = BIT(0), + .num_nodes = 4, + .nodes = { &qhm_gic, &qxm_pimem, + &xm_gic, &qns_gemnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .num_nodes = 1, + .nodes = { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .num_nodes = 1, + .nodes = { &qnm_lpass_noc }, +}; + +static struct qcom_icc_bcm bcm_sn7 = { + .name = "SN7", + .num_nodes = 1, + .nodes = { &qns_pcie_mem_noc }, +}; + +static struct qcom_icc_bcm * const clk_virt_bcms[] = { + &bcm_qup0, + &bcm_qup1, +}; + +static struct qcom_icc_node * const clk_virt_nodes[] = { + [MASTER_QUP_CORE_0] = &qup0_core_master, + [MASTER_QUP_CORE_1] = &qup1_core_master, + [SLAVE_QUP_CORE_0] = &qup0_core_slave, + [SLAVE_QUP_CORE_1] = &qup1_core_slave, +}; + +static const struct qcom_icc_desc sar2130p_clk_virt = { + .nodes = clk_virt_nodes, + .num_nodes = ARRAY_SIZE(clk_virt_nodes), + .bcms = clk_virt_bcms, + .num_bcms = ARRAY_SIZE(clk_virt_bcms), +}; + +static struct qcom_icc_bcm * const config_noc_bcms[] = { + &bcm_cn0, +}; + +static struct qcom_icc_node * const config_noc_nodes[] = { + [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, + [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, + [MASTER_QDSS_DAP] = &xm_qdss_dap, + [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, + [SLAVE_AOSS] = &qhs_aoss, + [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, + [SLAVE_CLK_CTL] = &qhs_clk_ctl, + [SLAVE_CDSP_CFG] = &qhs_compute_cfg, + [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, + [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, + [SLAVE_RBCPR_MXA_CFG] = &qhs_cpr_mxa, + [SLAVE_RBCPR_MXC_CFG] = &qhs_cpr_mxc, + [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx, + [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, + [SLAVE_CX_RDPM] = &qhs_cx_rdpm, + [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, + [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, + [SLAVE_IMEM_CFG] = &qhs_imem_cfg, + [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, + [SLAVE_LPASS] = &qhs_lpass_cfg, + [SLAVE_MX_RDPM] = &qhs_mx_rdpm, + [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, + [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, + [SLAVE_PDM] = &qhs_pdm, + [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, + [SLAVE_PRNG] = &qhs_prng, + [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, + [SLAVE_QSPI_0] = &qhs_qspi, + [SLAVE_QUP_0] = &qhs_qup0, + [SLAVE_QUP_1] = &qhs_qup1, + [SLAVE_SDCC_1] = &qhs_sdc1, + [SLAVE_TCSR] = &qhs_tcsr, + [SLAVE_TLMM] = &qhs_tlmm, + [SLAVE_TME_CFG] = &qhs_tme_cfg, + [SLAVE_USB3_0] = &qhs_usb3_0, + [SLAVE_VENUS_CFG] = &qhs_venus_cfg, + [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, + [SLAVE_WLAN_Q6_CFG] = &qhs_wlan_q6, + [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, + [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg, + [SLAVE_SNOC_CFG] = &qns_snoc_cfg, + [SLAVE_IMEM] = &qxs_imem, + [SLAVE_PIMEM] = &qxs_pimem, + [SLAVE_SERVICE_CNOC] = &srvc_cnoc, + [SLAVE_PCIE_0] = &xs_pcie_0, + [SLAVE_PCIE_1] = &xs_pcie_1, + [SLAVE_QDSS_STM] = &xs_qdss_stm, + [SLAVE_TCU] = &xs_sys_tcu_cfg, +}; + +static const struct qcom_icc_desc sar2130p_config_noc = { + .config = &icc_regmap_config, + .nodes = config_noc_nodes, + .num_nodes = ARRAY_SIZE(config_noc_nodes), + .bcms = config_noc_bcms, + .num_bcms = ARRAY_SIZE(config_noc_bcms), +}; + +static struct qcom_icc_bcm * const gem_noc_bcms[] = { + &bcm_sh0, + &bcm_sh1, +}; + +static struct qcom_icc_node * const gem_noc_nodes[] = { + [MASTER_GPU_TCU] = &alm_gpu_tcu, + [MASTER_SYS_TCU] = &alm_sys_tcu, + [MASTER_APPSS_PROC] = &chm_apps, + [MASTER_GFX3D] = &qnm_gpu, + [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, + [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, + [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc, + [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, + [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, + [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, + [MASTER_WLAN_Q6] = &qxm_wlan_q6, + [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, + [SLAVE_LLCC] = &qns_llcc, + [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, +}; + +static const struct qcom_icc_desc sar2130p_gem_noc = { + .config = &icc_regmap_config, + .nodes = gem_noc_nodes, + .num_nodes = ARRAY_SIZE(gem_noc_nodes), + .bcms = gem_noc_bcms, + .num_bcms = ARRAY_SIZE(gem_noc_bcms), +}; + +static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { +}; + +static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { + [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, + [MASTER_LPASS_PROC] = &qxm_lpass_dsp, + [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, + [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, + [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, + [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, + [SLAVE_LPASS_SNOC] = &qns_sysnoc, + [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, + [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, +}; + +static const struct qcom_icc_desc sar2130p_lpass_ag_noc = { + .config = &icc_regmap_config, + .nodes = lpass_ag_noc_nodes, + .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), + .bcms = lpass_ag_noc_bcms, + .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), +}; + +static struct qcom_icc_bcm * const mc_virt_bcms[] = { + &bcm_acv, + &bcm_mc0, +}; + +static struct qcom_icc_node * const mc_virt_nodes[] = { + [MASTER_LLCC] = &llcc_mc, + [SLAVE_EBI1] = &ebi, +}; + +static const struct qcom_icc_desc sar2130p_mc_virt = { + .nodes = mc_virt_nodes, + .num_nodes = ARRAY_SIZE(mc_virt_nodes), + .bcms = mc_virt_bcms, + .num_bcms = ARRAY_SIZE(mc_virt_bcms), +}; + +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { + &bcm_mm0, + &bcm_mm1, +}; + +static struct qcom_icc_node * const mmss_noc_nodes[] = { + [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, + [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, + [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, + [MASTER_LSR] = &qnm_lsr, + [MASTER_MDP] = &qnm_mdp, + [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg, + [MASTER_VIDEO] = &qnm_video, + [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu, + [MASTER_VIDEO_PROC] = &qnm_video_cvp, + [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, + [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, + [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, + [SLAVE_SERVICE_MNOC] = &srvc_mnoc, +}; + +static const struct qcom_icc_desc sar2130p_mmss_noc = { + .config = &icc_regmap_config, + .nodes = mmss_noc_nodes, + .num_nodes = ARRAY_SIZE(mmss_noc_nodes), + .bcms = mmss_noc_bcms, + .num_bcms = ARRAY_SIZE(mmss_noc_bcms), +}; + +static struct qcom_icc_bcm * const nsp_noc_bcms[] = { + &bcm_co0, +}; + +static struct qcom_icc_node * const nsp_noc_nodes[] = { + [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, + [MASTER_CDSP_PROC] = &qxm_nsp, + [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, + [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, +}; + +static const struct qcom_icc_desc sar2130p_nsp_noc = { + .config = &icc_regmap_config, + .nodes = nsp_noc_nodes, + .num_nodes = ARRAY_SIZE(nsp_noc_nodes), + .bcms = nsp_noc_bcms, + .num_bcms = ARRAY_SIZE(nsp_noc_bcms), +}; + +static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { + &bcm_sn7, +}; + +static struct qcom_icc_node * const pcie_anoc_nodes[] = { + [MASTER_PCIE_0] = &xm_pcie3_0, + [MASTER_PCIE_1] = &xm_pcie3_1, + [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, +}; + +static const struct qcom_icc_desc sar2130p_pcie_anoc = { + .config = &icc_regmap_config, + .nodes = pcie_anoc_nodes, + .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), + .bcms = pcie_anoc_bcms, + .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), +}; + +static struct qcom_icc_bcm * const system_noc_bcms[] = { + &bcm_ce0, + &bcm_sn0, + &bcm_sn1, + &bcm_sn3, + &bcm_sn4, +}; + +static struct qcom_icc_node * const system_noc_nodes[] = { + [MASTER_GIC_AHB] = &qhm_gic, + [MASTER_QDSS_BAM] = &qhm_qdss_bam, + [MASTER_QSPI_0] = &qhm_qspi, + [MASTER_QUP_0] = &qhm_qup0, + [MASTER_QUP_1] = &qhm_qup1, + [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, + [MASTER_CNOC_DATAPATH] = &qnm_cnoc_datapath, + [MASTER_LPASS_ANOC] = &qnm_lpass_noc, + [MASTER_SNOC_CFG] = &qnm_snoc_cfg, + [MASTER_CRYPTO] = &qxm_crypto, + [MASTER_PIMEM] = &qxm_pimem, + [MASTER_GIC] = &xm_gic, + [MASTER_QDSS_ETR] = &xm_qdss_etr_0, + [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, + [MASTER_SDCC_1] = &xm_sdc1, + [MASTER_USB3_0] = &xm_usb3_0, + [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, + [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, + [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, + [SLAVE_SERVICE_SNOC] = &srvc_snoc, +}; + +static const struct qcom_icc_desc sar2130p_system_noc = { + .config = &icc_regmap_config, + .nodes = system_noc_nodes, + .num_nodes = ARRAY_SIZE(system_noc_nodes), + .bcms = system_noc_bcms, + .num_bcms = ARRAY_SIZE(system_noc_bcms), +}; + +static const struct of_device_id qnoc_of_match[] = { + { .compatible = "qcom,sar2130p-clk-virt", .data = &sar2130p_clk_virt}, + { .compatible = "qcom,sar2130p-config-noc", .data = &sar2130p_config_noc}, + { .compatible = "qcom,sar2130p-gem-noc", .data = &sar2130p_gem_noc}, + { .compatible = "qcom,sar2130p-lpass-ag-noc", .data = &sar2130p_lpass_ag_noc}, + { .compatible = "qcom,sar2130p-mc-virt", .data = &sar2130p_mc_virt}, + { .compatible = "qcom,sar2130p-mmss-noc", .data = &sar2130p_mmss_noc}, + { .compatible = "qcom,sar2130p-nsp-noc", .data = &sar2130p_nsp_noc}, + { .compatible = "qcom,sar2130p-pcie-anoc", .data = &sar2130p_pcie_anoc}, + { .compatible = "qcom,sar2130p-system-noc", .data = &sar2130p_system_noc}, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver = { + .probe = qcom_icc_rpmh_probe, + .remove = qcom_icc_rpmh_remove, + .driver = { + .name = "qnoc-sar2130p", + .of_match_table = qnoc_of_match, + .sync_state = icc_sync_state, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&qnoc_driver); +} + +module_exit(qnoc_driver_exit); +MODULE_DESCRIPTION("Qualcomm SAR2130P NoC driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/interconnect/qcom/sc7180.c b/drivers/interconnect/qcom/sc7180.c index 34a1d163d6e1..0ea06facf81e 100644 --- a/drivers/interconnect/qcom/sc7180.c +++ b/drivers/interconnect/qcom/sc7180.c @@ -14,1224 +14,1210 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sc7180.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup_0; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_emmc; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node qhm_a2noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup_1; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node qhm_usb3; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_hf1_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qnm_npu; +static struct qcom_icc_node qxm_npu_dsp; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc_dc_noc; +static struct qcom_icc_node acm_apps0; +static struct qcom_icc_node acm_sys_tcu; +static struct qcom_icc_node qhm_gemnoc_cfg; +static struct qcom_icc_node qnm_cmpnoc; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_gpu; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qxm_camnoc_hf0; +static struct qcom_icc_node qxm_camnoc_hf1; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qxm_venus0; +static struct qcom_icc_node qxm_venus_arm9; +static struct qcom_icc_node amm_npu_sys; +static struct qcom_icc_node qhm_npu_cfg; +static struct qcom_icc_node qup_core_master_1; +static struct qcom_icc_node qup_core_master_2; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gemnoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qns_cdsp_gemnoc; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_a2_noc_cfg; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy2; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_boot_rom; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_camera_nrt_throttle_cfg; +static struct qcom_icc_node qhs_camera_rt_throttle_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_display_rt_throttle_cfg; +static struct qcom_icc_node qhs_display_throttle_cfg; +static struct qcom_icc_node qhs_emmc_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_npu_cfg; +static struct qcom_icc_node qhs_npu_dma_throttle_cfg; +static struct qcom_icc_node qhs_npu_dsp_throttle_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qm_cfg; +static struct qcom_icc_node qhs_qm_mpu_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_security; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm_1; +static struct qcom_icc_node qhs_tlmm_2; +static struct qcom_icc_node qhs_tlmm_3; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_venus_throttle_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_gemnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_gem_noc_snoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node srvc_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_cal_dp0; +static struct qcom_icc_node qhs_cp; +static struct qcom_icc_node qhs_dma_bwmon; +static struct qcom_icc_node qhs_dpm; +static struct qcom_icc_node qhs_isense; +static struct qcom_icc_node qhs_llm; +static struct qcom_icc_node qhs_tcm; +static struct qcom_icc_node qns_npu_sys; +static struct qcom_icc_node srvc_noc; +static struct qcom_icc_node qup_core_slave_1; +static struct qcom_icc_node qup_core_slave_2; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; static struct qcom_icc_node qhm_a1noc_cfg = { .name = "qhm_a1noc_cfg", - .id = SC7180_MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_SLAVE_SERVICE_A1NOC }, + .link_nodes = { &srvc_aggre1_noc }, }; static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = SC7180_MASTER_QSPI, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup_0 = { .name = "qhm_qup_0", - .id = SC7180_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SC7180_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_emmc = { .name = "xm_emmc", - .id = SC7180_MASTER_EMMC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SC7180_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_a2noc_cfg = { .name = "qhm_a2noc_cfg", - .id = SC7180_MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_SLAVE_SERVICE_A2NOC }, + .link_nodes = { &srvc_aggre2_noc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SC7180_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup_1 = { .name = "qhm_qup_1", - .id = SC7180_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SC7180_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SC7180_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = SC7180_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_usb3 = { .name = "qhm_usb3", - .id = SC7180_MASTER_USB3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { .name = "qxm_camnoc_hf0_uncomp", - .id = SC7180_MASTER_CAMNOC_HF0_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC7180_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { .name = "qxm_camnoc_hf1_uncomp", - .id = SC7180_MASTER_CAMNOC_HF1_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC7180_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_sf_uncomp = { .name = "qxm_camnoc_sf_uncomp", - .id = SC7180_MASTER_CAMNOC_SF_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC7180_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qnm_npu = { .name = "qnm_npu", - .id = SC7180_MASTER_NPU, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC7180_SLAVE_CDSP_GEM_NOC }, + .link_nodes = { &qns_cdsp_gemnoc }, }; static struct qcom_icc_node qxm_npu_dsp = { .name = "qxm_npu_dsp", - .id = SC7180_MASTER_NPU_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_SLAVE_CDSP_GEM_NOC }, + .link_nodes = { &qns_cdsp_gemnoc }, }; static struct qcom_icc_node qnm_snoc = { .name = "qnm_snoc", - .id = SC7180_MASTER_SNOC_CNOC, .channels = 1, .buswidth = 8, .num_links = 51, - .links = { SC7180_SLAVE_A1NOC_CFG, - SC7180_SLAVE_A2NOC_CFG, - SC7180_SLAVE_AHB2PHY_SOUTH, - SC7180_SLAVE_AHB2PHY_CENTER, - SC7180_SLAVE_AOP, - SC7180_SLAVE_AOSS, - SC7180_SLAVE_BOOT_ROM, - SC7180_SLAVE_CAMERA_CFG, - SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, - SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, - SC7180_SLAVE_CLK_CTL, - SC7180_SLAVE_RBCPR_CX_CFG, - SC7180_SLAVE_RBCPR_MX_CFG, - SC7180_SLAVE_CRYPTO_0_CFG, - SC7180_SLAVE_DCC_CFG, - SC7180_SLAVE_CNOC_DDRSS, - SC7180_SLAVE_DISPLAY_CFG, - SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, - SC7180_SLAVE_DISPLAY_THROTTLE_CFG, - SC7180_SLAVE_EMMC_CFG, - SC7180_SLAVE_GLM, - SC7180_SLAVE_GFX3D_CFG, - SC7180_SLAVE_IMEM_CFG, - SC7180_SLAVE_IPA_CFG, - SC7180_SLAVE_CNOC_MNOC_CFG, - SC7180_SLAVE_CNOC_MSS, - SC7180_SLAVE_NPU_CFG, - SC7180_SLAVE_NPU_DMA_BWMON_CFG, - SC7180_SLAVE_NPU_PROC_BWMON_CFG, - SC7180_SLAVE_PDM, - SC7180_SLAVE_PIMEM_CFG, - SC7180_SLAVE_PRNG, - SC7180_SLAVE_QDSS_CFG, - SC7180_SLAVE_QM_CFG, - SC7180_SLAVE_QM_MPU_CFG, - SC7180_SLAVE_QSPI_0, - SC7180_SLAVE_QUP_0, - SC7180_SLAVE_QUP_1, - SC7180_SLAVE_SDCC_2, - SC7180_SLAVE_SECURITY, - SC7180_SLAVE_SNOC_CFG, - SC7180_SLAVE_TCSR, - SC7180_SLAVE_TLMM_WEST, - SC7180_SLAVE_TLMM_NORTH, - SC7180_SLAVE_TLMM_SOUTH, - SC7180_SLAVE_UFS_MEM_CFG, - SC7180_SLAVE_USB3, - SC7180_SLAVE_VENUS_CFG, - SC7180_SLAVE_VENUS_THROTTLE_CFG, - SC7180_SLAVE_VSENSE_CTRL_CFG, - SC7180_SLAVE_SERVICE_CNOC - }, + .link_nodes = { &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_ahb2phy0, + &qhs_ahb2phy2, + &qhs_aop, + &qhs_aoss, + &qhs_boot_rom, + &qhs_camera_cfg, + &qhs_camera_nrt_throttle_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_clk_ctl, + &qhs_cpr_cx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_display_rt_throttle_cfg, + &qhs_display_throttle_cfg, + &qhs_emmc_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_mss_cfg, + &qhs_npu_cfg, + &qhs_npu_dma_throttle_cfg, + &qhs_npu_dsp_throttle_cfg, + &qhs_pdm, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qm_cfg, + &qhs_qm_mpu_cfg, + &qhs_qspi, + &qhs_qup0, + &qhs_qup1, + &qhs_sdc2, + &qhs_security, + &qhs_snoc_cfg, + &qhs_tcsr, + &qhs_tlmm_1, + &qhs_tlmm_2, + &qhs_tlmm_3, + &qhs_ufs_mem_cfg, + &qhs_usb3, + &qhs_venus_cfg, + &qhs_venus_throttle_cfg, + &qhs_vsense_ctrl_cfg, + &srvc_cnoc }, }; static struct qcom_icc_node xm_qdss_dap = { .name = "xm_qdss_dap", - .id = SC7180_MASTER_QDSS_DAP, .channels = 1, .buswidth = 8, .num_links = 51, - .links = { SC7180_SLAVE_A1NOC_CFG, - SC7180_SLAVE_A2NOC_CFG, - SC7180_SLAVE_AHB2PHY_SOUTH, - SC7180_SLAVE_AHB2PHY_CENTER, - SC7180_SLAVE_AOP, - SC7180_SLAVE_AOSS, - SC7180_SLAVE_BOOT_ROM, - SC7180_SLAVE_CAMERA_CFG, - SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, - SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, - SC7180_SLAVE_CLK_CTL, - SC7180_SLAVE_RBCPR_CX_CFG, - SC7180_SLAVE_RBCPR_MX_CFG, - SC7180_SLAVE_CRYPTO_0_CFG, - SC7180_SLAVE_DCC_CFG, - SC7180_SLAVE_CNOC_DDRSS, - SC7180_SLAVE_DISPLAY_CFG, - SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, - SC7180_SLAVE_DISPLAY_THROTTLE_CFG, - SC7180_SLAVE_EMMC_CFG, - SC7180_SLAVE_GLM, - SC7180_SLAVE_GFX3D_CFG, - SC7180_SLAVE_IMEM_CFG, - SC7180_SLAVE_IPA_CFG, - SC7180_SLAVE_CNOC_MNOC_CFG, - SC7180_SLAVE_CNOC_MSS, - SC7180_SLAVE_NPU_CFG, - SC7180_SLAVE_NPU_DMA_BWMON_CFG, - SC7180_SLAVE_NPU_PROC_BWMON_CFG, - SC7180_SLAVE_PDM, - SC7180_SLAVE_PIMEM_CFG, - SC7180_SLAVE_PRNG, - SC7180_SLAVE_QDSS_CFG, - SC7180_SLAVE_QM_CFG, - SC7180_SLAVE_QM_MPU_CFG, - SC7180_SLAVE_QSPI_0, - SC7180_SLAVE_QUP_0, - SC7180_SLAVE_QUP_1, - SC7180_SLAVE_SDCC_2, - SC7180_SLAVE_SECURITY, - SC7180_SLAVE_SNOC_CFG, - SC7180_SLAVE_TCSR, - SC7180_SLAVE_TLMM_WEST, - SC7180_SLAVE_TLMM_NORTH, - SC7180_SLAVE_TLMM_SOUTH, - SC7180_SLAVE_UFS_MEM_CFG, - SC7180_SLAVE_USB3, - SC7180_SLAVE_VENUS_CFG, - SC7180_SLAVE_VENUS_THROTTLE_CFG, - SC7180_SLAVE_VSENSE_CTRL_CFG, - SC7180_SLAVE_SERVICE_CNOC - }, + .link_nodes = { &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_ahb2phy0, + &qhs_ahb2phy2, + &qhs_aop, + &qhs_aoss, + &qhs_boot_rom, + &qhs_camera_cfg, + &qhs_camera_nrt_throttle_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_clk_ctl, + &qhs_cpr_cx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_display_rt_throttle_cfg, + &qhs_display_throttle_cfg, + &qhs_emmc_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_mss_cfg, + &qhs_npu_cfg, + &qhs_npu_dma_throttle_cfg, + &qhs_npu_dsp_throttle_cfg, + &qhs_pdm, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qm_cfg, + &qhs_qm_mpu_cfg, + &qhs_qspi, + &qhs_qup0, + &qhs_qup1, + &qhs_sdc2, + &qhs_security, + &qhs_snoc_cfg, + &qhs_tcsr, + &qhs_tlmm_1, + &qhs_tlmm_2, + &qhs_tlmm_3, + &qhs_ufs_mem_cfg, + &qhs_usb3, + &qhs_venus_cfg, + &qhs_venus_throttle_cfg, + &qhs_vsense_ctrl_cfg, + &srvc_cnoc }, }; static struct qcom_icc_node qhm_cnoc_dc_noc = { .name = "qhm_cnoc_dc_noc", - .id = SC7180_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SC7180_SLAVE_GEM_NOC_CFG, - SC7180_SLAVE_LLCC_CFG - }, + .link_nodes = { &qhs_gemnoc, + &qhs_llcc }, }; static struct qcom_icc_node acm_apps0 = { .name = "acm_apps0", - .id = SC7180_MASTER_APPSS_PROC, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SC7180_SLAVE_GEM_NOC_SNOC, - SC7180_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_snoc, + &qns_llcc }, }; static struct qcom_icc_node acm_sys_tcu = { .name = "acm_sys_tcu", - .id = SC7180_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SC7180_SLAVE_GEM_NOC_SNOC, - SC7180_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_snoc, + &qns_llcc }, }; static struct qcom_icc_node qhm_gemnoc_cfg = { .name = "qhm_gemnoc_cfg", - .id = SC7180_MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, - SC7180_SLAVE_SERVICE_GEM_NOC - }, + .link_nodes = { &qhs_mdsp_ms_mpu_cfg, + &srvc_gemnoc }, }; static struct qcom_icc_node qnm_cmpnoc = { .name = "qnm_cmpnoc", - .id = SC7180_MASTER_COMPUTE_NOC, .channels = 1, .buswidth = 32, .num_links = 2, - .links = { SC7180_SLAVE_GEM_NOC_SNOC, - SC7180_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_snoc, + &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SC7180_MASTER_MNOC_HF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC7180_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SC7180_MASTER_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 2, - .links = { SC7180_SLAVE_GEM_NOC_SNOC, - SC7180_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_snoc, + &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SC7180_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SC7180_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7180_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qxm_gpu = { .name = "qxm_gpu", - .id = SC7180_MASTER_GFX3D, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SC7180_SLAVE_GEM_NOC_SNOC, - SC7180_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_snoc, + &qns_llcc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SC7180_MASTER_LLCC, .channels = 2, .buswidth = 4, .num_links = 1, - .links = { SC7180_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qhm_mnoc_cfg = { .name = "qhm_mnoc_cfg", - .id = SC7180_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qxm_camnoc_hf0 = { .name = "qxm_camnoc_hf0", - .id = SC7180_MASTER_CAMNOC_HF0, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC7180_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_hf1 = { .name = "qxm_camnoc_hf1", - .id = SC7180_MASTER_CAMNOC_HF1, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC7180_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_sf = { .name = "qxm_camnoc_sf", - .id = SC7180_MASTER_CAMNOC_SF, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qxm_mdp0 = { .name = "qxm_mdp0", - .id = SC7180_MASTER_MDP0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC7180_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_rot = { .name = "qxm_rot", - .id = SC7180_MASTER_ROTATOR, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qxm_venus0 = { .name = "qxm_venus0", - .id = SC7180_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qxm_venus_arm9 = { .name = "qxm_venus_arm9", - .id = SC7180_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node amm_npu_sys = { .name = "amm_npu_sys", - .id = SC7180_MASTER_NPU_SYS, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC7180_SLAVE_NPU_COMPUTE_NOC }, + .link_nodes = { &qns_npu_sys }, }; static struct qcom_icc_node qhm_npu_cfg = { .name = "qhm_npu_cfg", - .id = SC7180_MASTER_NPU_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 8, - .links = { SC7180_SLAVE_NPU_CAL_DP0, - SC7180_SLAVE_NPU_CP, - SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, - SC7180_SLAVE_NPU_DPM, - SC7180_SLAVE_ISENSE_CFG, - SC7180_SLAVE_NPU_LLM_CFG, - SC7180_SLAVE_NPU_TCM, - SC7180_SLAVE_SERVICE_NPU_NOC - }, + .link_nodes = { &qhs_cal_dp0, + &qhs_cp, + &qhs_dma_bwmon, + &qhs_dpm, + &qhs_isense, + &qhs_llm, + &qhs_tcm, + &srvc_noc }, }; static struct qcom_icc_node qup_core_master_1 = { .name = "qup_core_master_1", - .id = SC7180_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup_core_slave_1 }, }; static struct qcom_icc_node qup_core_master_2 = { .name = "qup_core_master_2", - .id = SC7180_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_SLAVE_QUP_CORE_1 }, + .link_nodes = { &qup_core_slave_2 }, }; static struct qcom_icc_node qhm_snoc_cfg = { .name = "qhm_snoc_cfg", - .id = SC7180_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SC7180_MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 6, - .links = { SC7180_SLAVE_APPSS, - SC7180_SLAVE_SNOC_CNOC, - SC7180_SLAVE_SNOC_GEM_NOC_SF, - SC7180_SLAVE_IMEM, - SC7180_SLAVE_PIMEM, - SC7180_SLAVE_QDSS_STM - }, + .link_nodes = { &qhs_apss, + &qns_cnoc, + &qns_gemnoc_sf, + &qxs_imem, + &qxs_pimem, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SC7180_MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 7, - .links = { SC7180_SLAVE_APPSS, - SC7180_SLAVE_SNOC_CNOC, - SC7180_SLAVE_SNOC_GEM_NOC_SF, - SC7180_SLAVE_IMEM, - SC7180_SLAVE_PIMEM, - SC7180_SLAVE_QDSS_STM, - SC7180_SLAVE_TCU - }, + .link_nodes = { &qhs_apss, + &qns_cnoc, + &qns_gemnoc_sf, + &qxs_imem, + &qxs_pimem, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc = { .name = "qnm_gemnoc", - .id = SC7180_MASTER_GEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 6, - .links = { SC7180_SLAVE_APPSS, - SC7180_SLAVE_SNOC_CNOC, - SC7180_SLAVE_IMEM, - SC7180_SLAVE_PIMEM, - SC7180_SLAVE_QDSS_STM, - SC7180_SLAVE_TCU - }, + .link_nodes = { &qhs_apss, + &qns_cnoc, + &qxs_imem, + &qxs_pimem, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = SC7180_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SC7180_SLAVE_SNOC_GEM_NOC_GC, - SC7180_SLAVE_IMEM - }, + .link_nodes = { &qns_gemnoc_gc, + &qxs_imem }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SC7180_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7180_MASTER_A1NOC_SNOC }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node srvc_aggre1_noc = { .name = "srvc_aggre1_noc", - .id = SC7180_SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SC7180_SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7180_MASTER_A2NOC_SNOC }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node srvc_aggre2_noc = { .name = "srvc_aggre2_noc", - .id = SC7180_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_camnoc_uncomp = { .name = "qns_camnoc_uncomp", - .id = SC7180_SLAVE_CAMNOC_UNCOMP, .channels = 1, .buswidth = 32, }; static struct qcom_icc_node qns_cdsp_gemnoc = { .name = "qns_cdsp_gemnoc", - .id = SC7180_SLAVE_CDSP_GEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC7180_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_cmpnoc }, }; static struct qcom_icc_node qhs_a1_noc_cfg = { .name = "qhs_a1_noc_cfg", - .id = SC7180_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_MASTER_A1NOC_CFG }, + .link_nodes = { &qhm_a1noc_cfg }, }; static struct qcom_icc_node qhs_a2_noc_cfg = { .name = "qhs_a2_noc_cfg", - .id = SC7180_SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_MASTER_A2NOC_CFG }, + .link_nodes = { &qhm_a2noc_cfg }, }; static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", - .id = SC7180_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ahb2phy2 = { .name = "qhs_ahb2phy2", - .id = SC7180_SLAVE_AHB2PHY_CENTER, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aop = { .name = "qhs_aop", - .id = SC7180_SLAVE_AOP, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SC7180_SLAVE_AOSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_boot_rom = { .name = "qhs_boot_rom", - .id = SC7180_SLAVE_BOOT_ROM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SC7180_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = { .name = "qhs_camera_nrt_throttle_cfg", - .id = SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { .name = "qhs_camera_rt_throttle_cfg", - .id = SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SC7180_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SC7180_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_mx = { .name = "qhs_cpr_mx", - .id = SC7180_SLAVE_RBCPR_MX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SC7180_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dcc_cfg = { .name = "qhs_dcc_cfg", - .id = SC7180_SLAVE_DCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ddrss_cfg = { .name = "qhs_ddrss_cfg", - .id = SC7180_SLAVE_CNOC_DDRSS, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_MASTER_CNOC_DC_NOC }, + .link_nodes = { &qhm_cnoc_dc_noc }, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SC7180_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_display_rt_throttle_cfg = { .name = "qhs_display_rt_throttle_cfg", - .id = SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_display_throttle_cfg = { .name = "qhs_display_throttle_cfg", - .id = SC7180_SLAVE_DISPLAY_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_emmc_cfg = { .name = "qhs_emmc_cfg", - .id = SC7180_SLAVE_EMMC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_glm = { .name = "qhs_glm", - .id = SC7180_SLAVE_GLM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SC7180_SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SC7180_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SC7180_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mnoc_cfg = { .name = "qhs_mnoc_cfg", - .id = SC7180_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qhm_mnoc_cfg }, }; static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", - .id = SC7180_SLAVE_CNOC_MSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_npu_cfg = { .name = "qhs_npu_cfg", - .id = SC7180_SLAVE_NPU_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_MASTER_NPU_NOC_CFG }, + .link_nodes = { &qhm_npu_cfg }, }; static struct qcom_icc_node qhs_npu_dma_throttle_cfg = { .name = "qhs_npu_dma_throttle_cfg", - .id = SC7180_SLAVE_NPU_DMA_BWMON_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_npu_dsp_throttle_cfg = { .name = "qhs_npu_dsp_throttle_cfg", - .id = SC7180_SLAVE_NPU_PROC_BWMON_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SC7180_SLAVE_PDM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SC7180_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SC7180_SLAVE_PRNG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SC7180_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qm_cfg = { .name = "qhs_qm_cfg", - .id = SC7180_SLAVE_QM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qm_mpu_cfg = { .name = "qhs_qm_mpu_cfg", - .id = SC7180_SLAVE_QM_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = SC7180_SLAVE_QSPI_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", - .id = SC7180_SLAVE_QUP_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = SC7180_SLAVE_QUP_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SC7180_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_security = { .name = "qhs_security", - .id = SC7180_SLAVE_SECURITY, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_snoc_cfg = { .name = "qhs_snoc_cfg", - .id = SC7180_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_MASTER_SNOC_CFG }, + .link_nodes = { &qhm_snoc_cfg }, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SC7180_SLAVE_TCSR, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_1 = { .name = "qhs_tlmm_1", - .id = SC7180_SLAVE_TLMM_WEST, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_2 = { .name = "qhs_tlmm_2", - .id = SC7180_SLAVE_TLMM_NORTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_3 = { .name = "qhs_tlmm_3", - .id = SC7180_SLAVE_TLMM_SOUTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SC7180_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3 = { .name = "qhs_usb3", - .id = SC7180_SLAVE_USB3, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SC7180_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_throttle_cfg = { .name = "qhs_venus_throttle_cfg", - .id = SC7180_SLAVE_VENUS_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SC7180_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_cnoc = { .name = "srvc_cnoc", - .id = SC7180_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gemnoc = { .name = "qhs_gemnoc", - .id = SC7180_SLAVE_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7180_MASTER_GEM_NOC_CFG }, + .link_nodes = { &qhm_gemnoc_cfg }, }; static struct qcom_icc_node qhs_llcc = { .name = "qhs_llcc", - .id = SC7180_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { .name = "qhs_mdsp_ms_mpu_cfg", - .id = SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_gem_noc_snoc = { .name = "qns_gem_noc_snoc", - .id = SC7180_SLAVE_GEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_MASTER_GEM_NOC_SNOC }, + .link_nodes = { &qnm_gemnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SC7180_SLAVE_LLCC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7180_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node srvc_gemnoc = { .name = "srvc_gemnoc", - .id = SC7180_SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SC7180_SLAVE_EBI1, .channels = 2, .buswidth = 4, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SC7180_SLAVE_MNOC_HF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC7180_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", - .id = SC7180_SLAVE_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC7180_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SC7180_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cal_dp0 = { .name = "qhs_cal_dp0", - .id = SC7180_SLAVE_NPU_CAL_DP0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cp = { .name = "qhs_cp", - .id = SC7180_SLAVE_NPU_CP, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dma_bwmon = { .name = "qhs_dma_bwmon", - .id = SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dpm = { .name = "qhs_dpm", - .id = SC7180_SLAVE_NPU_DPM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_isense = { .name = "qhs_isense", - .id = SC7180_SLAVE_ISENSE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_llm = { .name = "qhs_llm", - .id = SC7180_SLAVE_NPU_LLM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tcm = { .name = "qhs_tcm", - .id = SC7180_SLAVE_NPU_TCM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_npu_sys = { .name = "qns_npu_sys", - .id = SC7180_SLAVE_NPU_COMPUTE_NOC, .channels = 2, .buswidth = 32, }; static struct qcom_icc_node srvc_noc = { .name = "srvc_noc", - .id = SC7180_SLAVE_SERVICE_NPU_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qup_core_slave_1 = { .name = "qup_core_slave_1", - .id = SC7180_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qup_core_slave_2 = { .name = "qup_core_slave_2", - .id = SC7180_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SC7180_SLAVE_APPSS, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qns_cnoc = { .name = "qns_cnoc", - .id = SC7180_SLAVE_SNOC_CNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_MASTER_SNOC_CNOC }, + .link_nodes = { &qnm_snoc }, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = SC7180_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7180_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SC7180_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7180_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SC7180_SLAVE_IMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = SC7180_SLAVE_PIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SC7180_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SC7180_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SC7180_SLAVE_TCU, .channels = 1, .buswidth = 8, }; @@ -1807,7 +1793,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove_new = qcom_icc_rpmh_remove, + .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sc7180", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sc7180.h b/drivers/interconnect/qcom/sc7180.h deleted file mode 100644 index 2b718922c109..000000000000 --- a/drivers/interconnect/qcom/sc7180.h +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm #define SC7180 interconnect IDs - * - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SC7180_H -#define __DRIVERS_INTERCONNECT_QCOM_SC7180_H - -#define SC7180_MASTER_APPSS_PROC 0 -#define SC7180_MASTER_SYS_TCU 1 -#define SC7180_MASTER_NPU_SYS 2 -/* 3 was used by MASTER_IPA_CORE, now represented as RPMh clock */ -#define SC7180_MASTER_LLCC 4 -#define SC7180_MASTER_A1NOC_CFG 5 -#define SC7180_MASTER_A2NOC_CFG 6 -#define SC7180_MASTER_CNOC_DC_NOC 7 -#define SC7180_MASTER_GEM_NOC_CFG 8 -#define SC7180_MASTER_CNOC_MNOC_CFG 9 -#define SC7180_MASTER_NPU_NOC_CFG 10 -#define SC7180_MASTER_QDSS_BAM 11 -#define SC7180_MASTER_QSPI 12 -#define SC7180_MASTER_QUP_0 13 -#define SC7180_MASTER_QUP_1 14 -#define SC7180_MASTER_SNOC_CFG 15 -#define SC7180_MASTER_A1NOC_SNOC 16 -#define SC7180_MASTER_A2NOC_SNOC 17 -#define SC7180_MASTER_COMPUTE_NOC 18 -#define SC7180_MASTER_GEM_NOC_SNOC 19 -#define SC7180_MASTER_MNOC_HF_MEM_NOC 20 -#define SC7180_MASTER_MNOC_SF_MEM_NOC 21 -#define SC7180_MASTER_NPU 22 -#define SC7180_MASTER_SNOC_CNOC 23 -#define SC7180_MASTER_SNOC_GC_MEM_NOC 24 -#define SC7180_MASTER_SNOC_SF_MEM_NOC 25 -#define SC7180_MASTER_QUP_CORE_0 26 -#define SC7180_MASTER_QUP_CORE_1 27 -#define SC7180_MASTER_CAMNOC_HF0 28 -#define SC7180_MASTER_CAMNOC_HF1 29 -#define SC7180_MASTER_CAMNOC_HF0_UNCOMP 30 -#define SC7180_MASTER_CAMNOC_HF1_UNCOMP 31 -#define SC7180_MASTER_CAMNOC_SF 32 -#define SC7180_MASTER_CAMNOC_SF_UNCOMP 33 -#define SC7180_MASTER_CRYPTO 34 -#define SC7180_MASTER_GFX3D 35 -#define SC7180_MASTER_IPA 36 -#define SC7180_MASTER_MDP0 37 -#define SC7180_MASTER_NPU_PROC 38 -#define SC7180_MASTER_PIMEM 39 -#define SC7180_MASTER_ROTATOR 40 -#define SC7180_MASTER_VIDEO_P0 41 -#define SC7180_MASTER_VIDEO_PROC 42 -#define SC7180_MASTER_QDSS_DAP 43 -#define SC7180_MASTER_QDSS_ETR 44 -#define SC7180_MASTER_SDCC_2 45 -#define SC7180_MASTER_UFS_MEM 46 -#define SC7180_MASTER_USB3 47 -#define SC7180_MASTER_EMMC 48 -#define SC7180_SLAVE_EBI1 49 -/* 50 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SC7180_SLAVE_A1NOC_CFG 51 -#define SC7180_SLAVE_A2NOC_CFG 52 -#define SC7180_SLAVE_AHB2PHY_SOUTH 53 -#define SC7180_SLAVE_AHB2PHY_CENTER 54 -#define SC7180_SLAVE_AOP 55 -#define SC7180_SLAVE_AOSS 56 -#define SC7180_SLAVE_APPSS 57 -#define SC7180_SLAVE_BOOT_ROM 58 -#define SC7180_SLAVE_NPU_CAL_DP0 59 -#define SC7180_SLAVE_CAMERA_CFG 60 -#define SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG 61 -#define SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG 62 -#define SC7180_SLAVE_CLK_CTL 63 -#define SC7180_SLAVE_NPU_CP 64 -#define SC7180_SLAVE_RBCPR_CX_CFG 65 -#define SC7180_SLAVE_RBCPR_MX_CFG 66 -#define SC7180_SLAVE_CRYPTO_0_CFG 67 -#define SC7180_SLAVE_DCC_CFG 68 -#define SC7180_SLAVE_CNOC_DDRSS 69 -#define SC7180_SLAVE_DISPLAY_CFG 70 -#define SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG 71 -#define SC7180_SLAVE_DISPLAY_THROTTLE_CFG 72 -#define SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG 73 -#define SC7180_SLAVE_NPU_DPM 74 -#define SC7180_SLAVE_EMMC_CFG 75 -#define SC7180_SLAVE_GEM_NOC_CFG 76 -#define SC7180_SLAVE_GLM 77 -#define SC7180_SLAVE_GFX3D_CFG 78 -#define SC7180_SLAVE_IMEM_CFG 79 -#define SC7180_SLAVE_IPA_CFG 80 -#define SC7180_SLAVE_ISENSE_CFG 81 -#define SC7180_SLAVE_LLCC_CFG 82 -#define SC7180_SLAVE_NPU_LLM_CFG 83 -#define SC7180_SLAVE_MSS_PROC_MS_MPU_CFG 84 -#define SC7180_SLAVE_CNOC_MNOC_CFG 85 -#define SC7180_SLAVE_CNOC_MSS 86 -#define SC7180_SLAVE_NPU_CFG 87 -#define SC7180_SLAVE_NPU_DMA_BWMON_CFG 88 -#define SC7180_SLAVE_NPU_PROC_BWMON_CFG 89 -#define SC7180_SLAVE_PDM 90 -#define SC7180_SLAVE_PIMEM_CFG 91 -#define SC7180_SLAVE_PRNG 92 -#define SC7180_SLAVE_QDSS_CFG 93 -#define SC7180_SLAVE_QM_CFG 94 -#define SC7180_SLAVE_QM_MPU_CFG 95 -#define SC7180_SLAVE_QSPI_0 96 -#define SC7180_SLAVE_QUP_0 97 -#define SC7180_SLAVE_QUP_1 98 -#define SC7180_SLAVE_SDCC_2 99 -#define SC7180_SLAVE_SECURITY 100 -#define SC7180_SLAVE_SNOC_CFG 101 -#define SC7180_SLAVE_NPU_TCM 102 -#define SC7180_SLAVE_TCSR 103 -#define SC7180_SLAVE_TLMM_WEST 104 -#define SC7180_SLAVE_TLMM_NORTH 105 -#define SC7180_SLAVE_TLMM_SOUTH 106 -#define SC7180_SLAVE_UFS_MEM_CFG 107 -#define SC7180_SLAVE_USB3 108 -#define SC7180_SLAVE_VENUS_CFG 109 -#define SC7180_SLAVE_VENUS_THROTTLE_CFG 110 -#define SC7180_SLAVE_VSENSE_CTRL_CFG 111 -#define SC7180_SLAVE_A1NOC_SNOC 112 -#define SC7180_SLAVE_A2NOC_SNOC 113 -#define SC7180_SLAVE_CAMNOC_UNCOMP 114 -#define SC7180_SLAVE_CDSP_GEM_NOC 115 -#define SC7180_SLAVE_SNOC_CNOC 116 -#define SC7180_SLAVE_GEM_NOC_SNOC 117 -#define SC7180_SLAVE_SNOC_GEM_NOC_GC 118 -#define SC7180_SLAVE_SNOC_GEM_NOC_SF 119 -#define SC7180_SLAVE_LLCC 120 -#define SC7180_SLAVE_MNOC_HF_MEM_NOC 121 -#define SC7180_SLAVE_MNOC_SF_MEM_NOC 122 -#define SC7180_SLAVE_NPU_COMPUTE_NOC 123 -#define SC7180_SLAVE_QUP_CORE_0 124 -#define SC7180_SLAVE_QUP_CORE_1 125 -#define SC7180_SLAVE_IMEM 126 -#define SC7180_SLAVE_PIMEM 127 -#define SC7180_SLAVE_SERVICE_A1NOC 128 -#define SC7180_SLAVE_SERVICE_A2NOC 129 -#define SC7180_SLAVE_SERVICE_CNOC 130 -#define SC7180_SLAVE_SERVICE_GEM_NOC 131 -#define SC7180_SLAVE_SERVICE_MNOC 132 -#define SC7180_SLAVE_SERVICE_NPU_NOC 133 -#define SC7180_SLAVE_SERVICE_SNOC 134 -#define SC7180_SLAVE_QDSS_STM 135 -#define SC7180_SLAVE_TCU 136 - -#endif diff --git a/drivers/interconnect/qcom/sc7280.c b/drivers/interconnect/qcom/sc7280.c index 167971f8e8be..c4cb6443f2d4 100644 --- a/drivers/interconnect/qcom/sc7280.c +++ b/drivers/interconnect/qcom/sc7280.c @@ -15,11 +15,152 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sc7280.h" + +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qnm_a1noc_cfg; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb2; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qnm_a2noc_cfg; +static struct qcom_icc_node qnm_cnoc_datapath; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qnm_cnoc3_cnoc2; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qnm_cnoc2_cnoc3; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node qnm_cnoc_dc_noc; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_cmpnoc; +static struct qcom_icc_node qnm_gemnoc_cfg; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qhm_config_noc; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_mnoc_cfg; +static struct qcom_icc_node qnm_video0; +static struct qcom_icc_node qnm_video_cpu; +static struct qcom_icc_node qxm_camnoc_hf; +static struct qcom_icc_node qxm_camnoc_icp; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qhm_nsp_noc_config; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_snoc_cfg; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_hwkm; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_lpass_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_pka_wrapper_cfg; +static struct qcom_icc_node qhs_pmu_wrapper_cfg; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_security; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb2; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_a1_noc_cfg; +static struct qcom_icc_node qns_a2_noc_cfg; +static struct qcom_icc_node qns_cnoc2_cnoc3; +static struct qcom_icc_node qns_mnoc_cfg; +static struct qcom_icc_node qns_snoc_cfg; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc3_cnoc2; +static struct qcom_icc_node qns_cnoc_a2noc; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qxs_boot_imem; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qns_gemnoc; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qhs_modem_ms_mpu_cfg; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node srvc_even_gemnoc; +static struct qcom_icc_node srvc_odd_gemnoc; +static struct qcom_icc_node srvc_sys_gemnoc; +static struct qcom_icc_node qhs_lpass_core; +static struct qcom_icc_node qhs_lpass_lpi; +static struct qcom_icc_node qhs_lpass_mpu; +static struct qcom_icc_node qhs_lpass_top; +static struct qcom_icc_node srvc_niu_aml_noc; +static struct qcom_icc_node srvc_niu_lpass_agnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node service_nsp_noc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node srvc_snoc; static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = SC7280_MASTER_QSPI_0, .channels = 1, .buswidth = 4, .qosbox = &(const struct qcom_icc_qosbox) { @@ -29,12 +170,11 @@ static struct qcom_icc_node qhm_qspi = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", - .id = SC7280_MASTER_QUP_0, .channels = 1, .buswidth = 4, .qosbox = &(const struct qcom_icc_qosbox) { @@ -44,12 +184,11 @@ static struct qcom_icc_node qhm_qup0 = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = SC7280_MASTER_QUP_1, .channels = 1, .buswidth = 4, .qosbox = &(const struct qcom_icc_qosbox) { @@ -59,21 +198,19 @@ static struct qcom_icc_node qhm_qup1 = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qnm_a1noc_cfg = { .name = "qnm_a1noc_cfg", - .id = SC7280_MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_SLAVE_SERVICE_A1NOC }, + .link_nodes = { &srvc_aggre1_noc }, }; static struct qcom_icc_node xm_sdc1 = { .name = "xm_sdc1", - .id = SC7280_MASTER_SDCC_1, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -83,12 +220,11 @@ static struct qcom_icc_node xm_sdc1 = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SC7280_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -98,12 +234,11 @@ static struct qcom_icc_node xm_sdc2 = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SC7280_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -113,12 +248,11 @@ static struct qcom_icc_node xm_sdc4 = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SC7280_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -128,21 +262,19 @@ static struct qcom_icc_node xm_ufs_mem = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb2 = { .name = "xm_usb2", - .id = SC7280_MASTER_USB2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SC7280_MASTER_USB3_0, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -152,12 +284,11 @@ static struct qcom_icc_node xm_usb3_0 = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SC7280_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .qosbox = &(const struct qcom_icc_qosbox) { @@ -167,21 +298,19 @@ static struct qcom_icc_node qhm_qdss_bam = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_a2noc_cfg = { .name = "qnm_a2noc_cfg", - .id = SC7280_MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_SLAVE_SERVICE_A2NOC }, + .link_nodes = { &srvc_aggre2_noc }, }; static struct qcom_icc_node qnm_cnoc_datapath = { .name = "qnm_cnoc_datapath", - .id = SC7280_MASTER_CNOC_A2NOC, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -191,12 +320,11 @@ static struct qcom_icc_node qnm_cnoc_datapath = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SC7280_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -206,12 +334,11 @@ static struct qcom_icc_node qxm_crypto = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SC7280_MASTER_IPA, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -221,29 +348,27 @@ static struct qcom_icc_node qxm_ipa = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", - .id = SC7280_MASTER_PCIE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", - .id = SC7280_MASTER_PCIE_1, .channels = 1, .buswidth = 8, - .links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC }, + .num_links = 1, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = SC7280_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -253,135 +378,126 @@ static struct qcom_icc_node xm_qdss_etr = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", - .id = SC7280_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { .name = "qup1_core_master", - .id = SC7280_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_SLAVE_QUP_CORE_1 }, + .link_nodes = { &qup1_core_slave }, }; static struct qcom_icc_node qnm_cnoc3_cnoc2 = { .name = "qnm_cnoc3_cnoc2", - .id = SC7280_MASTER_CNOC3_CNOC2, .channels = 1, .buswidth = 8, .num_links = 44, - .links = { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH, - SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL, - SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG, - SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG, - SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG, - SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG, - SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG, - SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG, - SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS, - SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG, - SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM, - SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG, - SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG, - SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0, - SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1, - SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4, - SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR, - SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG, - SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0, - SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG, - SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG, - SC7280_SLAVE_CNOC_MNOC_CFG, SC7280_SLAVE_SNOC_CFG }, + .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_compute_cfg, &qhs_cpr_cx, + &qhs_cpr_mx, &qhs_crypto0_cfg, + &qhs_cx_rdpm, &qhs_dcc_cfg, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_hwkm, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_lpass_cfg, &qhs_mss_cfg, + &qhs_mx_rdpm, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_pdm, + &qhs_pimem_cfg, &qhs_pka_wrapper_cfg, + &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc1, + &qhs_sdc2, &qhs_sdc4, + &qhs_security, &qhs_tcsr, + &qhs_tlmm, &qhs_ufs_mem_cfg, + &qhs_usb2, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qns_a1_noc_cfg, &qns_a2_noc_cfg, + &qns_mnoc_cfg, &qns_snoc_cfg }, }; static struct qcom_icc_node xm_qdss_dap = { .name = "xm_qdss_dap", - .id = SC7280_MASTER_QDSS_DAP, .channels = 1, .buswidth = 8, .num_links = 45, - .links = { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH, - SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL, - SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG, - SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG, - SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG, - SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG, - SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG, - SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG, - SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS, - SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG, - SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM, - SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG, - SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG, - SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0, - SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1, - SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4, - SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR, - SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG, - SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0, - SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG, - SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG, - SC7280_SLAVE_CNOC2_CNOC3, SC7280_SLAVE_CNOC_MNOC_CFG, - SC7280_SLAVE_SNOC_CFG }, + .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_compute_cfg, &qhs_cpr_cx, + &qhs_cpr_mx, &qhs_crypto0_cfg, + &qhs_cx_rdpm, &qhs_dcc_cfg, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_hwkm, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_lpass_cfg, &qhs_mss_cfg, + &qhs_mx_rdpm, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_pdm, + &qhs_pimem_cfg, &qhs_pka_wrapper_cfg, + &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_sdc1, + &qhs_sdc2, &qhs_sdc4, + &qhs_security, &qhs_tcsr, + &qhs_tlmm, &qhs_ufs_mem_cfg, + &qhs_usb2, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qns_a1_noc_cfg, &qns_a2_noc_cfg, + &qns_cnoc2_cnoc3, &qns_mnoc_cfg, + &qns_snoc_cfg }, }; static struct qcom_icc_node qnm_cnoc2_cnoc3 = { .name = "qnm_cnoc2_cnoc3", - .id = SC7280_MASTER_CNOC2_CNOC3, .channels = 1, .buswidth = 8, .num_links = 9, - .links = { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS, - SC7280_SLAVE_CNOC_A2NOC, SC7280_SLAVE_DDRSS_CFG, - SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM, - SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM, - SC7280_SLAVE_TCU }, + .link_nodes = { &qhs_aoss, &qhs_apss, + &qns_cnoc_a2noc, &qns_ddrss_cfg, + &qxs_boot_imem, &qxs_imem, + &qxs_pimem, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", - .id = SC7280_MASTER_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 9, - .links = { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS, - SC7280_SLAVE_CNOC3_CNOC2, SC7280_SLAVE_DDRSS_CFG, - SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM, - SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM, - SC7280_SLAVE_TCU }, + .link_nodes = { &qhs_aoss, &qhs_apss, + &qns_cnoc3_cnoc2, &qns_ddrss_cfg, + &qxs_boot_imem, &qxs_imem, + &qxs_pimem, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = SC7280_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SC7280_SLAVE_PCIE_0, SC7280_SLAVE_PCIE_1 }, + .link_nodes = { &xs_pcie_0, &xs_pcie_1 }, }; static struct qcom_icc_node qnm_cnoc_dc_noc = { .name = "qnm_cnoc_dc_noc", - .id = SC7280_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SC7280_SLAVE_LLCC_CFG, SC7280_SLAVE_GEM_NOC_CFG }, + .link_nodes = { &qhs_llcc, &qns_gemnoc }, }; static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", - .id = SC7280_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -391,12 +507,11 @@ static struct qcom_icc_node alm_gpu_tcu = { .urg_fwd = 0, }, .num_links = 2, - .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", - .id = SC7280_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -406,22 +521,20 @@ static struct qcom_icc_node alm_sys_tcu = { .urg_fwd = 0, }, .num_links = 2, - .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", - .id = SC7280_MASTER_APPSS_PROC, .channels = 1, .buswidth = 32, .num_links = 3, - .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC, - SC7280_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_cmpnoc = { .name = "qnm_cmpnoc", - .id = SC7280_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { @@ -431,23 +544,21 @@ static struct qcom_icc_node qnm_cmpnoc = { .urg_fwd = 1, }, .num_links = 2, - .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_gemnoc_cfg = { .name = "qnm_gemnoc_cfg", - .id = SC7280_MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 5, - .links = { SC7280_SLAVE_MSS_PROC_MS_MPU_CFG, SC7280_SLAVE_MCDMA_MS_MPU_CFG, - SC7280_SLAVE_SERVICE_GEM_NOC_1, SC7280_SLAVE_SERVICE_GEM_NOC_2, - SC7280_SLAVE_SERVICE_GEM_NOC }, + .link_nodes = { &qhs_mdsp_ms_mpu_cfg, &qhs_modem_ms_mpu_cfg, + &srvc_even_gemnoc, &srvc_odd_gemnoc, + &srvc_sys_gemnoc }, }; static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", - .id = SC7280_MASTER_GFX3D, .channels = 2, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { @@ -457,12 +568,11 @@ static struct qcom_icc_node qnm_gpu = { .urg_fwd = 0, }, .num_links = 2, - .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SC7280_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { @@ -472,12 +582,11 @@ static struct qcom_icc_node qnm_mnoc_hf = { .urg_fwd = 1, }, .num_links = 1, - .links = { SC7280_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SC7280_MASTER_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { @@ -487,21 +596,19 @@ static struct qcom_icc_node qnm_mnoc_sf = { .urg_fwd = 1, }, .num_links = 2, - .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = SC7280_MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SC7280_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -511,12 +618,11 @@ static struct qcom_icc_node qnm_snoc_gc = { .urg_fwd = 1, }, .num_links = 1, - .links = { SC7280_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SC7280_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .qosbox = &(const struct qcom_icc_qosbox) { @@ -526,42 +632,38 @@ static struct qcom_icc_node qnm_snoc_sf = { .urg_fwd = 1, }, .num_links = 3, - .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC, - SC7280_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qhm_config_noc = { .name = "qhm_config_noc", - .id = SC7280_MASTER_CNOC_LPASS_AG_NOC, .channels = 1, .buswidth = 4, .num_links = 6, - .links = { SC7280_SLAVE_LPASS_CORE_CFG, SC7280_SLAVE_LPASS_LPI_CFG, - SC7280_SLAVE_LPASS_MPU_CFG, SC7280_SLAVE_LPASS_TOP_CFG, - SC7280_SLAVE_SERVICES_LPASS_AML_NOC, SC7280_SLAVE_SERVICE_LPASS_AG_NOC }, + .link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi, + &qhs_lpass_mpu, &qhs_lpass_top, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SC7280_MASTER_LLCC, .channels = 2, .buswidth = 4, .num_links = 1, - .links = { SC7280_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qnm_mnoc_cfg = { .name = "qnm_mnoc_cfg", - .id = SC7280_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qnm_video0 = { .name = "qnm_video0", - .id = SC7280_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { @@ -571,12 +673,11 @@ static struct qcom_icc_node qnm_video0 = { .urg_fwd = 1, }, .num_links = 1, - .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_cpu = { .name = "qnm_video_cpu", - .id = SC7280_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -586,12 +687,11 @@ static struct qcom_icc_node qnm_video_cpu = { .urg_fwd = 1, }, .num_links = 1, - .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qxm_camnoc_hf = { .name = "qxm_camnoc_hf", - .id = SC7280_MASTER_CAMNOC_HF, .channels = 2, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { @@ -601,12 +701,11 @@ static struct qcom_icc_node qxm_camnoc_hf = { .urg_fwd = 1, }, .num_links = 1, - .links = { SC7280_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_icp = { .name = "qxm_camnoc_icp", - .id = SC7280_MASTER_CAMNOC_ICP, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -616,12 +715,11 @@ static struct qcom_icc_node qxm_camnoc_icp = { .urg_fwd = 1, }, .num_links = 1, - .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qxm_camnoc_sf = { .name = "qxm_camnoc_sf", - .id = SC7280_MASTER_CAMNOC_SF, .channels = 1, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { @@ -631,12 +729,11 @@ static struct qcom_icc_node qxm_camnoc_sf = { .urg_fwd = 1, }, .num_links = 1, - .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qxm_mdp0 = { .name = "qxm_mdp0", - .id = SC7280_MASTER_MDP0, .channels = 1, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { @@ -646,57 +743,51 @@ static struct qcom_icc_node qxm_mdp0 = { .urg_fwd = 1, }, .num_links = 1, - .links = { SC7280_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qhm_nsp_noc_config = { .name = "qhm_nsp_noc_config", - .id = SC7280_MASTER_CDSP_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_SLAVE_SERVICE_NSP_NOC }, + .link_nodes = { &service_nsp_noc }, }; static struct qcom_icc_node qxm_nsp = { .name = "qxm_nsp", - .id = SC7280_MASTER_CDSP_PROC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC7280_SLAVE_CDSP_MEM_NOC }, + .link_nodes = { &qns_nsp_gemnoc }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SC7280_MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7280_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SC7280_MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7280_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_snoc_cfg = { .name = "qnm_snoc_cfg", - .id = SC7280_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = SC7280_MASTER_PIMEM, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -706,12 +797,11 @@ static struct qcom_icc_node qxm_pimem = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SC7280_MASTER_GIC, .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { @@ -721,741 +811,585 @@ static struct qcom_icc_node xm_gic = { .urg_fwd = 0, }, .num_links = 1, - .links = { SC7280_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SC7280_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7280_MASTER_A1NOC_SNOC }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node srvc_aggre1_noc = { .name = "srvc_aggre1_noc", - .id = SC7280_SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SC7280_SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7280_MASTER_A2NOC_SNOC }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qns_pcie_mem_noc = { .name = "qns_pcie_mem_noc", - .id = SC7280_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7280_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node srvc_aggre2_noc = { .name = "srvc_aggre2_noc", - .id = SC7280_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", - .id = SC7280_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup1_core_slave = { .name = "qup1_core_slave", - .id = SC7280_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", - .id = SC7280_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy1 = { .name = "qhs_ahb2phy1", - .id = SC7280_SLAVE_AHB2PHY_NORTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SC7280_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SC7280_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_compute_cfg = { .name = "qhs_compute_cfg", - .id = SC7280_SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_MASTER_CDSP_NOC_CFG }, + .link_nodes = { &qhm_nsp_noc_config }, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SC7280_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mx = { .name = "qhs_cpr_mx", - .id = SC7280_SLAVE_RBCPR_MX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SC7280_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cx_rdpm = { .name = "qhs_cx_rdpm", - .id = SC7280_SLAVE_CX_RDPM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_dcc_cfg = { .name = "qhs_dcc_cfg", - .id = SC7280_SLAVE_DCC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SC7280_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SC7280_SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_hwkm = { .name = "qhs_hwkm", - .id = SC7280_SLAVE_HWKM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SC7280_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SC7280_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", - .id = SC7280_SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_cfg = { .name = "qhs_lpass_cfg", - .id = SC7280_SLAVE_LPASS, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_MASTER_CNOC_LPASS_AG_NOC }, + .link_nodes = { &qhm_config_noc }, }; static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", - .id = SC7280_SLAVE_CNOC_MSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mx_rdpm = { .name = "qhs_mx_rdpm", - .id = SC7280_SLAVE_MX_RDPM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = SC7280_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie1_cfg = { .name = "qhs_pcie1_cfg", - .id = SC7280_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SC7280_SLAVE_PDM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SC7280_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pka_wrapper_cfg = { .name = "qhs_pka_wrapper_cfg", - .id = SC7280_SLAVE_PKA_WRAPPER_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pmu_wrapper_cfg = { .name = "qhs_pmu_wrapper_cfg", - .id = SC7280_SLAVE_PMU_WRAPPER_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SC7280_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = SC7280_SLAVE_QSPI_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", - .id = SC7280_SLAVE_QUP_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = SC7280_SLAVE_QUP_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc1 = { .name = "qhs_sdc1", - .id = SC7280_SLAVE_SDCC_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SC7280_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SC7280_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_security = { .name = "qhs_security", - .id = SC7280_SLAVE_SECURITY, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SC7280_SLAVE_TCSR, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = SC7280_SLAVE_TLMM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SC7280_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb2 = { .name = "qhs_usb2", - .id = SC7280_SLAVE_USB2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SC7280_SLAVE_USB3_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SC7280_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SC7280_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_a1_noc_cfg = { .name = "qns_a1_noc_cfg", - .id = SC7280_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_MASTER_A1NOC_CFG }, + .link_nodes = { &qnm_a1noc_cfg }, }; static struct qcom_icc_node qns_a2_noc_cfg = { .name = "qns_a2_noc_cfg", - .id = SC7280_SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_MASTER_A2NOC_CFG }, + .link_nodes = { &qnm_a2noc_cfg }, }; static struct qcom_icc_node qns_cnoc2_cnoc3 = { .name = "qns_cnoc2_cnoc3", - .id = SC7280_SLAVE_CNOC2_CNOC3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7280_MASTER_CNOC2_CNOC3 }, + .link_nodes = { &qnm_cnoc2_cnoc3 }, }; static struct qcom_icc_node qns_mnoc_cfg = { .name = "qns_mnoc_cfg", - .id = SC7280_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qnm_mnoc_cfg }, }; static struct qcom_icc_node qns_snoc_cfg = { .name = "qns_snoc_cfg", - .id = SC7280_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_MASTER_SNOC_CFG }, + .link_nodes = { &qnm_snoc_cfg }, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SC7280_SLAVE_AOSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SC7280_SLAVE_APPSS, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qns_cnoc3_cnoc2 = { .name = "qns_cnoc3_cnoc2", - .id = SC7280_SLAVE_CNOC3_CNOC2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7280_MASTER_CNOC3_CNOC2 }, + .link_nodes = { &qnm_cnoc3_cnoc2 }, }; static struct qcom_icc_node qns_cnoc_a2noc = { .name = "qns_cnoc_a2noc", - .id = SC7280_SLAVE_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7280_MASTER_CNOC_A2NOC }, + .link_nodes = { &qnm_cnoc_datapath }, }; static struct qcom_icc_node qns_ddrss_cfg = { .name = "qns_ddrss_cfg", - .id = SC7280_SLAVE_DDRSS_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_MASTER_CNOC_DC_NOC }, + .link_nodes = { &qnm_cnoc_dc_noc }, }; static struct qcom_icc_node qxs_boot_imem = { .name = "qxs_boot_imem", - .id = SC7280_SLAVE_BOOT_IMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SC7280_SLAVE_IMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = SC7280_SLAVE_PIMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_0 = { .name = "xs_pcie_0", - .id = SC7280_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_1 = { .name = "xs_pcie_1", - .id = SC7280_SLAVE_PCIE_1, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SC7280_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SC7280_SLAVE_TCU, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_llcc = { .name = "qhs_llcc", - .id = SC7280_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_gemnoc = { .name = "qns_gemnoc", - .id = SC7280_SLAVE_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC7280_MASTER_GEM_NOC_CFG }, + .link_nodes = { &qnm_gemnoc_cfg }, }; static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { .name = "qhs_mdsp_ms_mpu_cfg", - .id = SC7280_SLAVE_MSS_PROC_MS_MPU_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_modem_ms_mpu_cfg = { .name = "qhs_modem_ms_mpu_cfg", - .id = SC7280_SLAVE_MCDMA_MS_MPU_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_gem_noc_cnoc = { .name = "qns_gem_noc_cnoc", - .id = SC7280_SLAVE_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7280_MASTER_GEM_NOC_CNOC }, + .link_nodes = { &qnm_gemnoc_cnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SC7280_SLAVE_LLCC, .channels = 2, .buswidth = 16, .num_links = 1, - .links = { SC7280_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_pcie = { .name = "qns_pcie", - .id = SC7280_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7280_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node srvc_even_gemnoc = { .name = "srvc_even_gemnoc", - .id = SC7280_SLAVE_SERVICE_GEM_NOC_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node srvc_odd_gemnoc = { .name = "srvc_odd_gemnoc", - .id = SC7280_SLAVE_SERVICE_GEM_NOC_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node srvc_sys_gemnoc = { .name = "srvc_sys_gemnoc", - .id = SC7280_SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_core = { .name = "qhs_lpass_core", - .id = SC7280_SLAVE_LPASS_CORE_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_lpi = { .name = "qhs_lpass_lpi", - .id = SC7280_SLAVE_LPASS_LPI_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_mpu = { .name = "qhs_lpass_mpu", - .id = SC7280_SLAVE_LPASS_MPU_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_top = { .name = "qhs_lpass_top", - .id = SC7280_SLAVE_LPASS_TOP_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node srvc_niu_aml_noc = { .name = "srvc_niu_aml_noc", - .id = SC7280_SLAVE_SERVICES_LPASS_AML_NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node srvc_niu_lpass_agnoc = { .name = "srvc_niu_lpass_agnoc", - .id = SC7280_SLAVE_SERVICE_LPASS_AG_NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SC7280_SLAVE_EBI1, .channels = 2, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SC7280_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC7280_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", - .id = SC7280_SLAVE_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC7280_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SC7280_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_nsp_gemnoc = { .name = "qns_nsp_gemnoc", - .id = SC7280_SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC7280_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_cmpnoc }, }; static struct qcom_icc_node service_nsp_noc = { .name = "service_nsp_noc", - .id = SC7280_SLAVE_SERVICE_NSP_NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = SC7280_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC7280_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SC7280_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC7280_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SC7280_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_bcm bcm_acv = { @@ -1691,7 +1625,7 @@ static const struct qcom_icc_desc sc7280_aggre1_noc = { .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), - .qos_clks_required = true, + .qos_requires_clocks = true, }; static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { @@ -1723,7 +1657,7 @@ static const struct qcom_icc_desc sc7280_aggre2_noc = { .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), - .qos_clks_required = true, + .qos_requires_clocks = true, }; static struct qcom_icc_bcm * const clk_virt_bcms[] = { @@ -2111,7 +2045,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove_new = qcom_icc_rpmh_remove, + .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sc7280", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sc7280.h b/drivers/interconnect/qcom/sc7280.h deleted file mode 100644 index 175e400305c5..000000000000 --- a/drivers/interconnect/qcom/sc7280.h +++ /dev/null @@ -1,154 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm #define SC7280 interconnect IDs - * - * Copyright (c) 2021, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SC7280_H -#define __DRIVERS_INTERCONNECT_QCOM_SC7280_H - -#define SC7280_MASTER_GPU_TCU 0 -#define SC7280_MASTER_SYS_TCU 1 -#define SC7280_MASTER_APPSS_PROC 2 -#define SC7280_MASTER_LLCC 3 -#define SC7280_MASTER_CNOC_LPASS_AG_NOC 4 -#define SC7280_MASTER_CDSP_NOC_CFG 5 -#define SC7280_MASTER_QDSS_BAM 6 -#define SC7280_MASTER_QSPI_0 7 -#define SC7280_MASTER_QUP_0 8 -#define SC7280_MASTER_QUP_1 9 -#define SC7280_MASTER_A1NOC_CFG 10 -#define SC7280_MASTER_A2NOC_CFG 11 -#define SC7280_MASTER_A1NOC_SNOC 12 -#define SC7280_MASTER_A2NOC_SNOC 13 -#define SC7280_MASTER_COMPUTE_NOC 14 -#define SC7280_MASTER_CNOC2_CNOC3 15 -#define SC7280_MASTER_CNOC3_CNOC2 16 -#define SC7280_MASTER_CNOC_A2NOC 17 -#define SC7280_MASTER_CNOC_DC_NOC 18 -#define SC7280_MASTER_GEM_NOC_CFG 19 -#define SC7280_MASTER_GEM_NOC_CNOC 20 -#define SC7280_MASTER_GEM_NOC_PCIE_SNOC 21 -#define SC7280_MASTER_GFX3D 22 -#define SC7280_MASTER_CNOC_MNOC_CFG 23 -#define SC7280_MASTER_MNOC_HF_MEM_NOC 24 -#define SC7280_MASTER_MNOC_SF_MEM_NOC 25 -#define SC7280_MASTER_ANOC_PCIE_GEM_NOC 26 -#define SC7280_MASTER_SNOC_CFG 27 -#define SC7280_MASTER_SNOC_GC_MEM_NOC 28 -#define SC7280_MASTER_SNOC_SF_MEM_NOC 29 -#define SC7280_MASTER_VIDEO_P0 30 -#define SC7280_MASTER_VIDEO_PROC 31 -#define SC7280_MASTER_QUP_CORE_0 32 -#define SC7280_MASTER_QUP_CORE_1 33 -#define SC7280_MASTER_CAMNOC_HF 34 -#define SC7280_MASTER_CAMNOC_ICP 35 -#define SC7280_MASTER_CAMNOC_SF 36 -#define SC7280_MASTER_CRYPTO 37 -#define SC7280_MASTER_IPA 38 -#define SC7280_MASTER_MDP0 39 -#define SC7280_MASTER_CDSP_PROC 40 -#define SC7280_MASTER_PIMEM 41 -#define SC7280_MASTER_GIC 42 -#define SC7280_MASTER_PCIE_0 43 -#define SC7280_MASTER_PCIE_1 44 -#define SC7280_MASTER_QDSS_DAP 45 -#define SC7280_MASTER_QDSS_ETR 46 -#define SC7280_MASTER_SDCC_1 47 -#define SC7280_MASTER_SDCC_2 48 -#define SC7280_MASTER_SDCC_4 49 -#define SC7280_MASTER_UFS_MEM 50 -#define SC7280_MASTER_USB2 51 -#define SC7280_MASTER_USB3_0 52 -#define SC7280_SLAVE_EBI1 53 -#define SC7280_SLAVE_AHB2PHY_SOUTH 54 -#define SC7280_SLAVE_AHB2PHY_NORTH 55 -#define SC7280_SLAVE_AOSS 56 -#define SC7280_SLAVE_APPSS 57 -#define SC7280_SLAVE_CAMERA_CFG 58 -#define SC7280_SLAVE_CLK_CTL 59 -#define SC7280_SLAVE_CDSP_CFG 60 -#define SC7280_SLAVE_RBCPR_CX_CFG 61 -#define SC7280_SLAVE_RBCPR_MX_CFG 62 -#define SC7280_SLAVE_CRYPTO_0_CFG 63 -#define SC7280_SLAVE_CX_RDPM 64 -#define SC7280_SLAVE_DCC_CFG 65 -#define SC7280_SLAVE_DISPLAY_CFG 66 -#define SC7280_SLAVE_GFX3D_CFG 67 -#define SC7280_SLAVE_HWKM 68 -#define SC7280_SLAVE_IMEM_CFG 69 -#define SC7280_SLAVE_IPA_CFG 70 -#define SC7280_SLAVE_IPC_ROUTER_CFG 71 -#define SC7280_SLAVE_LLCC_CFG 72 -#define SC7280_SLAVE_LPASS 73 -#define SC7280_SLAVE_LPASS_CORE_CFG 74 -#define SC7280_SLAVE_LPASS_LPI_CFG 75 -#define SC7280_SLAVE_LPASS_MPU_CFG 76 -#define SC7280_SLAVE_LPASS_TOP_CFG 77 -#define SC7280_SLAVE_MSS_PROC_MS_MPU_CFG 78 -#define SC7280_SLAVE_MCDMA_MS_MPU_CFG 79 -#define SC7280_SLAVE_CNOC_MSS 80 -#define SC7280_SLAVE_MX_RDPM 81 -#define SC7280_SLAVE_PCIE_0_CFG 82 -#define SC7280_SLAVE_PCIE_1_CFG 83 -#define SC7280_SLAVE_PDM 84 -#define SC7280_SLAVE_PIMEM_CFG 85 -#define SC7280_SLAVE_PKA_WRAPPER_CFG 86 -#define SC7280_SLAVE_PMU_WRAPPER_CFG 87 -#define SC7280_SLAVE_QDSS_CFG 88 -#define SC7280_SLAVE_QSPI_0 89 -#define SC7280_SLAVE_QUP_0 90 -#define SC7280_SLAVE_QUP_1 91 -#define SC7280_SLAVE_SDCC_1 92 -#define SC7280_SLAVE_SDCC_2 93 -#define SC7280_SLAVE_SDCC_4 94 -#define SC7280_SLAVE_SECURITY 95 -#define SC7280_SLAVE_TCSR 96 -#define SC7280_SLAVE_TLMM 97 -#define SC7280_SLAVE_UFS_MEM_CFG 98 -#define SC7280_SLAVE_USB2 99 -#define SC7280_SLAVE_USB3_0 100 -#define SC7280_SLAVE_VENUS_CFG 101 -#define SC7280_SLAVE_VSENSE_CTRL_CFG 102 -#define SC7280_SLAVE_A1NOC_CFG 103 -#define SC7280_SLAVE_A1NOC_SNOC 104 -#define SC7280_SLAVE_A2NOC_CFG 105 -#define SC7280_SLAVE_A2NOC_SNOC 106 -#define SC7280_SLAVE_CNOC2_CNOC3 107 -#define SC7280_SLAVE_CNOC3_CNOC2 108 -#define SC7280_SLAVE_CNOC_A2NOC 109 -#define SC7280_SLAVE_DDRSS_CFG 110 -#define SC7280_SLAVE_GEM_NOC_CNOC 111 -#define SC7280_SLAVE_GEM_NOC_CFG 112 -#define SC7280_SLAVE_SNOC_GEM_NOC_GC 113 -#define SC7280_SLAVE_SNOC_GEM_NOC_SF 114 -#define SC7280_SLAVE_LLCC 115 -#define SC7280_SLAVE_MNOC_HF_MEM_NOC 116 -#define SC7280_SLAVE_MNOC_SF_MEM_NOC 117 -#define SC7280_SLAVE_CNOC_MNOC_CFG 118 -#define SC7280_SLAVE_CDSP_MEM_NOC 119 -#define SC7280_SLAVE_MEM_NOC_PCIE_SNOC 120 -#define SC7280_SLAVE_ANOC_PCIE_GEM_NOC 121 -#define SC7280_SLAVE_SNOC_CFG 122 -#define SC7280_SLAVE_QUP_CORE_0 123 -#define SC7280_SLAVE_QUP_CORE_1 124 -#define SC7280_SLAVE_BOOT_IMEM 125 -#define SC7280_SLAVE_IMEM 126 -#define SC7280_SLAVE_PIMEM 127 -#define SC7280_SLAVE_SERVICE_NSP_NOC 128 -#define SC7280_SLAVE_SERVICE_A1NOC 129 -#define SC7280_SLAVE_SERVICE_A2NOC 130 -#define SC7280_SLAVE_SERVICE_GEM_NOC_1 131 -#define SC7280_SLAVE_SERVICE_MNOC 132 -#define SC7280_SLAVE_SERVICES_LPASS_AML_NOC 133 -#define SC7280_SLAVE_SERVICE_LPASS_AG_NOC 134 -#define SC7280_SLAVE_SERVICE_GEM_NOC_2 135 -#define SC7280_SLAVE_SERVICE_SNOC 136 -#define SC7280_SLAVE_SERVICE_GEM_NOC 137 -#define SC7280_SLAVE_PCIE_0 138 -#define SC7280_SLAVE_PCIE_1 139 -#define SC7280_SLAVE_QDSS_STM 140 -#define SC7280_SLAVE_TCU 141 - -#endif diff --git a/drivers/interconnect/qcom/sc8180x.c b/drivers/interconnect/qcom/sc8180x.c index 03d626776ba1..c9bf1af54e37 100644 --- a/drivers/interconnect/qcom/sc8180x.c +++ b/drivers/interconnect/qcom/sc8180x.c @@ -14,1331 +14,1331 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sc8180x.h" + +static struct qcom_icc_node mas_qhm_a1noc_cfg; +static struct qcom_icc_node mas_xm_ufs_card; +static struct qcom_icc_node mas_xm_ufs_g4; +static struct qcom_icc_node mas_xm_ufs_mem; +static struct qcom_icc_node mas_xm_usb3_0; +static struct qcom_icc_node mas_xm_usb3_1; +static struct qcom_icc_node mas_xm_usb3_2; +static struct qcom_icc_node mas_qhm_a2noc_cfg; +static struct qcom_icc_node mas_qhm_qdss_bam; +static struct qcom_icc_node mas_qhm_qspi; +static struct qcom_icc_node mas_qhm_qspi1; +static struct qcom_icc_node mas_qhm_qup0; +static struct qcom_icc_node mas_qhm_qup1; +static struct qcom_icc_node mas_qhm_qup2; +static struct qcom_icc_node mas_qhm_sensorss_ahb; +static struct qcom_icc_node mas_qxm_crypto; +static struct qcom_icc_node mas_qxm_ipa; +static struct qcom_icc_node mas_xm_emac; +static struct qcom_icc_node mas_xm_pcie3_0; +static struct qcom_icc_node mas_xm_pcie3_1; +static struct qcom_icc_node mas_xm_pcie3_2; +static struct qcom_icc_node mas_xm_pcie3_3; +static struct qcom_icc_node mas_xm_qdss_etr; +static struct qcom_icc_node mas_xm_sdc2; +static struct qcom_icc_node mas_xm_sdc4; +static struct qcom_icc_node mas_qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node mas_qxm_camnoc_hf1_uncomp; +static struct qcom_icc_node mas_qxm_camnoc_sf_uncomp; +static struct qcom_icc_node mas_qnm_npu; +static struct qcom_icc_node mas_qnm_snoc; +static struct qcom_icc_node mas_qhm_cnoc_dc_noc; +static struct qcom_icc_node mas_acm_apps; +static struct qcom_icc_node mas_acm_gpu_tcu; +static struct qcom_icc_node mas_acm_sys_tcu; +static struct qcom_icc_node mas_qhm_gemnoc_cfg; +static struct qcom_icc_node mas_qnm_cmpnoc; +static struct qcom_icc_node mas_qnm_gpu; +static struct qcom_icc_node mas_qnm_mnoc_hf; +static struct qcom_icc_node mas_qnm_mnoc_sf; +static struct qcom_icc_node mas_qnm_pcie; +static struct qcom_icc_node mas_qnm_snoc_gc; +static struct qcom_icc_node mas_qnm_snoc_sf; +static struct qcom_icc_node mas_qxm_ecc; +static struct qcom_icc_node mas_llcc_mc; +static struct qcom_icc_node mas_qhm_mnoc_cfg; +static struct qcom_icc_node mas_qxm_camnoc_hf0; +static struct qcom_icc_node mas_qxm_camnoc_hf1; +static struct qcom_icc_node mas_qxm_camnoc_sf; +static struct qcom_icc_node mas_qxm_mdp0; +static struct qcom_icc_node mas_qxm_mdp1; +static struct qcom_icc_node mas_qxm_rot; +static struct qcom_icc_node mas_qxm_venus0; +static struct qcom_icc_node mas_qxm_venus1; +static struct qcom_icc_node mas_qxm_venus_arm9; +static struct qcom_icc_node mas_qhm_snoc_cfg; +static struct qcom_icc_node mas_qnm_aggre1_noc; +static struct qcom_icc_node mas_qnm_aggre2_noc; +static struct qcom_icc_node mas_qnm_gemnoc; +static struct qcom_icc_node mas_qxm_pimem; +static struct qcom_icc_node mas_xm_gic; +static struct qcom_icc_node mas_qup_core_0; +static struct qcom_icc_node mas_qup_core_1; +static struct qcom_icc_node mas_qup_core_2; +static struct qcom_icc_node slv_qns_a1noc_snoc; +static struct qcom_icc_node slv_srvc_aggre1_noc; +static struct qcom_icc_node slv_qns_a2noc_snoc; +static struct qcom_icc_node slv_qns_pcie_mem_noc; +static struct qcom_icc_node slv_srvc_aggre2_noc; +static struct qcom_icc_node slv_qns_camnoc_uncomp; +static struct qcom_icc_node slv_qns_cdsp_mem_noc; +static struct qcom_icc_node slv_qhs_a1_noc_cfg; +static struct qcom_icc_node slv_qhs_a2_noc_cfg; +static struct qcom_icc_node slv_qhs_ahb2phy_refgen_center; +static struct qcom_icc_node slv_qhs_ahb2phy_refgen_east; +static struct qcom_icc_node slv_qhs_ahb2phy_refgen_west; +static struct qcom_icc_node slv_qhs_ahb2phy_south; +static struct qcom_icc_node slv_qhs_aop; +static struct qcom_icc_node slv_qhs_aoss; +static struct qcom_icc_node slv_qhs_camera_cfg; +static struct qcom_icc_node slv_qhs_clk_ctl; +static struct qcom_icc_node slv_qhs_compute_dsp; +static struct qcom_icc_node slv_qhs_cpr_cx; +static struct qcom_icc_node slv_qhs_cpr_mmcx; +static struct qcom_icc_node slv_qhs_cpr_mx; +static struct qcom_icc_node slv_qhs_crypto0_cfg; +static struct qcom_icc_node slv_qhs_ddrss_cfg; +static struct qcom_icc_node slv_qhs_display_cfg; +static struct qcom_icc_node slv_qhs_emac_cfg; +static struct qcom_icc_node slv_qhs_glm; +static struct qcom_icc_node slv_qhs_gpuss_cfg; +static struct qcom_icc_node slv_qhs_imem_cfg; +static struct qcom_icc_node slv_qhs_ipa; +static struct qcom_icc_node slv_qhs_mnoc_cfg; +static struct qcom_icc_node slv_qhs_npu_cfg; +static struct qcom_icc_node slv_qhs_pcie0_cfg; +static struct qcom_icc_node slv_qhs_pcie1_cfg; +static struct qcom_icc_node slv_qhs_pcie2_cfg; +static struct qcom_icc_node slv_qhs_pcie3_cfg; +static struct qcom_icc_node slv_qhs_pdm; +static struct qcom_icc_node slv_qhs_pimem_cfg; +static struct qcom_icc_node slv_qhs_prng; +static struct qcom_icc_node slv_qhs_qdss_cfg; +static struct qcom_icc_node slv_qhs_qspi_0; +static struct qcom_icc_node slv_qhs_qspi_1; +static struct qcom_icc_node slv_qhs_qupv3_east0; +static struct qcom_icc_node slv_qhs_qupv3_east1; +static struct qcom_icc_node slv_qhs_qupv3_west; +static struct qcom_icc_node slv_qhs_sdc2; +static struct qcom_icc_node slv_qhs_sdc4; +static struct qcom_icc_node slv_qhs_security; +static struct qcom_icc_node slv_qhs_snoc_cfg; +static struct qcom_icc_node slv_qhs_spss_cfg; +static struct qcom_icc_node slv_qhs_tcsr; +static struct qcom_icc_node slv_qhs_tlmm_east; +static struct qcom_icc_node slv_qhs_tlmm_south; +static struct qcom_icc_node slv_qhs_tlmm_west; +static struct qcom_icc_node slv_qhs_tsif; +static struct qcom_icc_node slv_qhs_ufs_card_cfg; +static struct qcom_icc_node slv_qhs_ufs_mem0_cfg; +static struct qcom_icc_node slv_qhs_ufs_mem1_cfg; +static struct qcom_icc_node slv_qhs_usb3_0; +static struct qcom_icc_node slv_qhs_usb3_1; +static struct qcom_icc_node slv_qhs_usb3_2; +static struct qcom_icc_node slv_qhs_venus_cfg; +static struct qcom_icc_node slv_qhs_vsense_ctrl_cfg; +static struct qcom_icc_node slv_srvc_cnoc; +static struct qcom_icc_node slv_qhs_gemnoc; +static struct qcom_icc_node slv_qhs_llcc; +static struct qcom_icc_node slv_qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node slv_qns_ecc; +static struct qcom_icc_node slv_qns_gem_noc_snoc; +static struct qcom_icc_node slv_qns_llcc; +static struct qcom_icc_node slv_srvc_gemnoc; +static struct qcom_icc_node slv_srvc_gemnoc1; +static struct qcom_icc_node slv_ebi; +static struct qcom_icc_node slv_qns2_mem_noc; +static struct qcom_icc_node slv_qns_mem_noc_hf; +static struct qcom_icc_node slv_srvc_mnoc; +static struct qcom_icc_node slv_qhs_apss; +static struct qcom_icc_node slv_qns_cnoc; +static struct qcom_icc_node slv_qns_gemnoc_gc; +static struct qcom_icc_node slv_qns_gemnoc_sf; +static struct qcom_icc_node slv_qxs_imem; +static struct qcom_icc_node slv_qxs_pimem; +static struct qcom_icc_node slv_srvc_snoc; +static struct qcom_icc_node slv_xs_pcie_0; +static struct qcom_icc_node slv_xs_pcie_1; +static struct qcom_icc_node slv_xs_pcie_2; +static struct qcom_icc_node slv_xs_pcie_3; +static struct qcom_icc_node slv_xs_qdss_stm; +static struct qcom_icc_node slv_xs_sys_tcu_cfg; +static struct qcom_icc_node slv_qup_core_0; +static struct qcom_icc_node slv_qup_core_1; +static struct qcom_icc_node slv_qup_core_2; static struct qcom_icc_node mas_qhm_a1noc_cfg = { .name = "mas_qhm_a1noc_cfg", - .id = SC8180X_MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_SLAVE_SERVICE_A1NOC } + .link_nodes = { &slv_srvc_aggre1_noc }, }; static struct qcom_icc_node mas_xm_ufs_card = { .name = "mas_xm_ufs_card", - .id = SC8180X_MASTER_UFS_CARD, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_A1NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a1noc_snoc }, }; static struct qcom_icc_node mas_xm_ufs_g4 = { .name = "mas_xm_ufs_g4", - .id = SC8180X_MASTER_UFS_GEN4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_A1NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a1noc_snoc }, }; static struct qcom_icc_node mas_xm_ufs_mem = { .name = "mas_xm_ufs_mem", - .id = SC8180X_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_A1NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a1noc_snoc }, }; static struct qcom_icc_node mas_xm_usb3_0 = { .name = "mas_xm_usb3_0", - .id = SC8180X_MASTER_USB3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_A1NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a1noc_snoc }, }; static struct qcom_icc_node mas_xm_usb3_1 = { .name = "mas_xm_usb3_1", - .id = SC8180X_MASTER_USB3_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_A1NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a1noc_snoc }, }; static struct qcom_icc_node mas_xm_usb3_2 = { .name = "mas_xm_usb3_2", - .id = SC8180X_MASTER_USB3_2, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8180X_A1NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a1noc_snoc }, }; static struct qcom_icc_node mas_qhm_a2noc_cfg = { .name = "mas_qhm_a2noc_cfg", - .id = SC8180X_MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_SLAVE_SERVICE_A2NOC } + .link_nodes = { &slv_srvc_aggre2_noc }, }; static struct qcom_icc_node mas_qhm_qdss_bam = { .name = "mas_qhm_qdss_bam", - .id = SC8180X_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_qhm_qspi = { .name = "mas_qhm_qspi", - .id = SC8180X_MASTER_QSPI_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_qhm_qspi1 = { .name = "mas_qhm_qspi1", - .id = SC8180X_MASTER_QSPI_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_qhm_qup0 = { .name = "mas_qhm_qup0", - .id = SC8180X_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_qhm_qup1 = { .name = "mas_qhm_qup1", - .id = SC8180X_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_qhm_qup2 = { .name = "mas_qhm_qup2", - .id = SC8180X_MASTER_QUP_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_qhm_sensorss_ahb = { .name = "mas_qhm_sensorss_ahb", - .id = SC8180X_MASTER_SENSORS_AHB, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_qxm_crypto = { .name = "mas_qxm_crypto", - .id = SC8180X_MASTER_CRYPTO_CORE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_qxm_ipa = { .name = "mas_qxm_ipa", - .id = SC8180X_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_xm_emac = { .name = "mas_xm_emac", - .id = SC8180X_MASTER_EMAC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_xm_pcie3_0 = { .name = "mas_xm_pcie3_0", - .id = SC8180X_MASTER_PCIE, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } + .link_nodes = { &slv_qns_pcie_mem_noc }, }; static struct qcom_icc_node mas_xm_pcie3_1 = { .name = "mas_xm_pcie3_1", - .id = SC8180X_MASTER_PCIE_1, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } + .link_nodes = { &slv_qns_pcie_mem_noc }, }; static struct qcom_icc_node mas_xm_pcie3_2 = { .name = "mas_xm_pcie3_2", - .id = SC8180X_MASTER_PCIE_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } + .link_nodes = { &slv_qns_pcie_mem_noc }, }; static struct qcom_icc_node mas_xm_pcie3_3 = { .name = "mas_xm_pcie3_3", - .id = SC8180X_MASTER_PCIE_3, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } + .link_nodes = { &slv_qns_pcie_mem_noc }, }; static struct qcom_icc_node mas_xm_qdss_etr = { .name = "mas_xm_qdss_etr", - .id = SC8180X_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_xm_sdc2 = { .name = "mas_xm_sdc2", - .id = SC8180X_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_xm_sdc4 = { .name = "mas_xm_sdc4", - .id = SC8180X_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_SLV } + .link_nodes = { &slv_qns_a2noc_snoc }, }; static struct qcom_icc_node mas_qxm_camnoc_hf0_uncomp = { .name = "mas_qxm_camnoc_hf0_uncomp", - .id = SC8180X_MASTER_CAMNOC_HF0_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_CAMNOC_UNCOMP } + .link_nodes = { &slv_qns_camnoc_uncomp }, }; static struct qcom_icc_node mas_qxm_camnoc_hf1_uncomp = { .name = "mas_qxm_camnoc_hf1_uncomp", - .id = SC8180X_MASTER_CAMNOC_HF1_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_CAMNOC_UNCOMP } + .link_nodes = { &slv_qns_camnoc_uncomp }, }; static struct qcom_icc_node mas_qxm_camnoc_sf_uncomp = { .name = "mas_qxm_camnoc_sf_uncomp", - .id = SC8180X_MASTER_CAMNOC_SF_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_CAMNOC_UNCOMP } + .link_nodes = { &slv_qns_camnoc_uncomp }, }; static struct qcom_icc_node mas_qnm_npu = { .name = "mas_qnm_npu", - .id = SC8180X_MASTER_NPU, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_CDSP_MEM_NOC } + .link_nodes = { &slv_qns_cdsp_mem_noc }, }; static struct qcom_icc_node mas_qnm_snoc = { .name = "mas_qnm_snoc", - .id = SC8180X_SNOC_CNOC_MAS, .channels = 1, .buswidth = 8, .num_links = 56, - .links = { SC8180X_SLAVE_TLMM_SOUTH, - SC8180X_SLAVE_CDSP_CFG, - SC8180X_SLAVE_SPSS_CFG, - SC8180X_SLAVE_CAMERA_CFG, - SC8180X_SLAVE_SDCC_4, - SC8180X_SLAVE_AHB2PHY_CENTER, - SC8180X_SLAVE_SDCC_2, - SC8180X_SLAVE_PCIE_2_CFG, - SC8180X_SLAVE_CNOC_MNOC_CFG, - SC8180X_SLAVE_EMAC_CFG, - SC8180X_SLAVE_QSPI_0, - SC8180X_SLAVE_QSPI_1, - SC8180X_SLAVE_TLMM_EAST, - SC8180X_SLAVE_SNOC_CFG, - SC8180X_SLAVE_AHB2PHY_EAST, - SC8180X_SLAVE_GLM, - SC8180X_SLAVE_PDM, - SC8180X_SLAVE_PCIE_1_CFG, - SC8180X_SLAVE_A2NOC_CFG, - SC8180X_SLAVE_QDSS_CFG, - SC8180X_SLAVE_DISPLAY_CFG, - SC8180X_SLAVE_TCSR, - SC8180X_SLAVE_UFS_MEM_0_CFG, - SC8180X_SLAVE_CNOC_DDRSS, - SC8180X_SLAVE_PCIE_0_CFG, - SC8180X_SLAVE_QUP_1, - SC8180X_SLAVE_QUP_2, - SC8180X_SLAVE_NPU_CFG, - SC8180X_SLAVE_CRYPTO_0_CFG, - SC8180X_SLAVE_GRAPHICS_3D_CFG, - SC8180X_SLAVE_VENUS_CFG, - SC8180X_SLAVE_TSIF, - SC8180X_SLAVE_IPA_CFG, - SC8180X_SLAVE_CLK_CTL, - SC8180X_SLAVE_SECURITY, - SC8180X_SLAVE_AOP, - SC8180X_SLAVE_AHB2PHY_WEST, - SC8180X_SLAVE_AHB2PHY_SOUTH, - SC8180X_SLAVE_SERVICE_CNOC, - SC8180X_SLAVE_UFS_CARD_CFG, - SC8180X_SLAVE_USB3_1, - SC8180X_SLAVE_USB3_2, - SC8180X_SLAVE_PCIE_3_CFG, - SC8180X_SLAVE_RBCPR_CX_CFG, - SC8180X_SLAVE_TLMM_WEST, - SC8180X_SLAVE_A1NOC_CFG, - SC8180X_SLAVE_AOSS, - SC8180X_SLAVE_PRNG, - SC8180X_SLAVE_VSENSE_CTRL_CFG, - SC8180X_SLAVE_QUP_0, - SC8180X_SLAVE_USB3, - SC8180X_SLAVE_RBCPR_MMCX_CFG, - SC8180X_SLAVE_PIMEM_CFG, - SC8180X_SLAVE_UFS_MEM_1_CFG, - SC8180X_SLAVE_RBCPR_MX_CFG, - SC8180X_SLAVE_IMEM_CFG } + .link_nodes = { &slv_qhs_tlmm_south, + &slv_qhs_compute_dsp, + &slv_qhs_spss_cfg, + &slv_qhs_camera_cfg, + &slv_qhs_sdc4, + &slv_qhs_ahb2phy_refgen_center, + &slv_qhs_sdc2, + &slv_qhs_pcie2_cfg, + &slv_qhs_mnoc_cfg, + &slv_qhs_emac_cfg, + &slv_qhs_qspi_0, + &slv_qhs_qspi_1, + &slv_qhs_tlmm_east, + &slv_qhs_snoc_cfg, + &slv_qhs_ahb2phy_refgen_east, + &slv_qhs_glm, + &slv_qhs_pdm, + &slv_qhs_pcie1_cfg, + &slv_qhs_a2_noc_cfg, + &slv_qhs_qdss_cfg, + &slv_qhs_display_cfg, + &slv_qhs_tcsr, + &slv_qhs_ufs_mem0_cfg, + &slv_qhs_ddrss_cfg, + &slv_qhs_pcie0_cfg, + &slv_qhs_qupv3_east0, + &slv_qhs_qupv3_east1, + &slv_qhs_npu_cfg, + &slv_qhs_crypto0_cfg, + &slv_qhs_gpuss_cfg, + &slv_qhs_venus_cfg, + &slv_qhs_tsif, + &slv_qhs_ipa, + &slv_qhs_clk_ctl, + &slv_qhs_security, + &slv_qhs_aop, + &slv_qhs_ahb2phy_refgen_west, + &slv_qhs_ahb2phy_south, + &slv_srvc_cnoc, + &slv_qhs_ufs_card_cfg, + &slv_qhs_usb3_1, + &slv_qhs_usb3_2, + &slv_qhs_pcie3_cfg, + &slv_qhs_cpr_cx, + &slv_qhs_tlmm_west, + &slv_qhs_a1_noc_cfg, + &slv_qhs_aoss, + &slv_qhs_prng, + &slv_qhs_vsense_ctrl_cfg, + &slv_qhs_qupv3_west, + &slv_qhs_usb3_0, + &slv_qhs_cpr_mmcx, + &slv_qhs_pimem_cfg, + &slv_qhs_ufs_mem1_cfg, + &slv_qhs_cpr_mx, + &slv_qhs_imem_cfg }, }; static struct qcom_icc_node mas_qhm_cnoc_dc_noc = { .name = "mas_qhm_cnoc_dc_noc", - .id = SC8180X_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SC8180X_SLAVE_LLCC_CFG, - SC8180X_SLAVE_GEM_NOC_CFG } + .link_nodes = { &slv_qhs_llcc, + &slv_qhs_gemnoc }, }; static struct qcom_icc_node mas_acm_apps = { .name = "mas_acm_apps", - .id = SC8180X_MASTER_AMPSS_M0, .channels = 4, .buswidth = 64, .num_links = 3, - .links = { SC8180X_SLAVE_ECC, - SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes = { &slv_qns_ecc, + &slv_qns_llcc, + &slv_qns_gem_noc_snoc }, }; static struct qcom_icc_node mas_acm_gpu_tcu = { .name = "mas_acm_gpu_tcu", - .id = SC8180X_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes = { &slv_qns_llcc, + &slv_qns_gem_noc_snoc }, }; static struct qcom_icc_node mas_acm_sys_tcu = { .name = "mas_acm_sys_tcu", - .id = SC8180X_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes = { &slv_qns_llcc, + &slv_qns_gem_noc_snoc }, }; static struct qcom_icc_node mas_qhm_gemnoc_cfg = { .name = "mas_qhm_gemnoc_cfg", - .id = SC8180X_MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 3, - .links = { SC8180X_SLAVE_SERVICE_GEM_NOC_1, - SC8180X_SLAVE_SERVICE_GEM_NOC, - SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG } + .link_nodes = { &slv_srvc_gemnoc1, + &slv_srvc_gemnoc, + &slv_qhs_mdsp_ms_mpu_cfg }, }; static struct qcom_icc_node mas_qnm_cmpnoc = { .name = "mas_qnm_cmpnoc", - .id = SC8180X_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, .num_links = 3, - .links = { SC8180X_SLAVE_ECC, - SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes = { &slv_qns_ecc, + &slv_qns_llcc, + &slv_qns_gem_noc_snoc }, }; static struct qcom_icc_node mas_qnm_gpu = { .name = "mas_qnm_gpu", - .id = SC8180X_MASTER_GRAPHICS_3D, .channels = 4, .buswidth = 32, .num_links = 2, - .links = { SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes = { &slv_qns_llcc, + &slv_qns_gem_noc_snoc }, }; static struct qcom_icc_node mas_qnm_mnoc_hf = { .name = "mas_qnm_mnoc_hf", - .id = SC8180X_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_LLCC } + .link_nodes = { &slv_qns_llcc }, }; static struct qcom_icc_node mas_qnm_mnoc_sf = { .name = "mas_qnm_mnoc_sf", - .id = SC8180X_MASTER_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 2, - .links = { SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes = { &slv_qns_llcc, + &slv_qns_gem_noc_snoc }, }; static struct qcom_icc_node mas_qnm_pcie = { .name = "mas_qnm_pcie", - .id = SC8180X_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 32, .num_links = 2, - .links = { SC8180X_SLAVE_LLCC, - SC8180X_SLAVE_GEM_NOC_SNOC } + .link_nodes = { &slv_qns_llcc, + &slv_qns_gem_noc_snoc }, }; static struct qcom_icc_node mas_qnm_snoc_gc = { .name = "mas_qnm_snoc_gc", - .id = SC8180X_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_SLAVE_LLCC } + .link_nodes = { &slv_qns_llcc }, }; static struct qcom_icc_node mas_qnm_snoc_sf = { .name = "mas_qnm_snoc_sf", - .id = SC8180X_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_LLCC } + .link_nodes = { &slv_qns_llcc }, }; static struct qcom_icc_node mas_qxm_ecc = { .name = "mas_qxm_ecc", - .id = SC8180X_MASTER_ECC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_LLCC } + .link_nodes = { &slv_qns_llcc }, }; static struct qcom_icc_node mas_llcc_mc = { .name = "mas_llcc_mc", - .id = SC8180X_MASTER_LLCC, .channels = 8, .buswidth = 4, .num_links = 1, - .links = { SC8180X_SLAVE_EBI_CH0 } + .link_nodes = { &slv_ebi }, }; static struct qcom_icc_node mas_qhm_mnoc_cfg = { .name = "mas_qhm_mnoc_cfg", - .id = SC8180X_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_SLAVE_SERVICE_MNOC } + .link_nodes = { &slv_srvc_mnoc }, }; static struct qcom_icc_node mas_qxm_camnoc_hf0 = { .name = "mas_qxm_camnoc_hf0", - .id = SC8180X_MASTER_CAMNOC_HF0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC } + .link_nodes = { &slv_qns_mem_noc_hf }, }; static struct qcom_icc_node mas_qxm_camnoc_hf1 = { .name = "mas_qxm_camnoc_hf1", - .id = SC8180X_MASTER_CAMNOC_HF1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC } + .link_nodes = { &slv_qns_mem_noc_hf }, }; static struct qcom_icc_node mas_qxm_camnoc_sf = { .name = "mas_qxm_camnoc_sf", - .id = SC8180X_MASTER_CAMNOC_SF, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } + .link_nodes = { &slv_qns2_mem_noc }, }; static struct qcom_icc_node mas_qxm_mdp0 = { .name = "mas_qxm_mdp0", - .id = SC8180X_MASTER_MDP_PORT0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC } + .link_nodes = { &slv_qns_mem_noc_hf }, }; static struct qcom_icc_node mas_qxm_mdp1 = { .name = "mas_qxm_mdp1", - .id = SC8180X_MASTER_MDP_PORT1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC } + .link_nodes = { &slv_qns_mem_noc_hf }, }; static struct qcom_icc_node mas_qxm_rot = { .name = "mas_qxm_rot", - .id = SC8180X_MASTER_ROTATOR, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } + .link_nodes = { &slv_qns2_mem_noc }, }; static struct qcom_icc_node mas_qxm_venus0 = { .name = "mas_qxm_venus0", - .id = SC8180X_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } + .link_nodes = { &slv_qns2_mem_noc }, }; static struct qcom_icc_node mas_qxm_venus1 = { .name = "mas_qxm_venus1", - .id = SC8180X_MASTER_VIDEO_P1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } + .link_nodes = { &slv_qns2_mem_noc }, }; static struct qcom_icc_node mas_qxm_venus_arm9 = { .name = "mas_qxm_venus_arm9", - .id = SC8180X_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } + .link_nodes = { &slv_qns2_mem_noc }, }; static struct qcom_icc_node mas_qhm_snoc_cfg = { .name = "mas_qhm_snoc_cfg", - .id = SC8180X_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_SLAVE_SERVICE_SNOC } + .link_nodes = { &slv_srvc_snoc }, }; static struct qcom_icc_node mas_qnm_aggre1_noc = { .name = "mas_qnm_aggre1_noc", - .id = SC8180X_A1NOC_SNOC_MAS, .channels = 1, .buswidth = 32, .num_links = 6, - .links = { SC8180X_SLAVE_SNOC_GEM_NOC_SF, - SC8180X_SLAVE_PIMEM, - SC8180X_SLAVE_OCIMEM, - SC8180X_SLAVE_APPSS, - SC8180X_SNOC_CNOC_SLV, - SC8180X_SLAVE_QDSS_STM } + .link_nodes = { &slv_qns_gemnoc_sf, + &slv_qxs_pimem, + &slv_qxs_imem, + &slv_qhs_apss, + &slv_qns_cnoc, + &slv_xs_qdss_stm }, }; static struct qcom_icc_node mas_qnm_aggre2_noc = { .name = "mas_qnm_aggre2_noc", - .id = SC8180X_A2NOC_SNOC_MAS, .channels = 1, .buswidth = 16, .num_links = 11, - .links = { SC8180X_SLAVE_SNOC_GEM_NOC_SF, - SC8180X_SLAVE_PIMEM, - SC8180X_SLAVE_PCIE_3, - SC8180X_SLAVE_OCIMEM, - SC8180X_SLAVE_APPSS, - SC8180X_SLAVE_PCIE_2, - SC8180X_SNOC_CNOC_SLV, - SC8180X_SLAVE_PCIE_0, - SC8180X_SLAVE_PCIE_1, - SC8180X_SLAVE_TCU, - SC8180X_SLAVE_QDSS_STM } + .link_nodes = { &slv_qns_gemnoc_sf, + &slv_qxs_pimem, + &slv_xs_pcie_3, + &slv_qxs_imem, + &slv_qhs_apss, + &slv_xs_pcie_2, + &slv_qns_cnoc, + &slv_xs_pcie_0, + &slv_xs_pcie_1, + &slv_xs_sys_tcu_cfg, + &slv_xs_qdss_stm }, }; static struct qcom_icc_node mas_qnm_gemnoc = { .name = "mas_qnm_gemnoc", - .id = SC8180X_MASTER_GEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 6, - .links = { SC8180X_SLAVE_PIMEM, - SC8180X_SLAVE_OCIMEM, - SC8180X_SLAVE_APPSS, - SC8180X_SNOC_CNOC_SLV, - SC8180X_SLAVE_TCU, - SC8180X_SLAVE_QDSS_STM } + .link_nodes = { &slv_qxs_pimem, + &slv_qxs_imem, + &slv_qhs_apss, + &slv_qns_cnoc, + &slv_xs_sys_tcu_cfg, + &slv_xs_qdss_stm }, }; static struct qcom_icc_node mas_qxm_pimem = { .name = "mas_qxm_pimem", - .id = SC8180X_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SC8180X_SLAVE_SNOC_GEM_NOC_GC, - SC8180X_SLAVE_OCIMEM } + .link_nodes = { &slv_qns_gemnoc_gc, + &slv_qxs_imem }, }; static struct qcom_icc_node mas_xm_gic = { .name = "mas_xm_gic", - .id = SC8180X_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SC8180X_SLAVE_SNOC_GEM_NOC_GC, - SC8180X_SLAVE_OCIMEM } + .link_nodes = { &slv_qns_gemnoc_gc, + &slv_qxs_imem }, }; static struct qcom_icc_node mas_qup_core_0 = { .name = "mas_qup_core_0", - .id = SC8180X_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_SLAVE_QUP_CORE_0 } + .link_nodes = { &slv_qup_core_0 }, }; static struct qcom_icc_node mas_qup_core_1 = { .name = "mas_qup_core_1", - .id = SC8180X_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_SLAVE_QUP_CORE_1 } + .link_nodes = { &slv_qup_core_1 }, }; static struct qcom_icc_node mas_qup_core_2 = { .name = "mas_qup_core_2", - .id = SC8180X_MASTER_QUP_CORE_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_SLAVE_QUP_CORE_2 } + .link_nodes = { &slv_qup_core_2 }, }; static struct qcom_icc_node slv_qns_a1noc_snoc = { .name = "slv_qns_a1noc_snoc", - .id = SC8180X_A1NOC_SNOC_SLV, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_A1NOC_SNOC_MAS } + .link_nodes = { &mas_qnm_aggre1_noc }, }; static struct qcom_icc_node slv_srvc_aggre1_noc = { .name = "slv_srvc_aggre1_noc", - .id = SC8180X_SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qns_a2noc_snoc = { .name = "slv_qns_a2noc_snoc", - .id = SC8180X_A2NOC_SNOC_SLV, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8180X_A2NOC_SNOC_MAS } + .link_nodes = { &mas_qnm_aggre2_noc }, }; static struct qcom_icc_node slv_qns_pcie_mem_noc = { .name = "slv_qns_pcie_mem_noc", - .id = SC8180X_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_MASTER_GEM_NOC_PCIE_SNOC } + .link_nodes = { &mas_qnm_pcie }, }; static struct qcom_icc_node slv_srvc_aggre2_noc = { .name = "slv_srvc_aggre2_noc", - .id = SC8180X_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qns_camnoc_uncomp = { .name = "slv_qns_camnoc_uncomp", - .id = SC8180X_SLAVE_CAMNOC_UNCOMP, .channels = 1, .buswidth = 32 }; static struct qcom_icc_node slv_qns_cdsp_mem_noc = { .name = "slv_qns_cdsp_mem_noc", - .id = SC8180X_SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC8180X_MASTER_COMPUTE_NOC } + .link_nodes = { &mas_qnm_cmpnoc }, }; static struct qcom_icc_node slv_qhs_a1_noc_cfg = { .name = "slv_qhs_a1_noc_cfg", - .id = SC8180X_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_MASTER_A1NOC_CFG } + .link_nodes = { &mas_qhm_a1noc_cfg }, }; static struct qcom_icc_node slv_qhs_a2_noc_cfg = { .name = "slv_qhs_a2_noc_cfg", - .id = SC8180X_SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_MASTER_A2NOC_CFG } + .link_nodes = { &mas_qhm_a2noc_cfg }, }; static struct qcom_icc_node slv_qhs_ahb2phy_refgen_center = { .name = "slv_qhs_ahb2phy_refgen_center", - .id = SC8180X_SLAVE_AHB2PHY_CENTER, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_ahb2phy_refgen_east = { .name = "slv_qhs_ahb2phy_refgen_east", - .id = SC8180X_SLAVE_AHB2PHY_EAST, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_ahb2phy_refgen_west = { .name = "slv_qhs_ahb2phy_refgen_west", - .id = SC8180X_SLAVE_AHB2PHY_WEST, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_ahb2phy_south = { .name = "slv_qhs_ahb2phy_south", - .id = SC8180X_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_aop = { .name = "slv_qhs_aop", - .id = SC8180X_SLAVE_AOP, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_aoss = { .name = "slv_qhs_aoss", - .id = SC8180X_SLAVE_AOSS, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_camera_cfg = { .name = "slv_qhs_camera_cfg", - .id = SC8180X_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_clk_ctl = { .name = "slv_qhs_clk_ctl", - .id = SC8180X_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_compute_dsp = { .name = "slv_qhs_compute_dsp", - .id = SC8180X_SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_cpr_cx = { .name = "slv_qhs_cpr_cx", - .id = SC8180X_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_cpr_mmcx = { .name = "slv_qhs_cpr_mmcx", - .id = SC8180X_SLAVE_RBCPR_MMCX_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_cpr_mx = { .name = "slv_qhs_cpr_mx", - .id = SC8180X_SLAVE_RBCPR_MX_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_crypto0_cfg = { .name = "slv_qhs_crypto0_cfg", - .id = SC8180X_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_ddrss_cfg = { .name = "slv_qhs_ddrss_cfg", - .id = SC8180X_SLAVE_CNOC_DDRSS, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_MASTER_CNOC_DC_NOC } + .link_nodes = { &mas_qhm_cnoc_dc_noc }, }; static struct qcom_icc_node slv_qhs_display_cfg = { .name = "slv_qhs_display_cfg", - .id = SC8180X_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_emac_cfg = { .name = "slv_qhs_emac_cfg", - .id = SC8180X_SLAVE_EMAC_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_glm = { .name = "slv_qhs_glm", - .id = SC8180X_SLAVE_GLM, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_gpuss_cfg = { .name = "slv_qhs_gpuss_cfg", - .id = SC8180X_SLAVE_GRAPHICS_3D_CFG, .channels = 1, .buswidth = 8 }; static struct qcom_icc_node slv_qhs_imem_cfg = { .name = "slv_qhs_imem_cfg", - .id = SC8180X_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_ipa = { .name = "slv_qhs_ipa", - .id = SC8180X_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_mnoc_cfg = { .name = "slv_qhs_mnoc_cfg", - .id = SC8180X_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_MASTER_CNOC_MNOC_CFG } + .link_nodes = { &mas_qhm_mnoc_cfg }, }; static struct qcom_icc_node slv_qhs_npu_cfg = { .name = "slv_qhs_npu_cfg", - .id = SC8180X_SLAVE_NPU_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_pcie0_cfg = { .name = "slv_qhs_pcie0_cfg", - .id = SC8180X_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_pcie1_cfg = { .name = "slv_qhs_pcie1_cfg", - .id = SC8180X_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_pcie2_cfg = { .name = "slv_qhs_pcie2_cfg", - .id = SC8180X_SLAVE_PCIE_2_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_pcie3_cfg = { .name = "slv_qhs_pcie3_cfg", - .id = SC8180X_SLAVE_PCIE_3_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_pdm = { .name = "slv_qhs_pdm", - .id = SC8180X_SLAVE_PDM, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_pimem_cfg = { .name = "slv_qhs_pimem_cfg", - .id = SC8180X_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_prng = { .name = "slv_qhs_prng", - .id = SC8180X_SLAVE_PRNG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_qdss_cfg = { .name = "slv_qhs_qdss_cfg", - .id = SC8180X_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_qspi_0 = { .name = "slv_qhs_qspi_0", - .id = SC8180X_SLAVE_QSPI_0, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_qspi_1 = { .name = "slv_qhs_qspi_1", - .id = SC8180X_SLAVE_QSPI_1, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_qupv3_east0 = { .name = "slv_qhs_qupv3_east0", - .id = SC8180X_SLAVE_QUP_1, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_qupv3_east1 = { .name = "slv_qhs_qupv3_east1", - .id = SC8180X_SLAVE_QUP_2, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_qupv3_west = { .name = "slv_qhs_qupv3_west", - .id = SC8180X_SLAVE_QUP_0, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_sdc2 = { .name = "slv_qhs_sdc2", - .id = SC8180X_SLAVE_SDCC_2, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_sdc4 = { .name = "slv_qhs_sdc4", - .id = SC8180X_SLAVE_SDCC_4, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_security = { .name = "slv_qhs_security", - .id = SC8180X_SLAVE_SECURITY, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_snoc_cfg = { .name = "slv_qhs_snoc_cfg", - .id = SC8180X_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_MASTER_SNOC_CFG } + .link_nodes = { &mas_qhm_snoc_cfg }, }; static struct qcom_icc_node slv_qhs_spss_cfg = { .name = "slv_qhs_spss_cfg", - .id = SC8180X_SLAVE_SPSS_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_tcsr = { .name = "slv_qhs_tcsr", - .id = SC8180X_SLAVE_TCSR, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_tlmm_east = { .name = "slv_qhs_tlmm_east", - .id = SC8180X_SLAVE_TLMM_EAST, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_tlmm_south = { .name = "slv_qhs_tlmm_south", - .id = SC8180X_SLAVE_TLMM_SOUTH, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_tlmm_west = { .name = "slv_qhs_tlmm_west", - .id = SC8180X_SLAVE_TLMM_WEST, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_tsif = { .name = "slv_qhs_tsif", - .id = SC8180X_SLAVE_TSIF, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_ufs_card_cfg = { .name = "slv_qhs_ufs_card_cfg", - .id = SC8180X_SLAVE_UFS_CARD_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_ufs_mem0_cfg = { .name = "slv_qhs_ufs_mem0_cfg", - .id = SC8180X_SLAVE_UFS_MEM_0_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_ufs_mem1_cfg = { .name = "slv_qhs_ufs_mem1_cfg", - .id = SC8180X_SLAVE_UFS_MEM_1_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_usb3_0 = { .name = "slv_qhs_usb3_0", - .id = SC8180X_SLAVE_USB3, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_usb3_1 = { .name = "slv_qhs_usb3_1", - .id = SC8180X_SLAVE_USB3_1, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_usb3_2 = { .name = "slv_qhs_usb3_2", - .id = SC8180X_SLAVE_USB3_2, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_venus_cfg = { .name = "slv_qhs_venus_cfg", - .id = SC8180X_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_vsense_ctrl_cfg = { .name = "slv_qhs_vsense_ctrl_cfg", - .id = SC8180X_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_srvc_cnoc = { .name = "slv_srvc_cnoc", - .id = SC8180X_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_gemnoc = { .name = "slv_qhs_gemnoc", - .id = SC8180X_SLAVE_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8180X_MASTER_GEM_NOC_CFG } + .link_nodes = { &mas_qhm_gemnoc_cfg }, }; static struct qcom_icc_node slv_qhs_llcc = { .name = "slv_qhs_llcc", - .id = SC8180X_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_mdsp_ms_mpu_cfg = { .name = "slv_qhs_mdsp_ms_mpu_cfg", - .id = SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qns_ecc = { .name = "slv_qns_ecc", - .id = SC8180X_SLAVE_ECC, .channels = 1, .buswidth = 32 }; static struct qcom_icc_node slv_qns_gem_noc_snoc = { .name = "slv_qns_gem_noc_snoc", - .id = SC8180X_SLAVE_GEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_MASTER_GEM_NOC_SNOC } + .link_nodes = { &mas_qnm_gemnoc }, }; static struct qcom_icc_node slv_qns_llcc = { .name = "slv_qns_llcc", - .id = SC8180X_SLAVE_LLCC, .channels = 8, .buswidth = 16, .num_links = 1, - .links = { SC8180X_MASTER_LLCC } + .link_nodes = { &mas_llcc_mc }, }; static struct qcom_icc_node slv_srvc_gemnoc = { .name = "slv_srvc_gemnoc", - .id = SC8180X_SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_srvc_gemnoc1 = { .name = "slv_srvc_gemnoc1", - .id = SC8180X_SLAVE_SERVICE_GEM_NOC_1, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_ebi = { .name = "slv_ebi", - .id = SC8180X_SLAVE_EBI_CH0, .channels = 8, .buswidth = 4 }; static struct qcom_icc_node slv_qns2_mem_noc = { .name = "slv_qns2_mem_noc", - .id = SC8180X_SLAVE_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_MASTER_MNOC_SF_MEM_NOC } + .link_nodes = { &mas_qnm_mnoc_sf }, }; static struct qcom_icc_node slv_qns_mem_noc_hf = { .name = "slv_qns_mem_noc_hf", - .id = SC8180X_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC8180X_MASTER_MNOC_HF_MEM_NOC } + .link_nodes = { &mas_qnm_mnoc_hf }, }; static struct qcom_icc_node slv_srvc_mnoc = { .name = "slv_srvc_mnoc", - .id = SC8180X_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qhs_apss = { .name = "slv_qhs_apss", - .id = SC8180X_SLAVE_APPSS, .channels = 1, .buswidth = 8 }; static struct qcom_icc_node slv_qns_cnoc = { .name = "slv_qns_cnoc", - .id = SC8180X_SNOC_CNOC_SLV, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_SNOC_CNOC_MAS } + .link_nodes = { &mas_qnm_snoc }, }; static struct qcom_icc_node slv_qns_gemnoc_gc = { .name = "slv_qns_gemnoc_gc", - .id = SC8180X_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8180X_MASTER_SNOC_GC_MEM_NOC } + .link_nodes = { &mas_qnm_snoc_gc }, }; static struct qcom_icc_node slv_qns_gemnoc_sf = { .name = "slv_qns_gemnoc_sf", - .id = SC8180X_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8180X_MASTER_SNOC_SF_MEM_NOC } + .link_nodes = { &mas_qnm_snoc_sf }, }; static struct qcom_icc_node slv_qxs_imem = { .name = "slv_qxs_imem", - .id = SC8180X_SLAVE_OCIMEM, .channels = 1, .buswidth = 8 }; static struct qcom_icc_node slv_qxs_pimem = { .name = "slv_qxs_pimem", - .id = SC8180X_SLAVE_PIMEM, .channels = 1, .buswidth = 8 }; static struct qcom_icc_node slv_srvc_snoc = { .name = "slv_srvc_snoc", - .id = SC8180X_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_xs_pcie_0 = { .name = "slv_xs_pcie_0", - .id = SC8180X_SLAVE_PCIE_0, .channels = 1, .buswidth = 8 }; static struct qcom_icc_node slv_xs_pcie_1 = { .name = "slv_xs_pcie_1", - .id = SC8180X_SLAVE_PCIE_1, .channels = 1, .buswidth = 8 }; static struct qcom_icc_node slv_xs_pcie_2 = { .name = "slv_xs_pcie_2", - .id = SC8180X_SLAVE_PCIE_2, .channels = 1, .buswidth = 8 }; static struct qcom_icc_node slv_xs_pcie_3 = { .name = "slv_xs_pcie_3", - .id = SC8180X_SLAVE_PCIE_3, .channels = 1, .buswidth = 8 }; static struct qcom_icc_node slv_xs_qdss_stm = { .name = "slv_xs_qdss_stm", - .id = SC8180X_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_xs_sys_tcu_cfg = { .name = "slv_xs_sys_tcu_cfg", - .id = SC8180X_SLAVE_TCU, .channels = 1, .buswidth = 8 }; static struct qcom_icc_node slv_qup_core_0 = { .name = "slv_qup_core_0", - .id = SC8180X_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qup_core_1 = { .name = "slv_qup_core_1", - .id = SC8180X_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4 }; static struct qcom_icc_node slv_qup_core_2 = { .name = "slv_qup_core_2", - .id = SC8180X_SLAVE_QUP_CORE_2, .channels = 1, .buswidth = 4 }; @@ -1492,34 +1492,40 @@ static struct qcom_icc_bcm bcm_sh3 = { static struct qcom_icc_bcm bcm_sn0 = { .name = "SN0", + .num_nodes = 1, .nodes = { &slv_qns_gemnoc_sf } }; static struct qcom_icc_bcm bcm_sn1 = { .name = "SN1", + .num_nodes = 1, .nodes = { &slv_qxs_imem } }; static struct qcom_icc_bcm bcm_sn2 = { .name = "SN2", .keepalive = true, + .num_nodes = 1, .nodes = { &slv_qns_gemnoc_gc } }; static struct qcom_icc_bcm bcm_co2 = { .name = "CO2", + .num_nodes = 1, .nodes = { &mas_qnm_npu } }; static struct qcom_icc_bcm bcm_sn3 = { .name = "SN3", .keepalive = true, + .num_nodes = 2, .nodes = { &slv_srvc_aggre1_noc, &slv_qns_cnoc } }; static struct qcom_icc_bcm bcm_sn4 = { .name = "SN4", + .num_nodes = 1, .nodes = { &slv_qxs_pimem } }; @@ -1889,7 +1895,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove_new = qcom_icc_rpmh_remove, + .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sc8180x", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sc8180x.h b/drivers/interconnect/qcom/sc8180x.h deleted file mode 100644 index f8d90598335a..000000000000 --- a/drivers/interconnect/qcom/sc8180x.h +++ /dev/null @@ -1,179 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm #define SC8180X interconnect IDs - * - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SC8180X_H -#define __DRIVERS_INTERCONNECT_QCOM_SC8180X_H - -#define SC8180X_MASTER_A1NOC_CFG 1 -#define SC8180X_MASTER_UFS_CARD 2 -#define SC8180X_MASTER_UFS_GEN4 3 -#define SC8180X_MASTER_UFS_MEM 4 -#define SC8180X_MASTER_USB3 5 -#define SC8180X_MASTER_USB3_1 6 -#define SC8180X_MASTER_USB3_2 7 -#define SC8180X_MASTER_A2NOC_CFG 8 -#define SC8180X_MASTER_QDSS_BAM 9 -#define SC8180X_MASTER_QSPI_0 10 -#define SC8180X_MASTER_QSPI_1 11 -#define SC8180X_MASTER_QUP_0 12 -#define SC8180X_MASTER_QUP_1 13 -#define SC8180X_MASTER_QUP_2 14 -#define SC8180X_MASTER_SENSORS_AHB 15 -#define SC8180X_MASTER_CRYPTO_CORE_0 16 -#define SC8180X_MASTER_IPA 17 -#define SC8180X_MASTER_EMAC 18 -#define SC8180X_MASTER_PCIE 19 -#define SC8180X_MASTER_PCIE_1 20 -#define SC8180X_MASTER_PCIE_2 21 -#define SC8180X_MASTER_PCIE_3 22 -#define SC8180X_MASTER_QDSS_ETR 23 -#define SC8180X_MASTER_SDCC_2 24 -#define SC8180X_MASTER_SDCC_4 25 -#define SC8180X_MASTER_CAMNOC_HF0_UNCOMP 26 -#define SC8180X_MASTER_CAMNOC_HF1_UNCOMP 27 -#define SC8180X_MASTER_CAMNOC_SF_UNCOMP 28 -#define SC8180X_MASTER_NPU 29 -#define SC8180X_SNOC_CNOC_MAS 30 -#define SC8180X_MASTER_CNOC_DC_NOC 31 -#define SC8180X_MASTER_AMPSS_M0 32 -#define SC8180X_MASTER_GPU_TCU 33 -#define SC8180X_MASTER_SYS_TCU 34 -#define SC8180X_MASTER_GEM_NOC_CFG 35 -#define SC8180X_MASTER_COMPUTE_NOC 36 -#define SC8180X_MASTER_GRAPHICS_3D 37 -#define SC8180X_MASTER_MNOC_HF_MEM_NOC 38 -#define SC8180X_MASTER_MNOC_SF_MEM_NOC 39 -#define SC8180X_MASTER_GEM_NOC_PCIE_SNOC 40 -#define SC8180X_MASTER_SNOC_GC_MEM_NOC 41 -#define SC8180X_MASTER_SNOC_SF_MEM_NOC 42 -#define SC8180X_MASTER_ECC 43 -/* 44 was used by MASTER_IPA_CORE, now represented as RPMh clock */ -#define SC8180X_MASTER_LLCC 45 -#define SC8180X_MASTER_CNOC_MNOC_CFG 46 -#define SC8180X_MASTER_CAMNOC_HF0 47 -#define SC8180X_MASTER_CAMNOC_HF1 48 -#define SC8180X_MASTER_CAMNOC_SF 49 -#define SC8180X_MASTER_MDP_PORT0 50 -#define SC8180X_MASTER_MDP_PORT1 51 -#define SC8180X_MASTER_ROTATOR 52 -#define SC8180X_MASTER_VIDEO_P0 53 -#define SC8180X_MASTER_VIDEO_P1 54 -#define SC8180X_MASTER_VIDEO_PROC 55 -#define SC8180X_MASTER_SNOC_CFG 56 -#define SC8180X_A1NOC_SNOC_MAS 57 -#define SC8180X_A2NOC_SNOC_MAS 58 -#define SC8180X_MASTER_GEM_NOC_SNOC 59 -#define SC8180X_MASTER_PIMEM 60 -#define SC8180X_MASTER_GIC 61 -#define SC8180X_MASTER_MNOC_HF_MEM_NOC_DISPLAY 62 -#define SC8180X_MASTER_MNOC_SF_MEM_NOC_DISPLAY 63 -#define SC8180X_MASTER_LLCC_DISPLAY 64 -#define SC8180X_MASTER_MDP_PORT0_DISPLAY 65 -#define SC8180X_MASTER_MDP_PORT1_DISPLAY 66 -#define SC8180X_MASTER_ROTATOR_DISPLAY 67 -#define SC8180X_A1NOC_SNOC_SLV 68 -#define SC8180X_SLAVE_SERVICE_A1NOC 69 -#define SC8180X_A2NOC_SNOC_SLV 70 -#define SC8180X_SLAVE_ANOC_PCIE_GEM_NOC 71 -#define SC8180X_SLAVE_SERVICE_A2NOC 72 -#define SC8180X_SLAVE_CAMNOC_UNCOMP 73 -#define SC8180X_SLAVE_CDSP_MEM_NOC 74 -#define SC8180X_SLAVE_A1NOC_CFG 75 -#define SC8180X_SLAVE_A2NOC_CFG 76 -#define SC8180X_SLAVE_AHB2PHY_CENTER 77 -#define SC8180X_SLAVE_AHB2PHY_EAST 78 -#define SC8180X_SLAVE_AHB2PHY_WEST 79 -#define SC8180X_SLAVE_AHB2PHY_SOUTH 80 -#define SC8180X_SLAVE_AOP 81 -#define SC8180X_SLAVE_AOSS 82 -#define SC8180X_SLAVE_CAMERA_CFG 83 -#define SC8180X_SLAVE_CLK_CTL 84 -#define SC8180X_SLAVE_CDSP_CFG 85 -#define SC8180X_SLAVE_RBCPR_CX_CFG 86 -#define SC8180X_SLAVE_RBCPR_MMCX_CFG 87 -#define SC8180X_SLAVE_RBCPR_MX_CFG 88 -#define SC8180X_SLAVE_CRYPTO_0_CFG 89 -#define SC8180X_SLAVE_CNOC_DDRSS 90 -#define SC8180X_SLAVE_DISPLAY_CFG 91 -#define SC8180X_SLAVE_EMAC_CFG 92 -#define SC8180X_SLAVE_GLM 93 -#define SC8180X_SLAVE_GRAPHICS_3D_CFG 94 -#define SC8180X_SLAVE_IMEM_CFG 95 -#define SC8180X_SLAVE_IPA_CFG 96 -#define SC8180X_SLAVE_CNOC_MNOC_CFG 97 -#define SC8180X_SLAVE_NPU_CFG 98 -#define SC8180X_SLAVE_PCIE_0_CFG 99 -#define SC8180X_SLAVE_PCIE_1_CFG 100 -#define SC8180X_SLAVE_PCIE_2_CFG 101 -#define SC8180X_SLAVE_PCIE_3_CFG 102 -#define SC8180X_SLAVE_PDM 103 -#define SC8180X_SLAVE_PIMEM_CFG 104 -#define SC8180X_SLAVE_PRNG 105 -#define SC8180X_SLAVE_QDSS_CFG 106 -#define SC8180X_SLAVE_QSPI_0 107 -#define SC8180X_SLAVE_QSPI_1 108 -#define SC8180X_SLAVE_QUP_1 109 -#define SC8180X_SLAVE_QUP_2 110 -#define SC8180X_SLAVE_QUP_0 111 -#define SC8180X_SLAVE_SDCC_2 112 -#define SC8180X_SLAVE_SDCC_4 113 -#define SC8180X_SLAVE_SECURITY 114 -#define SC8180X_SLAVE_SNOC_CFG 115 -#define SC8180X_SLAVE_SPSS_CFG 116 -#define SC8180X_SLAVE_TCSR 117 -#define SC8180X_SLAVE_TLMM_EAST 118 -#define SC8180X_SLAVE_TLMM_SOUTH 119 -#define SC8180X_SLAVE_TLMM_WEST 120 -#define SC8180X_SLAVE_TSIF 121 -#define SC8180X_SLAVE_UFS_CARD_CFG 122 -#define SC8180X_SLAVE_UFS_MEM_0_CFG 123 -#define SC8180X_SLAVE_UFS_MEM_1_CFG 124 -#define SC8180X_SLAVE_USB3 125 -#define SC8180X_SLAVE_USB3_1 126 -#define SC8180X_SLAVE_USB3_2 127 -#define SC8180X_SLAVE_VENUS_CFG 128 -#define SC8180X_SLAVE_VSENSE_CTRL_CFG 129 -#define SC8180X_SLAVE_SERVICE_CNOC 130 -#define SC8180X_SLAVE_GEM_NOC_CFG 131 -#define SC8180X_SLAVE_LLCC_CFG 132 -#define SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG 133 -#define SC8180X_SLAVE_ECC 134 -#define SC8180X_SLAVE_GEM_NOC_SNOC 135 -#define SC8180X_SLAVE_LLCC 136 -#define SC8180X_SLAVE_SERVICE_GEM_NOC 137 -#define SC8180X_SLAVE_SERVICE_GEM_NOC_1 138 -/* 139 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SC8180X_SLAVE_EBI_CH0 140 -#define SC8180X_SLAVE_MNOC_SF_MEM_NOC 141 -#define SC8180X_SLAVE_MNOC_HF_MEM_NOC 142 -#define SC8180X_SLAVE_SERVICE_MNOC 143 -#define SC8180X_SLAVE_APPSS 144 -#define SC8180X_SNOC_CNOC_SLV 145 -#define SC8180X_SLAVE_SNOC_GEM_NOC_GC 146 -#define SC8180X_SLAVE_SNOC_GEM_NOC_SF 147 -#define SC8180X_SLAVE_OCIMEM 148 -#define SC8180X_SLAVE_PIMEM 149 -#define SC8180X_SLAVE_SERVICE_SNOC 150 -#define SC8180X_SLAVE_PCIE_0 151 -#define SC8180X_SLAVE_PCIE_1 152 -#define SC8180X_SLAVE_PCIE_2 153 -#define SC8180X_SLAVE_PCIE_3 154 -#define SC8180X_SLAVE_QDSS_STM 155 -#define SC8180X_SLAVE_TCU 156 -#define SC8180X_SLAVE_LLCC_DISPLAY 157 -#define SC8180X_SLAVE_EBI_CH0_DISPLAY 158 -#define SC8180X_SLAVE_MNOC_SF_MEM_NOC_DISPLAY 159 -#define SC8180X_SLAVE_MNOC_HF_MEM_NOC_DISPLAY 160 - -#define SC8180X_MASTER_QUP_CORE_0 163 -#define SC8180X_MASTER_QUP_CORE_1 164 -#define SC8180X_MASTER_QUP_CORE_2 165 -#define SC8180X_SLAVE_QUP_CORE_0 166 -#define SC8180X_SLAVE_QUP_CORE_1 167 -#define SC8180X_SLAVE_QUP_CORE_2 168 - -#endif diff --git a/drivers/interconnect/qcom/sc8280xp.c b/drivers/interconnect/qcom/sc8280xp.c index 7acd152bf0dd..ed2161da37bf 100644 --- a/drivers/interconnect/qcom/sc8280xp.c +++ b/drivers/interconnect/qcom/sc8280xp.c @@ -14,1698 +14,1682 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sc8280xp.h" + +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qnm_a1noc_cfg; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_emac_1; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node xm_usb3_1; +static struct qcom_icc_node xm_usb3_mp; +static struct qcom_icc_node xm_usb4_host0; +static struct qcom_icc_node xm_usb4_host1; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qnm_a2noc_cfg; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_sensorss_q6; +static struct qcom_icc_node qxm_sp; +static struct qcom_icc_node xm_emac_0; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node xm_pcie3_2a; +static struct qcom_icc_node xm_pcie3_2b; +static struct qcom_icc_node xm_pcie3_3a; +static struct qcom_icc_node xm_pcie3_3b; +static struct qcom_icc_node xm_pcie3_4; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_ufs_card; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup2_core_master; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node qnm_cnoc_dc_noc; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_pcie_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_cmpnoc0; +static struct qcom_icc_node qnm_cmpnoc1; +static struct qcom_icc_node qnm_gemnoc_cfg; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qhm_config_noc; +static struct qcom_icc_node qxm_lpass_dsp; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_mdp0_0; +static struct qcom_icc_node qnm_mdp0_1; +static struct qcom_icc_node qnm_mdp1_0; +static struct qcom_icc_node qnm_mdp1_1; +static struct qcom_icc_node qnm_mnoc_cfg; +static struct qcom_icc_node qnm_rot_0; +static struct qcom_icc_node qnm_rot_1; +static struct qcom_icc_node qnm_video0; +static struct qcom_icc_node qnm_video1; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qxm_camnoc_icp; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qhm_nsp_noc_config; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node qhm_nspb_noc_config; +static struct qcom_icc_node qxm_nspb; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_aggre_usb_noc; +static struct qcom_icc_node qnm_lpass_noc; +static struct qcom_icc_node qnm_snoc_cfg; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_aggre_usb_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_pcie_gem_noc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup2_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_ahb2phy2; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute0_cfg; +static struct qcom_icc_node qhs_compute1_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_cpr_nspcx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_display0_cfg; +static struct qcom_icc_node qhs_display1_cfg; +static struct qcom_icc_node qhs_emac0_cfg; +static struct qcom_icc_node qhs_emac1_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_hwkm; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_lpass_cfg; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_mxc_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pcie2a_cfg; +static struct qcom_icc_node qhs_pcie2b_cfg; +static struct qcom_icc_node qhs_pcie3a_cfg; +static struct qcom_icc_node qhs_pcie3b_cfg; +static struct qcom_icc_node qhs_pcie4_cfg; +static struct qcom_icc_node qhs_pcie_rsc_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_pka_wrapper_cfg; +static struct qcom_icc_node qhs_pmu_wrapper_cfg; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_security; +static struct qcom_icc_node qhs_smmuv3_cfg; +static struct qcom_icc_node qhs_smss_cfg; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_ufs_card_cfg; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_usb3_1; +static struct qcom_icc_node qhs_usb3_mp; +static struct qcom_icc_node qhs_usb4_host_0; +static struct qcom_icc_node qhs_usb4_host_1; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_r_cfg; +static struct qcom_icc_node qns_a1_noc_cfg; +static struct qcom_icc_node qns_a2_noc_cfg; +static struct qcom_icc_node qns_anoc_pcie_bridge_cfg; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qns_mnoc_cfg; +static struct qcom_icc_node qns_snoc_cfg; +static struct qcom_icc_node qns_snoc_sf_bridge_cfg; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_pcie_2a; +static struct qcom_icc_node xs_pcie_2b; +static struct qcom_icc_node xs_pcie_3a; +static struct qcom_icc_node xs_pcie_3b; +static struct qcom_icc_node xs_pcie_4; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_smss; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qns_gemnoc; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node srvc_even_gemnoc; +static struct qcom_icc_node srvc_odd_gemnoc; +static struct qcom_icc_node srvc_sys_gemnoc; +static struct qcom_icc_node qhs_lpass_core; +static struct qcom_icc_node qhs_lpass_lpi; +static struct qcom_icc_node qhs_lpass_mpu; +static struct qcom_icc_node qhs_lpass_top; +static struct qcom_icc_node qns_sysnoc; +static struct qcom_icc_node srvc_niu_aml_noc; +static struct qcom_icc_node srvc_niu_lpass_agnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node qxs_nsp_xfr; +static struct qcom_icc_node service_nsp_noc; +static struct qcom_icc_node qns_nspb_gemnoc; +static struct qcom_icc_node qxs_nspb_xfr; +static struct qcom_icc_node service_nspb_noc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node srvc_snoc; static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = SC8280XP_MASTER_QSPI_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = SC8280XP_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", - .id = SC8280XP_MASTER_QUP_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qnm_a1noc_cfg = { .name = "qnm_a1noc_cfg", - .id = SC8280XP_MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, - .links = { SC8280XP_SLAVE_SERVICE_A1NOC }, + .num_links = 1, + .link_nodes = { &srvc_aggre1_noc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SC8280XP_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_emac_1 = { .name = "xm_emac_1", - .id = SC8280XP_MASTER_EMAC_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SC8280XP_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SC8280XP_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SC8280XP_MASTER_USB3_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, + .link_nodes = { &qns_aggre_usb_snoc }, }; static struct qcom_icc_node xm_usb3_1 = { .name = "xm_usb3_1", - .id = SC8280XP_MASTER_USB3_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, + .link_nodes = { &qns_aggre_usb_snoc }, }; static struct qcom_icc_node xm_usb3_mp = { .name = "xm_usb3_mp", - .id = SC8280XP_MASTER_USB3_MP, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, + .link_nodes = { &qns_aggre_usb_snoc }, }; static struct qcom_icc_node xm_usb4_host0 = { .name = "xm_usb4_host0", - .id = SC8280XP_MASTER_USB4_0, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, + .link_nodes = { &qns_aggre_usb_snoc }, }; static struct qcom_icc_node xm_usb4_host1 = { .name = "xm_usb4_host1", - .id = SC8280XP_MASTER_USB4_1, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_SLAVE_USB_NOC_SNOC }, + .link_nodes = { &qns_aggre_usb_snoc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SC8280XP_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", - .id = SC8280XP_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_a2noc_cfg = { .name = "qnm_a2noc_cfg", - .id = SC8280XP_MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_SERVICE_A2NOC }, + .link_nodes = { &srvc_aggre2_noc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SC8280XP_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_sensorss_q6 = { .name = "qxm_sensorss_q6", - .id = SC8280XP_MASTER_SENSORS_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_sp = { .name = "qxm_sp", - .id = SC8280XP_MASTER_SP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_emac_0 = { .name = "xm_emac_0", - .id = SC8280XP_MASTER_EMAC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", - .id = SC8280XP_MASTER_PCIE_0, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_gem_noc }, }; static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", - .id = SC8280XP_MASTER_PCIE_1, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_gem_noc }, }; static struct qcom_icc_node xm_pcie3_2a = { .name = "xm_pcie3_2a", - .id = SC8280XP_MASTER_PCIE_2A, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_gem_noc }, }; static struct qcom_icc_node xm_pcie3_2b = { .name = "xm_pcie3_2b", - .id = SC8280XP_MASTER_PCIE_2B, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_gem_noc }, }; static struct qcom_icc_node xm_pcie3_3a = { .name = "xm_pcie3_3a", - .id = SC8280XP_MASTER_PCIE_3A, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_gem_noc }, }; static struct qcom_icc_node xm_pcie3_3b = { .name = "xm_pcie3_3b", - .id = SC8280XP_MASTER_PCIE_3B, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_gem_noc }, }; static struct qcom_icc_node xm_pcie3_4 = { .name = "xm_pcie3_4", - .id = SC8280XP_MASTER_PCIE_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_gem_noc }, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = SC8280XP_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SC8280XP_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_ufs_card = { .name = "xm_ufs_card", - .id = SC8280XP_MASTER_UFS_CARD, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", - .id = SC8280XP_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { .name = "qup1_core_master", - .id = SC8280XP_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_QUP_CORE_1 }, + .link_nodes = { &qup1_core_slave }, }; static struct qcom_icc_node qup2_core_master = { .name = "qup2_core_master", - .id = SC8280XP_MASTER_QUP_CORE_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_QUP_CORE_2 }, + .link_nodes = { &qup2_core_slave }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", - .id = SC8280XP_MASTER_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 76, - .links = { SC8280XP_SLAVE_AHB2PHY_0, - SC8280XP_SLAVE_AHB2PHY_1, - SC8280XP_SLAVE_AHB2PHY_2, - SC8280XP_SLAVE_AOSS, - SC8280XP_SLAVE_APPSS, - SC8280XP_SLAVE_CAMERA_CFG, - SC8280XP_SLAVE_CLK_CTL, - SC8280XP_SLAVE_CDSP_CFG, - SC8280XP_SLAVE_CDSP1_CFG, - SC8280XP_SLAVE_RBCPR_CX_CFG, - SC8280XP_SLAVE_RBCPR_MMCX_CFG, - SC8280XP_SLAVE_RBCPR_MX_CFG, - SC8280XP_SLAVE_CPR_NSPCX, - SC8280XP_SLAVE_CRYPTO_0_CFG, - SC8280XP_SLAVE_CX_RDPM, - SC8280XP_SLAVE_DCC_CFG, - SC8280XP_SLAVE_DISPLAY_CFG, - SC8280XP_SLAVE_DISPLAY1_CFG, - SC8280XP_SLAVE_EMAC_CFG, - SC8280XP_SLAVE_EMAC1_CFG, - SC8280XP_SLAVE_GFX3D_CFG, - SC8280XP_SLAVE_HWKM, - SC8280XP_SLAVE_IMEM_CFG, - SC8280XP_SLAVE_IPA_CFG, - SC8280XP_SLAVE_IPC_ROUTER_CFG, - SC8280XP_SLAVE_LPASS, - SC8280XP_SLAVE_MX_RDPM, - SC8280XP_SLAVE_MXC_RDPM, - SC8280XP_SLAVE_PCIE_0_CFG, - SC8280XP_SLAVE_PCIE_1_CFG, - SC8280XP_SLAVE_PCIE_2A_CFG, - SC8280XP_SLAVE_PCIE_2B_CFG, - SC8280XP_SLAVE_PCIE_3A_CFG, - SC8280XP_SLAVE_PCIE_3B_CFG, - SC8280XP_SLAVE_PCIE_4_CFG, - SC8280XP_SLAVE_PCIE_RSC_CFG, - SC8280XP_SLAVE_PDM, - SC8280XP_SLAVE_PIMEM_CFG, - SC8280XP_SLAVE_PKA_WRAPPER_CFG, - SC8280XP_SLAVE_PMU_WRAPPER_CFG, - SC8280XP_SLAVE_QDSS_CFG, - SC8280XP_SLAVE_QSPI_0, - SC8280XP_SLAVE_QUP_0, - SC8280XP_SLAVE_QUP_1, - SC8280XP_SLAVE_QUP_2, - SC8280XP_SLAVE_SDCC_2, - SC8280XP_SLAVE_SDCC_4, - SC8280XP_SLAVE_SECURITY, - SC8280XP_SLAVE_SMMUV3_CFG, - SC8280XP_SLAVE_SMSS_CFG, - SC8280XP_SLAVE_SPSS_CFG, - SC8280XP_SLAVE_TCSR, - SC8280XP_SLAVE_TLMM, - SC8280XP_SLAVE_UFS_CARD_CFG, - SC8280XP_SLAVE_UFS_MEM_CFG, - SC8280XP_SLAVE_USB3_0, - SC8280XP_SLAVE_USB3_1, - SC8280XP_SLAVE_USB3_MP, - SC8280XP_SLAVE_USB4_0, - SC8280XP_SLAVE_USB4_1, - SC8280XP_SLAVE_VENUS_CFG, - SC8280XP_SLAVE_VSENSE_CTRL_CFG, - SC8280XP_SLAVE_VSENSE_CTRL_R_CFG, - SC8280XP_SLAVE_A1NOC_CFG, - SC8280XP_SLAVE_A2NOC_CFG, - SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG, - SC8280XP_SLAVE_DDRSS_CFG, - SC8280XP_SLAVE_CNOC_MNOC_CFG, - SC8280XP_SLAVE_SNOC_CFG, - SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG, - SC8280XP_SLAVE_IMEM, - SC8280XP_SLAVE_PIMEM, - SC8280XP_SLAVE_SERVICE_CNOC, - SC8280XP_SLAVE_QDSS_STM, - SC8280XP_SLAVE_SMSS, - SC8280XP_SLAVE_TCU - }, + .link_nodes = { &qhs_ahb2phy0, + &qhs_ahb2phy1, + &qhs_ahb2phy2, + &qhs_aoss, + &qhs_apss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute0_cfg, + &qhs_compute1_cfg, + &qhs_cpr_cx, + &qhs_cpr_mmcx, + &qhs_cpr_mx, + &qhs_cpr_nspcx, + &qhs_crypto0_cfg, + &qhs_cx_rdpm, + &qhs_dcc_cfg, + &qhs_display0_cfg, + &qhs_display1_cfg, + &qhs_emac0_cfg, + &qhs_emac1_cfg, + &qhs_gpuss_cfg, + &qhs_hwkm, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_ipc_router, + &qhs_lpass_cfg, + &qhs_mx_rdpm, + &qhs_mxc_rdpm, + &qhs_pcie0_cfg, + &qhs_pcie1_cfg, + &qhs_pcie2a_cfg, + &qhs_pcie2b_cfg, + &qhs_pcie3a_cfg, + &qhs_pcie3b_cfg, + &qhs_pcie4_cfg, + &qhs_pcie_rsc_cfg, + &qhs_pdm, + &qhs_pimem_cfg, + &qhs_pka_wrapper_cfg, + &qhs_pmu_wrapper_cfg, + &qhs_qdss_cfg, + &qhs_qspi, + &qhs_qup0, + &qhs_qup1, + &qhs_qup2, + &qhs_sdc2, + &qhs_sdc4, + &qhs_security, + &qhs_smmuv3_cfg, + &qhs_smss_cfg, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_usb3_mp, + &qhs_usb4_host_0, + &qhs_usb4_host_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qhs_vsense_ctrl_r_cfg, + &qns_a1_noc_cfg, + &qns_a2_noc_cfg, + &qns_anoc_pcie_bridge_cfg, + &qns_ddrss_cfg, + &qns_mnoc_cfg, + &qns_snoc_cfg, + &qns_snoc_sf_bridge_cfg, + &qxs_imem, + &qxs_pimem, + &srvc_cnoc, + &xs_qdss_stm, + &xs_smss, + &xs_sys_tcu_cfg, + NULL }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = SC8280XP_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 16, .num_links = 7, - .links = { SC8280XP_SLAVE_PCIE_0, - SC8280XP_SLAVE_PCIE_1, - SC8280XP_SLAVE_PCIE_2A, - SC8280XP_SLAVE_PCIE_2B, - SC8280XP_SLAVE_PCIE_3A, - SC8280XP_SLAVE_PCIE_3B, - SC8280XP_SLAVE_PCIE_4 - }, + .link_nodes = { &xs_pcie_0, + &xs_pcie_1, + &xs_pcie_2a, + &xs_pcie_2b, + &xs_pcie_3a, + &xs_pcie_3b, + &xs_pcie_4 }, }; static struct qcom_icc_node qnm_cnoc_dc_noc = { .name = "qnm_cnoc_dc_noc", - .id = SC8280XP_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SC8280XP_SLAVE_LLCC_CFG, - SC8280XP_SLAVE_GEM_NOC_CFG - }, + .link_nodes = { &qhs_llcc, + &qns_gemnoc }, }; static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", - .id = SC8280XP_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node alm_pcie_tcu = { .name = "alm_pcie_tcu", - .id = SC8280XP_MASTER_PCIE_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", - .id = SC8280XP_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", - .id = SC8280XP_MASTER_APPSS_PROC, .channels = 2, .buswidth = 32, .num_links = 3, - .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC, - SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_cmpnoc0 = { .name = "qnm_cmpnoc0", - .id = SC8280XP_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node qnm_cmpnoc1 = { .name = "qnm_cmpnoc1", - .id = SC8280XP_MASTER_COMPUTE_NOC_1, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node qnm_gemnoc_cfg = { .name = "qnm_gemnoc_cfg", - .id = SC8280XP_MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 3, - .links = { SC8280XP_SLAVE_SERVICE_GEM_NOC_1, - SC8280XP_SLAVE_SERVICE_GEM_NOC_2, - SC8280XP_SLAVE_SERVICE_GEM_NOC - }, + .link_nodes = { &srvc_even_gemnoc, + &srvc_odd_gemnoc, + &srvc_sys_gemnoc }, }; static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", - .id = SC8280XP_MASTER_GFX3D, .channels = 4, .buswidth = 32, .num_links = 2, - .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SC8280XP_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SC8280XP_SLAVE_LLCC, - SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC - }, + .link_nodes = { &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SC8280XP_MASTER_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = SC8280XP_MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 32, .num_links = 2, - .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SC8280XP_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SC8280XP_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SC8280XP_SLAVE_GEM_NOC_CNOC, - SC8280XP_SLAVE_LLCC, - SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qhm_config_noc = { .name = "qhm_config_noc", - .id = SC8280XP_MASTER_CNOC_LPASS_AG_NOC, .channels = 1, .buswidth = 4, .num_links = 6, - .links = { SC8280XP_SLAVE_LPASS_CORE_CFG, - SC8280XP_SLAVE_LPASS_LPI_CFG, - SC8280XP_SLAVE_LPASS_MPU_CFG, - SC8280XP_SLAVE_LPASS_TOP_CFG, - SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC, - SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC - }, + .link_nodes = { &qhs_lpass_core, + &qhs_lpass_lpi, + &qhs_lpass_mpu, + &qhs_lpass_top, + &srvc_niu_aml_noc, + &srvc_niu_lpass_agnoc }, }; static struct qcom_icc_node qxm_lpass_dsp = { .name = "qxm_lpass_dsp", - .id = SC8280XP_MASTER_LPASS_PROC, .channels = 1, .buswidth = 8, .num_links = 4, - .links = { SC8280XP_SLAVE_LPASS_TOP_CFG, - SC8280XP_SLAVE_LPASS_SNOC, - SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC, - SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC - }, + .link_nodes = { &qhs_lpass_top, + &qns_sysnoc, + &srvc_niu_aml_noc, + &srvc_niu_lpass_agnoc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SC8280XP_MASTER_LLCC, .channels = 8, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qnm_camnoc_hf = { .name = "qnm_camnoc_hf", - .id = SC8280XP_MASTER_CAMNOC_HF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_mdp0_0 = { .name = "qnm_mdp0_0", - .id = SC8280XP_MASTER_MDP0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_mdp0_1 = { .name = "qnm_mdp0_1", - .id = SC8280XP_MASTER_MDP1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_mdp1_0 = { .name = "qnm_mdp1_0", - .id = SC8280XP_MASTER_MDP_CORE1_0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_mdp1_1 = { .name = "qnm_mdp1_1", - .id = SC8280XP_MASTER_MDP_CORE1_1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_mnoc_cfg = { .name = "qnm_mnoc_cfg", - .id = SC8280XP_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qnm_rot_0 = { .name = "qnm_rot_0", - .id = SC8280XP_MASTER_ROTATOR, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_rot_1 = { .name = "qnm_rot_1", - .id = SC8280XP_MASTER_ROTATOR_1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video0 = { .name = "qnm_video0", - .id = SC8280XP_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video1 = { .name = "qnm_video1", - .id = SC8280XP_MASTER_VIDEO_P1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_cvp = { .name = "qnm_video_cvp", - .id = SC8280XP_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qxm_camnoc_icp = { .name = "qxm_camnoc_icp", - .id = SC8280XP_MASTER_CAMNOC_ICP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qxm_camnoc_sf = { .name = "qxm_camnoc_sf", - .id = SC8280XP_MASTER_CAMNOC_SF, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qhm_nsp_noc_config = { .name = "qhm_nsp_noc_config", - .id = SC8280XP_MASTER_CDSP_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_SERVICE_NSP_NOC }, + .link_nodes = { &service_nsp_noc }, }; static struct qcom_icc_node qxm_nsp = { .name = "qxm_nsp", - .id = SC8280XP_MASTER_CDSP_PROC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SC8280XP_SLAVE_CDSP_MEM_NOC, - SC8280XP_SLAVE_NSP_XFR - }, + .link_nodes = { &qns_nsp_gemnoc, + &qxs_nsp_xfr }, }; static struct qcom_icc_node qhm_nspb_noc_config = { .name = "qhm_nspb_noc_config", - .id = SC8280XP_MASTER_CDSPB_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_SERVICE_NSPB_NOC }, + .link_nodes = { &service_nspb_noc }, }; static struct qcom_icc_node qxm_nspb = { .name = "qxm_nspb", - .id = SC8280XP_MASTER_CDSP_PROC_B, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SC8280XP_SLAVE_CDSPB_MEM_NOC, - SC8280XP_SLAVE_NSPB_XFR - }, + .link_nodes = { &qns_nspb_gemnoc, + &qxs_nspb_xfr }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SC8280XP_MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SC8280XP_MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre_usb_noc = { .name = "qnm_aggre_usb_noc", - .id = SC8280XP_MASTER_USB_NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_lpass_noc = { .name = "qnm_lpass_noc", - .id = SC8280XP_MASTER_LPASS_ANOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_snoc_cfg = { .name = "qnm_snoc_cfg", - .id = SC8280XP_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = SC8280XP_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SC8280XP_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SC8280XP_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_MASTER_A1NOC_SNOC }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node qns_aggre_usb_snoc = { .name = "qns_aggre_usb_snoc", - .id = SC8280XP_SLAVE_USB_NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_MASTER_USB_NOC_SNOC }, + .link_nodes = { &qnm_aggre_usb_noc }, }; static struct qcom_icc_node srvc_aggre1_noc = { .name = "srvc_aggre1_noc", - .id = SC8280XP_SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SC8280XP_SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_MASTER_A2NOC_SNOC }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qns_pcie_gem_noc = { .name = "qns_pcie_gem_noc", - .id = SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node srvc_aggre2_noc = { .name = "srvc_aggre2_noc", - .id = SC8280XP_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", - .id = SC8280XP_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qup1_core_slave = { .name = "qup1_core_slave", - .id = SC8280XP_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qup2_core_slave = { .name = "qup2_core_slave", - .id = SC8280XP_SLAVE_QUP_CORE_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", - .id = SC8280XP_SLAVE_AHB2PHY_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ahb2phy1 = { .name = "qhs_ahb2phy1", - .id = SC8280XP_SLAVE_AHB2PHY_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ahb2phy2 = { .name = "qhs_ahb2phy2", - .id = SC8280XP_SLAVE_AHB2PHY_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SC8280XP_SLAVE_AOSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SC8280XP_SLAVE_APPSS, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SC8280XP_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SC8280XP_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_compute0_cfg = { .name = "qhs_compute0_cfg", - .id = SC8280XP_SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_MASTER_CDSP_NOC_CFG }, + .link_nodes = { &qhm_nsp_noc_config }, }; static struct qcom_icc_node qhs_compute1_cfg = { .name = "qhs_compute1_cfg", - .id = SC8280XP_SLAVE_CDSP1_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_MASTER_CDSPB_NOC_CFG }, + .link_nodes = { &qhm_nspb_noc_config }, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SC8280XP_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_mmcx = { .name = "qhs_cpr_mmcx", - .id = SC8280XP_SLAVE_RBCPR_MMCX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_mx = { .name = "qhs_cpr_mx", - .id = SC8280XP_SLAVE_RBCPR_MX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_nspcx = { .name = "qhs_cpr_nspcx", - .id = SC8280XP_SLAVE_CPR_NSPCX, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SC8280XP_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cx_rdpm = { .name = "qhs_cx_rdpm", - .id = SC8280XP_SLAVE_CX_RDPM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dcc_cfg = { .name = "qhs_dcc_cfg", - .id = SC8280XP_SLAVE_DCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_display0_cfg = { .name = "qhs_display0_cfg", - .id = SC8280XP_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_display1_cfg = { .name = "qhs_display1_cfg", - .id = SC8280XP_SLAVE_DISPLAY1_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_emac0_cfg = { .name = "qhs_emac0_cfg", - .id = SC8280XP_SLAVE_EMAC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_emac1_cfg = { .name = "qhs_emac1_cfg", - .id = SC8280XP_SLAVE_EMAC1_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SC8280XP_SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_hwkm = { .name = "qhs_hwkm", - .id = SC8280XP_SLAVE_HWKM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SC8280XP_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SC8280XP_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", - .id = SC8280XP_SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_cfg = { .name = "qhs_lpass_cfg", - .id = SC8280XP_SLAVE_LPASS, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_MASTER_CNOC_LPASS_AG_NOC }, + .link_nodes = { &qhm_config_noc }, }; static struct qcom_icc_node qhs_mx_rdpm = { .name = "qhs_mx_rdpm", - .id = SC8280XP_SLAVE_MX_RDPM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mxc_rdpm = { .name = "qhs_mxc_rdpm", - .id = SC8280XP_SLAVE_MXC_RDPM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = SC8280XP_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie1_cfg = { .name = "qhs_pcie1_cfg", - .id = SC8280XP_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie2a_cfg = { .name = "qhs_pcie2a_cfg", - .id = SC8280XP_SLAVE_PCIE_2A_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie2b_cfg = { .name = "qhs_pcie2b_cfg", - .id = SC8280XP_SLAVE_PCIE_2B_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie3a_cfg = { .name = "qhs_pcie3a_cfg", - .id = SC8280XP_SLAVE_PCIE_3A_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie3b_cfg = { .name = "qhs_pcie3b_cfg", - .id = SC8280XP_SLAVE_PCIE_3B_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie4_cfg = { .name = "qhs_pcie4_cfg", - .id = SC8280XP_SLAVE_PCIE_4_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie_rsc_cfg = { .name = "qhs_pcie_rsc_cfg", - .id = SC8280XP_SLAVE_PCIE_RSC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SC8280XP_SLAVE_PDM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SC8280XP_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pka_wrapper_cfg = { .name = "qhs_pka_wrapper_cfg", - .id = SC8280XP_SLAVE_PKA_WRAPPER_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pmu_wrapper_cfg = { .name = "qhs_pmu_wrapper_cfg", - .id = SC8280XP_SLAVE_PMU_WRAPPER_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SC8280XP_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = SC8280XP_SLAVE_QSPI_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", - .id = SC8280XP_SLAVE_QUP_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = SC8280XP_SLAVE_QUP_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup2 = { .name = "qhs_qup2", - .id = SC8280XP_SLAVE_QUP_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SC8280XP_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SC8280XP_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_security = { .name = "qhs_security", - .id = SC8280XP_SLAVE_SECURITY, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_smmuv3_cfg = { .name = "qhs_smmuv3_cfg", - .id = SC8280XP_SLAVE_SMMUV3_CFG, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_smss_cfg = { .name = "qhs_smss_cfg", - .id = SC8280XP_SLAVE_SMSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_spss_cfg = { .name = "qhs_spss_cfg", - .id = SC8280XP_SLAVE_SPSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SC8280XP_SLAVE_TCSR, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = SC8280XP_SLAVE_TLMM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_card_cfg = { .name = "qhs_ufs_card_cfg", - .id = SC8280XP_SLAVE_UFS_CARD_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SC8280XP_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SC8280XP_SLAVE_USB3_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_1 = { .name = "qhs_usb3_1", - .id = SC8280XP_SLAVE_USB3_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_mp = { .name = "qhs_usb3_mp", - .id = SC8280XP_SLAVE_USB3_MP, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb4_host_0 = { .name = "qhs_usb4_host_0", - .id = SC8280XP_SLAVE_USB4_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb4_host_1 = { .name = "qhs_usb4_host_1", - .id = SC8280XP_SLAVE_USB4_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SC8280XP_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SC8280XP_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_vsense_ctrl_r_cfg = { .name = "qhs_vsense_ctrl_r_cfg", - .id = SC8280XP_SLAVE_VSENSE_CTRL_R_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_a1_noc_cfg = { .name = "qns_a1_noc_cfg", - .id = SC8280XP_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_MASTER_A1NOC_CFG }, + .link_nodes = { &qnm_a1noc_cfg }, }; static struct qcom_icc_node qns_a2_noc_cfg = { .name = "qns_a2_noc_cfg", - .id = SC8280XP_SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_MASTER_A2NOC_CFG }, + .link_nodes = { &qnm_a2noc_cfg }, }; static struct qcom_icc_node qns_anoc_pcie_bridge_cfg = { .name = "qns_anoc_pcie_bridge_cfg", - .id = SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_ddrss_cfg = { .name = "qns_ddrss_cfg", - .id = SC8280XP_SLAVE_DDRSS_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_MASTER_CNOC_DC_NOC }, + .link_nodes = { &qnm_cnoc_dc_noc }, }; static struct qcom_icc_node qns_mnoc_cfg = { .name = "qns_mnoc_cfg", - .id = SC8280XP_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qnm_mnoc_cfg }, }; static struct qcom_icc_node qns_snoc_cfg = { .name = "qns_snoc_cfg", - .id = SC8280XP_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_MASTER_SNOC_CFG }, + .link_nodes = { &qnm_snoc_cfg }, }; static struct qcom_icc_node qns_snoc_sf_bridge_cfg = { .name = "qns_snoc_sf_bridge_cfg", - .id = SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SC8280XP_SLAVE_IMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = SC8280XP_SLAVE_PIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node srvc_cnoc = { .name = "srvc_cnoc", - .id = SC8280XP_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_pcie_0 = { .name = "xs_pcie_0", - .id = SC8280XP_SLAVE_PCIE_0, .channels = 1, .buswidth = 16, }; static struct qcom_icc_node xs_pcie_1 = { .name = "xs_pcie_1", - .id = SC8280XP_SLAVE_PCIE_1, .channels = 1, .buswidth = 16, }; static struct qcom_icc_node xs_pcie_2a = { .name = "xs_pcie_2a", - .id = SC8280XP_SLAVE_PCIE_2A, .channels = 1, .buswidth = 16, }; static struct qcom_icc_node xs_pcie_2b = { .name = "xs_pcie_2b", - .id = SC8280XP_SLAVE_PCIE_2B, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_pcie_3a = { .name = "xs_pcie_3a", - .id = SC8280XP_SLAVE_PCIE_3A, .channels = 1, .buswidth = 16, }; static struct qcom_icc_node xs_pcie_3b = { .name = "xs_pcie_3b", - .id = SC8280XP_SLAVE_PCIE_3B, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_pcie_4 = { .name = "xs_pcie_4", - .id = SC8280XP_SLAVE_PCIE_4, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SC8280XP_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_smss = { .name = "xs_smss", - .id = SC8280XP_SLAVE_SMSS, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SC8280XP_SLAVE_TCU, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_llcc = { .name = "qhs_llcc", - .id = SC8280XP_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_gemnoc = { .name = "qns_gemnoc", - .id = SC8280XP_SLAVE_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SC8280XP_MASTER_GEM_NOC_CFG }, + .link_nodes = { &qnm_gemnoc_cfg }, }; static struct qcom_icc_node qns_gem_noc_cnoc = { .name = "qns_gem_noc_cnoc", - .id = SC8280XP_SLAVE_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_MASTER_GEM_NOC_CNOC }, + .link_nodes = { &qnm_gemnoc_cnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SC8280XP_SLAVE_LLCC, .channels = 8, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_pcie = { .name = "qns_pcie", - .id = SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node srvc_even_gemnoc = { .name = "srvc_even_gemnoc", - .id = SC8280XP_SLAVE_SERVICE_GEM_NOC_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_odd_gemnoc = { .name = "srvc_odd_gemnoc", - .id = SC8280XP_SLAVE_SERVICE_GEM_NOC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_sys_gemnoc = { .name = "srvc_sys_gemnoc", - .id = SC8280XP_SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_core = { .name = "qhs_lpass_core", - .id = SC8280XP_SLAVE_LPASS_CORE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_lpi = { .name = "qhs_lpass_lpi", - .id = SC8280XP_SLAVE_LPASS_LPI_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_mpu = { .name = "qhs_lpass_mpu", - .id = SC8280XP_SLAVE_LPASS_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_top = { .name = "qhs_lpass_top", - .id = SC8280XP_SLAVE_LPASS_TOP_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_sysnoc = { .name = "qns_sysnoc", - .id = SC8280XP_SLAVE_LPASS_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_MASTER_LPASS_ANOC }, + .link_nodes = { &qnm_lpass_noc }, }; static struct qcom_icc_node srvc_niu_aml_noc = { .name = "srvc_niu_aml_noc", - .id = SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_niu_lpass_agnoc = { .name = "srvc_niu_lpass_agnoc", - .id = SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SC8280XP_SLAVE_EBI1, .channels = 8, .buswidth = 4, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SC8280XP_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", - .id = SC8280XP_SLAVE_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SC8280XP_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_nsp_gemnoc = { .name = "qns_nsp_gemnoc", - .id = SC8280XP_SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_cmpnoc0 }, }; static struct qcom_icc_node qxs_nsp_xfr = { .name = "qxs_nsp_xfr", - .id = SC8280XP_SLAVE_NSP_XFR, .channels = 1, .buswidth = 32, }; static struct qcom_icc_node service_nsp_noc = { .name = "service_nsp_noc", - .id = SC8280XP_SLAVE_SERVICE_NSP_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_nspb_gemnoc = { .name = "qns_nspb_gemnoc", - .id = SC8280XP_SLAVE_CDSPB_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SC8280XP_MASTER_COMPUTE_NOC_1 }, + .link_nodes = { &qnm_cmpnoc1 }, }; static struct qcom_icc_node qxs_nspb_xfr = { .name = "qxs_nspb_xfr", - .id = SC8280XP_SLAVE_NSPB_XFR, .channels = 1, .buswidth = 32, }; static struct qcom_icc_node service_nspb_noc = { .name = "service_nspb_noc", - .id = SC8280XP_SLAVE_SERVICE_NSPB_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = SC8280XP_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SC8280XP_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SC8280XP_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SC8280XP_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SC8280XP_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, }; @@ -2391,7 +2375,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove_new = qcom_icc_rpmh_remove, + .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sc8280xp", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sc8280xp.h b/drivers/interconnect/qcom/sc8280xp.h deleted file mode 100644 index c5c410fd5ec3..000000000000 --- a/drivers/interconnect/qcom/sc8280xp.h +++ /dev/null @@ -1,209 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2021, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SC8280XP_H -#define __DRIVERS_INTERCONNECT_QCOM_SC8280XP_H - -#define SC8280XP_MASTER_GPU_TCU 0 -#define SC8280XP_MASTER_PCIE_TCU 1 -#define SC8280XP_MASTER_SYS_TCU 2 -#define SC8280XP_MASTER_APPSS_PROC 3 -/* 4 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SC8280XP_MASTER_LLCC 5 -#define SC8280XP_MASTER_CNOC_LPASS_AG_NOC 6 -#define SC8280XP_MASTER_CDSP_NOC_CFG 7 -#define SC8280XP_MASTER_CDSPB_NOC_CFG 8 -#define SC8280XP_MASTER_QDSS_BAM 9 -#define SC8280XP_MASTER_QSPI_0 10 -#define SC8280XP_MASTER_QUP_0 11 -#define SC8280XP_MASTER_QUP_1 12 -#define SC8280XP_MASTER_QUP_2 13 -#define SC8280XP_MASTER_A1NOC_CFG 14 -#define SC8280XP_MASTER_A2NOC_CFG 15 -#define SC8280XP_MASTER_A1NOC_SNOC 16 -#define SC8280XP_MASTER_A2NOC_SNOC 17 -#define SC8280XP_MASTER_USB_NOC_SNOC 18 -#define SC8280XP_MASTER_CAMNOC_HF 19 -#define SC8280XP_MASTER_COMPUTE_NOC 20 -#define SC8280XP_MASTER_COMPUTE_NOC_1 21 -#define SC8280XP_MASTER_CNOC_DC_NOC 22 -#define SC8280XP_MASTER_GEM_NOC_CFG 23 -#define SC8280XP_MASTER_GEM_NOC_CNOC 24 -#define SC8280XP_MASTER_GEM_NOC_PCIE_SNOC 25 -#define SC8280XP_MASTER_GFX3D 26 -#define SC8280XP_MASTER_LPASS_ANOC 27 -#define SC8280XP_MASTER_MDP0 28 -#define SC8280XP_MASTER_MDP1 29 -#define SC8280XP_MASTER_MDP_CORE1_0 30 -#define SC8280XP_MASTER_MDP_CORE1_1 31 -#define SC8280XP_MASTER_CNOC_MNOC_CFG 32 -#define SC8280XP_MASTER_MNOC_HF_MEM_NOC 33 -#define SC8280XP_MASTER_MNOC_SF_MEM_NOC 34 -#define SC8280XP_MASTER_ANOC_PCIE_GEM_NOC 35 -#define SC8280XP_MASTER_ROTATOR 36 -#define SC8280XP_MASTER_ROTATOR_1 37 -#define SC8280XP_MASTER_SNOC_CFG 38 -#define SC8280XP_MASTER_SNOC_GC_MEM_NOC 39 -#define SC8280XP_MASTER_SNOC_SF_MEM_NOC 40 -#define SC8280XP_MASTER_VIDEO_P0 41 -#define SC8280XP_MASTER_VIDEO_P1 42 -#define SC8280XP_MASTER_VIDEO_PROC 43 -#define SC8280XP_MASTER_QUP_CORE_0 44 -#define SC8280XP_MASTER_QUP_CORE_1 45 -#define SC8280XP_MASTER_QUP_CORE_2 46 -#define SC8280XP_MASTER_CAMNOC_ICP 47 -#define SC8280XP_MASTER_CAMNOC_SF 48 -#define SC8280XP_MASTER_CRYPTO 49 -#define SC8280XP_MASTER_IPA 50 -#define SC8280XP_MASTER_LPASS_PROC 51 -#define SC8280XP_MASTER_CDSP_PROC 52 -#define SC8280XP_MASTER_CDSP_PROC_B 53 -#define SC8280XP_MASTER_PIMEM 54 -#define SC8280XP_MASTER_SENSORS_PROC 55 -#define SC8280XP_MASTER_SP 56 -#define SC8280XP_MASTER_EMAC 57 -#define SC8280XP_MASTER_EMAC_1 58 -#define SC8280XP_MASTER_GIC 59 -#define SC8280XP_MASTER_PCIE_0 60 -#define SC8280XP_MASTER_PCIE_1 61 -#define SC8280XP_MASTER_PCIE_2A 62 -#define SC8280XP_MASTER_PCIE_2B 63 -#define SC8280XP_MASTER_PCIE_3A 64 -#define SC8280XP_MASTER_PCIE_3B 65 -#define SC8280XP_MASTER_PCIE_4 66 -#define SC8280XP_MASTER_QDSS_ETR 67 -#define SC8280XP_MASTER_SDCC_2 68 -#define SC8280XP_MASTER_SDCC_4 69 -#define SC8280XP_MASTER_UFS_CARD 70 -#define SC8280XP_MASTER_UFS_MEM 71 -#define SC8280XP_MASTER_USB3_0 72 -#define SC8280XP_MASTER_USB3_1 73 -#define SC8280XP_MASTER_USB3_MP 74 -#define SC8280XP_MASTER_USB4_0 75 -#define SC8280XP_MASTER_USB4_1 76 -#define SC8280XP_SLAVE_EBI1 512 -/* 513 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SC8280XP_SLAVE_AHB2PHY_0 514 -#define SC8280XP_SLAVE_AHB2PHY_1 515 -#define SC8280XP_SLAVE_AHB2PHY_2 516 -#define SC8280XP_SLAVE_AOSS 517 -#define SC8280XP_SLAVE_APPSS 518 -#define SC8280XP_SLAVE_CAMERA_CFG 519 -#define SC8280XP_SLAVE_CLK_CTL 520 -#define SC8280XP_SLAVE_CDSP_CFG 521 -#define SC8280XP_SLAVE_CDSP1_CFG 522 -#define SC8280XP_SLAVE_RBCPR_CX_CFG 523 -#define SC8280XP_SLAVE_RBCPR_MMCX_CFG 524 -#define SC8280XP_SLAVE_RBCPR_MX_CFG 525 -#define SC8280XP_SLAVE_CPR_NSPCX 526 -#define SC8280XP_SLAVE_CRYPTO_0_CFG 527 -#define SC8280XP_SLAVE_CX_RDPM 528 -#define SC8280XP_SLAVE_DCC_CFG 529 -#define SC8280XP_SLAVE_DISPLAY_CFG 530 -#define SC8280XP_SLAVE_DISPLAY1_CFG 531 -#define SC8280XP_SLAVE_EMAC_CFG 532 -#define SC8280XP_SLAVE_EMAC1_CFG 533 -#define SC8280XP_SLAVE_GFX3D_CFG 534 -#define SC8280XP_SLAVE_HWKM 535 -#define SC8280XP_SLAVE_IMEM_CFG 536 -#define SC8280XP_SLAVE_IPA_CFG 537 -#define SC8280XP_SLAVE_IPC_ROUTER_CFG 538 -#define SC8280XP_SLAVE_LLCC_CFG 539 -#define SC8280XP_SLAVE_LPASS 540 -#define SC8280XP_SLAVE_LPASS_CORE_CFG 541 -#define SC8280XP_SLAVE_LPASS_LPI_CFG 542 -#define SC8280XP_SLAVE_LPASS_MPU_CFG 543 -#define SC8280XP_SLAVE_LPASS_TOP_CFG 544 -#define SC8280XP_SLAVE_MX_RDPM 545 -#define SC8280XP_SLAVE_MXC_RDPM 546 -#define SC8280XP_SLAVE_PCIE_0_CFG 547 -#define SC8280XP_SLAVE_PCIE_1_CFG 548 -#define SC8280XP_SLAVE_PCIE_2A_CFG 549 -#define SC8280XP_SLAVE_PCIE_2B_CFG 550 -#define SC8280XP_SLAVE_PCIE_3A_CFG 551 -#define SC8280XP_SLAVE_PCIE_3B_CFG 552 -#define SC8280XP_SLAVE_PCIE_4_CFG 553 -#define SC8280XP_SLAVE_PCIE_RSC_CFG 554 -#define SC8280XP_SLAVE_PDM 555 -#define SC8280XP_SLAVE_PIMEM_CFG 556 -#define SC8280XP_SLAVE_PKA_WRAPPER_CFG 557 -#define SC8280XP_SLAVE_PMU_WRAPPER_CFG 558 -#define SC8280XP_SLAVE_QDSS_CFG 559 -#define SC8280XP_SLAVE_QSPI_0 560 -#define SC8280XP_SLAVE_QUP_0 561 -#define SC8280XP_SLAVE_QUP_1 562 -#define SC8280XP_SLAVE_QUP_2 563 -#define SC8280XP_SLAVE_SDCC_2 564 -#define SC8280XP_SLAVE_SDCC_4 565 -#define SC8280XP_SLAVE_SECURITY 566 -#define SC8280XP_SLAVE_SMMUV3_CFG 567 -#define SC8280XP_SLAVE_SMSS_CFG 568 -#define SC8280XP_SLAVE_SPSS_CFG 569 -#define SC8280XP_SLAVE_TCSR 570 -#define SC8280XP_SLAVE_TLMM 571 -#define SC8280XP_SLAVE_UFS_CARD_CFG 572 -#define SC8280XP_SLAVE_UFS_MEM_CFG 573 -#define SC8280XP_SLAVE_USB3_0 574 -#define SC8280XP_SLAVE_USB3_1 575 -#define SC8280XP_SLAVE_USB3_MP 576 -#define SC8280XP_SLAVE_USB4_0 577 -#define SC8280XP_SLAVE_USB4_1 578 -#define SC8280XP_SLAVE_VENUS_CFG 579 -#define SC8280XP_SLAVE_VSENSE_CTRL_CFG 580 -#define SC8280XP_SLAVE_VSENSE_CTRL_R_CFG 581 -#define SC8280XP_SLAVE_A1NOC_CFG 582 -#define SC8280XP_SLAVE_A1NOC_SNOC 583 -#define SC8280XP_SLAVE_A2NOC_CFG 584 -#define SC8280XP_SLAVE_A2NOC_SNOC 585 -#define SC8280XP_SLAVE_USB_NOC_SNOC 586 -#define SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG 587 -#define SC8280XP_SLAVE_DDRSS_CFG 588 -#define SC8280XP_SLAVE_GEM_NOC_CNOC 589 -#define SC8280XP_SLAVE_GEM_NOC_CFG 590 -#define SC8280XP_SLAVE_SNOC_GEM_NOC_GC 591 -#define SC8280XP_SLAVE_SNOC_GEM_NOC_SF 592 -#define SC8280XP_SLAVE_LLCC 593 -#define SC8280XP_SLAVE_MNOC_HF_MEM_NOC 594 -#define SC8280XP_SLAVE_MNOC_SF_MEM_NOC 595 -#define SC8280XP_SLAVE_CNOC_MNOC_CFG 596 -#define SC8280XP_SLAVE_CDSP_MEM_NOC 597 -#define SC8280XP_SLAVE_CDSPB_MEM_NOC 598 -#define SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC 599 -#define SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC 600 -#define SC8280XP_SLAVE_SNOC_CFG 601 -#define SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG 602 -#define SC8280XP_SLAVE_LPASS_SNOC 603 -#define SC8280XP_SLAVE_QUP_CORE_0 604 -#define SC8280XP_SLAVE_QUP_CORE_1 605 -#define SC8280XP_SLAVE_QUP_CORE_2 606 -#define SC8280XP_SLAVE_IMEM 607 -#define SC8280XP_SLAVE_NSP_XFR 608 -#define SC8280XP_SLAVE_NSPB_XFR 609 -#define SC8280XP_SLAVE_PIMEM 610 -#define SC8280XP_SLAVE_SERVICE_NSP_NOC 611 -#define SC8280XP_SLAVE_SERVICE_NSPB_NOC 612 -#define SC8280XP_SLAVE_SERVICE_A1NOC 613 -#define SC8280XP_SLAVE_SERVICE_A2NOC 614 -#define SC8280XP_SLAVE_SERVICE_CNOC 615 -#define SC8280XP_SLAVE_SERVICE_GEM_NOC_1 616 -#define SC8280XP_SLAVE_SERVICE_MNOC 617 -#define SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC 618 -#define SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC 619 -#define SC8280XP_SLAVE_SERVICE_GEM_NOC_2 620 -#define SC8280XP_SLAVE_SERVICE_SNOC 621 -#define SC8280XP_SLAVE_SERVICE_GEM_NOC 622 -#define SC8280XP_SLAVE_PCIE_0 623 -#define SC8280XP_SLAVE_PCIE_1 624 -#define SC8280XP_SLAVE_PCIE_2A 625 -#define SC8280XP_SLAVE_PCIE_2B 626 -#define SC8280XP_SLAVE_PCIE_3A 627 -#define SC8280XP_SLAVE_PCIE_3B 628 -#define SC8280XP_SLAVE_PCIE_4 629 -#define SC8280XP_SLAVE_QDSS_STM 630 -#define SC8280XP_SLAVE_SMSS 631 -#define SC8280XP_SLAVE_TCU 632 - -#endif - diff --git a/drivers/interconnect/qcom/sdm660.c b/drivers/interconnect/qcom/sdm660.c index ab91de446da8..7392bebba334 100644 --- a/drivers/interconnect/qcom/sdm660.c +++ b/drivers/interconnect/qcom/sdm660.c @@ -1714,7 +1714,7 @@ MODULE_DEVICE_TABLE(of, sdm660_noc_of_match); static struct platform_driver sdm660_noc_driver = { .probe = qnoc_probe, - .remove_new = qnoc_remove, + .remove = qnoc_remove, .driver = { .name = "qnoc-sdm660", .of_match_table = sdm660_noc_of_match, diff --git a/drivers/interconnect/qcom/sdm670.c b/drivers/interconnect/qcom/sdm670.c index e5ee7fbaa641..88f4768b765c 100644 --- a/drivers/interconnect/qcom/sdm670.c +++ b/drivers/interconnect/qcom/sdm670.c @@ -13,1034 +13,1020 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sdm670.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qhm_tsif; +static struct qcom_icc_node xm_emmc; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node qhm_a2noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_hf1_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qhm_spdm; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node qhm_cnoc; +static struct qcom_icc_node acm_l3; +static struct qcom_icc_node pm_gnoc_cfg; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node acm_tcu; +static struct qcom_icc_node qhm_memnoc_cfg; +static struct qcom_icc_node qnm_apps; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_gpu; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qxm_camnoc_hf0; +static struct qcom_icc_node qxm_camnoc_hf1; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_mdp1; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qxm_venus0; +static struct qcom_icc_node qxm_venus1; +static struct qcom_icc_node qxm_venus_arm9; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gladiator_sodv; +static struct qcom_icc_node qnm_memnoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_a2_noc_cfg; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_dsp_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_emmc_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_phy_refgen_south; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qupv3_north; +static struct qcom_icc_node qhs_qupv3_south; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spdm; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm_north; +static struct qcom_icc_node qhs_tlmm_south; +static struct qcom_icc_node qhs_tsif; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_cnoc_a2noc; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_memnoc; +static struct qcom_icc_node qns_gladiator_sodv; +static struct qcom_icc_node qns_gnoc_memnoc; +static struct qcom_icc_node srvc_gnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_apps_io; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_memnoc_snoc; +static struct qcom_icc_node srvc_memnoc; +static struct qcom_icc_node qns2_mem_noc; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_memnoc_gc; +static struct qcom_icc_node qns_memnoc_sf; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; static struct qcom_icc_node qhm_a1noc_cfg = { .name = "qhm_a1noc_cfg", - .id = SDM670_MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_SLAVE_SERVICE_A1NOC }, + .link_nodes = { &srvc_aggre1_noc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = SDM670_MASTER_BLSP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_tsif = { .name = "qhm_tsif", - .id = SDM670_MASTER_TSIF, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_emmc = { .name = "xm_emmc", - .id = SDM670_MASTER_EMMC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SDM670_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SDM670_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SDM670_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_a2noc_cfg = { .name = "qhm_a2noc_cfg", - .id = SDM670_MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_SLAVE_SERVICE_A2NOC }, + .link_nodes = { &srvc_aggre2_noc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SDM670_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", - .id = SDM670_MASTER_BLSP_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_cnoc = { .name = "qnm_cnoc", - .id = SDM670_MASTER_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SDM670_MASTER_CRYPTO_CORE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SDM670_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = SDM670_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SDM670_MASTER_USB3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { .name = "qxm_camnoc_hf0_uncomp", - .id = SDM670_MASTER_CAMNOC_HF0_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { .name = "qxm_camnoc_hf1_uncomp", - .id = SDM670_MASTER_CAMNOC_HF1_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_sf_uncomp = { .name = "qxm_camnoc_sf_uncomp", - .id = SDM670_MASTER_CAMNOC_SF_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qhm_spdm = { .name = "qhm_spdm", - .id = SDM670_MASTER_SPDM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_SLAVE_CNOC_A2NOC }, + .link_nodes = { &qns_cnoc_a2noc }, }; static struct qcom_icc_node qnm_snoc = { .name = "qnm_snoc", - .id = SDM670_MASTER_SNOC_CNOC, .channels = 1, .buswidth = 8, .num_links = 38, - .links = { SDM670_SLAVE_TLMM_SOUTH, - SDM670_SLAVE_CAMERA_CFG, - SDM670_SLAVE_SDCC_4, - SDM670_SLAVE_SDCC_2, - SDM670_SLAVE_CNOC_MNOC_CFG, - SDM670_SLAVE_UFS_MEM_CFG, - SDM670_SLAVE_GLM, - SDM670_SLAVE_PDM, - SDM670_SLAVE_A2NOC_CFG, - SDM670_SLAVE_QDSS_CFG, - SDM670_SLAVE_DISPLAY_CFG, - SDM670_SLAVE_TCSR, - SDM670_SLAVE_DCC_CFG, - SDM670_SLAVE_CNOC_DDRSS, - SDM670_SLAVE_SNOC_CFG, - SDM670_SLAVE_SOUTH_PHY_CFG, - SDM670_SLAVE_GRAPHICS_3D_CFG, - SDM670_SLAVE_VENUS_CFG, - SDM670_SLAVE_TSIF, - SDM670_SLAVE_CDSP_CFG, - SDM670_SLAVE_AOP, - SDM670_SLAVE_BLSP_2, - SDM670_SLAVE_SERVICE_CNOC, - SDM670_SLAVE_USB3, - SDM670_SLAVE_IPA_CFG, - SDM670_SLAVE_RBCPR_CX_CFG, - SDM670_SLAVE_A1NOC_CFG, - SDM670_SLAVE_AOSS, - SDM670_SLAVE_PRNG, - SDM670_SLAVE_VSENSE_CTRL_CFG, - SDM670_SLAVE_EMMC_CFG, - SDM670_SLAVE_BLSP_1, - SDM670_SLAVE_SPDM_WRAPPER, - SDM670_SLAVE_CRYPTO_0_CFG, - SDM670_SLAVE_PIMEM_CFG, - SDM670_SLAVE_TLMM_NORTH, - SDM670_SLAVE_CLK_CTL, - SDM670_SLAVE_IMEM_CFG - }, + .link_nodes = { &qhs_tlmm_south, + &qhs_camera_cfg, + &qhs_sdc4, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_ufs_mem_cfg, + &qhs_glm, + &qhs_pdm, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_display_cfg, + &qhs_tcsr, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_snoc_cfg, + &qhs_phy_refgen_south, + &qhs_gpuss_cfg, + &qhs_venus_cfg, + &qhs_tsif, + &qhs_compute_dsp_cfg, + &qhs_aop, + &qhs_qupv3_north, + &srvc_cnoc, + &qhs_usb3_0, + &qhs_ipa, + &qhs_cpr_cx, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_vsense_ctrl_cfg, + &qhs_emmc_cfg, + &qhs_qupv3_south, + &qhs_spdm, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_tlmm_north, + &qhs_clk_ctl, + &qhs_imem_cfg }, }; static struct qcom_icc_node qhm_cnoc = { .name = "qhm_cnoc", - .id = SDM670_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SDM670_SLAVE_MEM_NOC_CFG, - SDM670_SLAVE_LLCC_CFG - }, + .link_nodes = { &qhs_memnoc, + &qhs_llcc }, }; static struct qcom_icc_node acm_l3 = { .name = "acm_l3", - .id = SDM670_MASTER_AMPSS_M0, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SDM670_SLAVE_SERVICE_GNOC, - SDM670_SLAVE_GNOC_SNOC, - SDM670_SLAVE_GNOC_MEM_NOC - }, + .link_nodes = { &srvc_gnoc, + &qns_gladiator_sodv, + &qns_gnoc_memnoc }, }; static struct qcom_icc_node pm_gnoc_cfg = { .name = "pm_gnoc_cfg", - .id = SDM670_MASTER_GNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_SLAVE_SERVICE_GNOC }, + .link_nodes = { &srvc_gnoc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SDM670_MASTER_LLCC, .channels = 2, .buswidth = 4, .num_links = 1, - .links = { SDM670_SLAVE_EBI_CH0 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node acm_tcu = { .name = "acm_tcu", - .id = SDM670_MASTER_TCU_0, .channels = 1, .buswidth = 8, .num_links = 3, - .links = { SDM670_SLAVE_MEM_NOC_GNOC, - SDM670_SLAVE_LLCC, - SDM670_SLAVE_MEM_NOC_SNOC - }, + .link_nodes = { &qns_apps_io, + &qns_llcc, + &qns_memnoc_snoc }, }; static struct qcom_icc_node qhm_memnoc_cfg = { .name = "qhm_memnoc_cfg", - .id = SDM670_MASTER_MEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SDM670_SLAVE_SERVICE_MEM_NOC, - SDM670_SLAVE_MSS_PROC_MS_MPU_CFG - }, + .link_nodes = { &srvc_memnoc, + &qhs_mdsp_ms_mpu_cfg }, }; static struct qcom_icc_node qnm_apps = { .name = "qnm_apps", - .id = SDM670_MASTER_GNOC_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SDM670_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SDM670_MASTER_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 3, - .links = { SDM670_SLAVE_MEM_NOC_GNOC, - SDM670_SLAVE_LLCC, - SDM670_SLAVE_MEM_NOC_SNOC - }, + .link_nodes = { &qns_apps_io, + &qns_llcc, + &qns_memnoc_snoc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SDM670_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SDM670_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SDM670_SLAVE_MEM_NOC_GNOC, - SDM670_SLAVE_LLCC - }, + .link_nodes = { &qns_apps_io, + &qns_llcc }, }; static struct qcom_icc_node qxm_gpu = { .name = "qxm_gpu", - .id = SDM670_MASTER_GRAPHICS_3D, .channels = 2, .buswidth = 32, .num_links = 3, - .links = { SDM670_SLAVE_MEM_NOC_GNOC, - SDM670_SLAVE_LLCC, - SDM670_SLAVE_MEM_NOC_SNOC - }, + .link_nodes = { &qns_apps_io, + &qns_llcc, + &qns_memnoc_snoc }, }; static struct qcom_icc_node qhm_mnoc_cfg = { .name = "qhm_mnoc_cfg", - .id = SDM670_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qxm_camnoc_hf0 = { .name = "qxm_camnoc_hf0", - .id = SDM670_MASTER_CAMNOC_HF0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_hf1 = { .name = "qxm_camnoc_hf1", - .id = SDM670_MASTER_CAMNOC_HF1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_sf = { .name = "qxm_camnoc_sf", - .id = SDM670_MASTER_CAMNOC_SF, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_mdp0 = { .name = "qxm_mdp0", - .id = SDM670_MASTER_MDP_PORT0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_mdp1 = { .name = "qxm_mdp1", - .id = SDM670_MASTER_MDP_PORT1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_rot = { .name = "qxm_rot", - .id = SDM670_MASTER_ROTATOR, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus0 = { .name = "qxm_venus0", - .id = SDM670_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus1 = { .name = "qxm_venus1", - .id = SDM670_MASTER_VIDEO_P1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus_arm9 = { .name = "qxm_venus_arm9", - .id = SDM670_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qhm_snoc_cfg = { .name = "qhm_snoc_cfg", - .id = SDM670_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SDM670_MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 6, - .links = { SDM670_SLAVE_PIMEM, - SDM670_SLAVE_SNOC_MEM_NOC_SF, - SDM670_SLAVE_OCIMEM, - SDM670_SLAVE_APPSS, - SDM670_SLAVE_SNOC_CNOC, - SDM670_SLAVE_QDSS_STM - }, + .link_nodes = { &qxs_pimem, + &qns_memnoc_sf, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SDM670_MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 7, - .links = { SDM670_SLAVE_PIMEM, - SDM670_SLAVE_SNOC_MEM_NOC_SF, - SDM670_SLAVE_OCIMEM, - SDM670_SLAVE_APPSS, - SDM670_SLAVE_SNOC_CNOC, - SDM670_SLAVE_TCU, - SDM670_SLAVE_QDSS_STM - }, + .link_nodes = { &qxs_pimem, + &qns_memnoc_sf, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_gladiator_sodv = { .name = "qnm_gladiator_sodv", - .id = SDM670_MASTER_GNOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 6, - .links = { SDM670_SLAVE_PIMEM, - SDM670_SLAVE_OCIMEM, - SDM670_SLAVE_APPSS, - SDM670_SLAVE_SNOC_CNOC, - SDM670_SLAVE_TCU, - SDM670_SLAVE_QDSS_STM - }, + .link_nodes = { &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_memnoc = { .name = "qnm_memnoc", - .id = SDM670_MASTER_MEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 5, - .links = { SDM670_SLAVE_OCIMEM, - SDM670_SLAVE_APPSS, - SDM670_SLAVE_PIMEM, - SDM670_SLAVE_SNOC_CNOC, - SDM670_SLAVE_QDSS_STM - }, + .link_nodes = { &qxs_imem, + &qhs_apss, + &qxs_pimem, + &qns_cnoc, + &xs_qdss_stm }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = SDM670_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SDM670_SLAVE_OCIMEM, - SDM670_SLAVE_SNOC_MEM_NOC_GC - }, + .link_nodes = { &qxs_imem, + &qns_memnoc_gc }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SDM670_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SDM670_SLAVE_OCIMEM, - SDM670_SLAVE_SNOC_MEM_NOC_GC - }, + .link_nodes = { &qxs_imem, + &qns_memnoc_gc }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SDM670_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDM670_MASTER_A1NOC_SNOC }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node srvc_aggre1_noc = { .name = "srvc_aggre1_noc", - .id = SDM670_SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SDM670_SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDM670_MASTER_A2NOC_SNOC }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node srvc_aggre2_noc = { .name = "srvc_aggre2_noc", - .id = SDM670_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_camnoc_uncomp = { .name = "qns_camnoc_uncomp", - .id = SDM670_SLAVE_CAMNOC_UNCOMP, .channels = 1, .buswidth = 32, }; static struct qcom_icc_node qhs_a1_noc_cfg = { .name = "qhs_a1_noc_cfg", - .id = SDM670_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_MASTER_A1NOC_CFG }, + .link_nodes = { &qhm_a1noc_cfg }, }; static struct qcom_icc_node qhs_a2_noc_cfg = { .name = "qhs_a2_noc_cfg", - .id = SDM670_SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_MASTER_A2NOC_CFG }, + .link_nodes = { &qhm_a2noc_cfg }, }; static struct qcom_icc_node qhs_aop = { .name = "qhs_aop", - .id = SDM670_SLAVE_AOP, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SDM670_SLAVE_AOSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SDM670_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SDM670_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_compute_dsp_cfg = { .name = "qhs_compute_dsp_cfg", - .id = SDM670_SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SDM670_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SDM670_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dcc_cfg = { .name = "qhs_dcc_cfg", - .id = SDM670_SLAVE_DCC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_MASTER_CNOC_DC_NOC }, + .link_nodes = { &qhm_cnoc }, }; static struct qcom_icc_node qhs_ddrss_cfg = { .name = "qhs_ddrss_cfg", - .id = SDM670_SLAVE_CNOC_DDRSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SDM670_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_emmc_cfg = { .name = "qhs_emmc_cfg", - .id = SDM670_SLAVE_EMMC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_glm = { .name = "qhs_glm", - .id = SDM670_SLAVE_GLM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SDM670_SLAVE_GRAPHICS_3D_CFG, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SDM670_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SDM670_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mnoc_cfg = { .name = "qhs_mnoc_cfg", - .id = SDM670_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qhm_mnoc_cfg }, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SDM670_SLAVE_PDM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_phy_refgen_south = { .name = "qhs_phy_refgen_south", - .id = SDM670_SLAVE_SOUTH_PHY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SDM670_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SDM670_SLAVE_PRNG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SDM670_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qupv3_north = { .name = "qhs_qupv3_north", - .id = SDM670_SLAVE_BLSP_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qupv3_south = { .name = "qhs_qupv3_south", - .id = SDM670_SLAVE_BLSP_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SDM670_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SDM670_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_snoc_cfg = { .name = "qhs_snoc_cfg", - .id = SDM670_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_MASTER_SNOC_CFG }, + .link_nodes = { &qhm_snoc_cfg }, }; static struct qcom_icc_node qhs_spdm = { .name = "qhs_spdm", - .id = SDM670_SLAVE_SPDM_WRAPPER, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SDM670_SLAVE_TCSR, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_north = { .name = "qhs_tlmm_north", - .id = SDM670_SLAVE_TLMM_NORTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_south = { .name = "qhs_tlmm_south", - .id = SDM670_SLAVE_TLMM_SOUTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tsif = { .name = "qhs_tsif", - .id = SDM670_SLAVE_TSIF, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SDM670_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SDM670_SLAVE_USB3, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SDM670_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SDM670_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_cnoc_a2noc = { .name = "qns_cnoc_a2noc", - .id = SDM670_SLAVE_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_MASTER_CNOC_A2NOC }, + .link_nodes = { &qnm_cnoc }, }; static struct qcom_icc_node srvc_cnoc = { .name = "srvc_cnoc", - .id = SDM670_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_llcc = { .name = "qhs_llcc", - .id = SDM670_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_memnoc = { .name = "qhs_memnoc", - .id = SDM670_SLAVE_MEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM670_MASTER_MEM_NOC_CFG }, + .link_nodes = { &qhm_memnoc_cfg }, }; static struct qcom_icc_node qns_gladiator_sodv = { .name = "qns_gladiator_sodv", - .id = SDM670_SLAVE_GNOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_MASTER_GNOC_SNOC }, + .link_nodes = { &qnm_gladiator_sodv }, }; static struct qcom_icc_node qns_gnoc_memnoc = { .name = "qns_gnoc_memnoc", - .id = SDM670_SLAVE_GNOC_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SDM670_MASTER_GNOC_MEM_NOC }, + .link_nodes = { &qnm_apps }, }; static struct qcom_icc_node srvc_gnoc = { .name = "srvc_gnoc", - .id = SDM670_SLAVE_SERVICE_GNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SDM670_SLAVE_EBI_CH0, .channels = 2, .buswidth = 4, }; static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { .name = "qhs_mdsp_ms_mpu_cfg", - .id = SDM670_SLAVE_MSS_PROC_MS_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_apps_io = { .name = "qns_apps_io", - .id = SDM670_SLAVE_MEM_NOC_GNOC, .channels = 1, .buswidth = 32, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SDM670_SLAVE_LLCC, .channels = 2, .buswidth = 16, .num_links = 1, - .links = { SDM670_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_memnoc_snoc = { .name = "qns_memnoc_snoc", - .id = SDM670_SLAVE_MEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_MASTER_MEM_NOC_SNOC }, + .link_nodes = { &qnm_memnoc }, }; static struct qcom_icc_node srvc_memnoc = { .name = "srvc_memnoc", - .id = SDM670_SLAVE_SERVICE_MEM_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns2_mem_noc = { .name = "qns2_mem_noc", - .id = SDM670_SLAVE_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM670_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SDM670_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SDM670_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SDM670_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SDM670_SLAVE_APPSS, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qns_cnoc = { .name = "qns_cnoc", - .id = SDM670_SLAVE_SNOC_CNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_MASTER_SNOC_CNOC }, + .link_nodes = { &qnm_snoc }, }; static struct qcom_icc_node qns_memnoc_gc = { .name = "qns_memnoc_gc", - .id = SDM670_SLAVE_SNOC_MEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM670_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_memnoc_sf = { .name = "qns_memnoc_sf", - .id = SDM670_SLAVE_SNOC_MEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDM670_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SDM670_SLAVE_OCIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = SDM670_SLAVE_PIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SDM670_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SDM670_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SDM670_SLAVE_TCU, .channels = 1, .buswidth = 8, }; @@ -1533,7 +1519,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove_new = qcom_icc_rpmh_remove, + .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sdm670", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sdm670.h b/drivers/interconnect/qcom/sdm670.h deleted file mode 100644 index 14155f244c43..000000000000 --- a/drivers/interconnect/qcom/sdm670.h +++ /dev/null @@ -1,128 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm #define SDM670 interconnect IDs - * - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SDM670_H -#define __DRIVERS_INTERCONNECT_QCOM_SDM670_H - -#define SDM670_MASTER_A1NOC_CFG 0 -#define SDM670_MASTER_A1NOC_SNOC 1 -#define SDM670_MASTER_A2NOC_CFG 2 -#define SDM670_MASTER_A2NOC_SNOC 3 -#define SDM670_MASTER_AMPSS_M0 4 -#define SDM670_MASTER_BLSP_1 5 -#define SDM670_MASTER_BLSP_2 6 -#define SDM670_MASTER_CAMNOC_HF0 7 -#define SDM670_MASTER_CAMNOC_HF0_UNCOMP 8 -#define SDM670_MASTER_CAMNOC_HF1 9 -#define SDM670_MASTER_CAMNOC_HF1_UNCOMP 10 -#define SDM670_MASTER_CAMNOC_SF 11 -#define SDM670_MASTER_CAMNOC_SF_UNCOMP 12 -#define SDM670_MASTER_CNOC_A2NOC 13 -#define SDM670_MASTER_CNOC_DC_NOC 14 -#define SDM670_MASTER_CNOC_MNOC_CFG 15 -#define SDM670_MASTER_CRYPTO_CORE_0 16 -#define SDM670_MASTER_EMMC 17 -#define SDM670_MASTER_GIC 18 -#define SDM670_MASTER_GNOC_CFG 19 -#define SDM670_MASTER_GNOC_MEM_NOC 20 -#define SDM670_MASTER_GNOC_SNOC 21 -#define SDM670_MASTER_GRAPHICS_3D 22 -#define SDM670_MASTER_IPA 23 -#define SDM670_MASTER_LLCC 24 -#define SDM670_MASTER_MDP_PORT0 25 -#define SDM670_MASTER_MDP_PORT1 26 -#define SDM670_MASTER_MEM_NOC_CFG 27 -#define SDM670_MASTER_MEM_NOC_SNOC 28 -#define SDM670_MASTER_MNOC_HF_MEM_NOC 29 -#define SDM670_MASTER_MNOC_SF_MEM_NOC 30 -#define SDM670_MASTER_PIMEM 31 -#define SDM670_MASTER_QDSS_BAM 32 -#define SDM670_MASTER_QDSS_ETR 33 -#define SDM670_MASTER_ROTATOR 34 -#define SDM670_MASTER_SDCC_2 35 -#define SDM670_MASTER_SDCC_4 36 -#define SDM670_MASTER_SNOC_CFG 37 -#define SDM670_MASTER_SNOC_CNOC 38 -#define SDM670_MASTER_SNOC_GC_MEM_NOC 39 -#define SDM670_MASTER_SNOC_SF_MEM_NOC 40 -#define SDM670_MASTER_SPDM 41 -#define SDM670_MASTER_TCU_0 42 -#define SDM670_MASTER_TSIF 43 -#define SDM670_MASTER_UFS_MEM 44 -#define SDM670_MASTER_USB3 45 -#define SDM670_MASTER_VIDEO_P0 46 -#define SDM670_MASTER_VIDEO_P1 47 -#define SDM670_MASTER_VIDEO_PROC 48 -#define SDM670_SLAVE_A1NOC_CFG 49 -#define SDM670_SLAVE_A1NOC_SNOC 50 -#define SDM670_SLAVE_A2NOC_CFG 51 -#define SDM670_SLAVE_A2NOC_SNOC 52 -#define SDM670_SLAVE_AOP 53 -#define SDM670_SLAVE_AOSS 54 -#define SDM670_SLAVE_APPSS 55 -#define SDM670_SLAVE_BLSP_1 56 -#define SDM670_SLAVE_BLSP_2 57 -#define SDM670_SLAVE_CAMERA_CFG 58 -#define SDM670_SLAVE_CAMNOC_UNCOMP 59 -#define SDM670_SLAVE_CDSP_CFG 60 -#define SDM670_SLAVE_CLK_CTL 61 -#define SDM670_SLAVE_CNOC_A2NOC 62 -#define SDM670_SLAVE_CNOC_DDRSS 63 -#define SDM670_SLAVE_CNOC_MNOC_CFG 64 -#define SDM670_SLAVE_CRYPTO_0_CFG 65 -#define SDM670_SLAVE_DCC_CFG 66 -#define SDM670_SLAVE_DISPLAY_CFG 67 -#define SDM670_SLAVE_EBI_CH0 68 -#define SDM670_SLAVE_EMMC_CFG 69 -#define SDM670_SLAVE_GLM 70 -#define SDM670_SLAVE_GNOC_MEM_NOC 71 -#define SDM670_SLAVE_GNOC_SNOC 72 -#define SDM670_SLAVE_GRAPHICS_3D_CFG 73 -#define SDM670_SLAVE_IMEM_CFG 74 -#define SDM670_SLAVE_IPA_CFG 75 -#define SDM670_SLAVE_LLCC 76 -#define SDM670_SLAVE_LLCC_CFG 77 -#define SDM670_SLAVE_MEM_NOC_CFG 78 -#define SDM670_SLAVE_MEM_NOC_GNOC 79 -#define SDM670_SLAVE_MEM_NOC_SNOC 80 -#define SDM670_SLAVE_MNOC_HF_MEM_NOC 81 -#define SDM670_SLAVE_MNOC_SF_MEM_NOC 82 -#define SDM670_SLAVE_MSS_PROC_MS_MPU_CFG 83 -#define SDM670_SLAVE_OCIMEM 84 -#define SDM670_SLAVE_PDM 85 -#define SDM670_SLAVE_PIMEM 86 -#define SDM670_SLAVE_PIMEM_CFG 87 -#define SDM670_SLAVE_PRNG 88 -#define SDM670_SLAVE_QDSS_CFG 89 -#define SDM670_SLAVE_QDSS_STM 90 -#define SDM670_SLAVE_RBCPR_CX_CFG 91 -#define SDM670_SLAVE_SDCC_2 92 -#define SDM670_SLAVE_SDCC_4 93 -#define SDM670_SLAVE_SERVICE_A1NOC 94 -#define SDM670_SLAVE_SERVICE_A2NOC 95 -#define SDM670_SLAVE_SERVICE_CNOC 96 -#define SDM670_SLAVE_SERVICE_GNOC 97 -#define SDM670_SLAVE_SERVICE_MEM_NOC 98 -#define SDM670_SLAVE_SERVICE_MNOC 99 -#define SDM670_SLAVE_SERVICE_SNOC 100 -#define SDM670_SLAVE_SNOC_CFG 101 -#define SDM670_SLAVE_SNOC_CNOC 102 -#define SDM670_SLAVE_SNOC_MEM_NOC_GC 103 -#define SDM670_SLAVE_SNOC_MEM_NOC_SF 104 -#define SDM670_SLAVE_SOUTH_PHY_CFG 105 -#define SDM670_SLAVE_SPDM_WRAPPER 106 -#define SDM670_SLAVE_TCSR 107 -#define SDM670_SLAVE_TCU 108 -#define SDM670_SLAVE_TLMM_NORTH 109 -#define SDM670_SLAVE_TLMM_SOUTH 110 -#define SDM670_SLAVE_TSIF 111 -#define SDM670_SLAVE_UFS_MEM_CFG 112 -#define SDM670_SLAVE_USB3 113 -#define SDM670_SLAVE_VENUS_CFG 114 -#define SDM670_SLAVE_VSENSE_CTRL_CFG 115 - -#endif diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom/sdm845.c index 584800ac871a..6d5bbeda0689 100644 --- a/drivers/interconnect/qcom/sdm845.c +++ b/drivers/interconnect/qcom/sdm845.c @@ -14,1251 +14,1231 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sdm845.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qhm_tsif; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_card; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_pcie_0; +static struct qcom_icc_node qhm_a2noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node xm_usb3_1; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_hf1_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qhm_spdm; +static struct qcom_icc_node qhm_tic; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc; +static struct qcom_icc_node acm_l3; +static struct qcom_icc_node pm_gnoc_cfg; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node acm_tcu; +static struct qcom_icc_node qhm_memnoc_cfg; +static struct qcom_icc_node qnm_apps; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_gpu; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qxm_camnoc_hf0; +static struct qcom_icc_node qxm_camnoc_hf1; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_mdp1; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qxm_venus0; +static struct qcom_icc_node qxm_venus1; +static struct qcom_icc_node qxm_venus_arm9; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gladiator_sodv; +static struct qcom_icc_node qnm_memnoc; +static struct qcom_icc_node qnm_pcie_anoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_pcie_a1noc_snoc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_pcie_snoc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_a2_noc_cfg; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_dsp_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie_gen3_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_phy_refgen_south; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qupv3_north; +static struct qcom_icc_node qhs_qupv3_south; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spdm; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm_north; +static struct qcom_icc_node qhs_tlmm_south; +static struct qcom_icc_node qhs_tsif; +static struct qcom_icc_node qhs_ufs_card_cfg; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_usb3_1; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_cnoc_a2noc; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_memnoc; +static struct qcom_icc_node qns_gladiator_sodv; +static struct qcom_icc_node qns_gnoc_memnoc; +static struct qcom_icc_node srvc_gnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_apps_io; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_memnoc_snoc; +static struct qcom_icc_node srvc_memnoc; +static struct qcom_icc_node qns2_mem_noc; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_memnoc_gc; +static struct qcom_icc_node qns_memnoc_sf; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pcie; +static struct qcom_icc_node qxs_pcie_gen3; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; static struct qcom_icc_node qhm_a1noc_cfg = { .name = "qhm_a1noc_cfg", - .id = SDM845_MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_SLAVE_SERVICE_A1NOC }, + .link_nodes = { &srvc_aggre1_noc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = SDM845_MASTER_BLSP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_tsif = { .name = "qhm_tsif", - .id = SDM845_MASTER_TSIF, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SDM845_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SDM845_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_card = { .name = "xm_ufs_card", - .id = SDM845_MASTER_UFS_CARD, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SDM845_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_pcie_0 = { .name = "xm_pcie_0", - .id = SDM845_MASTER_PCIE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC }, + .link_nodes = { &qns_pcie_a1noc_snoc }, }; static struct qcom_icc_node qhm_a2noc_cfg = { .name = "qhm_a2noc_cfg", - .id = SDM845_MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_SLAVE_SERVICE_A2NOC }, + .link_nodes = { &srvc_aggre2_noc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SDM845_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", - .id = SDM845_MASTER_BLSP_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_cnoc = { .name = "qnm_cnoc", - .id = SDM845_MASTER_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SDM845_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SDM845_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", - .id = SDM845_MASTER_PCIE_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_ANOC_PCIE_SNOC }, + .link_nodes = { &qns_pcie_snoc }, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = SDM845_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SDM845_MASTER_USB3_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_usb3_1 = { .name = "xm_usb3_1", - .id = SDM845_MASTER_USB3_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { .name = "qxm_camnoc_hf0_uncomp", - .id = SDM845_MASTER_CAMNOC_HF0_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM845_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { .name = "qxm_camnoc_hf1_uncomp", - .id = SDM845_MASTER_CAMNOC_HF1_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM845_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_sf_uncomp = { .name = "qxm_camnoc_sf_uncomp", - .id = SDM845_MASTER_CAMNOC_SF_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM845_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qhm_spdm = { .name = "qhm_spdm", - .id = SDM845_MASTER_SPDM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_SLAVE_CNOC_A2NOC }, + .link_nodes = { &qns_cnoc_a2noc }, }; static struct qcom_icc_node qhm_tic = { .name = "qhm_tic", - .id = SDM845_MASTER_TIC, .channels = 1, .buswidth = 4, .num_links = 43, - .links = { SDM845_SLAVE_A1NOC_CFG, - SDM845_SLAVE_A2NOC_CFG, - SDM845_SLAVE_AOP, - SDM845_SLAVE_AOSS, - SDM845_SLAVE_CAMERA_CFG, - SDM845_SLAVE_CLK_CTL, - SDM845_SLAVE_CDSP_CFG, - SDM845_SLAVE_RBCPR_CX_CFG, - SDM845_SLAVE_CRYPTO_0_CFG, - SDM845_SLAVE_DCC_CFG, - SDM845_SLAVE_CNOC_DDRSS, - SDM845_SLAVE_DISPLAY_CFG, - SDM845_SLAVE_GLM, - SDM845_SLAVE_GFX3D_CFG, - SDM845_SLAVE_IMEM_CFG, - SDM845_SLAVE_IPA_CFG, - SDM845_SLAVE_CNOC_MNOC_CFG, - SDM845_SLAVE_PCIE_0_CFG, - SDM845_SLAVE_PCIE_1_CFG, - SDM845_SLAVE_PDM, - SDM845_SLAVE_SOUTH_PHY_CFG, - SDM845_SLAVE_PIMEM_CFG, - SDM845_SLAVE_PRNG, - SDM845_SLAVE_QDSS_CFG, - SDM845_SLAVE_BLSP_2, - SDM845_SLAVE_BLSP_1, - SDM845_SLAVE_SDCC_2, - SDM845_SLAVE_SDCC_4, - SDM845_SLAVE_SNOC_CFG, - SDM845_SLAVE_SPDM_WRAPPER, - SDM845_SLAVE_SPSS_CFG, - SDM845_SLAVE_TCSR, - SDM845_SLAVE_TLMM_NORTH, - SDM845_SLAVE_TLMM_SOUTH, - SDM845_SLAVE_TSIF, - SDM845_SLAVE_UFS_CARD_CFG, - SDM845_SLAVE_UFS_MEM_CFG, - SDM845_SLAVE_USB3_0, - SDM845_SLAVE_USB3_1, - SDM845_SLAVE_VENUS_CFG, - SDM845_SLAVE_VSENSE_CTRL_CFG, - SDM845_SLAVE_CNOC_A2NOC, - SDM845_SLAVE_SERVICE_CNOC - }, + .link_nodes = { &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_aop, + &qhs_aoss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_dsp_cfg, + &qhs_cpr_cx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_pcie0_cfg, + &qhs_pcie_gen3_cfg, + &qhs_pdm, + &qhs_phy_refgen_south, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qupv3_north, + &qhs_qupv3_south, + &qhs_sdc2, + &qhs_sdc4, + &qhs_snoc_cfg, + &qhs_spdm, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm_north, + &qhs_tlmm_south, + &qhs_tsif, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_cnoc_a2noc, + &srvc_cnoc }, }; static struct qcom_icc_node qnm_snoc = { .name = "qnm_snoc", - .id = SDM845_MASTER_SNOC_CNOC, .channels = 1, .buswidth = 8, .num_links = 42, - .links = { SDM845_SLAVE_A1NOC_CFG, - SDM845_SLAVE_A2NOC_CFG, - SDM845_SLAVE_AOP, - SDM845_SLAVE_AOSS, - SDM845_SLAVE_CAMERA_CFG, - SDM845_SLAVE_CLK_CTL, - SDM845_SLAVE_CDSP_CFG, - SDM845_SLAVE_RBCPR_CX_CFG, - SDM845_SLAVE_CRYPTO_0_CFG, - SDM845_SLAVE_DCC_CFG, - SDM845_SLAVE_CNOC_DDRSS, - SDM845_SLAVE_DISPLAY_CFG, - SDM845_SLAVE_GLM, - SDM845_SLAVE_GFX3D_CFG, - SDM845_SLAVE_IMEM_CFG, - SDM845_SLAVE_IPA_CFG, - SDM845_SLAVE_CNOC_MNOC_CFG, - SDM845_SLAVE_PCIE_0_CFG, - SDM845_SLAVE_PCIE_1_CFG, - SDM845_SLAVE_PDM, - SDM845_SLAVE_SOUTH_PHY_CFG, - SDM845_SLAVE_PIMEM_CFG, - SDM845_SLAVE_PRNG, - SDM845_SLAVE_QDSS_CFG, - SDM845_SLAVE_BLSP_2, - SDM845_SLAVE_BLSP_1, - SDM845_SLAVE_SDCC_2, - SDM845_SLAVE_SDCC_4, - SDM845_SLAVE_SNOC_CFG, - SDM845_SLAVE_SPDM_WRAPPER, - SDM845_SLAVE_SPSS_CFG, - SDM845_SLAVE_TCSR, - SDM845_SLAVE_TLMM_NORTH, - SDM845_SLAVE_TLMM_SOUTH, - SDM845_SLAVE_TSIF, - SDM845_SLAVE_UFS_CARD_CFG, - SDM845_SLAVE_UFS_MEM_CFG, - SDM845_SLAVE_USB3_0, - SDM845_SLAVE_USB3_1, - SDM845_SLAVE_VENUS_CFG, - SDM845_SLAVE_VSENSE_CTRL_CFG, - SDM845_SLAVE_SERVICE_CNOC - }, + .link_nodes = { &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_aop, + &qhs_aoss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_dsp_cfg, + &qhs_cpr_cx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_pcie0_cfg, + &qhs_pcie_gen3_cfg, + &qhs_pdm, + &qhs_phy_refgen_south, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qupv3_north, + &qhs_qupv3_south, + &qhs_sdc2, + &qhs_sdc4, + &qhs_snoc_cfg, + &qhs_spdm, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm_north, + &qhs_tlmm_south, + &qhs_tsif, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &srvc_cnoc }, }; static struct qcom_icc_node xm_qdss_dap = { .name = "xm_qdss_dap", - .id = SDM845_MASTER_QDSS_DAP, .channels = 1, .buswidth = 8, .num_links = 43, - .links = { SDM845_SLAVE_A1NOC_CFG, - SDM845_SLAVE_A2NOC_CFG, - SDM845_SLAVE_AOP, - SDM845_SLAVE_AOSS, - SDM845_SLAVE_CAMERA_CFG, - SDM845_SLAVE_CLK_CTL, - SDM845_SLAVE_CDSP_CFG, - SDM845_SLAVE_RBCPR_CX_CFG, - SDM845_SLAVE_CRYPTO_0_CFG, - SDM845_SLAVE_DCC_CFG, - SDM845_SLAVE_CNOC_DDRSS, - SDM845_SLAVE_DISPLAY_CFG, - SDM845_SLAVE_GLM, - SDM845_SLAVE_GFX3D_CFG, - SDM845_SLAVE_IMEM_CFG, - SDM845_SLAVE_IPA_CFG, - SDM845_SLAVE_CNOC_MNOC_CFG, - SDM845_SLAVE_PCIE_0_CFG, - SDM845_SLAVE_PCIE_1_CFG, - SDM845_SLAVE_PDM, - SDM845_SLAVE_SOUTH_PHY_CFG, - SDM845_SLAVE_PIMEM_CFG, - SDM845_SLAVE_PRNG, - SDM845_SLAVE_QDSS_CFG, - SDM845_SLAVE_BLSP_2, - SDM845_SLAVE_BLSP_1, - SDM845_SLAVE_SDCC_2, - SDM845_SLAVE_SDCC_4, - SDM845_SLAVE_SNOC_CFG, - SDM845_SLAVE_SPDM_WRAPPER, - SDM845_SLAVE_SPSS_CFG, - SDM845_SLAVE_TCSR, - SDM845_SLAVE_TLMM_NORTH, - SDM845_SLAVE_TLMM_SOUTH, - SDM845_SLAVE_TSIF, - SDM845_SLAVE_UFS_CARD_CFG, - SDM845_SLAVE_UFS_MEM_CFG, - SDM845_SLAVE_USB3_0, - SDM845_SLAVE_USB3_1, - SDM845_SLAVE_VENUS_CFG, - SDM845_SLAVE_VSENSE_CTRL_CFG, - SDM845_SLAVE_CNOC_A2NOC, - SDM845_SLAVE_SERVICE_CNOC - }, + .link_nodes = { &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_aop, + &qhs_aoss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_dsp_cfg, + &qhs_cpr_cx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_pcie0_cfg, + &qhs_pcie_gen3_cfg, + &qhs_pdm, + &qhs_phy_refgen_south, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qupv3_north, + &qhs_qupv3_south, + &qhs_sdc2, + &qhs_sdc4, + &qhs_snoc_cfg, + &qhs_spdm, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm_north, + &qhs_tlmm_south, + &qhs_tsif, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_cnoc_a2noc, + &srvc_cnoc }, }; static struct qcom_icc_node qhm_cnoc = { .name = "qhm_cnoc", - .id = SDM845_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SDM845_SLAVE_LLCC_CFG, - SDM845_SLAVE_MEM_NOC_CFG - }, + .link_nodes = { &qhs_llcc, + &qhs_memnoc }, }; static struct qcom_icc_node acm_l3 = { .name = "acm_l3", - .id = SDM845_MASTER_APPSS_PROC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SDM845_SLAVE_GNOC_SNOC, - SDM845_SLAVE_GNOC_MEM_NOC, - SDM845_SLAVE_SERVICE_GNOC - }, + .link_nodes = { &qns_gladiator_sodv, + &qns_gnoc_memnoc, + &srvc_gnoc }, }; static struct qcom_icc_node pm_gnoc_cfg = { .name = "pm_gnoc_cfg", - .id = SDM845_MASTER_GNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_SLAVE_SERVICE_GNOC }, + .link_nodes = { &srvc_gnoc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SDM845_MASTER_LLCC, .channels = 4, .buswidth = 4, .num_links = 1, - .links = { SDM845_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node acm_tcu = { .name = "acm_tcu", - .id = SDM845_MASTER_TCU_0, .channels = 1, .buswidth = 8, .num_links = 3, - .links = { SDM845_SLAVE_MEM_NOC_GNOC, - SDM845_SLAVE_LLCC, - SDM845_SLAVE_MEM_NOC_SNOC - }, + .link_nodes = { &qns_apps_io, + &qns_llcc, + &qns_memnoc_snoc }, }; static struct qcom_icc_node qhm_memnoc_cfg = { .name = "qhm_memnoc_cfg", - .id = SDM845_MASTER_MEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, - SDM845_SLAVE_SERVICE_MEM_NOC - }, + .link_nodes = { &qhs_mdsp_ms_mpu_cfg, + &srvc_memnoc }, }; static struct qcom_icc_node qnm_apps = { .name = "qnm_apps", - .id = SDM845_MASTER_GNOC_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SDM845_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SDM845_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SDM845_SLAVE_MEM_NOC_GNOC, - SDM845_SLAVE_LLCC - }, + .link_nodes = { &qns_apps_io, + &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SDM845_MASTER_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 3, - .links = { SDM845_SLAVE_MEM_NOC_GNOC, - SDM845_SLAVE_LLCC, - SDM845_SLAVE_MEM_NOC_SNOC - }, + .link_nodes = { &qns_apps_io, + &qns_llcc, + &qns_memnoc_snoc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SDM845_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SDM845_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SDM845_SLAVE_MEM_NOC_GNOC, - SDM845_SLAVE_LLCC - }, + .link_nodes = { &qns_apps_io, + &qns_llcc }, }; static struct qcom_icc_node qxm_gpu = { .name = "qxm_gpu", - .id = SDM845_MASTER_GFX3D, .channels = 2, .buswidth = 32, .num_links = 3, - .links = { SDM845_SLAVE_MEM_NOC_GNOC, - SDM845_SLAVE_LLCC, - SDM845_SLAVE_MEM_NOC_SNOC - }, + .link_nodes = { &qns_apps_io, + &qns_llcc, + &qns_memnoc_snoc }, }; static struct qcom_icc_node qhm_mnoc_cfg = { .name = "qhm_mnoc_cfg", - .id = SDM845_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qxm_camnoc_hf0 = { .name = "qxm_camnoc_hf0", - .id = SDM845_MASTER_CAMNOC_HF0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_hf1 = { .name = "qxm_camnoc_hf1", - .id = SDM845_MASTER_CAMNOC_HF1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_sf = { .name = "qxm_camnoc_sf", - .id = SDM845_MASTER_CAMNOC_SF, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_mdp0 = { .name = "qxm_mdp0", - .id = SDM845_MASTER_MDP0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_mdp1 = { .name = "qxm_mdp1", - .id = SDM845_MASTER_MDP1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_rot = { .name = "qxm_rot", - .id = SDM845_MASTER_ROTATOR, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus0 = { .name = "qxm_venus0", - .id = SDM845_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus1 = { .name = "qxm_venus1", - .id = SDM845_MASTER_VIDEO_P1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus_arm9 = { .name = "qxm_venus_arm9", - .id = SDM845_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qhm_snoc_cfg = { .name = "qhm_snoc_cfg", - .id = SDM845_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SDM845_MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 6, - .links = { SDM845_SLAVE_APPSS, - SDM845_SLAVE_SNOC_CNOC, - SDM845_SLAVE_SNOC_MEM_NOC_SF, - SDM845_SLAVE_IMEM, - SDM845_SLAVE_PIMEM, - SDM845_SLAVE_QDSS_STM - }, + .link_nodes = { &qhs_apss, + &qns_cnoc, + &qns_memnoc_sf, + &qxs_imem, + &qxs_pimem, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SDM845_MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 9, - .links = { SDM845_SLAVE_APPSS, - SDM845_SLAVE_SNOC_CNOC, - SDM845_SLAVE_SNOC_MEM_NOC_SF, - SDM845_SLAVE_IMEM, - SDM845_SLAVE_PCIE_0, - SDM845_SLAVE_PCIE_1, - SDM845_SLAVE_PIMEM, - SDM845_SLAVE_QDSS_STM, - SDM845_SLAVE_TCU - }, + .link_nodes = { &qhs_apss, + &qns_cnoc, + &qns_memnoc_sf, + &qxs_imem, + &qxs_pcie, + &qxs_pcie_gen3, + &qxs_pimem, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gladiator_sodv = { .name = "qnm_gladiator_sodv", - .id = SDM845_MASTER_GNOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 8, - .links = { SDM845_SLAVE_APPSS, - SDM845_SLAVE_SNOC_CNOC, - SDM845_SLAVE_IMEM, - SDM845_SLAVE_PCIE_0, - SDM845_SLAVE_PCIE_1, - SDM845_SLAVE_PIMEM, - SDM845_SLAVE_QDSS_STM, - SDM845_SLAVE_TCU - }, + .link_nodes = { &qhs_apss, + &qns_cnoc, + &qxs_imem, + &qxs_pcie, + &qxs_pcie_gen3, + &qxs_pimem, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_memnoc = { .name = "qnm_memnoc", - .id = SDM845_MASTER_MEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 5, - .links = { SDM845_SLAVE_APPSS, - SDM845_SLAVE_SNOC_CNOC, - SDM845_SLAVE_IMEM, - SDM845_SLAVE_PIMEM, - SDM845_SLAVE_QDSS_STM - }, + .link_nodes = { &qhs_apss, + &qns_cnoc, + &qxs_imem, + &qxs_pimem, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_pcie_anoc = { .name = "qnm_pcie_anoc", - .id = SDM845_MASTER_ANOC_PCIE_SNOC, .channels = 1, .buswidth = 16, .num_links = 5, - .links = { SDM845_SLAVE_APPSS, - SDM845_SLAVE_SNOC_CNOC, - SDM845_SLAVE_SNOC_MEM_NOC_SF, - SDM845_SLAVE_IMEM, - SDM845_SLAVE_QDSS_STM - }, + .link_nodes = { &qhs_apss, + &qns_cnoc, + &qns_memnoc_sf, + &qxs_imem, + &xs_qdss_stm }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = SDM845_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SDM845_SLAVE_SNOC_MEM_NOC_GC, - SDM845_SLAVE_IMEM - }, + .link_nodes = { &qns_memnoc_gc, + &qxs_imem }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SDM845_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SDM845_SLAVE_SNOC_MEM_NOC_GC, - SDM845_SLAVE_IMEM - }, + .link_nodes = { &qns_memnoc_gc, + &qxs_imem }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SDM845_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDM845_MASTER_A1NOC_SNOC }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node srvc_aggre1_noc = { .name = "srvc_aggre1_noc", - .id = SDM845_SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4, - .num_links = 1, - .links = { 0 }, }; static struct qcom_icc_node qns_pcie_a1noc_snoc = { .name = "qns_pcie_a1noc_snoc", - .id = SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDM845_MASTER_ANOC_PCIE_SNOC }, + .link_nodes = { &qnm_pcie_anoc }, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SDM845_SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDM845_MASTER_A2NOC_SNOC }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qns_pcie_snoc = { .name = "qns_pcie_snoc", - .id = SDM845_SLAVE_ANOC_PCIE_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDM845_MASTER_ANOC_PCIE_SNOC }, + .link_nodes = { &qnm_pcie_anoc }, }; static struct qcom_icc_node srvc_aggre2_noc = { .name = "srvc_aggre2_noc", - .id = SDM845_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_camnoc_uncomp = { .name = "qns_camnoc_uncomp", - .id = SDM845_SLAVE_CAMNOC_UNCOMP, .channels = 1, .buswidth = 32, }; static struct qcom_icc_node qhs_a1_noc_cfg = { .name = "qhs_a1_noc_cfg", - .id = SDM845_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_MASTER_A1NOC_CFG }, + .link_nodes = { &qhm_a1noc_cfg }, }; static struct qcom_icc_node qhs_a2_noc_cfg = { .name = "qhs_a2_noc_cfg", - .id = SDM845_SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_MASTER_A2NOC_CFG }, + .link_nodes = { &qhm_a2noc_cfg }, }; static struct qcom_icc_node qhs_aop = { .name = "qhs_aop", - .id = SDM845_SLAVE_AOP, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SDM845_SLAVE_AOSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SDM845_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SDM845_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_compute_dsp_cfg = { .name = "qhs_compute_dsp_cfg", - .id = SDM845_SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SDM845_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SDM845_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dcc_cfg = { .name = "qhs_dcc_cfg", - .id = SDM845_SLAVE_DCC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_MASTER_CNOC_DC_NOC }, + .link_nodes = { &qhm_cnoc }, }; static struct qcom_icc_node qhs_ddrss_cfg = { .name = "qhs_ddrss_cfg", - .id = SDM845_SLAVE_CNOC_DDRSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SDM845_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_glm = { .name = "qhs_glm", - .id = SDM845_SLAVE_GLM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SDM845_SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SDM845_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SDM845_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mnoc_cfg = { .name = "qhs_mnoc_cfg", - .id = SDM845_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qhm_mnoc_cfg }, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = SDM845_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie_gen3_cfg = { .name = "qhs_pcie_gen3_cfg", - .id = SDM845_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SDM845_SLAVE_PDM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_phy_refgen_south = { .name = "qhs_phy_refgen_south", - .id = SDM845_SLAVE_SOUTH_PHY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SDM845_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SDM845_SLAVE_PRNG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SDM845_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qupv3_north = { .name = "qhs_qupv3_north", - .id = SDM845_SLAVE_BLSP_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qupv3_south = { .name = "qhs_qupv3_south", - .id = SDM845_SLAVE_BLSP_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SDM845_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SDM845_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_snoc_cfg = { .name = "qhs_snoc_cfg", - .id = SDM845_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_MASTER_SNOC_CFG }, + .link_nodes = { &qhm_snoc_cfg }, }; static struct qcom_icc_node qhs_spdm = { .name = "qhs_spdm", - .id = SDM845_SLAVE_SPDM_WRAPPER, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_spss_cfg = { .name = "qhs_spss_cfg", - .id = SDM845_SLAVE_SPSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SDM845_SLAVE_TCSR, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_north = { .name = "qhs_tlmm_north", - .id = SDM845_SLAVE_TLMM_NORTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_south = { .name = "qhs_tlmm_south", - .id = SDM845_SLAVE_TLMM_SOUTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tsif = { .name = "qhs_tsif", - .id = SDM845_SLAVE_TSIF, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_card_cfg = { .name = "qhs_ufs_card_cfg", - .id = SDM845_SLAVE_UFS_CARD_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SDM845_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SDM845_SLAVE_USB3_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_1 = { .name = "qhs_usb3_1", - .id = SDM845_SLAVE_USB3_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SDM845_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SDM845_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_cnoc_a2noc = { .name = "qns_cnoc_a2noc", - .id = SDM845_SLAVE_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_MASTER_CNOC_A2NOC }, + .link_nodes = { &qnm_cnoc }, }; static struct qcom_icc_node srvc_cnoc = { .name = "srvc_cnoc", - .id = SDM845_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_llcc = { .name = "qhs_llcc", - .id = SDM845_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_memnoc = { .name = "qhs_memnoc", - .id = SDM845_SLAVE_MEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDM845_MASTER_MEM_NOC_CFG }, + .link_nodes = { &qhm_memnoc_cfg }, }; static struct qcom_icc_node qns_gladiator_sodv = { .name = "qns_gladiator_sodv", - .id = SDM845_SLAVE_GNOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_MASTER_GNOC_SNOC }, + .link_nodes = { &qnm_gladiator_sodv }, }; static struct qcom_icc_node qns_gnoc_memnoc = { .name = "qns_gnoc_memnoc", - .id = SDM845_SLAVE_GNOC_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SDM845_MASTER_GNOC_MEM_NOC }, + .link_nodes = { &qnm_apps }, }; static struct qcom_icc_node srvc_gnoc = { .name = "srvc_gnoc", - .id = SDM845_SLAVE_SERVICE_GNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SDM845_SLAVE_EBI1, .channels = 4, .buswidth = 4, }; static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { .name = "qhs_mdsp_ms_mpu_cfg", - .id = SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_apps_io = { .name = "qns_apps_io", - .id = SDM845_SLAVE_MEM_NOC_GNOC, .channels = 1, .buswidth = 32, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SDM845_SLAVE_LLCC, .channels = 4, .buswidth = 16, .num_links = 1, - .links = { SDM845_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_memnoc_snoc = { .name = "qns_memnoc_snoc", - .id = SDM845_SLAVE_MEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_MASTER_MEM_NOC_SNOC }, + .link_nodes = { &qnm_memnoc }, }; static struct qcom_icc_node srvc_memnoc = { .name = "srvc_memnoc", - .id = SDM845_SLAVE_SERVICE_MEM_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns2_mem_noc = { .name = "qns2_mem_noc", - .id = SDM845_SLAVE_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SDM845_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SDM845_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SDM845_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SDM845_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SDM845_SLAVE_APPSS, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qns_cnoc = { .name = "qns_cnoc", - .id = SDM845_SLAVE_SNOC_CNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_MASTER_SNOC_CNOC }, + .link_nodes = { &qnm_snoc }, }; static struct qcom_icc_node qns_memnoc_gc = { .name = "qns_memnoc_gc", - .id = SDM845_SLAVE_SNOC_MEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDM845_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_memnoc_sf = { .name = "qns_memnoc_sf", - .id = SDM845_SLAVE_SNOC_MEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDM845_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SDM845_SLAVE_IMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_pcie = { .name = "qxs_pcie", - .id = SDM845_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_pcie_gen3 = { .name = "qxs_pcie_gen3", - .id = SDM845_SLAVE_PCIE_1, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = SDM845_SLAVE_PIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SDM845_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SDM845_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SDM845_SLAVE_TCU, .channels = 1, .buswidth = 8, }; @@ -1802,7 +1782,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove_new = qcom_icc_rpmh_remove, + .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sdm845", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sdm845.h b/drivers/interconnect/qcom/sdm845.h deleted file mode 100644 index bc7e425ce985..000000000000 --- a/drivers/interconnect/qcom/sdm845.h +++ /dev/null @@ -1,140 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SDM845_H__ -#define __DRIVERS_INTERCONNECT_QCOM_SDM845_H__ - -#define SDM845_MASTER_A1NOC_CFG 1 -#define SDM845_MASTER_BLSP_1 2 -#define SDM845_MASTER_TSIF 3 -#define SDM845_MASTER_SDCC_2 4 -#define SDM845_MASTER_SDCC_4 5 -#define SDM845_MASTER_UFS_CARD 6 -#define SDM845_MASTER_UFS_MEM 7 -#define SDM845_MASTER_PCIE_0 8 -#define SDM845_MASTER_A2NOC_CFG 9 -#define SDM845_MASTER_QDSS_BAM 10 -#define SDM845_MASTER_BLSP_2 11 -#define SDM845_MASTER_CNOC_A2NOC 12 -#define SDM845_MASTER_CRYPTO 13 -#define SDM845_MASTER_IPA 14 -#define SDM845_MASTER_PCIE_1 15 -#define SDM845_MASTER_QDSS_ETR 16 -#define SDM845_MASTER_USB3_0 17 -#define SDM845_MASTER_USB3_1 18 -#define SDM845_MASTER_CAMNOC_HF0_UNCOMP 19 -#define SDM845_MASTER_CAMNOC_HF1_UNCOMP 20 -#define SDM845_MASTER_CAMNOC_SF_UNCOMP 21 -#define SDM845_MASTER_SPDM 22 -#define SDM845_MASTER_TIC 23 -#define SDM845_MASTER_SNOC_CNOC 24 -#define SDM845_MASTER_QDSS_DAP 25 -#define SDM845_MASTER_CNOC_DC_NOC 26 -#define SDM845_MASTER_APPSS_PROC 27 -#define SDM845_MASTER_GNOC_CFG 28 -#define SDM845_MASTER_LLCC 29 -#define SDM845_MASTER_TCU_0 30 -#define SDM845_MASTER_MEM_NOC_CFG 31 -#define SDM845_MASTER_GNOC_MEM_NOC 32 -#define SDM845_MASTER_MNOC_HF_MEM_NOC 33 -#define SDM845_MASTER_MNOC_SF_MEM_NOC 34 -#define SDM845_MASTER_SNOC_GC_MEM_NOC 35 -#define SDM845_MASTER_SNOC_SF_MEM_NOC 36 -#define SDM845_MASTER_GFX3D 37 -#define SDM845_MASTER_CNOC_MNOC_CFG 38 -#define SDM845_MASTER_CAMNOC_HF0 39 -#define SDM845_MASTER_CAMNOC_HF1 40 -#define SDM845_MASTER_CAMNOC_SF 41 -#define SDM845_MASTER_MDP0 42 -#define SDM845_MASTER_MDP1 43 -#define SDM845_MASTER_ROTATOR 44 -#define SDM845_MASTER_VIDEO_P0 45 -#define SDM845_MASTER_VIDEO_P1 46 -#define SDM845_MASTER_VIDEO_PROC 47 -#define SDM845_MASTER_SNOC_CFG 48 -#define SDM845_MASTER_A1NOC_SNOC 49 -#define SDM845_MASTER_A2NOC_SNOC 50 -#define SDM845_MASTER_GNOC_SNOC 51 -#define SDM845_MASTER_MEM_NOC_SNOC 52 -#define SDM845_MASTER_ANOC_PCIE_SNOC 53 -#define SDM845_MASTER_PIMEM 54 -#define SDM845_MASTER_GIC 55 -#define SDM845_SLAVE_A1NOC_SNOC 56 -#define SDM845_SLAVE_SERVICE_A1NOC 57 -#define SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC 58 -#define SDM845_SLAVE_A2NOC_SNOC 59 -#define SDM845_SLAVE_ANOC_PCIE_SNOC 60 -#define SDM845_SLAVE_SERVICE_A2NOC 61 -#define SDM845_SLAVE_CAMNOC_UNCOMP 62 -#define SDM845_SLAVE_A1NOC_CFG 63 -#define SDM845_SLAVE_A2NOC_CFG 64 -#define SDM845_SLAVE_AOP 65 -#define SDM845_SLAVE_AOSS 66 -#define SDM845_SLAVE_CAMERA_CFG 67 -#define SDM845_SLAVE_CLK_CTL 68 -#define SDM845_SLAVE_CDSP_CFG 69 -#define SDM845_SLAVE_RBCPR_CX_CFG 70 -#define SDM845_SLAVE_CRYPTO_0_CFG 71 -#define SDM845_SLAVE_DCC_CFG 72 -#define SDM845_SLAVE_CNOC_DDRSS 73 -#define SDM845_SLAVE_DISPLAY_CFG 74 -#define SDM845_SLAVE_GLM 75 -#define SDM845_SLAVE_GFX3D_CFG 76 -#define SDM845_SLAVE_IMEM_CFG 77 -#define SDM845_SLAVE_IPA_CFG 78 -#define SDM845_SLAVE_CNOC_MNOC_CFG 79 -#define SDM845_SLAVE_PCIE_0_CFG 80 -#define SDM845_SLAVE_PCIE_1_CFG 81 -#define SDM845_SLAVE_PDM 82 -#define SDM845_SLAVE_SOUTH_PHY_CFG 83 -#define SDM845_SLAVE_PIMEM_CFG 84 -#define SDM845_SLAVE_PRNG 85 -#define SDM845_SLAVE_QDSS_CFG 86 -#define SDM845_SLAVE_BLSP_2 87 -#define SDM845_SLAVE_BLSP_1 88 -#define SDM845_SLAVE_SDCC_2 89 -#define SDM845_SLAVE_SDCC_4 90 -#define SDM845_SLAVE_SNOC_CFG 91 -#define SDM845_SLAVE_SPDM_WRAPPER 92 -#define SDM845_SLAVE_SPSS_CFG 93 -#define SDM845_SLAVE_TCSR 94 -#define SDM845_SLAVE_TLMM_NORTH 95 -#define SDM845_SLAVE_TLMM_SOUTH 96 -#define SDM845_SLAVE_TSIF 97 -#define SDM845_SLAVE_UFS_CARD_CFG 98 -#define SDM845_SLAVE_UFS_MEM_CFG 99 -#define SDM845_SLAVE_USB3_0 100 -#define SDM845_SLAVE_USB3_1 101 -#define SDM845_SLAVE_VENUS_CFG 102 -#define SDM845_SLAVE_VSENSE_CTRL_CFG 103 -#define SDM845_SLAVE_CNOC_A2NOC 104 -#define SDM845_SLAVE_SERVICE_CNOC 105 -#define SDM845_SLAVE_LLCC_CFG 106 -#define SDM845_SLAVE_MEM_NOC_CFG 107 -#define SDM845_SLAVE_GNOC_SNOC 108 -#define SDM845_SLAVE_GNOC_MEM_NOC 109 -#define SDM845_SLAVE_SERVICE_GNOC 110 -#define SDM845_SLAVE_EBI1 111 -#define SDM845_SLAVE_MSS_PROC_MS_MPU_CFG 112 -#define SDM845_SLAVE_MEM_NOC_GNOC 113 -#define SDM845_SLAVE_LLCC 114 -#define SDM845_SLAVE_MEM_NOC_SNOC 115 -#define SDM845_SLAVE_SERVICE_MEM_NOC 116 -#define SDM845_SLAVE_MNOC_SF_MEM_NOC 117 -#define SDM845_SLAVE_MNOC_HF_MEM_NOC 118 -#define SDM845_SLAVE_SERVICE_MNOC 119 -#define SDM845_SLAVE_APPSS 120 -#define SDM845_SLAVE_SNOC_CNOC 121 -#define SDM845_SLAVE_SNOC_MEM_NOC_GC 122 -#define SDM845_SLAVE_SNOC_MEM_NOC_SF 123 -#define SDM845_SLAVE_IMEM 124 -#define SDM845_SLAVE_PCIE_0 125 -#define SDM845_SLAVE_PCIE_1 126 -#define SDM845_SLAVE_PIMEM 127 -#define SDM845_SLAVE_SERVICE_SNOC 128 -#define SDM845_SLAVE_QDSS_STM 129 -#define SDM845_SLAVE_TCU 130 - -#endif /* __DRIVERS_INTERCONNECT_QCOM_SDM845_H__ */ diff --git a/drivers/interconnect/qcom/sdx55.c b/drivers/interconnect/qcom/sdx55.c index e97f28b8d2b2..75ced1286919 100644 --- a/drivers/interconnect/qcom/sdx55.c +++ b/drivers/interconnect/qcom/sdx55.c @@ -17,628 +17,617 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sdx55.h" + +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node acm_tcu; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node xm_apps_rdwr; +static struct qcom_icc_node qhm_audio; +static struct qcom_icc_node qhm_blsp1; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qpic; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qhm_spmi_fetcher1; +static struct qcom_icc_node qnm_aggre_noc; +static struct qcom_icc_node qnm_ipa; +static struct qcom_icc_node qnm_memnoc; +static struct qcom_icc_node qnm_memnoc_pcie; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node xm_emac; +static struct qcom_icc_node xm_ipa2pcie_slv; +static struct qcom_icc_node xm_pcie; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_usb3; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_memnoc_snoc; +static struct qcom_icc_node qns_sys_pcie; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qhs_audio; +static struct qcom_icc_node qhs_blsp1; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_ecc_cfg; +static struct qcom_icc_node qhs_emac_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_pcie_parf; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qpic; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spmi_fetcher; +static struct qcom_icc_node qhs_spmi_vgi_coex; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_usb3; +static struct qcom_icc_node qhs_usb3_phy; +static struct qcom_icc_node qns_aggre_noc; +static struct qcom_icc_node qns_snoc_memnoc; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_pcie; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SDX55_MASTER_LLCC, .channels = 4, .buswidth = 4, .num_links = 1, - .links = { SDX55_SLAVE_EBI_CH0 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node acm_tcu = { .name = "acm_tcu", - .id = SDX55_MASTER_TCU_0, .channels = 1, .buswidth = 8, .num_links = 3, - .links = { SDX55_SLAVE_LLCC, - SDX55_SLAVE_MEM_NOC_SNOC, - SDX55_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_memnoc_snoc, + &qns_sys_pcie }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SDX55_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX55_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node xm_apps_rdwr = { .name = "xm_apps_rdwr", - .id = SDX55_MASTER_AMPSS_M0, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SDX55_SLAVE_LLCC, - SDX55_SLAVE_MEM_NOC_SNOC, - SDX55_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_memnoc_snoc, + &qns_sys_pcie }, }; static struct qcom_icc_node qhm_audio = { .name = "qhm_audio", - .id = SDX55_MASTER_AUDIO, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX55_SLAVE_ANOC_SNOC }, + .link_nodes = { &qns_aggre_noc }, }; static struct qcom_icc_node qhm_blsp1 = { .name = "qhm_blsp1", - .id = SDX55_MASTER_BLSP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX55_SLAVE_ANOC_SNOC }, + .link_nodes = { &qns_aggre_noc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SDX55_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 28, - .links = { SDX55_SLAVE_SNOC_CFG, - SDX55_SLAVE_EMAC_CFG, - SDX55_SLAVE_USB3, - SDX55_SLAVE_TLMM, - SDX55_SLAVE_SPMI_FETCHER, - SDX55_SLAVE_QDSS_CFG, - SDX55_SLAVE_PDM, - SDX55_SLAVE_SNOC_MEM_NOC_GC, - SDX55_SLAVE_TCSR, - SDX55_SLAVE_CNOC_DDRSS, - SDX55_SLAVE_SPMI_VGI_COEX, - SDX55_SLAVE_QPIC, - SDX55_SLAVE_OCIMEM, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_USB3_PHY_CFG, - SDX55_SLAVE_AOP, - SDX55_SLAVE_BLSP_1, - SDX55_SLAVE_SDCC_1, - SDX55_SLAVE_CNOC_MSS, - SDX55_SLAVE_PCIE_PARF, - SDX55_SLAVE_ECC_CFG, - SDX55_SLAVE_AUDIO, - SDX55_SLAVE_AOSS, - SDX55_SLAVE_PRNG, - SDX55_SLAVE_CRYPTO_0_CFG, - SDX55_SLAVE_TCU, - SDX55_SLAVE_CLK_CTL, - SDX55_SLAVE_IMEM_CFG - }, + .link_nodes = { &qhs_snoc_cfg, + &qhs_emac_cfg, + &qhs_usb3, + &qhs_tlmm, + &qhs_spmi_fetcher, + &qhs_qdss_cfg, + &qhs_pdm, + &qns_snoc_memnoc, + &qhs_tcsr, + &qhs_ddrss_cfg, + &qhs_spmi_vgi_coex, + &qhs_qpic, + &qxs_imem, + &qhs_ipa, + &qhs_usb3_phy, + &qhs_aop, + &qhs_blsp1, + &qhs_sdc1, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_ecc_cfg, + &qhs_audio, + &qhs_aoss, + &qhs_prng, + &qhs_crypto0_cfg, + &xs_sys_tcu_cfg, + &qhs_clk_ctl, + &qhs_imem_cfg }, }; static struct qcom_icc_node qhm_qpic = { .name = "qhm_qpic", - .id = SDX55_MASTER_QPIC, .channels = 1, .buswidth = 4, .num_links = 5, - .links = { SDX55_SLAVE_AOSS, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_ANOC_SNOC, - SDX55_SLAVE_AOP, - SDX55_SLAVE_AUDIO - }, + .link_nodes = { &qhs_aoss, + &qhs_ipa, + &qns_aggre_noc, + &qhs_aop, + &qhs_audio }, }; static struct qcom_icc_node qhm_snoc_cfg = { .name = "qhm_snoc_cfg", - .id = SDX55_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX55_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qhm_spmi_fetcher1 = { .name = "qhm_spmi_fetcher1", - .id = SDX55_MASTER_SPMI_FETCHER, .channels = 1, .buswidth = 4, .num_links = 3, - .links = { SDX55_SLAVE_AOSS, - SDX55_SLAVE_ANOC_SNOC, - SDX55_SLAVE_AOP - }, + .link_nodes = { &qhs_aoss, + &qns_aggre_noc, + &qhs_aop }, }; static struct qcom_icc_node qnm_aggre_noc = { .name = "qnm_aggre_noc", - .id = SDX55_MASTER_ANOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 30, - .links = { SDX55_SLAVE_PCIE_0, - SDX55_SLAVE_SNOC_CFG, - SDX55_SLAVE_SDCC_1, - SDX55_SLAVE_TLMM, - SDX55_SLAVE_SPMI_FETCHER, - SDX55_SLAVE_QDSS_CFG, - SDX55_SLAVE_PDM, - SDX55_SLAVE_SNOC_MEM_NOC_GC, - SDX55_SLAVE_TCSR, - SDX55_SLAVE_CNOC_DDRSS, - SDX55_SLAVE_SPMI_VGI_COEX, - SDX55_SLAVE_QDSS_STM, - SDX55_SLAVE_QPIC, - SDX55_SLAVE_OCIMEM, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_USB3_PHY_CFG, - SDX55_SLAVE_AOP, - SDX55_SLAVE_BLSP_1, - SDX55_SLAVE_USB3, - SDX55_SLAVE_CNOC_MSS, - SDX55_SLAVE_PCIE_PARF, - SDX55_SLAVE_ECC_CFG, - SDX55_SLAVE_APPSS, - SDX55_SLAVE_AUDIO, - SDX55_SLAVE_AOSS, - SDX55_SLAVE_PRNG, - SDX55_SLAVE_CRYPTO_0_CFG, - SDX55_SLAVE_TCU, - SDX55_SLAVE_CLK_CTL, - SDX55_SLAVE_IMEM_CFG - }, + .link_nodes = { &xs_pcie, + &qhs_snoc_cfg, + &qhs_sdc1, + &qhs_tlmm, + &qhs_spmi_fetcher, + &qhs_qdss_cfg, + &qhs_pdm, + &qns_snoc_memnoc, + &qhs_tcsr, + &qhs_ddrss_cfg, + &qhs_spmi_vgi_coex, + &xs_qdss_stm, + &qhs_qpic, + &qxs_imem, + &qhs_ipa, + &qhs_usb3_phy, + &qhs_aop, + &qhs_blsp1, + &qhs_usb3, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_ecc_cfg, + &qhs_apss, + &qhs_audio, + &qhs_aoss, + &qhs_prng, + &qhs_crypto0_cfg, + &xs_sys_tcu_cfg, + &qhs_clk_ctl, + &qhs_imem_cfg }, }; static struct qcom_icc_node qnm_ipa = { .name = "qnm_ipa", - .id = SDX55_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 27, - .links = { SDX55_SLAVE_SNOC_CFG, - SDX55_SLAVE_EMAC_CFG, - SDX55_SLAVE_USB3, - SDX55_SLAVE_AOSS, - SDX55_SLAVE_SPMI_FETCHER, - SDX55_SLAVE_QDSS_CFG, - SDX55_SLAVE_PDM, - SDX55_SLAVE_SNOC_MEM_NOC_GC, - SDX55_SLAVE_TCSR, - SDX55_SLAVE_CNOC_DDRSS, - SDX55_SLAVE_QDSS_STM, - SDX55_SLAVE_QPIC, - SDX55_SLAVE_OCIMEM, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_USB3_PHY_CFG, - SDX55_SLAVE_AOP, - SDX55_SLAVE_BLSP_1, - SDX55_SLAVE_SDCC_1, - SDX55_SLAVE_CNOC_MSS, - SDX55_SLAVE_PCIE_PARF, - SDX55_SLAVE_ECC_CFG, - SDX55_SLAVE_AUDIO, - SDX55_SLAVE_TLMM, - SDX55_SLAVE_PRNG, - SDX55_SLAVE_CRYPTO_0_CFG, - SDX55_SLAVE_CLK_CTL, - SDX55_SLAVE_IMEM_CFG - }, + .link_nodes = { &qhs_snoc_cfg, + &qhs_emac_cfg, + &qhs_usb3, + &qhs_aoss, + &qhs_spmi_fetcher, + &qhs_qdss_cfg, + &qhs_pdm, + &qns_snoc_memnoc, + &qhs_tcsr, + &qhs_ddrss_cfg, + &xs_qdss_stm, + &qhs_qpic, + &qxs_imem, + &qhs_ipa, + &qhs_usb3_phy, + &qhs_aop, + &qhs_blsp1, + &qhs_sdc1, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_ecc_cfg, + &qhs_audio, + &qhs_tlmm, + &qhs_prng, + &qhs_crypto0_cfg, + &qhs_clk_ctl, + &qhs_imem_cfg }, }; static struct qcom_icc_node qnm_memnoc = { .name = "qnm_memnoc", - .id = SDX55_MASTER_MEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 29, - .links = { SDX55_SLAVE_SNOC_CFG, - SDX55_SLAVE_EMAC_CFG, - SDX55_SLAVE_USB3, - SDX55_SLAVE_TLMM, - SDX55_SLAVE_SPMI_FETCHER, - SDX55_SLAVE_QDSS_CFG, - SDX55_SLAVE_PDM, - SDX55_SLAVE_TCSR, - SDX55_SLAVE_CNOC_DDRSS, - SDX55_SLAVE_SPMI_VGI_COEX, - SDX55_SLAVE_QDSS_STM, - SDX55_SLAVE_QPIC, - SDX55_SLAVE_OCIMEM, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_USB3_PHY_CFG, - SDX55_SLAVE_AOP, - SDX55_SLAVE_BLSP_1, - SDX55_SLAVE_SDCC_1, - SDX55_SLAVE_CNOC_MSS, - SDX55_SLAVE_PCIE_PARF, - SDX55_SLAVE_ECC_CFG, - SDX55_SLAVE_APPSS, - SDX55_SLAVE_AUDIO, - SDX55_SLAVE_AOSS, - SDX55_SLAVE_PRNG, - SDX55_SLAVE_CRYPTO_0_CFG, - SDX55_SLAVE_TCU, - SDX55_SLAVE_CLK_CTL, - SDX55_SLAVE_IMEM_CFG - }, + .link_nodes = { &qhs_snoc_cfg, + &qhs_emac_cfg, + &qhs_usb3, + &qhs_tlmm, + &qhs_spmi_fetcher, + &qhs_qdss_cfg, + &qhs_pdm, + &qhs_tcsr, + &qhs_ddrss_cfg, + &qhs_spmi_vgi_coex, + &xs_qdss_stm, + &qhs_qpic, + &qxs_imem, + &qhs_ipa, + &qhs_usb3_phy, + &qhs_aop, + &qhs_blsp1, + &qhs_sdc1, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_ecc_cfg, + &qhs_apss, + &qhs_audio, + &qhs_aoss, + &qhs_prng, + &qhs_crypto0_cfg, + &xs_sys_tcu_cfg, + &qhs_clk_ctl, + &qhs_imem_cfg }, }; static struct qcom_icc_node qnm_memnoc_pcie = { .name = "qnm_memnoc_pcie", - .id = SDX55_MASTER_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX55_SLAVE_PCIE_0 }, + .link_nodes = { &xs_pcie }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SDX55_MASTER_CRYPTO_CORE_0, .channels = 1, .buswidth = 8, .num_links = 3, - .links = { SDX55_SLAVE_AOSS, - SDX55_SLAVE_ANOC_SNOC, - SDX55_SLAVE_AOP - }, + .link_nodes = { &qhs_aoss, + &qns_aggre_noc, + &qhs_aop }, }; static struct qcom_icc_node xm_emac = { .name = "xm_emac", - .id = SDX55_MASTER_EMAC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX55_SLAVE_ANOC_SNOC }, + .link_nodes = { &qns_aggre_noc }, }; static struct qcom_icc_node xm_ipa2pcie_slv = { .name = "xm_ipa2pcie_slv", - .id = SDX55_MASTER_IPA_PCIE, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX55_SLAVE_PCIE_0 }, + .link_nodes = { &xs_pcie }, }; static struct qcom_icc_node xm_pcie = { .name = "xm_pcie", - .id = SDX55_MASTER_PCIE, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX55_SLAVE_ANOC_SNOC }, + .link_nodes = { &qns_aggre_noc }, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = SDX55_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 28, - .links = { SDX55_SLAVE_SNOC_CFG, - SDX55_SLAVE_EMAC_CFG, - SDX55_SLAVE_USB3, - SDX55_SLAVE_AOSS, - SDX55_SLAVE_SPMI_FETCHER, - SDX55_SLAVE_QDSS_CFG, - SDX55_SLAVE_PDM, - SDX55_SLAVE_SNOC_MEM_NOC_GC, - SDX55_SLAVE_TCSR, - SDX55_SLAVE_CNOC_DDRSS, - SDX55_SLAVE_SPMI_VGI_COEX, - SDX55_SLAVE_QPIC, - SDX55_SLAVE_OCIMEM, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_USB3_PHY_CFG, - SDX55_SLAVE_AOP, - SDX55_SLAVE_BLSP_1, - SDX55_SLAVE_SDCC_1, - SDX55_SLAVE_CNOC_MSS, - SDX55_SLAVE_PCIE_PARF, - SDX55_SLAVE_ECC_CFG, - SDX55_SLAVE_AUDIO, - SDX55_SLAVE_AOSS, - SDX55_SLAVE_PRNG, - SDX55_SLAVE_CRYPTO_0_CFG, - SDX55_SLAVE_TCU, - SDX55_SLAVE_CLK_CTL, - SDX55_SLAVE_IMEM_CFG - }, + .link_nodes = { &qhs_snoc_cfg, + &qhs_emac_cfg, + &qhs_usb3, + &qhs_aoss, + &qhs_spmi_fetcher, + &qhs_qdss_cfg, + &qhs_pdm, + &qns_snoc_memnoc, + &qhs_tcsr, + &qhs_ddrss_cfg, + &qhs_spmi_vgi_coex, + &qhs_qpic, + &qxs_imem, + &qhs_ipa, + &qhs_usb3_phy, + &qhs_aop, + &qhs_blsp1, + &qhs_sdc1, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_ecc_cfg, + &qhs_audio, + &qhs_aoss, + &qhs_prng, + &qhs_crypto0_cfg, + &xs_sys_tcu_cfg, + &qhs_clk_ctl, + &qhs_imem_cfg }, }; static struct qcom_icc_node xm_sdc1 = { .name = "xm_sdc1", - .id = SDX55_MASTER_SDCC_1, .channels = 1, .buswidth = 8, .num_links = 5, - .links = { SDX55_SLAVE_AOSS, - SDX55_SLAVE_IPA_CFG, - SDX55_SLAVE_ANOC_SNOC, - SDX55_SLAVE_AOP, - SDX55_SLAVE_AUDIO - }, + .link_nodes = { &qhs_aoss, + &qhs_ipa, + &qns_aggre_noc, + &qhs_aop, + &qhs_audio }, }; static struct qcom_icc_node xm_usb3 = { .name = "xm_usb3", - .id = SDX55_MASTER_USB3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX55_SLAVE_ANOC_SNOC }, + .link_nodes = { &qns_aggre_noc }, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SDX55_SLAVE_EBI_CH0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SDX55_SLAVE_LLCC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDX55_SLAVE_EBI_CH0 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qns_memnoc_snoc = { .name = "qns_memnoc_snoc", - .id = SDX55_SLAVE_MEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX55_MASTER_MEM_NOC_SNOC }, + .link_nodes = { &qnm_memnoc }, }; static struct qcom_icc_node qns_sys_pcie = { .name = "qns_sys_pcie", - .id = SDX55_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX55_MASTER_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_memnoc_pcie }, }; static struct qcom_icc_node qhs_aop = { .name = "qhs_aop", - .id = SDX55_SLAVE_AOP, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SDX55_SLAVE_AOSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SDX55_SLAVE_APPSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_audio = { .name = "qhs_audio", - .id = SDX55_SLAVE_AUDIO, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_blsp1 = { .name = "qhs_blsp1", - .id = SDX55_SLAVE_BLSP_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SDX55_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SDX55_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ddrss_cfg = { .name = "qhs_ddrss_cfg", - .id = SDX55_SLAVE_CNOC_DDRSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ecc_cfg = { .name = "qhs_ecc_cfg", - .id = SDX55_SLAVE_ECC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_emac_cfg = { .name = "qhs_emac_cfg", - .id = SDX55_SLAVE_EMAC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SDX55_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SDX55_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", - .id = SDX55_SLAVE_CNOC_MSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie_parf = { .name = "qhs_pcie_parf", - .id = SDX55_SLAVE_PCIE_PARF, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SDX55_SLAVE_PDM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SDX55_SLAVE_PRNG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SDX55_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qpic = { .name = "qhs_qpic", - .id = SDX55_SLAVE_QPIC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc1 = { .name = "qhs_sdc1", - .id = SDX55_SLAVE_SDCC_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_snoc_cfg = { .name = "qhs_snoc_cfg", - .id = SDX55_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX55_MASTER_SNOC_CFG }, + .link_nodes = { &qhm_snoc_cfg }, }; static struct qcom_icc_node qhs_spmi_fetcher = { .name = "qhs_spmi_fetcher", - .id = SDX55_SLAVE_SPMI_FETCHER, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_spmi_vgi_coex = { .name = "qhs_spmi_vgi_coex", - .id = SDX55_SLAVE_SPMI_VGI_COEX, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SDX55_SLAVE_TCSR, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = SDX55_SLAVE_TLMM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3 = { .name = "qhs_usb3", - .id = SDX55_SLAVE_USB3, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_phy = { .name = "qhs_usb3_phy", - .id = SDX55_SLAVE_USB3_PHY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_aggre_noc = { .name = "qns_aggre_noc", - .id = SDX55_SLAVE_ANOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX55_MASTER_ANOC_SNOC }, + .link_nodes = { &qnm_aggre_noc }, }; static struct qcom_icc_node qns_snoc_memnoc = { .name = "qns_snoc_memnoc", - .id = SDX55_SLAVE_SNOC_MEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX55_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SDX55_SLAVE_OCIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SDX55_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_pcie = { .name = "xs_pcie", - .id = SDX55_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SDX55_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SDX55_SLAVE_TCU, .channels = 1, .buswidth = 8, }; @@ -913,7 +902,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove_new = qcom_icc_rpmh_remove, + .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sdx55", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sdx55.h b/drivers/interconnect/qcom/sdx55.h deleted file mode 100644 index 46cbabec8aa1..000000000000 --- a/drivers/interconnect/qcom/sdx55.h +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2021, Linaro Ltd. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX55_H -#define __DRIVERS_INTERCONNECT_QCOM_SDX55_H - -/* 0 was used by MASTER_IPA_CORE, now represented as RPMh clock */ -#define SDX55_MASTER_LLCC 1 -#define SDX55_MASTER_TCU_0 2 -#define SDX55_MASTER_SNOC_GC_MEM_NOC 3 -#define SDX55_MASTER_AMPSS_M0 4 -#define SDX55_MASTER_AUDIO 5 -#define SDX55_MASTER_BLSP_1 6 -#define SDX55_MASTER_QDSS_BAM 7 -#define SDX55_MASTER_QPIC 8 -#define SDX55_MASTER_SNOC_CFG 9 -#define SDX55_MASTER_SPMI_FETCHER 10 -#define SDX55_MASTER_ANOC_SNOC 11 -#define SDX55_MASTER_IPA 12 -#define SDX55_MASTER_MEM_NOC_SNOC 13 -#define SDX55_MASTER_MEM_NOC_PCIE_SNOC 14 -#define SDX55_MASTER_CRYPTO_CORE_0 15 -#define SDX55_MASTER_EMAC 16 -#define SDX55_MASTER_IPA_PCIE 17 -#define SDX55_MASTER_PCIE 18 -#define SDX55_MASTER_QDSS_ETR 19 -#define SDX55_MASTER_SDCC_1 20 -#define SDX55_MASTER_USB3 21 -/* 22 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SDX55_SLAVE_EBI_CH0 23 -#define SDX55_SLAVE_LLCC 24 -#define SDX55_SLAVE_MEM_NOC_SNOC 25 -#define SDX55_SLAVE_MEM_NOC_PCIE_SNOC 26 -#define SDX55_SLAVE_ANOC_SNOC 27 -#define SDX55_SLAVE_SNOC_CFG 28 -#define SDX55_SLAVE_EMAC_CFG 29 -#define SDX55_SLAVE_USB3 30 -#define SDX55_SLAVE_TLMM 31 -#define SDX55_SLAVE_SPMI_FETCHER 32 -#define SDX55_SLAVE_QDSS_CFG 33 -#define SDX55_SLAVE_PDM 34 -#define SDX55_SLAVE_SNOC_MEM_NOC_GC 35 -#define SDX55_SLAVE_TCSR 36 -#define SDX55_SLAVE_CNOC_DDRSS 37 -#define SDX55_SLAVE_SPMI_VGI_COEX 38 -#define SDX55_SLAVE_QPIC 39 -#define SDX55_SLAVE_OCIMEM 40 -#define SDX55_SLAVE_IPA_CFG 41 -#define SDX55_SLAVE_USB3_PHY_CFG 42 -#define SDX55_SLAVE_AOP 43 -#define SDX55_SLAVE_BLSP_1 44 -#define SDX55_SLAVE_SDCC_1 45 -#define SDX55_SLAVE_CNOC_MSS 46 -#define SDX55_SLAVE_PCIE_PARF 47 -#define SDX55_SLAVE_ECC_CFG 48 -#define SDX55_SLAVE_AUDIO 49 -#define SDX55_SLAVE_AOSS 51 -#define SDX55_SLAVE_PRNG 52 -#define SDX55_SLAVE_CRYPTO_0_CFG 53 -#define SDX55_SLAVE_TCU 54 -#define SDX55_SLAVE_CLK_CTL 55 -#define SDX55_SLAVE_IMEM_CFG 56 -#define SDX55_SLAVE_SERVICE_SNOC 57 -#define SDX55_SLAVE_PCIE_0 58 -#define SDX55_SLAVE_QDSS_STM 59 -#define SDX55_SLAVE_APPSS 60 - -#endif diff --git a/drivers/interconnect/qcom/sdx65.c b/drivers/interconnect/qcom/sdx65.c index 2f3f5479d8a5..6c5b4e1ec82f 100644 --- a/drivers/interconnect/qcom/sdx65.c +++ b/drivers/interconnect/qcom/sdx65.c @@ -13,593 +13,582 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sdx65.h" + +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node acm_tcu; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node xm_apps_rdwr; +static struct qcom_icc_node qhm_audio; +static struct qcom_icc_node qhm_blsp1; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qpic; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qhm_spmi_fetcher1; +static struct qcom_icc_node qnm_aggre_noc; +static struct qcom_icc_node qnm_ipa; +static struct qcom_icc_node qnm_memnoc; +static struct qcom_icc_node qnm_memnoc_pcie; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node xm_ipa2pcie_slv; +static struct qcom_icc_node xm_pcie; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_usb3; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_memnoc_snoc; +static struct qcom_icc_node qns_sys_pcie; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qhs_audio; +static struct qcom_icc_node qhs_blsp1; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_ecc_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_pcie_parf; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qpic; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spmi_fetcher; +static struct qcom_icc_node qhs_spmi_vgi_coex; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_usb3; +static struct qcom_icc_node qhs_usb3_phy; +static struct qcom_icc_node qns_aggre_noc; +static struct qcom_icc_node qns_snoc_memnoc; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_pcie; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SDX65_MASTER_LLCC, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX65_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node acm_tcu = { .name = "acm_tcu", - .id = SDX65_MASTER_TCU_0, .channels = 1, .buswidth = 8, .num_links = 3, - .links = { SDX65_SLAVE_LLCC, - SDX65_SLAVE_MEM_NOC_SNOC, - SDX65_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_memnoc_snoc, + &qns_sys_pcie }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SDX65_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDX65_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node xm_apps_rdwr = { .name = "xm_apps_rdwr", - .id = SDX65_MASTER_APPSS_PROC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SDX65_SLAVE_LLCC, - SDX65_SLAVE_MEM_NOC_SNOC, - SDX65_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_memnoc_snoc, + &qns_sys_pcie }, }; static struct qcom_icc_node qhm_audio = { .name = "qhm_audio", - .id = SDX65_MASTER_AUDIO, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX65_SLAVE_ANOC_SNOC }, + .link_nodes = { &qns_aggre_noc }, }; static struct qcom_icc_node qhm_blsp1 = { .name = "qhm_blsp1", - .id = SDX65_MASTER_BLSP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX65_SLAVE_ANOC_SNOC }, + .link_nodes = { &qns_aggre_noc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SDX65_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 26, - .links = { SDX65_SLAVE_AOSS, - SDX65_SLAVE_AUDIO, - SDX65_SLAVE_BLSP_1, - SDX65_SLAVE_CLK_CTL, - SDX65_SLAVE_CRYPTO_0_CFG, - SDX65_SLAVE_CNOC_DDRSS, - SDX65_SLAVE_ECC_CFG, - SDX65_SLAVE_IMEM_CFG, - SDX65_SLAVE_IPA_CFG, - SDX65_SLAVE_CNOC_MSS, - SDX65_SLAVE_PCIE_PARF, - SDX65_SLAVE_PDM, - SDX65_SLAVE_PRNG, - SDX65_SLAVE_QDSS_CFG, - SDX65_SLAVE_QPIC, - SDX65_SLAVE_SDCC_1, - SDX65_SLAVE_SNOC_CFG, - SDX65_SLAVE_SPMI_FETCHER, - SDX65_SLAVE_SPMI_VGI_COEX, - SDX65_SLAVE_TCSR, - SDX65_SLAVE_TLMM, - SDX65_SLAVE_USB3, - SDX65_SLAVE_USB3_PHY_CFG, - SDX65_SLAVE_SNOC_MEM_NOC_GC, - SDX65_SLAVE_IMEM, - SDX65_SLAVE_TCU - }, + .link_nodes = { &qhs_aoss, + &qhs_audio, + &qhs_blsp1, + &qhs_clk_ctl, + &qhs_crypto0_cfg, + &qhs_ddrss_cfg, + &qhs_ecc_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_pdm, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qpic, + &qhs_sdc1, + &qhs_snoc_cfg, + &qhs_spmi_fetcher, + &qhs_spmi_vgi_coex, + &qhs_tcsr, + &qhs_tlmm, + &qhs_usb3, + &qhs_usb3_phy, + &qns_snoc_memnoc, + &qxs_imem, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qhm_qpic = { .name = "qhm_qpic", - .id = SDX65_MASTER_QPIC, .channels = 1, .buswidth = 4, .num_links = 4, - .links = { SDX65_SLAVE_AOSS, - SDX65_SLAVE_AUDIO, - SDX65_SLAVE_IPA_CFG, - SDX65_SLAVE_ANOC_SNOC - }, + .link_nodes = { &qhs_aoss, + &qhs_audio, + &qhs_ipa, + &qns_aggre_noc }, }; static struct qcom_icc_node qhm_snoc_cfg = { .name = "qhm_snoc_cfg", - .id = SDX65_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX65_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qhm_spmi_fetcher1 = { .name = "qhm_spmi_fetcher1", - .id = SDX65_MASTER_SPMI_FETCHER, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SDX65_SLAVE_AOSS, - SDX65_SLAVE_ANOC_SNOC - }, + .link_nodes = { &qhs_aoss, + &qns_aggre_noc }, }; static struct qcom_icc_node qnm_aggre_noc = { .name = "qnm_aggre_noc", - .id = SDX65_MASTER_ANOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 29, - .links = { SDX65_SLAVE_AOSS, - SDX65_SLAVE_APPSS, - SDX65_SLAVE_AUDIO, - SDX65_SLAVE_BLSP_1, - SDX65_SLAVE_CLK_CTL, - SDX65_SLAVE_CRYPTO_0_CFG, - SDX65_SLAVE_CNOC_DDRSS, - SDX65_SLAVE_ECC_CFG, - SDX65_SLAVE_IMEM_CFG, - SDX65_SLAVE_IPA_CFG, - SDX65_SLAVE_CNOC_MSS, - SDX65_SLAVE_PCIE_PARF, - SDX65_SLAVE_PDM, - SDX65_SLAVE_PRNG, - SDX65_SLAVE_QDSS_CFG, - SDX65_SLAVE_QPIC, - SDX65_SLAVE_SDCC_1, - SDX65_SLAVE_SNOC_CFG, - SDX65_SLAVE_SPMI_FETCHER, - SDX65_SLAVE_SPMI_VGI_COEX, - SDX65_SLAVE_TCSR, - SDX65_SLAVE_TLMM, - SDX65_SLAVE_USB3, - SDX65_SLAVE_USB3_PHY_CFG, - SDX65_SLAVE_SNOC_MEM_NOC_GC, - SDX65_SLAVE_IMEM, - SDX65_SLAVE_PCIE_0, - SDX65_SLAVE_QDSS_STM, - SDX65_SLAVE_TCU - }, + .link_nodes = { &qhs_aoss, + &qhs_apss, + &qhs_audio, + &qhs_blsp1, + &qhs_clk_ctl, + &qhs_crypto0_cfg, + &qhs_ddrss_cfg, + &qhs_ecc_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_pdm, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qpic, + &qhs_sdc1, + &qhs_snoc_cfg, + &qhs_spmi_fetcher, + &qhs_spmi_vgi_coex, + &qhs_tcsr, + &qhs_tlmm, + &qhs_usb3, + &qhs_usb3_phy, + &qns_snoc_memnoc, + &qxs_imem, + &xs_pcie, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_ipa = { .name = "qnm_ipa", - .id = SDX65_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 26, - .links = { SDX65_SLAVE_AOSS, - SDX65_SLAVE_AUDIO, - SDX65_SLAVE_BLSP_1, - SDX65_SLAVE_CLK_CTL, - SDX65_SLAVE_CRYPTO_0_CFG, - SDX65_SLAVE_CNOC_DDRSS, - SDX65_SLAVE_ECC_CFG, - SDX65_SLAVE_IMEM_CFG, - SDX65_SLAVE_IPA_CFG, - SDX65_SLAVE_CNOC_MSS, - SDX65_SLAVE_PCIE_PARF, - SDX65_SLAVE_PDM, - SDX65_SLAVE_PRNG, - SDX65_SLAVE_QDSS_CFG, - SDX65_SLAVE_QPIC, - SDX65_SLAVE_SDCC_1, - SDX65_SLAVE_SNOC_CFG, - SDX65_SLAVE_SPMI_FETCHER, - SDX65_SLAVE_TCSR, - SDX65_SLAVE_TLMM, - SDX65_SLAVE_USB3, - SDX65_SLAVE_USB3_PHY_CFG, - SDX65_SLAVE_SNOC_MEM_NOC_GC, - SDX65_SLAVE_IMEM, - SDX65_SLAVE_PCIE_0, - SDX65_SLAVE_QDSS_STM - }, + .link_nodes = { &qhs_aoss, + &qhs_audio, + &qhs_blsp1, + &qhs_clk_ctl, + &qhs_crypto0_cfg, + &qhs_ddrss_cfg, + &qhs_ecc_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_pdm, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qpic, + &qhs_sdc1, + &qhs_snoc_cfg, + &qhs_spmi_fetcher, + &qhs_tcsr, + &qhs_tlmm, + &qhs_usb3, + &qhs_usb3_phy, + &qns_snoc_memnoc, + &qxs_imem, + &xs_pcie, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_memnoc = { .name = "qnm_memnoc", - .id = SDX65_MASTER_MEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 27, - .links = { SDX65_SLAVE_AOSS, - SDX65_SLAVE_APPSS, - SDX65_SLAVE_AUDIO, - SDX65_SLAVE_BLSP_1, - SDX65_SLAVE_CLK_CTL, - SDX65_SLAVE_CRYPTO_0_CFG, - SDX65_SLAVE_CNOC_DDRSS, - SDX65_SLAVE_ECC_CFG, - SDX65_SLAVE_IMEM_CFG, - SDX65_SLAVE_IPA_CFG, - SDX65_SLAVE_CNOC_MSS, - SDX65_SLAVE_PCIE_PARF, - SDX65_SLAVE_PDM, - SDX65_SLAVE_PRNG, - SDX65_SLAVE_QDSS_CFG, - SDX65_SLAVE_QPIC, - SDX65_SLAVE_SDCC_1, - SDX65_SLAVE_SNOC_CFG, - SDX65_SLAVE_SPMI_FETCHER, - SDX65_SLAVE_SPMI_VGI_COEX, - SDX65_SLAVE_TCSR, - SDX65_SLAVE_TLMM, - SDX65_SLAVE_USB3, - SDX65_SLAVE_USB3_PHY_CFG, - SDX65_SLAVE_IMEM, - SDX65_SLAVE_QDSS_STM, - SDX65_SLAVE_TCU - }, + .link_nodes = { &qhs_aoss, + &qhs_apss, + &qhs_audio, + &qhs_blsp1, + &qhs_clk_ctl, + &qhs_crypto0_cfg, + &qhs_ddrss_cfg, + &qhs_ecc_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_pdm, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qpic, + &qhs_sdc1, + &qhs_snoc_cfg, + &qhs_spmi_fetcher, + &qhs_spmi_vgi_coex, + &qhs_tcsr, + &qhs_tlmm, + &qhs_usb3, + &qhs_usb3_phy, + &qxs_imem, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_memnoc_pcie = { .name = "qnm_memnoc_pcie", - .id = SDX65_MASTER_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX65_SLAVE_PCIE_0 }, + .link_nodes = { &xs_pcie }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SDX65_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SDX65_SLAVE_AOSS, - SDX65_SLAVE_ANOC_SNOC - }, + .link_nodes = { &qhs_aoss, + &qns_aggre_noc }, }; static struct qcom_icc_node xm_ipa2pcie_slv = { .name = "xm_ipa2pcie_slv", - .id = SDX65_MASTER_IPA_PCIE, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX65_SLAVE_PCIE_0 }, + .link_nodes = { &xs_pcie }, }; static struct qcom_icc_node xm_pcie = { .name = "xm_pcie", - .id = SDX65_MASTER_PCIE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX65_SLAVE_ANOC_SNOC }, + .link_nodes = { &qns_aggre_noc }, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = SDX65_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 26, - .links = { SDX65_SLAVE_AOSS, - SDX65_SLAVE_AUDIO, - SDX65_SLAVE_BLSP_1, - SDX65_SLAVE_CLK_CTL, - SDX65_SLAVE_CRYPTO_0_CFG, - SDX65_SLAVE_CNOC_DDRSS, - SDX65_SLAVE_ECC_CFG, - SDX65_SLAVE_IMEM_CFG, - SDX65_SLAVE_IPA_CFG, - SDX65_SLAVE_CNOC_MSS, - SDX65_SLAVE_PCIE_PARF, - SDX65_SLAVE_PDM, - SDX65_SLAVE_PRNG, - SDX65_SLAVE_QDSS_CFG, - SDX65_SLAVE_QPIC, - SDX65_SLAVE_SDCC_1, - SDX65_SLAVE_SNOC_CFG, - SDX65_SLAVE_SPMI_FETCHER, - SDX65_SLAVE_SPMI_VGI_COEX, - SDX65_SLAVE_TCSR, - SDX65_SLAVE_TLMM, - SDX65_SLAVE_USB3, - SDX65_SLAVE_USB3_PHY_CFG, - SDX65_SLAVE_SNOC_MEM_NOC_GC, - SDX65_SLAVE_IMEM, - SDX65_SLAVE_TCU - }, + .link_nodes = { &qhs_aoss, + &qhs_audio, + &qhs_blsp1, + &qhs_clk_ctl, + &qhs_crypto0_cfg, + &qhs_ddrss_cfg, + &qhs_ecc_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_pdm, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qpic, + &qhs_sdc1, + &qhs_snoc_cfg, + &qhs_spmi_fetcher, + &qhs_spmi_vgi_coex, + &qhs_tcsr, + &qhs_tlmm, + &qhs_usb3, + &qhs_usb3_phy, + &qns_snoc_memnoc, + &qxs_imem, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node xm_sdc1 = { .name = "xm_sdc1", - .id = SDX65_MASTER_SDCC_1, .channels = 1, .buswidth = 8, .num_links = 4, - .links = { SDX65_SLAVE_AOSS, - SDX65_SLAVE_AUDIO, - SDX65_SLAVE_IPA_CFG, - SDX65_SLAVE_ANOC_SNOC - }, + .link_nodes = { &qhs_aoss, + &qhs_audio, + &qhs_ipa, + &qns_aggre_noc }, }; static struct qcom_icc_node xm_usb3 = { .name = "xm_usb3", - .id = SDX65_MASTER_USB3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX65_SLAVE_ANOC_SNOC }, + .link_nodes = { &qns_aggre_noc }, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SDX65_SLAVE_EBI1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SDX65_SLAVE_LLCC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDX65_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_memnoc_snoc = { .name = "qns_memnoc_snoc", - .id = SDX65_SLAVE_MEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX65_MASTER_MEM_NOC_SNOC }, + .link_nodes = { &qnm_memnoc }, }; static struct qcom_icc_node qns_sys_pcie = { .name = "qns_sys_pcie", - .id = SDX65_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX65_MASTER_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_memnoc_pcie }, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SDX65_SLAVE_AOSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SDX65_SLAVE_APPSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_audio = { .name = "qhs_audio", - .id = SDX65_SLAVE_AUDIO, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_blsp1 = { .name = "qhs_blsp1", - .id = SDX65_SLAVE_BLSP_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SDX65_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SDX65_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ddrss_cfg = { .name = "qhs_ddrss_cfg", - .id = SDX65_SLAVE_CNOC_DDRSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ecc_cfg = { .name = "qhs_ecc_cfg", - .id = SDX65_SLAVE_ECC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SDX65_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SDX65_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", - .id = SDX65_SLAVE_CNOC_MSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie_parf = { .name = "qhs_pcie_parf", - .id = SDX65_SLAVE_PCIE_PARF, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SDX65_SLAVE_PDM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SDX65_SLAVE_PRNG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SDX65_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qpic = { .name = "qhs_qpic", - .id = SDX65_SLAVE_QPIC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc1 = { .name = "qhs_sdc1", - .id = SDX65_SLAVE_SDCC_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_snoc_cfg = { .name = "qhs_snoc_cfg", - .id = SDX65_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX65_MASTER_SNOC_CFG }, + .link_nodes = { &qhm_snoc_cfg }, }; static struct qcom_icc_node qhs_spmi_fetcher = { .name = "qhs_spmi_fetcher", - .id = SDX65_SLAVE_SPMI_FETCHER, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_spmi_vgi_coex = { .name = "qhs_spmi_vgi_coex", - .id = SDX65_SLAVE_SPMI_VGI_COEX, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SDX65_SLAVE_TCSR, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = SDX65_SLAVE_TLMM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3 = { .name = "qhs_usb3", - .id = SDX65_SLAVE_USB3, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_phy = { .name = "qhs_usb3_phy", - .id = SDX65_SLAVE_USB3_PHY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_aggre_noc = { .name = "qns_aggre_noc", - .id = SDX65_SLAVE_ANOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX65_MASTER_ANOC_SNOC }, + .link_nodes = { &qnm_aggre_noc }, }; static struct qcom_icc_node qns_snoc_memnoc = { .name = "qns_snoc_memnoc", - .id = SDX65_SLAVE_SNOC_MEM_NOC_GC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDX65_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SDX65_SLAVE_IMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SDX65_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_pcie = { .name = "xs_pcie", - .id = SDX65_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SDX65_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SDX65_SLAVE_TCU, .channels = 1, .buswidth = 8, }; @@ -897,7 +886,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove_new = qcom_icc_rpmh_remove, + .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sdx65", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sdx65.h b/drivers/interconnect/qcom/sdx65.h deleted file mode 100644 index 5dca6e8b32c9..000000000000 --- a/drivers/interconnect/qcom/sdx65.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX65_H -#define __DRIVERS_INTERCONNECT_QCOM_SDX65_H - -#define SDX65_MASTER_TCU_0 0 -#define SDX65_MASTER_LLCC 1 -#define SDX65_MASTER_AUDIO 2 -#define SDX65_MASTER_BLSP_1 3 -#define SDX65_MASTER_QDSS_BAM 4 -#define SDX65_MASTER_QPIC 5 -#define SDX65_MASTER_SNOC_CFG 6 -#define SDX65_MASTER_SPMI_FETCHER 7 -#define SDX65_MASTER_ANOC_SNOC 8 -#define SDX65_MASTER_IPA 9 -#define SDX65_MASTER_MEM_NOC_SNOC 10 -#define SDX65_MASTER_MEM_NOC_PCIE_SNOC 11 -#define SDX65_MASTER_SNOC_GC_MEM_NOC 12 -#define SDX65_MASTER_CRYPTO 13 -#define SDX65_MASTER_APPSS_PROC 14 -#define SDX65_MASTER_IPA_PCIE 15 -#define SDX65_MASTER_PCIE_0 16 -#define SDX65_MASTER_QDSS_ETR 17 -#define SDX65_MASTER_SDCC_1 18 -#define SDX65_MASTER_USB3 19 -#define SDX65_SLAVE_EBI1 512 -#define SDX65_SLAVE_AOSS 513 -#define SDX65_SLAVE_APPSS 514 -#define SDX65_SLAVE_AUDIO 515 -#define SDX65_SLAVE_BLSP_1 516 -#define SDX65_SLAVE_CLK_CTL 517 -#define SDX65_SLAVE_CRYPTO_0_CFG 518 -#define SDX65_SLAVE_CNOC_DDRSS 519 -#define SDX65_SLAVE_ECC_CFG 520 -#define SDX65_SLAVE_IMEM_CFG 521 -#define SDX65_SLAVE_IPA_CFG 522 -#define SDX65_SLAVE_CNOC_MSS 523 -#define SDX65_SLAVE_PCIE_PARF 524 -#define SDX65_SLAVE_PDM 525 -#define SDX65_SLAVE_PRNG 526 -#define SDX65_SLAVE_QDSS_CFG 527 -#define SDX65_SLAVE_QPIC 528 -#define SDX65_SLAVE_SDCC_1 529 -#define SDX65_SLAVE_SNOC_CFG 530 -#define SDX65_SLAVE_SPMI_FETCHER 531 -#define SDX65_SLAVE_SPMI_VGI_COEX 532 -#define SDX65_SLAVE_TCSR 533 -#define SDX65_SLAVE_TLMM 534 -#define SDX65_SLAVE_USB3 535 -#define SDX65_SLAVE_USB3_PHY_CFG 536 -#define SDX65_SLAVE_ANOC_SNOC 537 -#define SDX65_SLAVE_LLCC 538 -#define SDX65_SLAVE_MEM_NOC_SNOC 539 -#define SDX65_SLAVE_SNOC_MEM_NOC_GC 540 -#define SDX65_SLAVE_MEM_NOC_PCIE_SNOC 541 -#define SDX65_SLAVE_IMEM 542 -#define SDX65_SLAVE_SERVICE_SNOC 543 -#define SDX65_SLAVE_PCIE_0 544 -#define SDX65_SLAVE_QDSS_STM 545 -#define SDX65_SLAVE_TCU 546 - -#endif diff --git a/drivers/interconnect/qcom/sdx75.c b/drivers/interconnect/qcom/sdx75.c index 7f422c27488d..5cfccc6cfd1b 100644 --- a/drivers/interconnect/qcom/sdx75.c +++ b/drivers/interconnect/qcom/sdx75.c @@ -14,782 +14,724 @@ #include "bcm-voter.h" #include "icc-common.h" #include "icc-rpmh.h" -#include "sdx75.h" -static struct qcom_icc_node qpic_core_master = { - .name = "qpic_core_master", - .id = SDX75_MASTER_QPIC_CORE, - .channels = 1, - .buswidth = 4, - .num_links = 1, - .links = { SDX75_SLAVE_QPIC_CORE }, -}; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gemnoc_cfg; +static struct qcom_icc_node qnm_mdsp; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node xm_ipa2pcie; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node xm_pcie3_2; +static struct qcom_icc_node qhm_audio; +static struct qcom_icc_node qhm_gic; +static struct qcom_icc_node qhm_pcie_rscc; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qpic; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qnm_aggre_noc; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node qnm_system_noc_cfg; +static struct qcom_icc_node qnm_system_noc_pcie_cfg; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node qxm_mvmss; +static struct qcom_icc_node xm_emac_0; +static struct qcom_icc_node xm_emac_1; +static struct qcom_icc_node xm_qdss_etr0; +static struct qcom_icc_node xm_qdss_etr1; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_usb3; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qhs_lagg; +static struct qcom_icc_node qhs_mccc_master; +static struct qcom_icc_node qns_gemnoc; +static struct qcom_icc_node qss_snoop_bwmon; +static struct qcom_icc_node qns_gemnoc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node srvc_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_pcie_gemnoc; +static struct qcom_icc_node ps_eth0_cfg; +static struct qcom_icc_node ps_eth1_cfg; +static struct qcom_icc_node qhs_audio; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_crypto_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_mvmss_cfg; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pcie2_cfg; +static struct qcom_icc_node qhs_pcie_rscc; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qpic; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_spmi_vgi_coex; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_usb3; +static struct qcom_icc_node qhs_usb3_phy; +static struct qcom_icc_node qns_a1noc; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qns_system_noc_cfg; +static struct qcom_icc_node qns_system_noc_pcie_cfg; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node srvc_pcie_system_noc; +static struct qcom_icc_node srvc_system_noc; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_pcie_2; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", - .id = SDX75_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qnm_cnoc = { .name = "qnm_cnoc", - .id = SDX75_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 4, - .links = { SDX75_SLAVE_LAGG_CFG, SDX75_SLAVE_MCCC_MASTER, - SDX75_SLAVE_GEM_NOC_CFG, SDX75_SLAVE_SNOOP_BWMON }, + .link_nodes = { &qhs_lagg, &qhs_mccc_master, + &qns_gemnoc, &qss_snoop_bwmon }, }; static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", - .id = SDX75_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC }, + .link_nodes = { &qns_gemnoc_cnoc, &qns_llcc }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", - .id = SDX75_MASTER_APPSS_PROC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC, - SDX75_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gemnoc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_gemnoc_cfg = { .name = "qnm_gemnoc_cfg", - .id = SDX75_MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_SLAVE_SERVICE_GEM_NOC }, + .link_nodes = { &srvc_gemnoc }, }; static struct qcom_icc_node qnm_mdsp = { .name = "qnm_mdsp", - .id = SDX75_MASTER_MSS_PROC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC, - SDX75_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gemnoc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = SDX75_MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC }, + .link_nodes = { &qns_gemnoc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SDX75_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SDX75_SLAVE_GEM_NOC_CNOC, SDX75_SLAVE_LLCC, - SDX75_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gemnoc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SDX75_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node xm_ipa2pcie = { .name = "xm_ipa2pcie", - .id = SDX75_MASTER_IPA_PCIE, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_pcie }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SDX75_MASTER_LLCC, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", - .id = SDX75_MASTER_PCIE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_gemnoc }, }; static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", - .id = SDX75_MASTER_PCIE_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_gemnoc }, }; static struct qcom_icc_node xm_pcie3_2 = { .name = "xm_pcie3_2", - .id = SDX75_MASTER_PCIE_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_gemnoc }, }; static struct qcom_icc_node qhm_audio = { .name = "qhm_audio", - .id = SDX75_MASTER_AUDIO, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qhm_gic = { .name = "qhm_gic", - .id = SDX75_MASTER_GIC_AHB, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qhm_pcie_rscc = { .name = "qhm_pcie_rscc", - .id = SDX75_MASTER_PCIE_RSCC, .channels = 1, .buswidth = 4, .num_links = 31, - .links = { SDX75_SLAVE_ETH0_CFG, SDX75_SLAVE_ETH1_CFG, - SDX75_SLAVE_AUDIO, SDX75_SLAVE_CLK_CTL, - SDX75_SLAVE_CRYPTO_0_CFG, SDX75_SLAVE_IMEM_CFG, - SDX75_SLAVE_IPA_CFG, SDX75_SLAVE_IPC_ROUTER_CFG, - SDX75_SLAVE_CNOC_MSS, SDX75_SLAVE_ICBDI_MVMSS_CFG, - SDX75_SLAVE_PCIE_0_CFG, SDX75_SLAVE_PCIE_1_CFG, - SDX75_SLAVE_PCIE_2_CFG, SDX75_SLAVE_PDM, - SDX75_SLAVE_PRNG, SDX75_SLAVE_QDSS_CFG, - SDX75_SLAVE_QPIC, SDX75_SLAVE_QUP_0, - SDX75_SLAVE_SDCC_1, SDX75_SLAVE_SDCC_4, - SDX75_SLAVE_SPMI_VGI_COEX, SDX75_SLAVE_TCSR, - SDX75_SLAVE_TLMM, SDX75_SLAVE_USB3, - SDX75_SLAVE_USB3_PHY_CFG, SDX75_SLAVE_DDRSS_CFG, - SDX75_SLAVE_SNOC_CFG, SDX75_SLAVE_PCIE_ANOC_CFG, - SDX75_SLAVE_IMEM, SDX75_SLAVE_QDSS_STM, - SDX75_SLAVE_TCU }, + .link_nodes = { &ps_eth0_cfg, &ps_eth1_cfg, + &qhs_audio, &qhs_clk_ctl, + &qhs_crypto_cfg, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_mss_cfg, &qhs_mvmss_cfg, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pcie2_cfg, &qhs_pdm, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qpic, &qhs_qup0, + &qhs_sdc1, &qhs_sdc4, + &qhs_spmi_vgi_coex, &qhs_tcsr, + &qhs_tlmm, &qhs_usb3, + &qhs_usb3_phy, &qns_ddrss_cfg, + &qns_system_noc_cfg, &qns_system_noc_pcie_cfg, + &qxs_imem, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SDX75_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes = { &qns_a1noc }, }; static struct qcom_icc_node qhm_qpic = { .name = "qhm_qpic", - .id = SDX75_MASTER_QPIC, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes = { &qns_a1noc }, }; static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", - .id = SDX75_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes = { &qns_a1noc }, }; static struct qcom_icc_node qnm_aggre_noc = { .name = "qnm_aggre_noc", - .id = SDX75_MASTER_ANOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", - .id = SDX75_MASTER_GEM_NOC_CNOC, .channels = 1, .buswidth = 8, .num_links = 32, - .links = { SDX75_SLAVE_ETH0_CFG, SDX75_SLAVE_ETH1_CFG, - SDX75_SLAVE_AUDIO, SDX75_SLAVE_CLK_CTL, - SDX75_SLAVE_CRYPTO_0_CFG, SDX75_SLAVE_IMEM_CFG, - SDX75_SLAVE_IPA_CFG, SDX75_SLAVE_IPC_ROUTER_CFG, - SDX75_SLAVE_CNOC_MSS, SDX75_SLAVE_ICBDI_MVMSS_CFG, - SDX75_SLAVE_PCIE_0_CFG, SDX75_SLAVE_PCIE_1_CFG, - SDX75_SLAVE_PCIE_2_CFG, SDX75_SLAVE_PCIE_RSC_CFG, - SDX75_SLAVE_PDM, SDX75_SLAVE_PRNG, - SDX75_SLAVE_QDSS_CFG, SDX75_SLAVE_QPIC, - SDX75_SLAVE_QUP_0, SDX75_SLAVE_SDCC_1, - SDX75_SLAVE_SDCC_4, SDX75_SLAVE_SPMI_VGI_COEX, - SDX75_SLAVE_TCSR, SDX75_SLAVE_TLMM, - SDX75_SLAVE_USB3, SDX75_SLAVE_USB3_PHY_CFG, - SDX75_SLAVE_DDRSS_CFG, SDX75_SLAVE_SNOC_CFG, - SDX75_SLAVE_PCIE_ANOC_CFG, SDX75_SLAVE_IMEM, - SDX75_SLAVE_QDSS_STM, SDX75_SLAVE_TCU }, + .link_nodes = { &ps_eth0_cfg, &ps_eth1_cfg, + &qhs_audio, &qhs_clk_ctl, + &qhs_crypto_cfg, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_mss_cfg, &qhs_mvmss_cfg, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pcie2_cfg, &qhs_pcie_rscc, + &qhs_pdm, &qhs_prng, + &qhs_qdss_cfg, &qhs_qpic, + &qhs_qup0, &qhs_sdc1, + &qhs_sdc4, &qhs_spmi_vgi_coex, + &qhs_tcsr, &qhs_tlmm, + &qhs_usb3, &qhs_usb3_phy, + &qns_ddrss_cfg, &qns_system_noc_cfg, + &qns_system_noc_pcie_cfg, &qxs_imem, + &xs_qdss_stm, &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = SDX75_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SDX75_SLAVE_PCIE_0, SDX75_SLAVE_PCIE_1, - SDX75_SLAVE_PCIE_2 }, + .link_nodes = { &xs_pcie_0, &xs_pcie_1, + &xs_pcie_2 }, }; static struct qcom_icc_node qnm_system_noc_cfg = { .name = "qnm_system_noc_cfg", - .id = SDX75_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_system_noc }, }; static struct qcom_icc_node qnm_system_noc_pcie_cfg = { .name = "qnm_system_noc_pcie_cfg", - .id = SDX75_MASTER_PCIE_ANOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_SLAVE_SERVICE_PCIE_ANOC }, + .link_nodes = { &srvc_pcie_system_noc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SDX75_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes = { &qns_a1noc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SDX75_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qxm_mvmss = { .name = "qxm_mvmss", - .id = SDX75_MASTER_MVMSS, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes = { &qns_a1noc }, }; static struct qcom_icc_node xm_emac_0 = { .name = "xm_emac_0", - .id = SDX75_MASTER_EMAC_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes = { &qns_a1noc }, }; static struct qcom_icc_node xm_emac_1 = { .name = "xm_emac_1", - .id = SDX75_MASTER_EMAC_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes = { &qns_a1noc }, }; static struct qcom_icc_node xm_qdss_etr0 = { .name = "xm_qdss_etr0", - .id = SDX75_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes = { &qns_a1noc }, }; static struct qcom_icc_node xm_qdss_etr1 = { .name = "xm_qdss_etr1", - .id = SDX75_MASTER_QDSS_ETR_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes = { &qns_a1noc }, }; static struct qcom_icc_node xm_sdc1 = { .name = "xm_sdc1", - .id = SDX75_MASTER_SDCC_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes = { &qns_a1noc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SDX75_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_A1NOC_CFG }, + .link_nodes = { &qns_a1noc }, }; static struct qcom_icc_node xm_usb3 = { .name = "xm_usb3", - .id = SDX75_MASTER_USB3_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_SLAVE_A1NOC_CFG }, -}; - -static struct qcom_icc_node qpic_core_slave = { - .name = "qpic_core_slave", - .id = SDX75_SLAVE_QPIC_CORE, - .channels = 1, - .buswidth = 4, - .num_links = 0, + .link_nodes = { &qns_a1noc }, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", - .id = SDX75_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lagg = { .name = "qhs_lagg", - .id = SDX75_SLAVE_LAGG_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mccc_master = { .name = "qhs_mccc_master", - .id = SDX75_SLAVE_MCCC_MASTER, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_gemnoc = { .name = "qns_gemnoc", - .id = SDX75_SLAVE_GEM_NOC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qss_snoop_bwmon = { .name = "qss_snoop_bwmon", - .id = SDX75_SLAVE_SNOOP_BWMON, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_gemnoc_cnoc = { .name = "qns_gemnoc_cnoc", - .id = SDX75_SLAVE_GEM_NOC_CNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_MASTER_GEM_NOC_CNOC }, + .link_nodes = { &qnm_gemnoc_cnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SDX75_SLAVE_LLCC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDX75_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_pcie = { .name = "qns_pcie", - .id = SDX75_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDX75_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node srvc_gemnoc = { .name = "srvc_gemnoc", - .id = SDX75_SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SDX75_SLAVE_EBI1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_pcie_gemnoc = { .name = "qns_pcie_gemnoc", - .id = SDX75_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDX75_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node ps_eth0_cfg = { .name = "ps_eth0_cfg", - .id = SDX75_SLAVE_ETH0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node ps_eth1_cfg = { .name = "ps_eth1_cfg", - .id = SDX75_SLAVE_ETH1_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_audio = { .name = "qhs_audio", - .id = SDX75_SLAVE_AUDIO, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SDX75_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_crypto_cfg = { .name = "qhs_crypto_cfg", - .id = SDX75_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SDX75_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SDX75_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", - .id = SDX75_SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", - .id = SDX75_SLAVE_CNOC_MSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mvmss_cfg = { .name = "qhs_mvmss_cfg", - .id = SDX75_SLAVE_ICBDI_MVMSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = SDX75_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie1_cfg = { .name = "qhs_pcie1_cfg", - .id = SDX75_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie2_cfg = { .name = "qhs_pcie2_cfg", - .id = SDX75_SLAVE_PCIE_2_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie_rscc = { .name = "qhs_pcie_rscc", - .id = SDX75_SLAVE_PCIE_RSC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SDX75_SLAVE_PDM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SDX75_SLAVE_PRNG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SDX75_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qpic = { .name = "qhs_qpic", - .id = SDX75_SLAVE_QPIC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", - .id = SDX75_SLAVE_QUP_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc1 = { .name = "qhs_sdc1", - .id = SDX75_SLAVE_SDCC_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SDX75_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_spmi_vgi_coex = { .name = "qhs_spmi_vgi_coex", - .id = SDX75_SLAVE_SPMI_VGI_COEX, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SDX75_SLAVE_TCSR, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = SDX75_SLAVE_TLMM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3 = { .name = "qhs_usb3", - .id = SDX75_SLAVE_USB3, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3_phy = { .name = "qhs_usb3_phy", - .id = SDX75_SLAVE_USB3_PHY_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_a1noc = { .name = "qns_a1noc", - .id = SDX75_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SDX75_MASTER_ANOC_SNOC }, + .link_nodes = { &qnm_aggre_noc }, }; static struct qcom_icc_node qns_ddrss_cfg = { .name = "qns_ddrss_cfg", - .id = SDX75_SLAVE_DDRSS_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_MASTER_CNOC_DC_NOC }, + .link_nodes = { &qnm_cnoc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SDX75_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SDX75_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node qns_system_noc_cfg = { .name = "qns_system_noc_cfg", - .id = SDX75_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_MASTER_SNOC_CFG }, + .link_nodes = { &qnm_system_noc_cfg }, }; static struct qcom_icc_node qns_system_noc_pcie_cfg = { .name = "qns_system_noc_pcie_cfg", - .id = SDX75_SLAVE_PCIE_ANOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SDX75_MASTER_PCIE_ANOC_CFG }, + .link_nodes = { &qnm_system_noc_pcie_cfg }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SDX75_SLAVE_IMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node srvc_pcie_system_noc = { .name = "srvc_pcie_system_noc", - .id = SDX75_SLAVE_SERVICE_PCIE_ANOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node srvc_system_noc = { .name = "srvc_system_noc", - .id = SDX75_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_0 = { .name = "xs_pcie_0", - .id = SDX75_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_1 = { .name = "xs_pcie_1", - .id = SDX75_SLAVE_PCIE_1, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_2 = { .name = "xs_pcie_2", - .id = SDX75_SLAVE_PCIE_2, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SDX75_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SDX75_SLAVE_TCU, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_bcm bcm_ce0 = { @@ -831,12 +773,6 @@ static struct qcom_icc_bcm bcm_mc0 = { .nodes = { &ebi }, }; -static struct qcom_icc_bcm bcm_qp0 = { - .name = "QP0", - .num_nodes = 1, - .nodes = { &qpic_core_slave }, -}; - static struct qcom_icc_bcm bcm_qup0 = { .name = "QUP0", .keepalive = true, @@ -898,14 +834,11 @@ static struct qcom_icc_bcm bcm_sn4 = { }; static struct qcom_icc_bcm * const clk_virt_bcms[] = { - &bcm_qp0, &bcm_qup0, }; static struct qcom_icc_node * const clk_virt_nodes[] = { - [MASTER_QPIC_CORE] = &qpic_core_master, [MASTER_QUP_CORE_0] = &qup0_core_master, - [SLAVE_QPIC_CORE] = &qpic_core_slave, [SLAVE_QUP_CORE_0] = &qup0_core_slave, }; @@ -1083,7 +1016,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove_new = qcom_icc_rpmh_remove, + .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sdx75", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sdx75.h b/drivers/interconnect/qcom/sdx75.h deleted file mode 100644 index 24e887159920..000000000000 --- a/drivers/interconnect/qcom/sdx75.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX75_H -#define __DRIVERS_INTERCONNECT_QCOM_SDX75_H - -#define SDX75_MASTER_ANOC_PCIE_GEM_NOC 0 -#define SDX75_MASTER_ANOC_SNOC 1 -#define SDX75_MASTER_APPSS_PROC 2 -#define SDX75_MASTER_AUDIO 3 -#define SDX75_MASTER_CNOC_DC_NOC 4 -#define SDX75_MASTER_CRYPTO 5 -#define SDX75_MASTER_EMAC_0 6 -#define SDX75_MASTER_EMAC_1 7 -#define SDX75_MASTER_GEM_NOC_CFG 8 -#define SDX75_MASTER_GEM_NOC_CNOC 9 -#define SDX75_MASTER_GEM_NOC_PCIE_SNOC 10 -#define SDX75_MASTER_GIC 11 -#define SDX75_MASTER_GIC_AHB 12 -#define SDX75_MASTER_IPA 13 -#define SDX75_MASTER_IPA_PCIE 14 -#define SDX75_MASTER_LLCC 15 -#define SDX75_MASTER_MSS_PROC 16 -#define SDX75_MASTER_MVMSS 17 -#define SDX75_MASTER_PCIE_0 18 -#define SDX75_MASTER_PCIE_1 19 -#define SDX75_MASTER_PCIE_2 20 -#define SDX75_MASTER_PCIE_ANOC_CFG 21 -#define SDX75_MASTER_PCIE_RSCC 22 -#define SDX75_MASTER_QDSS_BAM 23 -#define SDX75_MASTER_QDSS_ETR 24 -#define SDX75_MASTER_QDSS_ETR_1 25 -#define SDX75_MASTER_QPIC 26 -#define SDX75_MASTER_QPIC_CORE 27 -#define SDX75_MASTER_QUP_0 28 -#define SDX75_MASTER_QUP_CORE_0 29 -#define SDX75_MASTER_SDCC_1 30 -#define SDX75_MASTER_SDCC_4 31 -#define SDX75_MASTER_SNOC_CFG 32 -#define SDX75_MASTER_SNOC_SF_MEM_NOC 33 -#define SDX75_MASTER_SYS_TCU 34 -#define SDX75_MASTER_USB3_0 35 -#define SDX75_SLAVE_A1NOC_CFG 36 -#define SDX75_SLAVE_ANOC_PCIE_GEM_NOC 37 -#define SDX75_SLAVE_AUDIO 38 -#define SDX75_SLAVE_CLK_CTL 39 -#define SDX75_SLAVE_CRYPTO_0_CFG 40 -#define SDX75_SLAVE_CNOC_MSS 41 -#define SDX75_SLAVE_DDRSS_CFG 42 -#define SDX75_SLAVE_EBI1 43 -#define SDX75_SLAVE_ETH0_CFG 44 -#define SDX75_SLAVE_ETH1_CFG 45 -#define SDX75_SLAVE_GEM_NOC_CFG 46 -#define SDX75_SLAVE_GEM_NOC_CNOC 47 -#define SDX75_SLAVE_ICBDI_MVMSS_CFG 48 -#define SDX75_SLAVE_IMEM 49 -#define SDX75_SLAVE_IMEM_CFG 50 -#define SDX75_SLAVE_IPA_CFG 51 -#define SDX75_SLAVE_IPC_ROUTER_CFG 52 -#define SDX75_SLAVE_LAGG_CFG 53 -#define SDX75_SLAVE_LLCC 54 -#define SDX75_SLAVE_MCCC_MASTER 55 -#define SDX75_SLAVE_MEM_NOC_PCIE_SNOC 56 -#define SDX75_SLAVE_PCIE_0 57 -#define SDX75_SLAVE_PCIE_1 58 -#define SDX75_SLAVE_PCIE_2 59 -#define SDX75_SLAVE_PCIE_0_CFG 60 -#define SDX75_SLAVE_PCIE_1_CFG 61 -#define SDX75_SLAVE_PCIE_2_CFG 62 -#define SDX75_SLAVE_PCIE_ANOC_CFG 63 -#define SDX75_SLAVE_PCIE_RSC_CFG 64 -#define SDX75_SLAVE_PDM 65 -#define SDX75_SLAVE_PRNG 66 -#define SDX75_SLAVE_QDSS_CFG 67 -#define SDX75_SLAVE_QDSS_STM 68 -#define SDX75_SLAVE_QPIC 69 -#define SDX75_SLAVE_QPIC_CORE 70 -#define SDX75_SLAVE_QUP_0 71 -#define SDX75_SLAVE_QUP_CORE_0 72 -#define SDX75_SLAVE_SDCC_1 73 -#define SDX75_SLAVE_SDCC_4 74 -#define SDX75_SLAVE_SERVICE_GEM_NOC 75 -#define SDX75_SLAVE_SERVICE_PCIE_ANOC 76 -#define SDX75_SLAVE_SERVICE_SNOC 77 -#define SDX75_SLAVE_SNOC_CFG 78 -#define SDX75_SLAVE_SNOC_GEM_NOC_SF 79 -#define SDX75_SLAVE_SNOOP_BWMON 80 -#define SDX75_SLAVE_SPMI_VGI_COEX 81 -#define SDX75_SLAVE_TCSR 82 -#define SDX75_SLAVE_TCU 83 -#define SDX75_SLAVE_TLMM 84 -#define SDX75_SLAVE_USB3 85 -#define SDX75_SLAVE_USB3_PHY_CFG 86 - -#endif diff --git a/drivers/interconnect/qcom/sm6115.c b/drivers/interconnect/qcom/sm6115.c index 271b07c74862..3ee12c8a4d56 100644 --- a/drivers/interconnect/qcom/sm6115.c +++ b/drivers/interconnect/qcom/sm6115.c @@ -1402,7 +1402,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qnoc_probe, - .remove_new = qnoc_remove, + .remove = qnoc_remove, .driver = { .name = "qnoc-sm6115", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom/sm6350.c index 20923e8e6110..d96bec1cbb26 100644 --- a/drivers/interconnect/qcom/sm6350.c +++ b/drivers/interconnect/qcom/sm6350.c @@ -13,1151 +13,1359 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sm6350.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qup_0; +static struct qcom_icc_node xm_emmc; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node qhm_a2noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup_1; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_icp_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qnm_npu; +static struct qcom_icc_node qxm_npu_dsp; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc_dc_noc; +static struct qcom_icc_node acm_apps; +static struct qcom_icc_node acm_sys_tcu; +static struct qcom_icc_node qhm_gemnoc_cfg; +static struct qcom_icc_node qnm_cmpnoc; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_gpu; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qnm_video0; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qxm_camnoc_hf; +static struct qcom_icc_node qxm_camnoc_icp; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node amm_npu_sys; +static struct qcom_icc_node qhm_npu_cfg; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gemnoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qns_cdsp_gemnoc; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_a2_noc_cfg; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy2; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_boot_rom; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_camera_nrt_thrott_cfg; +static struct qcom_icc_node qhs_camera_rt_throttle_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_display_throttle_cfg; +static struct qcom_icc_node qhs_emmc_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_npu_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qm_cfg; +static struct qcom_icc_node qhs_qm_mpu_cfg; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_security; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_venus_throttle_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_gemnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_mcdma_ms_mpu_cfg; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_gem_noc_snoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node srvc_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_cal_dp0; +static struct qcom_icc_node qhs_cp; +static struct qcom_icc_node qhs_dma_bwmon; +static struct qcom_icc_node qhs_dpm; +static struct qcom_icc_node qhs_isense; +static struct qcom_icc_node qhs_llm; +static struct qcom_icc_node qhs_tcm; +static struct qcom_icc_node qns_npu_sys; +static struct qcom_icc_node srvc_noc; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; static struct qcom_icc_node qhm_a1noc_cfg = { .name = "qhm_a1noc_cfg", - .id = SM6350_MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_SLAVE_SERVICE_A1NOC }, + .link_nodes = { &srvc_aggre1_noc }, +}; + +static struct qcom_icc_qosbox qhm_qup_0_qos = { + .num_ports = 1, + .port_offsets = { 0xa000 }, + .prio = 2, + .urg_fwd = 0, }; static struct qcom_icc_node qhm_qup_0 = { .name = "qhm_qup_0", - .id = SM6350_MASTER_QUP_0, .channels = 1, .buswidth = 4, + .qosbox = &qhm_qup_0_qos, .num_links = 1, - .links = { SM6350_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_qosbox xm_emmc_qos = { + .num_ports = 1, + .port_offsets = { 0x7000 }, + .prio = 2, + .urg_fwd = 0, }; static struct qcom_icc_node xm_emmc = { .name = "xm_emmc", - .id = SM6350_MASTER_EMMC, .channels = 1, .buswidth = 8, + .qosbox = &xm_emmc_qos, .num_links = 1, - .links = { SM6350_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_qosbox xm_ufs_mem_qos = { + .num_ports = 1, + .port_offsets = { 0x8000 }, + .prio = 4, + .urg_fwd = 0, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SM6350_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, + .qosbox = &xm_ufs_mem_qos, .num_links = 1, - .links = { SM6350_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_a2noc_cfg = { .name = "qhm_a2noc_cfg", - .id = SM6350_MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_SLAVE_SERVICE_A2NOC }, + .link_nodes = { &srvc_aggre2_noc }, +}; + +static struct qcom_icc_qosbox qhm_qdss_bam_qos = { + .num_ports = 1, + .port_offsets = { 0xb000 }, + .prio = 2, + .urg_fwd = 0, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SM6350_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, + .qosbox = &qhm_qdss_bam_qos, .num_links = 1, - .links = { SM6350_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; +static struct qcom_icc_qosbox qhm_qup_1_qos = { + .num_ports = 1, + .port_offsets = { 0x9000 }, + .prio = 2, + .urg_fwd = 0, +}; static struct qcom_icc_node qhm_qup_1 = { .name = "qhm_qup_1", - .id = SM6350_MASTER_QUP_1, .channels = 1, .buswidth = 4, + .qosbox = &qhm_qup_1_qos, .num_links = 1, - .links = { SM6350_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_qosbox qxm_crypto_qos = { + .num_ports = 1, + .port_offsets = { 0x6000 }, + .prio = 2, + .urg_fwd = 0, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SM6350_MASTER_CRYPTO_CORE_0, .channels = 1, .buswidth = 8, + .qosbox = &qxm_crypto_qos, .num_links = 1, - .links = { SM6350_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_qosbox qxm_ipa_qos = { + .num_ports = 1, + .port_offsets = { 0x7000 }, + .prio = 2, + .urg_fwd = 0, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SM6350_MASTER_IPA, .channels = 1, .buswidth = 8, + .qosbox = &qxm_ipa_qos, .num_links = 1, - .links = { SM6350_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_qosbox xm_qdss_etr_qos = { + .num_ports = 1, + .port_offsets = { 0xc000 }, + .prio = 2, + .urg_fwd = 0, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = SM6350_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, + .qosbox = &xm_qdss_etr_qos, .num_links = 1, - .links = { SM6350_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_qosbox xm_sdc2_qos = { + .num_ports = 1, + .port_offsets = { 0x18000 }, + .prio = 2, + .urg_fwd = 0, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SM6350_MASTER_SDCC_2, .channels = 1, .buswidth = 8, + .qosbox = &xm_sdc2_qos, .num_links = 1, - .links = { SM6350_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_qosbox xm_usb3_0_qos = { + .num_ports = 1, + .port_offsets = { 0xd000 }, + .prio = 2, + .urg_fwd = 0, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SM6350_MASTER_USB3, .channels = 1, .buswidth = 8, + .qosbox = &xm_usb3_0_qos, .num_links = 1, - .links = { SM6350_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { .name = "qxm_camnoc_hf0_uncomp", - .id = SM6350_MASTER_CAMNOC_HF0_UNCOMP, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM6350_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_icp_uncomp = { .name = "qxm_camnoc_icp_uncomp", - .id = SM6350_MASTER_CAMNOC_ICP_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM6350_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_sf_uncomp = { .name = "qxm_camnoc_sf_uncomp", - .id = SM6350_MASTER_CAMNOC_SF_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM6350_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", - .id = SM6350_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { .name = "qup1_core_master", - .id = SM6350_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_SLAVE_QUP_CORE_1 }, + .link_nodes = { &qup1_core_slave }, +}; + +static struct qcom_icc_qosbox qnm_npu_qos = { + .num_ports = 2, + .port_offsets = { 0xf000, 0x11000 }, + .prio = 0, + .urg_fwd = 1, }; static struct qcom_icc_node qnm_npu = { .name = "qnm_npu", - .id = SM6350_MASTER_NPU, .channels = 2, .buswidth = 32, + .qosbox = &qnm_npu_qos, .num_links = 1, - .links = { SM6350_SLAVE_CDSP_GEM_NOC }, + .link_nodes = { &qns_cdsp_gemnoc }, +}; + +static struct qcom_icc_qosbox qxm_npu_dsp_qos = { + .num_ports = 1, + .port_offsets = { 0x13000 }, + .prio = 0, + .urg_fwd = 1, }; static struct qcom_icc_node qxm_npu_dsp = { .name = "qxm_npu_dsp", - .id = SM6350_MASTER_NPU_PROC, .channels = 1, .buswidth = 8, + .qosbox = &qxm_npu_dsp_qos, .num_links = 1, - .links = { SM6350_SLAVE_CDSP_GEM_NOC }, + .link_nodes = { &qns_cdsp_gemnoc }, }; static struct qcom_icc_node qnm_snoc = { .name = "qnm_snoc", - .id = SM6350_SNOC_CNOC_MAS, .channels = 1, .buswidth = 8, .num_links = 42, - .links = { SM6350_SLAVE_CAMERA_CFG, - SM6350_SLAVE_SDCC_2, - SM6350_SLAVE_CNOC_MNOC_CFG, - SM6350_SLAVE_UFS_MEM_CFG, - SM6350_SLAVE_QM_CFG, - SM6350_SLAVE_SNOC_CFG, - SM6350_SLAVE_QM_MPU_CFG, - SM6350_SLAVE_GLM, - SM6350_SLAVE_PDM, - SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, - SM6350_SLAVE_A2NOC_CFG, - SM6350_SLAVE_QDSS_CFG, - SM6350_SLAVE_VSENSE_CTRL_CFG, - SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, - SM6350_SLAVE_DISPLAY_CFG, - SM6350_SLAVE_TCSR, - SM6350_SLAVE_DCC_CFG, - SM6350_SLAVE_CNOC_DDRSS, - SM6350_SLAVE_DISPLAY_THROTTLE_CFG, - SM6350_SLAVE_NPU_CFG, - SM6350_SLAVE_AHB2PHY, - SM6350_SLAVE_GRAPHICS_3D_CFG, - SM6350_SLAVE_BOOT_ROM, - SM6350_SLAVE_VENUS_CFG, - SM6350_SLAVE_IPA_CFG, - SM6350_SLAVE_SECURITY, - SM6350_SLAVE_IMEM_CFG, - SM6350_SLAVE_CNOC_MSS, - SM6350_SLAVE_SERVICE_CNOC, - SM6350_SLAVE_USB3, - SM6350_SLAVE_VENUS_THROTTLE_CFG, - SM6350_SLAVE_RBCPR_CX_CFG, - SM6350_SLAVE_A1NOC_CFG, - SM6350_SLAVE_AOSS, - SM6350_SLAVE_PRNG, - SM6350_SLAVE_EMMC_CFG, - SM6350_SLAVE_CRYPTO_0_CFG, - SM6350_SLAVE_PIMEM_CFG, - SM6350_SLAVE_RBCPR_MX_CFG, - SM6350_SLAVE_QUP_0, - SM6350_SLAVE_QUP_1, - SM6350_SLAVE_CLK_CTL - }, + .link_nodes = { &qhs_camera_cfg, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_ufs_mem_cfg, + &qhs_qm_cfg, + &qhs_snoc_cfg, + &qhs_qm_mpu_cfg, + &qhs_glm, + &qhs_pdm, + &qhs_camera_nrt_thrott_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_vsense_ctrl_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_display_cfg, + &qhs_tcsr, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_throttle_cfg, + &qhs_npu_cfg, + &qhs_ahb2phy0, + &qhs_gpuss_cfg, + &qhs_boot_rom, + &qhs_venus_cfg, + &qhs_ipa, + &qhs_security, + &qhs_imem_cfg, + &qhs_mss_cfg, + &srvc_cnoc, + &qhs_usb3_0, + &qhs_venus_throttle_cfg, + &qhs_cpr_cx, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_emmc_cfg, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_cpr_mx, + &qhs_qup0, + &qhs_qup1, + &qhs_clk_ctl }, }; static struct qcom_icc_node xm_qdss_dap = { .name = "xm_qdss_dap", - .id = SM6350_MASTER_QDSS_DAP, .channels = 1, .buswidth = 8, .num_links = 42, - .links = { SM6350_SLAVE_CAMERA_CFG, - SM6350_SLAVE_SDCC_2, - SM6350_SLAVE_CNOC_MNOC_CFG, - SM6350_SLAVE_UFS_MEM_CFG, - SM6350_SLAVE_QM_CFG, - SM6350_SLAVE_SNOC_CFG, - SM6350_SLAVE_QM_MPU_CFG, - SM6350_SLAVE_GLM, - SM6350_SLAVE_PDM, - SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, - SM6350_SLAVE_A2NOC_CFG, - SM6350_SLAVE_QDSS_CFG, - SM6350_SLAVE_VSENSE_CTRL_CFG, - SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, - SM6350_SLAVE_DISPLAY_CFG, - SM6350_SLAVE_TCSR, - SM6350_SLAVE_DCC_CFG, - SM6350_SLAVE_CNOC_DDRSS, - SM6350_SLAVE_DISPLAY_THROTTLE_CFG, - SM6350_SLAVE_NPU_CFG, - SM6350_SLAVE_AHB2PHY, - SM6350_SLAVE_GRAPHICS_3D_CFG, - SM6350_SLAVE_BOOT_ROM, - SM6350_SLAVE_VENUS_CFG, - SM6350_SLAVE_IPA_CFG, - SM6350_SLAVE_SECURITY, - SM6350_SLAVE_IMEM_CFG, - SM6350_SLAVE_CNOC_MSS, - SM6350_SLAVE_SERVICE_CNOC, - SM6350_SLAVE_USB3, - SM6350_SLAVE_VENUS_THROTTLE_CFG, - SM6350_SLAVE_RBCPR_CX_CFG, - SM6350_SLAVE_A1NOC_CFG, - SM6350_SLAVE_AOSS, - SM6350_SLAVE_PRNG, - SM6350_SLAVE_EMMC_CFG, - SM6350_SLAVE_CRYPTO_0_CFG, - SM6350_SLAVE_PIMEM_CFG, - SM6350_SLAVE_RBCPR_MX_CFG, - SM6350_SLAVE_QUP_0, - SM6350_SLAVE_QUP_1, - SM6350_SLAVE_CLK_CTL - }, + .link_nodes = { &qhs_camera_cfg, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_ufs_mem_cfg, + &qhs_qm_cfg, + &qhs_snoc_cfg, + &qhs_qm_mpu_cfg, + &qhs_glm, + &qhs_pdm, + &qhs_camera_nrt_thrott_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_vsense_ctrl_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_display_cfg, + &qhs_tcsr, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_throttle_cfg, + &qhs_npu_cfg, + &qhs_ahb2phy0, + &qhs_gpuss_cfg, + &qhs_boot_rom, + &qhs_venus_cfg, + &qhs_ipa, + &qhs_security, + &qhs_imem_cfg, + &qhs_mss_cfg, + &srvc_cnoc, + &qhs_usb3_0, + &qhs_venus_throttle_cfg, + &qhs_cpr_cx, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_emmc_cfg, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_cpr_mx, + &qhs_qup0, + &qhs_qup1, + &qhs_clk_ctl }, }; static struct qcom_icc_node qhm_cnoc_dc_noc = { .name = "qhm_cnoc_dc_noc", - .id = SM6350_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SM6350_SLAVE_LLCC_CFG, - SM6350_SLAVE_GEM_NOC_CFG - }, + .link_nodes = { &qhs_llcc, + &qhs_gemnoc }, +}; + +static struct qcom_icc_qosbox acm_apps_qos = { + .num_ports = 2, + .port_offsets = { 0x2f100, 0x2f000 }, + .prio = 0, + .urg_fwd = 0, }; static struct qcom_icc_node acm_apps = { .name = "acm_apps", - .id = SM6350_MASTER_AMPSS_M0, .channels = 1, .buswidth = 16, + .qosbox = &acm_apps_qos, .num_links = 2, - .links = { SM6350_SLAVE_LLCC, - SM6350_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, +}; + +static struct qcom_icc_qosbox acm_sys_tcu_qos = { + .num_ports = 1, + .port_offsets = { 0x35000 }, + .prio = 6, + .urg_fwd = 0, }; static struct qcom_icc_node acm_sys_tcu = { .name = "acm_sys_tcu", - .id = SM6350_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, + .qosbox = &acm_sys_tcu_qos, .num_links = 2, - .links = { SM6350_SLAVE_LLCC, - SM6350_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qhm_gemnoc_cfg = { .name = "qhm_gemnoc_cfg", - .id = SM6350_MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 3, - .links = { SM6350_SLAVE_MCDMA_MS_MPU_CFG, - SM6350_SLAVE_SERVICE_GEM_NOC, - SM6350_SLAVE_MSS_PROC_MS_MPU_CFG - }, + .link_nodes = { &qhs_mcdma_ms_mpu_cfg, + &srvc_gemnoc, + &qhs_mdsp_ms_mpu_cfg }, +}; + +static struct qcom_icc_qosbox qnm_cmpnoc_qos = { + .num_ports = 1, + .port_offsets = { 0x2e000 }, + .prio = 0, + .urg_fwd = 1, }; static struct qcom_icc_node qnm_cmpnoc = { .name = "qnm_cmpnoc", - .id = SM6350_MASTER_COMPUTE_NOC, .channels = 1, .buswidth = 32, + .qosbox = &qnm_cmpnoc_qos, .num_links = 2, - .links = { SM6350_SLAVE_LLCC, - SM6350_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, +}; + +static struct qcom_icc_qosbox qnm_mnoc_hf_qos = { + .num_ports = 1, + .port_offsets = { 0x30000 }, + .prio = 0, + .urg_fwd = 1, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SM6350_MASTER_MNOC_HF_MEM_NOC, .channels = 1, .buswidth = 32, + .qosbox = &qnm_mnoc_hf_qos, .num_links = 2, - .links = { SM6350_SLAVE_LLCC, - SM6350_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, +}; + +static struct qcom_icc_qosbox qnm_mnoc_sf_qos = { + .num_ports = 1, + .port_offsets = { 0x34000 }, + .prio = 0, + .urg_fwd = 1, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SM6350_MASTER_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, + .qosbox = &qnm_mnoc_sf_qos, .num_links = 2, - .links = { SM6350_SLAVE_LLCC, - SM6350_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, +}; + +static struct qcom_icc_qosbox qnm_snoc_gc_qos = { + .num_ports = 1, + .port_offsets = { 0x32000 }, + .prio = 0, + .urg_fwd = 1, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SM6350_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, + .qosbox = &qnm_snoc_gc_qos, .num_links = 1, - .links = { SM6350_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, +}; + +static struct qcom_icc_qosbox qnm_snoc_sf_qos = { + .num_ports = 1, + .port_offsets = { 0x31000 }, + .prio = 0, + .urg_fwd = 1, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SM6350_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, + .qosbox = &qnm_snoc_sf_qos, .num_links = 1, - .links = { SM6350_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, +}; + +static struct qcom_icc_qosbox qxm_gpu_qos = { + .num_ports = 2, + .port_offsets = { 0x33000, 0x33080 }, + .prio = 0, + .urg_fwd = 0, }; static struct qcom_icc_node qxm_gpu = { .name = "qxm_gpu", - .id = SM6350_MASTER_GRAPHICS_3D, .channels = 2, .buswidth = 32, + .qosbox = &qxm_gpu_qos, .num_links = 2, - .links = { SM6350_SLAVE_LLCC, - SM6350_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SM6350_MASTER_LLCC, .channels = 2, .buswidth = 4, .num_links = 1, - .links = { SM6350_SLAVE_EBI_CH0 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qhm_mnoc_cfg = { .name = "qhm_mnoc_cfg", - .id = SM6350_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, +}; + +static struct qcom_icc_qosbox qnm_video0_qos = { + .num_ports = 1, + .port_offsets = { 0xf000 }, + .prio = 2, + .urg_fwd = 1, }; static struct qcom_icc_node qnm_video0 = { .name = "qnm_video0", - .id = SM6350_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, + .qosbox = &qnm_video0_qos, .num_links = 1, - .links = { SM6350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_qosbox qnm_video_cvp_qos = { + .num_ports = 1, + .port_offsets = { 0xe000 }, + .prio = 5, + .urg_fwd = 1, }; static struct qcom_icc_node qnm_video_cvp = { .name = "qnm_video_cvp", - .id = SM6350_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 8, + .qosbox = &qnm_video_cvp_qos, .num_links = 1, - .links = { SM6350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_qosbox qxm_camnoc_hf_qos = { + .num_ports = 2, + .port_offsets = { 0xa000, 0xb000 }, + .prio = 3, + .urg_fwd = 1, }; static struct qcom_icc_node qxm_camnoc_hf = { .name = "qxm_camnoc_hf", - .id = SM6350_MASTER_CAMNOC_HF, .channels = 2, .buswidth = 32, + .qosbox = &qxm_camnoc_hf_qos, .num_links = 1, - .links = { SM6350_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_qosbox qxm_camnoc_icp_qos = { + .num_ports = 1, + .port_offsets = { 0xd000 }, + .prio = 5, + .urg_fwd = 0, }; static struct qcom_icc_node qxm_camnoc_icp = { .name = "qxm_camnoc_icp", - .id = SM6350_MASTER_CAMNOC_ICP, .channels = 1, .buswidth = 8, + .qosbox = &qxm_camnoc_icp_qos, .num_links = 1, - .links = { SM6350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_qosbox qxm_camnoc_sf_qos = { + .num_ports = 1, + .port_offsets = { 0x9000 }, + .prio = 3, + .urg_fwd = 1, }; static struct qcom_icc_node qxm_camnoc_sf = { .name = "qxm_camnoc_sf", - .id = SM6350_MASTER_CAMNOC_SF, .channels = 1, .buswidth = 32, + .qosbox = &qxm_camnoc_sf_qos, .num_links = 1, - .links = { SM6350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_qosbox qxm_mdp0_qos = { + .num_ports = 1, + .port_offsets = { 0xc000 }, + .prio = 3, + .urg_fwd = 1, }; static struct qcom_icc_node qxm_mdp0 = { .name = "qxm_mdp0", - .id = SM6350_MASTER_MDP_PORT0, .channels = 1, .buswidth = 32, + .qosbox = &qxm_mdp0_qos, .num_links = 1, - .links = { SM6350_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node amm_npu_sys = { .name = "amm_npu_sys", - .id = SM6350_MASTER_NPU_SYS, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM6350_SLAVE_NPU_COMPUTE_NOC }, + .link_nodes = { &qns_npu_sys }, }; static struct qcom_icc_node qhm_npu_cfg = { .name = "qhm_npu_cfg", - .id = SM6350_MASTER_NPU_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 8, - .links = { SM6350_SLAVE_SERVICE_NPU_NOC, - SM6350_SLAVE_ISENSE_CFG, - SM6350_SLAVE_NPU_LLM_CFG, - SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, - SM6350_SLAVE_NPU_CP, - SM6350_SLAVE_NPU_TCM, - SM6350_SLAVE_NPU_CAL_DP0, - SM6350_SLAVE_NPU_DPM - }, + .link_nodes = { &srvc_noc, + &qhs_isense, + &qhs_llm, + &qhs_dma_bwmon, + &qhs_cp, + &qhs_tcm, + &qhs_cal_dp0, + &qhs_dpm }, }; static struct qcom_icc_node qhm_snoc_cfg = { .name = "qhm_snoc_cfg", - .id = SM6350_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SM6350_A1NOC_SNOC_MAS, .channels = 1, .buswidth = 16, .num_links = 6, - .links = { SM6350_SLAVE_SNOC_GEM_NOC_SF, - SM6350_SLAVE_PIMEM, - SM6350_SLAVE_OCIMEM, - SM6350_SLAVE_APPSS, - SM6350_SNOC_CNOC_SLV, - SM6350_SLAVE_QDSS_STM - }, + .link_nodes = { &qns_gemnoc_sf, + &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SM6350_A2NOC_SNOC_MAS, .channels = 1, .buswidth = 16, .num_links = 7, - .links = { SM6350_SLAVE_SNOC_GEM_NOC_SF, - SM6350_SLAVE_PIMEM, - SM6350_SLAVE_OCIMEM, - SM6350_SLAVE_APPSS, - SM6350_SNOC_CNOC_SLV, - SM6350_SLAVE_TCU, - SM6350_SLAVE_QDSS_STM - }, + .link_nodes = { &qns_gemnoc_sf, + &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_gemnoc = { .name = "qnm_gemnoc", - .id = SM6350_MASTER_GEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 6, - .links = { SM6350_SLAVE_PIMEM, - SM6350_SLAVE_OCIMEM, - SM6350_SLAVE_APPSS, - SM6350_SNOC_CNOC_SLV, - SM6350_SLAVE_TCU, - SM6350_SLAVE_QDSS_STM - }, + .link_nodes = { &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, +}; + +static struct qcom_icc_qosbox qxm_pimem_qos = { + .num_ports = 1, + .port_offsets = { 0xd000 }, + .prio = 2, + .urg_fwd = 0, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = SM6350_MASTER_PIMEM, .channels = 1, .buswidth = 8, + .qosbox = &qxm_pimem_qos, .num_links = 2, - .links = { SM6350_SLAVE_SNOC_GEM_NOC_GC, - SM6350_SLAVE_OCIMEM - }, + .link_nodes = { &qns_gemnoc_gc, + &qxs_imem }, +}; + +static struct qcom_icc_qosbox xm_gic_qos = { + .num_ports = 1, + .port_offsets = { 0xb000 }, + .prio = 3, + .urg_fwd = 0, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SM6350_MASTER_GIC, .channels = 1, .buswidth = 8, + .qosbox = &xm_gic_qos, .num_links = 1, - .links = { SM6350_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SM6350_A1NOC_SNOC_SLV, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM6350_A1NOC_SNOC_MAS }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node srvc_aggre1_noc = { .name = "srvc_aggre1_noc", - .id = SM6350_SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SM6350_A2NOC_SNOC_SLV, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM6350_A2NOC_SNOC_MAS }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node srvc_aggre2_noc = { .name = "srvc_aggre2_noc", - .id = SM6350_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_camnoc_uncomp = { .name = "qns_camnoc_uncomp", - .id = SM6350_SLAVE_CAMNOC_UNCOMP, .channels = 1, .buswidth = 32, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", - .id = SM6350_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qup1_core_slave = { .name = "qup1_core_slave", - .id = SM6350_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_cdsp_gemnoc = { .name = "qns_cdsp_gemnoc", - .id = SM6350_SLAVE_CDSP_GEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM6350_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_cmpnoc }, }; static struct qcom_icc_node qhs_a1_noc_cfg = { .name = "qhs_a1_noc_cfg", - .id = SM6350_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_MASTER_A1NOC_CFG }, + .link_nodes = { &qhm_a1noc_cfg }, }; static struct qcom_icc_node qhs_a2_noc_cfg = { .name = "qhs_a2_noc_cfg", - .id = SM6350_SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_MASTER_A2NOC_CFG }, + .link_nodes = { &qhm_a2noc_cfg }, }; static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", - .id = SM6350_SLAVE_AHB2PHY, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ahb2phy2 = { .name = "qhs_ahb2phy2", - .id = SM6350_SLAVE_AHB2PHY_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SM6350_SLAVE_AOSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_boot_rom = { .name = "qhs_boot_rom", - .id = SM6350_SLAVE_BOOT_ROM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SM6350_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_nrt_thrott_cfg = { .name = "qhs_camera_nrt_thrott_cfg", - .id = SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { .name = "qhs_camera_rt_throttle_cfg", - .id = SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SM6350_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SM6350_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_mx = { .name = "qhs_cpr_mx", - .id = SM6350_SLAVE_RBCPR_MX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SM6350_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dcc_cfg = { .name = "qhs_dcc_cfg", - .id = SM6350_SLAVE_DCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ddrss_cfg = { .name = "qhs_ddrss_cfg", - .id = SM6350_SLAVE_CNOC_DDRSS, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_MASTER_CNOC_DC_NOC }, + .link_nodes = { &qhm_cnoc_dc_noc }, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SM6350_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_display_throttle_cfg = { .name = "qhs_display_throttle_cfg", - .id = SM6350_SLAVE_DISPLAY_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_emmc_cfg = { .name = "qhs_emmc_cfg", - .id = SM6350_SLAVE_EMMC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_glm = { .name = "qhs_glm", - .id = SM6350_SLAVE_GLM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SM6350_SLAVE_GRAPHICS_3D_CFG, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SM6350_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SM6350_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mnoc_cfg = { .name = "qhs_mnoc_cfg", - .id = SM6350_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qhm_mnoc_cfg }, }; static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", - .id = SM6350_SLAVE_CNOC_MSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_npu_cfg = { .name = "qhs_npu_cfg", - .id = SM6350_SLAVE_NPU_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_MASTER_NPU_NOC_CFG }, + .link_nodes = { &qhm_npu_cfg }, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SM6350_SLAVE_PDM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SM6350_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SM6350_SLAVE_PRNG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SM6350_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qm_cfg = { .name = "qhs_qm_cfg", - .id = SM6350_SLAVE_QM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qm_mpu_cfg = { .name = "qhs_qm_mpu_cfg", - .id = SM6350_SLAVE_QM_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", - .id = SM6350_SLAVE_QUP_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = SM6350_SLAVE_QUP_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SM6350_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_security = { .name = "qhs_security", - .id = SM6350_SLAVE_SECURITY, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_snoc_cfg = { .name = "qhs_snoc_cfg", - .id = SM6350_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_MASTER_SNOC_CFG }, + .link_nodes = { &qhm_snoc_cfg }, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SM6350_SLAVE_TCSR, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SM6350_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SM6350_SLAVE_USB3, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SM6350_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_throttle_cfg = { .name = "qhs_venus_throttle_cfg", - .id = SM6350_SLAVE_VENUS_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SM6350_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_cnoc = { .name = "srvc_cnoc", - .id = SM6350_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gemnoc = { .name = "qhs_gemnoc", - .id = SM6350_SLAVE_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM6350_MASTER_GEM_NOC_CFG }, + .link_nodes = { &qhm_gemnoc_cfg }, }; static struct qcom_icc_node qhs_llcc = { .name = "qhs_llcc", - .id = SM6350_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mcdma_ms_mpu_cfg = { .name = "qhs_mcdma_ms_mpu_cfg", - .id = SM6350_SLAVE_MCDMA_MS_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { .name = "qhs_mdsp_ms_mpu_cfg", - .id = SM6350_SLAVE_MSS_PROC_MS_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_gem_noc_snoc = { .name = "qns_gem_noc_snoc", - .id = SM6350_SLAVE_GEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM6350_MASTER_GEM_NOC_SNOC }, + .link_nodes = { &qnm_gemnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SM6350_SLAVE_LLCC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM6350_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node srvc_gemnoc = { .name = "srvc_gemnoc", - .id = SM6350_SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SM6350_SLAVE_EBI_CH0, .channels = 2, .buswidth = 4, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SM6350_SLAVE_MNOC_HF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM6350_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", - .id = SM6350_SLAVE_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM6350_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SM6350_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cal_dp0 = { .name = "qhs_cal_dp0", - .id = SM6350_SLAVE_NPU_CAL_DP0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cp = { .name = "qhs_cp", - .id = SM6350_SLAVE_NPU_CP, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dma_bwmon = { .name = "qhs_dma_bwmon", - .id = SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dpm = { .name = "qhs_dpm", - .id = SM6350_SLAVE_NPU_DPM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_isense = { .name = "qhs_isense", - .id = SM6350_SLAVE_ISENSE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_llm = { .name = "qhs_llm", - .id = SM6350_SLAVE_NPU_LLM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tcm = { .name = "qhs_tcm", - .id = SM6350_SLAVE_NPU_TCM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_npu_sys = { .name = "qns_npu_sys", - .id = SM6350_SLAVE_NPU_COMPUTE_NOC, .channels = 2, .buswidth = 32, }; static struct qcom_icc_node srvc_noc = { .name = "srvc_noc", - .id = SM6350_SLAVE_SERVICE_NPU_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SM6350_SLAVE_APPSS, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qns_cnoc = { .name = "qns_cnoc", - .id = SM6350_SNOC_CNOC_SLV, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM6350_SNOC_CNOC_MAS }, + .link_nodes = { &qnm_snoc }, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = SM6350_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM6350_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SM6350_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM6350_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SM6350_SLAVE_OCIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = SM6350_SLAVE_PIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SM6350_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SM6350_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SM6350_SLAVE_TCU, .channels = 1, .buswidth = 8, }; @@ -1403,11 +1611,21 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, }; +static const struct regmap_config sm6350_aggre1_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x15080, + .fast_io = true, +}; + static const struct qcom_icc_desc sm6350_aggre1_noc = { + .config = &sm6350_aggre1_noc_regmap_config, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), + .qos_requires_clocks = true, }; static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { @@ -1428,11 +1646,21 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, }; +static const struct regmap_config sm6350_aggre2_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1f880, + .fast_io = true, +}; + static const struct qcom_icc_desc sm6350_aggre2_noc = { + .config = &sm6350_aggre2_noc_regmap_config, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), + .qos_requires_clocks = true, }; static struct qcom_icc_bcm * const clk_virt_bcms[] = { @@ -1474,7 +1702,16 @@ static struct qcom_icc_node * const compute_noc_nodes[] = { [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc, }; +static const struct regmap_config sm6350_compute_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1f880, + .fast_io = true, +}; + static const struct qcom_icc_desc sm6350_compute_noc = { + .config = &sm6350_compute_noc_regmap_config, .nodes = compute_noc_nodes, .num_nodes = ARRAY_SIZE(compute_noc_nodes), .bcms = compute_noc_bcms, @@ -1541,20 +1778,24 @@ static const struct qcom_icc_desc sm6350_config_noc = { .num_bcms = ARRAY_SIZE(config_noc_bcms), }; -static struct qcom_icc_bcm * const dc_noc_bcms[] = { -}; - static struct qcom_icc_node * const dc_noc_nodes[] = { [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc, [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc, [SLAVE_LLCC_CFG] = &qhs_llcc, }; +static const struct regmap_config sm6350_dc_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x3200, + .fast_io = true, +}; + static const struct qcom_icc_desc sm6350_dc_noc = { + .config = &sm6350_dc_noc_regmap_config, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), - .bcms = dc_noc_bcms, - .num_bcms = ARRAY_SIZE(dc_noc_bcms), }; static struct qcom_icc_bcm * const gem_noc_bcms[] = { @@ -1581,7 +1822,16 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, }; +static const struct regmap_config sm6350_gem_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x3e200, + .fast_io = true, +}; + static const struct qcom_icc_desc sm6350_gem_noc = { + .config = &sm6350_gem_noc_regmap_config, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1608,16 +1858,22 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { [SLAVE_SERVICE_MNOC] = &srvc_mnoc, }; +static const struct regmap_config sm6350_mmss_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1c100, + .fast_io = true, +}; + static const struct qcom_icc_desc sm6350_mmss_noc = { + .config = &sm6350_mmss_noc_regmap_config, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, .num_bcms = ARRAY_SIZE(mmss_noc_bcms), }; -static struct qcom_icc_bcm * const npu_noc_bcms[] = { -}; - static struct qcom_icc_node * const npu_noc_nodes[] = { [MASTER_NPU_SYS] = &amm_npu_sys, [MASTER_NPU_NOC_CFG] = &qhm_npu_cfg, @@ -1635,8 +1891,6 @@ static struct qcom_icc_node * const npu_noc_nodes[] = { static const struct qcom_icc_desc sm6350_npu_noc = { .nodes = npu_noc_nodes, .num_nodes = ARRAY_SIZE(npu_noc_nodes), - .bcms = npu_noc_bcms, - .num_bcms = ARRAY_SIZE(npu_noc_bcms), }; static struct qcom_icc_bcm * const system_noc_bcms[] = { @@ -1668,7 +1922,16 @@ static struct qcom_icc_node * const system_noc_nodes[] = { [SLAVE_TCU] = &xs_sys_tcu_cfg, }; +static const struct regmap_config sm6350_system_noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x17080, + .fast_io = true, +}; + static const struct qcom_icc_desc sm6350_system_noc = { + .config = &sm6350_system_noc_regmap_config, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, @@ -1702,7 +1965,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove_new = qcom_icc_rpmh_remove, + .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sm6350", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sm6350.h b/drivers/interconnect/qcom/sm6350.h deleted file mode 100644 index 43cf2930c88a..000000000000 --- a/drivers/interconnect/qcom/sm6350.h +++ /dev/null @@ -1,139 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm #define SM6350 interconnect IDs - * - * Copyright (C) 2022 Luca Weiss <luca.weiss@fairphone.com> - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM6350_H -#define __DRIVERS_INTERCONNECT_QCOM_SM6350_H - -#define SM6350_A1NOC_SNOC_MAS 0 -#define SM6350_A1NOC_SNOC_SLV 1 -#define SM6350_A2NOC_SNOC_MAS 2 -#define SM6350_A2NOC_SNOC_SLV 3 -#define SM6350_MASTER_A1NOC_CFG 4 -#define SM6350_MASTER_A2NOC_CFG 5 -#define SM6350_MASTER_AMPSS_M0 6 -#define SM6350_MASTER_CAMNOC_HF 7 -#define SM6350_MASTER_CAMNOC_HF0_UNCOMP 8 -#define SM6350_MASTER_CAMNOC_ICP 9 -#define SM6350_MASTER_CAMNOC_ICP_UNCOMP 10 -#define SM6350_MASTER_CAMNOC_SF 11 -#define SM6350_MASTER_CAMNOC_SF_UNCOMP 12 -#define SM6350_MASTER_CNOC_DC_NOC 13 -#define SM6350_MASTER_CNOC_MNOC_CFG 14 -#define SM6350_MASTER_COMPUTE_NOC 15 -#define SM6350_MASTER_CRYPTO_CORE_0 16 -#define SM6350_MASTER_EMMC 17 -#define SM6350_MASTER_GEM_NOC_CFG 18 -#define SM6350_MASTER_GEM_NOC_SNOC 19 -#define SM6350_MASTER_GIC 20 -#define SM6350_MASTER_GRAPHICS_3D 21 -#define SM6350_MASTER_IPA 22 -#define SM6350_MASTER_LLCC 23 -#define SM6350_MASTER_MDP_PORT0 24 -#define SM6350_MASTER_MNOC_HF_MEM_NOC 25 -#define SM6350_MASTER_MNOC_SF_MEM_NOC 26 -#define SM6350_MASTER_NPU 27 -#define SM6350_MASTER_NPU_NOC_CFG 28 -#define SM6350_MASTER_NPU_PROC 29 -#define SM6350_MASTER_NPU_SYS 30 -#define SM6350_MASTER_PIMEM 31 -#define SM6350_MASTER_QDSS_BAM 32 -#define SM6350_MASTER_QDSS_DAP 33 -#define SM6350_MASTER_QDSS_ETR 34 -#define SM6350_MASTER_QUP_0 35 -#define SM6350_MASTER_QUP_1 36 -#define SM6350_MASTER_QUP_CORE_0 37 -#define SM6350_MASTER_QUP_CORE_1 38 -#define SM6350_MASTER_SDCC_2 39 -#define SM6350_MASTER_SNOC_CFG 40 -#define SM6350_MASTER_SNOC_GC_MEM_NOC 41 -#define SM6350_MASTER_SNOC_SF_MEM_NOC 42 -#define SM6350_MASTER_SYS_TCU 43 -#define SM6350_MASTER_UFS_MEM 44 -#define SM6350_MASTER_USB3 45 -#define SM6350_MASTER_VIDEO_P0 46 -#define SM6350_MASTER_VIDEO_PROC 47 -#define SM6350_SLAVE_A1NOC_CFG 48 -#define SM6350_SLAVE_A2NOC_CFG 49 -#define SM6350_SLAVE_AHB2PHY 50 -#define SM6350_SLAVE_AHB2PHY_2 51 -#define SM6350_SLAVE_AOSS 52 -#define SM6350_SLAVE_APPSS 53 -#define SM6350_SLAVE_BOOT_ROM 54 -#define SM6350_SLAVE_CAMERA_CFG 55 -#define SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG 56 -#define SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG 57 -#define SM6350_SLAVE_CAMNOC_UNCOMP 58 -#define SM6350_SLAVE_CDSP_GEM_NOC 59 -#define SM6350_SLAVE_CLK_CTL 60 -#define SM6350_SLAVE_CNOC_DDRSS 61 -#define SM6350_SLAVE_CNOC_MNOC_CFG 62 -#define SM6350_SLAVE_CNOC_MSS 63 -#define SM6350_SLAVE_CRYPTO_0_CFG 64 -#define SM6350_SLAVE_DCC_CFG 65 -#define SM6350_SLAVE_DISPLAY_CFG 66 -#define SM6350_SLAVE_DISPLAY_THROTTLE_CFG 67 -#define SM6350_SLAVE_EBI_CH0 68 -#define SM6350_SLAVE_EMMC_CFG 69 -#define SM6350_SLAVE_GEM_NOC_CFG 70 -#define SM6350_SLAVE_GEM_NOC_SNOC 71 -#define SM6350_SLAVE_GLM 72 -#define SM6350_SLAVE_GRAPHICS_3D_CFG 73 -#define SM6350_SLAVE_IMEM_CFG 74 -#define SM6350_SLAVE_IPA_CFG 75 -#define SM6350_SLAVE_ISENSE_CFG 76 -#define SM6350_SLAVE_LLCC 77 -#define SM6350_SLAVE_LLCC_CFG 78 -#define SM6350_SLAVE_MCDMA_MS_MPU_CFG 79 -#define SM6350_SLAVE_MNOC_HF_MEM_NOC 80 -#define SM6350_SLAVE_MNOC_SF_MEM_NOC 81 -#define SM6350_SLAVE_MSS_PROC_MS_MPU_CFG 82 -#define SM6350_SLAVE_NPU_CAL_DP0 83 -#define SM6350_SLAVE_NPU_CFG 84 -#define SM6350_SLAVE_NPU_COMPUTE_NOC 85 -#define SM6350_SLAVE_NPU_CP 86 -#define SM6350_SLAVE_NPU_DPM 87 -#define SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG 88 -#define SM6350_SLAVE_NPU_LLM_CFG 89 -#define SM6350_SLAVE_NPU_TCM 90 -#define SM6350_SLAVE_OCIMEM 91 -#define SM6350_SLAVE_PDM 92 -#define SM6350_SLAVE_PIMEM 93 -#define SM6350_SLAVE_PIMEM_CFG 94 -#define SM6350_SLAVE_PRNG 95 -#define SM6350_SLAVE_QDSS_CFG 96 -#define SM6350_SLAVE_QDSS_STM 97 -#define SM6350_SLAVE_QM_CFG 98 -#define SM6350_SLAVE_QM_MPU_CFG 99 -#define SM6350_SLAVE_QUP_0 100 -#define SM6350_SLAVE_QUP_1 101 -#define SM6350_SLAVE_QUP_CORE_0 102 -#define SM6350_SLAVE_QUP_CORE_1 103 -#define SM6350_SLAVE_RBCPR_CX_CFG 104 -#define SM6350_SLAVE_RBCPR_MX_CFG 105 -#define SM6350_SLAVE_SDCC_2 106 -#define SM6350_SLAVE_SECURITY 107 -#define SM6350_SLAVE_SERVICE_A1NOC 108 -#define SM6350_SLAVE_SERVICE_A2NOC 109 -#define SM6350_SLAVE_SERVICE_CNOC 110 -#define SM6350_SLAVE_SERVICE_GEM_NOC 111 -#define SM6350_SLAVE_SERVICE_MNOC 112 -#define SM6350_SLAVE_SERVICE_NPU_NOC 113 -#define SM6350_SLAVE_SERVICE_SNOC 114 -#define SM6350_SLAVE_SNOC_CFG 115 -#define SM6350_SLAVE_SNOC_GEM_NOC_GC 116 -#define SM6350_SLAVE_SNOC_GEM_NOC_SF 117 -#define SM6350_SLAVE_TCSR 118 -#define SM6350_SLAVE_TCU 119 -#define SM6350_SLAVE_UFS_MEM_CFG 120 -#define SM6350_SLAVE_USB3 121 -#define SM6350_SLAVE_VENUS_CFG 122 -#define SM6350_SLAVE_VENUS_THROTTLE_CFG 123 -#define SM6350_SLAVE_VSENSE_CTRL_CFG 124 -#define SM6350_SNOC_CNOC_MAS 125 -#define SM6350_SNOC_CNOC_SLV 126 - -#endif diff --git a/drivers/interconnect/qcom/sm7150.c b/drivers/interconnect/qcom/sm7150.c index dc0d1343f510..0390d0468b48 100644 --- a/drivers/interconnect/qcom/sm7150.c +++ b/drivers/interconnect/qcom/sm7150.c @@ -14,1169 +14,1154 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sm7150.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qup_center; +static struct qcom_icc_node qhm_tsif; +static struct qcom_icc_node xm_emmc; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node qhm_a2noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup_north; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_rt_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qxm_camnoc_nrt_uncomp; +static struct qcom_icc_node qnm_npu; +static struct qcom_icc_node qhm_spdm; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc_dc_noc; +static struct qcom_icc_node acm_apps; +static struct qcom_icc_node acm_sys_tcu; +static struct qcom_icc_node qhm_gemnoc_cfg; +static struct qcom_icc_node qnm_cmpnoc; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_gpu; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qxm_camnoc_hf; +static struct qcom_icc_node qxm_camnoc_nrt; +static struct qcom_icc_node qxm_camnoc_rt; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_mdp1; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qxm_venus0; +static struct qcom_icc_node qxm_venus1; +static struct qcom_icc_node qxm_venus_arm9; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gemnoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_pcie_gemnoc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qns_cdsp_gemnoc; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_a2_noc_cfg; +static struct qcom_icc_node qhs_ahb2phy_north; +static struct qcom_icc_node qhs_ahb2phy_south; +static struct qcom_icc_node qhs_ahb2phy_west; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_camera_nrt_thrott_cfg; +static struct qcom_icc_node qhs_camera_rt_throttle_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_dsp_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_display_throttle_cfg; +static struct qcom_icc_node qhs_emmc_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_pcie_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qupv3_center; +static struct qcom_icc_node qhs_qupv3_north; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spdm; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm_north; +static struct qcom_icc_node qhs_tlmm_south; +static struct qcom_icc_node qhs_tlmm_west; +static struct qcom_icc_node qhs_tsif; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_venus_cvp_throttle_cfg; +static struct qcom_icc_node qhs_venus_throttle_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_cnoc_a2noc; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_gemnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_gem_noc_snoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node srvc_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns2_mem_noc; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; static struct qcom_icc_node qhm_a1noc_cfg = { - .name = "qhm-a1noc-cfg", - .id = SM7150_MASTER_A1NOC_CFG, + .name = "qhm_a1noc_cfg", .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_SLAVE_SERVICE_A1NOC }, + .link_nodes = { &srvc_aggre1_noc }, }; static struct qcom_icc_node qhm_qup_center = { .name = "qhm_qup_center", - .id = SM7150_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_tsif = { .name = "qhm_tsif", - .id = SM7150_MASTER_TSIF, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_emmc = { .name = "xm_emmc", - .id = SM7150_MASTER_EMMC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SM7150_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SM7150_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SM7150_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_a2noc_cfg = { .name = "qhm_a2noc_cfg", - .id = SM7150_MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_SLAVE_SERVICE_A2NOC }, + .link_nodes = { &srvc_aggre2_noc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SM7150_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup_north = { .name = "qhm_qup_north", - .id = SM7150_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_cnoc = { .name = "qnm_cnoc", - .id = SM7150_MASTER_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SM7150_MASTER_CRYPTO_CORE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SM7150_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", - .id = SM7150_MASTER_PCIE, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_gemnoc }, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = SM7150_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SM7150_MASTER_USB3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { .name = "qxm_camnoc_hf0_uncomp", - .id = SM7150_MASTER_CAMNOC_HF0_UNCOMP, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_rt_uncomp = { .name = "qxm_camnoc_rt_uncomp", - .id = SM7150_MASTER_CAMNOC_RT_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_sf_uncomp = { .name = "qxm_camnoc_sf_uncomp", - .id = SM7150_MASTER_CAMNOC_SF_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_nrt_uncomp = { .name = "qxm_camnoc_nrt_uncomp", - .id = SM7150_MASTER_CAMNOC_NRT_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qnm_npu = { .name = "qnm_npu", - .id = SM7150_MASTER_NPU, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_CDSP_GEM_NOC }, + .link_nodes = { &qns_cdsp_gemnoc }, }; static struct qcom_icc_node qhm_spdm = { .name = "qhm_spdm", - .id = SM7150_MASTER_SPDM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_SLAVE_CNOC_A2NOC }, + .link_nodes = { &qns_cnoc_a2noc }, }; static struct qcom_icc_node qnm_snoc = { .name = "qnm_snoc", - .id = SM7150_SNOC_CNOC_MAS, .channels = 1, .buswidth = 8, .num_links = 47, - .links = { SM7150_SLAVE_TLMM_SOUTH, - SM7150_SLAVE_CAMERA_CFG, - SM7150_SLAVE_SDCC_4, - SM7150_SLAVE_SDCC_2, - SM7150_SLAVE_CNOC_MNOC_CFG, - SM7150_SLAVE_UFS_MEM_CFG, - SM7150_SLAVE_QUP_0, - SM7150_SLAVE_GLM, - SM7150_SLAVE_PDM, - SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG, - SM7150_SLAVE_A2NOC_CFG, - SM7150_SLAVE_QDSS_CFG, - SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG, - SM7150_SLAVE_DISPLAY_CFG, - SM7150_SLAVE_PCIE_CFG, - SM7150_SLAVE_DISPLAY_THROTTLE_CFG, - SM7150_SLAVE_TCSR, - SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG, - SM7150_SLAVE_CNOC_DDRSS, - SM7150_SLAVE_AHB2PHY_NORTH, - SM7150_SLAVE_SNOC_CFG, - SM7150_SLAVE_GRAPHICS_3D_CFG, - SM7150_SLAVE_VENUS_CFG, - SM7150_SLAVE_TSIF, - SM7150_SLAVE_CDSP_CFG, - SM7150_SLAVE_CLK_CTL, - SM7150_SLAVE_AOP, - SM7150_SLAVE_QUP_1, - SM7150_SLAVE_AHB2PHY_SOUTH, - SM7150_SLAVE_SERVICE_CNOC, - SM7150_SLAVE_AHB2PHY_WEST, - SM7150_SLAVE_USB3, - SM7150_SLAVE_VENUS_THROTTLE_CFG, - SM7150_SLAVE_IPA_CFG, - SM7150_SLAVE_RBCPR_CX_CFG, - SM7150_SLAVE_TLMM_WEST, - SM7150_SLAVE_A1NOC_CFG, - SM7150_SLAVE_AOSS, - SM7150_SLAVE_PRNG, - SM7150_SLAVE_VSENSE_CTRL_CFG, - SM7150_SLAVE_EMMC_CFG, - SM7150_SLAVE_SPDM_WRAPPER, - SM7150_SLAVE_CRYPTO_0_CFG, - SM7150_SLAVE_PIMEM_CFG, - SM7150_SLAVE_TLMM_NORTH, - SM7150_SLAVE_RBCPR_MX_CFG, - SM7150_SLAVE_IMEM_CFG - }, + .link_nodes = { &qhs_tlmm_south, + &qhs_camera_cfg, + &qhs_sdc4, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_ufs_mem_cfg, + &qhs_qupv3_center, + &qhs_glm, + &qhs_pdm, + &qhs_camera_nrt_thrott_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_display_cfg, + &qhs_pcie_cfg, + &qhs_display_throttle_cfg, + &qhs_tcsr, + &qhs_venus_cvp_throttle_cfg, + &qhs_ddrss_cfg, + &qhs_ahb2phy_north, + &qhs_snoc_cfg, + &qhs_gpuss_cfg, + &qhs_venus_cfg, + &qhs_tsif, + &qhs_compute_dsp_cfg, + &qhs_clk_ctl, + &qhs_aop, + &qhs_qupv3_north, + &qhs_ahb2phy_south, + &srvc_cnoc, + &qhs_ahb2phy_west, + &qhs_usb3_0, + &qhs_venus_throttle_cfg, + &qhs_ipa, + &qhs_cpr_cx, + &qhs_tlmm_west, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_vsense_ctrl_cfg, + &qhs_emmc_cfg, + &qhs_spdm, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_tlmm_north, + &qhs_cpr_mx, + &qhs_imem_cfg }, }; static struct qcom_icc_node xm_qdss_dap = { .name = "xm_qdss_dap", - .id = SM7150_MASTER_QDSS_DAP, .channels = 1, .buswidth = 8, .num_links = 48, - .links = { SM7150_SLAVE_TLMM_SOUTH, - SM7150_SLAVE_CAMERA_CFG, - SM7150_SLAVE_SDCC_4, - SM7150_SLAVE_SDCC_2, - SM7150_SLAVE_CNOC_MNOC_CFG, - SM7150_SLAVE_UFS_MEM_CFG, - SM7150_SLAVE_QUP_0, - SM7150_SLAVE_GLM, - SM7150_SLAVE_PDM, - SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG, - SM7150_SLAVE_A2NOC_CFG, - SM7150_SLAVE_QDSS_CFG, - SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG, - SM7150_SLAVE_DISPLAY_CFG, - SM7150_SLAVE_PCIE_CFG, - SM7150_SLAVE_DISPLAY_THROTTLE_CFG, - SM7150_SLAVE_TCSR, - SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG, - SM7150_SLAVE_CNOC_DDRSS, - SM7150_SLAVE_CNOC_A2NOC, - SM7150_SLAVE_AHB2PHY_NORTH, - SM7150_SLAVE_SNOC_CFG, - SM7150_SLAVE_GRAPHICS_3D_CFG, - SM7150_SLAVE_VENUS_CFG, - SM7150_SLAVE_TSIF, - SM7150_SLAVE_CDSP_CFG, - SM7150_SLAVE_CLK_CTL, - SM7150_SLAVE_AOP, - SM7150_SLAVE_QUP_1, - SM7150_SLAVE_AHB2PHY_SOUTH, - SM7150_SLAVE_SERVICE_CNOC, - SM7150_SLAVE_AHB2PHY_WEST, - SM7150_SLAVE_USB3, - SM7150_SLAVE_VENUS_THROTTLE_CFG, - SM7150_SLAVE_IPA_CFG, - SM7150_SLAVE_RBCPR_CX_CFG, - SM7150_SLAVE_TLMM_WEST, - SM7150_SLAVE_A1NOC_CFG, - SM7150_SLAVE_AOSS, - SM7150_SLAVE_PRNG, - SM7150_SLAVE_VSENSE_CTRL_CFG, - SM7150_SLAVE_EMMC_CFG, - SM7150_SLAVE_SPDM_WRAPPER, - SM7150_SLAVE_CRYPTO_0_CFG, - SM7150_SLAVE_PIMEM_CFG, - SM7150_SLAVE_TLMM_NORTH, - SM7150_SLAVE_RBCPR_MX_CFG, - SM7150_SLAVE_IMEM_CFG - }, + .link_nodes = { &qhs_tlmm_south, + &qhs_camera_cfg, + &qhs_sdc4, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_ufs_mem_cfg, + &qhs_qupv3_center, + &qhs_glm, + &qhs_pdm, + &qhs_camera_nrt_thrott_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_display_cfg, + &qhs_pcie_cfg, + &qhs_display_throttle_cfg, + &qhs_tcsr, + &qhs_venus_cvp_throttle_cfg, + &qhs_ddrss_cfg, + &qns_cnoc_a2noc, + &qhs_ahb2phy_north, + &qhs_snoc_cfg, + &qhs_gpuss_cfg, + &qhs_venus_cfg, + &qhs_tsif, + &qhs_compute_dsp_cfg, + &qhs_clk_ctl, + &qhs_aop, + &qhs_qupv3_north, + &qhs_ahb2phy_south, + &srvc_cnoc, + &qhs_ahb2phy_west, + &qhs_usb3_0, + &qhs_venus_throttle_cfg, + &qhs_ipa, + &qhs_cpr_cx, + &qhs_tlmm_west, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_vsense_ctrl_cfg, + &qhs_emmc_cfg, + &qhs_spdm, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_tlmm_north, + &qhs_cpr_mx, + &qhs_imem_cfg }, }; static struct qcom_icc_node qhm_cnoc_dc_noc = { .name = "qhm_cnoc_dc_noc", - .id = SM7150_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SM7150_SLAVE_LLCC_CFG, - SM7150_SLAVE_GEM_NOC_CFG - }, + .link_nodes = { &qhs_llcc, + &qhs_gemnoc }, }; static struct qcom_icc_node acm_apps = { .name = "acm_apps", - .id = SM7150_MASTER_AMPSS_M0, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SM7150_SLAVE_LLCC, - SM7150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node acm_sys_tcu = { .name = "acm_sys_tcu", - .id = SM7150_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM7150_SLAVE_LLCC, - SM7150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qhm_gemnoc_cfg = { .name = "qhm_gemnoc_cfg", - .id = SM7150_MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SM7150_SLAVE_SERVICE_GEM_NOC, - SM7150_SLAVE_MSS_PROC_MS_MPU_CFG - }, + .link_nodes = { &srvc_gemnoc, + &qhs_mdsp_ms_mpu_cfg }, }; static struct qcom_icc_node qnm_cmpnoc = { .name = "qnm_cmpnoc", - .id = SM7150_MASTER_COMPUTE_NOC, .channels = 1, .buswidth = 32, .num_links = 2, - .links = { SM7150_SLAVE_LLCC, - SM7150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SM7150_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SM7150_MASTER_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 2, - .links = { SM7150_SLAVE_LLCC, - SM7150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = SM7150_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM7150_SLAVE_LLCC, - SM7150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SM7150_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SM7150_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM7150_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qxm_gpu = { .name = "qxm_gpu", - .id = SM7150_MASTER_GRAPHICS_3D, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM7150_SLAVE_LLCC, - SM7150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SM7150_MASTER_LLCC, .channels = 2, .buswidth = 4, .num_links = 1, - .links = { SM7150_SLAVE_EBI_CH0 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qhm_mnoc_cfg = { .name = "qhm_mnoc_cfg", - .id = SM7150_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qxm_camnoc_hf = { .name = "qxm_camnoc_hf", - .id = SM7150_MASTER_CAMNOC_HF0, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_nrt = { .name = "qxm_camnoc_nrt", - .id = SM7150_MASTER_CAMNOC_NRT, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_camnoc_rt = { .name = "qxm_camnoc_rt", - .id = SM7150_MASTER_CAMNOC_RT, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_sf = { .name = "qxm_camnoc_sf", - .id = SM7150_MASTER_CAMNOC_SF, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_mdp0 = { .name = "qxm_mdp0", - .id = SM7150_MASTER_MDP_PORT0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_mdp1 = { .name = "qxm_mdp1", - .id = SM7150_MASTER_MDP_PORT1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_rot = { .name = "qxm_rot", - .id = SM7150_MASTER_ROTATOR, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus0 = { .name = "qxm_venus0", - .id = SM7150_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus1 = { .name = "qxm_venus1", - .id = SM7150_MASTER_VIDEO_P1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus_arm9 = { .name = "qxm_venus_arm9", - .id = SM7150_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qhm_snoc_cfg = { .name = "qhm_snoc_cfg", - .id = SM7150_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SM7150_A1NOC_SNOC_MAS, .channels = 1, .buswidth = 16, .num_links = 6, - .links = { SM7150_SLAVE_SNOC_GEM_NOC_SF, - SM7150_SLAVE_PIMEM, - SM7150_SLAVE_OCIMEM, - SM7150_SLAVE_APPSS, - SM7150_SNOC_CNOC_SLV, - SM7150_SLAVE_QDSS_STM - }, + .link_nodes = { &qns_gemnoc_sf, + &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SM7150_A2NOC_SNOC_MAS, .channels = 1, .buswidth = 16, .num_links = 7, - .links = { SM7150_SLAVE_SNOC_GEM_NOC_SF, - SM7150_SLAVE_PIMEM, - SM7150_SLAVE_OCIMEM, - SM7150_SLAVE_APPSS, - SM7150_SNOC_CNOC_SLV, - SM7150_SLAVE_TCU, - SM7150_SLAVE_QDSS_STM - }, + .link_nodes = { &qns_gemnoc_sf, + &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_gemnoc = { .name = "qnm_gemnoc", - .id = SM7150_MASTER_GEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 6, - .links = { SM7150_SLAVE_PIMEM, - SM7150_SLAVE_OCIMEM, - SM7150_SLAVE_APPSS, - SM7150_SNOC_CNOC_SLV, - SM7150_SLAVE_TCU, - SM7150_SLAVE_QDSS_STM - }, + .link_nodes = { &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = SM7150_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM7150_SLAVE_SNOC_GEM_NOC_GC, - SM7150_SLAVE_OCIMEM - }, + .link_nodes = { &qns_gemnoc_gc, + &qxs_imem }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SM7150_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM7150_SLAVE_SNOC_GEM_NOC_GC, - SM7150_SLAVE_OCIMEM - }, + .link_nodes = { &qns_gemnoc_gc, + &qxs_imem }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SM7150_A1NOC_SNOC_SLV, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM7150_A1NOC_SNOC_MAS }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node srvc_aggre1_noc = { .name = "srvc_aggre1_noc", - .id = SM7150_SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SM7150_A2NOC_SNOC_SLV, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM7150_A2NOC_SNOC_MAS }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qns_pcie_gemnoc = { .name = "qns_pcie_gemnoc", - .id = SM7150_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node srvc_aggre2_noc = { .name = "srvc_aggre2_noc", - .id = SM7150_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_camnoc_uncomp = { .name = "qns_camnoc_uncomp", - .id = SM7150_SLAVE_CAMNOC_UNCOMP, .channels = 1, .buswidth = 32, }; static struct qcom_icc_node qns_cdsp_gemnoc = { .name = "qns_cdsp_gemnoc", - .id = SM7150_SLAVE_CDSP_GEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_cmpnoc }, }; static struct qcom_icc_node qhs_a1_noc_cfg = { .name = "qhs_a1_noc_cfg", - .id = SM7150_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_MASTER_A1NOC_CFG }, + .link_nodes = { &qhm_a1noc_cfg }, }; static struct qcom_icc_node qhs_a2_noc_cfg = { .name = "qhs_a2_noc_cfg", - .id = SM7150_SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_MASTER_A2NOC_CFG }, + .link_nodes = { &qhm_a2noc_cfg }, }; static struct qcom_icc_node qhs_ahb2phy_north = { .name = "qhs_ahb2phy_north", - .id = SM7150_SLAVE_AHB2PHY_NORTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ahb2phy_south = { .name = "qhs_ahb2phy_south", - .id = SM7150_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ahb2phy_west = { .name = "qhs_ahb2phy_west", - .id = SM7150_SLAVE_AHB2PHY_WEST, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aop = { .name = "qhs_aop", - .id = SM7150_SLAVE_AOP, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SM7150_SLAVE_AOSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SM7150_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_nrt_thrott_cfg = { .name = "qhs_camera_nrt_thrott_cfg", - .id = SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { .name = "qhs_camera_rt_throttle_cfg", - .id = SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SM7150_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_compute_dsp_cfg = { .name = "qhs_compute_dsp_cfg", - .id = SM7150_SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SM7150_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_mx = { .name = "qhs_cpr_mx", - .id = SM7150_SLAVE_RBCPR_MX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SM7150_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ddrss_cfg = { .name = "qhs_ddrss_cfg", - .id = SM7150_SLAVE_CNOC_DDRSS, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_MASTER_CNOC_DC_NOC }, + .link_nodes = { &qhm_cnoc_dc_noc }, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SM7150_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_display_throttle_cfg = { .name = "qhs_display_throttle_cfg", - .id = SM7150_SLAVE_DISPLAY_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_emmc_cfg = { .name = "qhs_emmc_cfg", - .id = SM7150_SLAVE_EMMC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_glm = { .name = "qhs_glm", - .id = SM7150_SLAVE_GLM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SM7150_SLAVE_GRAPHICS_3D_CFG, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SM7150_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SM7150_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mnoc_cfg = { .name = "qhs_mnoc_cfg", - .id = SM7150_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qhm_mnoc_cfg }, }; static struct qcom_icc_node qhs_pcie_cfg = { .name = "qhs_pcie_cfg", - .id = SM7150_SLAVE_PCIE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SM7150_SLAVE_PDM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SM7150_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SM7150_SLAVE_PRNG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SM7150_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qupv3_center = { .name = "qhs_qupv3_center", - .id = SM7150_SLAVE_QUP_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qupv3_north = { .name = "qhs_qupv3_north", - .id = SM7150_SLAVE_QUP_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SM7150_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SM7150_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_snoc_cfg = { .name = "qhs_snoc_cfg", - .id = SM7150_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_MASTER_SNOC_CFG }, + .link_nodes = { &qhm_snoc_cfg }, }; static struct qcom_icc_node qhs_spdm = { .name = "qhs_spdm", - .id = SM7150_SLAVE_SPDM_WRAPPER, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SM7150_SLAVE_TCSR, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_north = { .name = "qhs_tlmm_north", - .id = SM7150_SLAVE_TLMM_NORTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_south = { .name = "qhs_tlmm_south", - .id = SM7150_SLAVE_TLMM_SOUTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_west = { .name = "qhs_tlmm_west", - .id = SM7150_SLAVE_TLMM_WEST, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tsif = { .name = "qhs_tsif", - .id = SM7150_SLAVE_TSIF, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SM7150_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SM7150_SLAVE_USB3, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SM7150_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = { .name = "qhs_venus_cvp_throttle_cfg", - .id = SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_throttle_cfg = { .name = "qhs_venus_throttle_cfg", - .id = SM7150_SLAVE_VENUS_THROTTLE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SM7150_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_cnoc_a2noc = { .name = "qns_cnoc_a2noc", - .id = SM7150_SLAVE_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_MASTER_CNOC_A2NOC }, + .link_nodes = { &qnm_cnoc }, }; static struct qcom_icc_node srvc_cnoc = { .name = "srvc_cnoc", - .id = SM7150_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gemnoc = { .name = "qhs_gemnoc", - .id = SM7150_SLAVE_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM7150_MASTER_GEM_NOC_CFG }, + .link_nodes = { &qhm_gemnoc_cfg }, }; static struct qcom_icc_node qhs_llcc = { .name = "qhs_llcc", - .id = SM7150_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { .name = "qhs_mdsp_ms_mpu_cfg", - .id = SM7150_SLAVE_MSS_PROC_MS_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_gem_noc_snoc = { .name = "qns_gem_noc_snoc", - .id = SM7150_SLAVE_GEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_MASTER_GEM_NOC_SNOC }, + .link_nodes = { &qnm_gemnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SM7150_SLAVE_LLCC, .channels = 2, .buswidth = 16, .num_links = 1, - .links = { SM7150_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node srvc_gemnoc = { .name = "srvc_gemnoc", - .id = SM7150_SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SM7150_SLAVE_EBI_CH0, .channels = 2, .buswidth = 4, }; static struct qcom_icc_node qns2_mem_noc = { .name = "qns2_mem_noc", - .id = SM7150_SLAVE_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM7150_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SM7150_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM7150_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SM7150_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SM7150_SLAVE_APPSS, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qns_cnoc = { .name = "qns_cnoc", - .id = SM7150_SNOC_CNOC_SLV, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_SNOC_CNOC_MAS }, + .link_nodes = { &qnm_snoc }, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = SM7150_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM7150_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SM7150_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM7150_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SM7150_SLAVE_OCIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = SM7150_SLAVE_PIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SM7150_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SM7150_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SM7150_SLAVE_TCU, .channels = 1, .buswidth = 8, }; @@ -1730,7 +1715,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove_new = qcom_icc_rpmh_remove, + .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sm7150", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sm7150.h b/drivers/interconnect/qcom/sm7150.h deleted file mode 100644 index e00a9b0c1279..000000000000 --- a/drivers/interconnect/qcom/sm7150.h +++ /dev/null @@ -1,140 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Qualcomm #define SM7150 interconnect IDs - * - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com> - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM7150_H -#define __DRIVERS_INTERCONNECT_QCOM_SM7150_H - -#define SM7150_A1NOC_SNOC_MAS 0 -#define SM7150_A1NOC_SNOC_SLV 1 -#define SM7150_A2NOC_SNOC_MAS 2 -#define SM7150_A2NOC_SNOC_SLV 3 -#define SM7150_MASTER_A1NOC_CFG 4 -#define SM7150_MASTER_A2NOC_CFG 5 -#define SM7150_MASTER_AMPSS_M0 6 -#define SM7150_MASTER_CAMNOC_HF0 7 -#define SM7150_MASTER_CAMNOC_HF0_UNCOMP 8 -#define SM7150_MASTER_CAMNOC_NRT 9 -#define SM7150_MASTER_CAMNOC_NRT_UNCOMP 10 -#define SM7150_MASTER_CAMNOC_RT 11 -#define SM7150_MASTER_CAMNOC_RT_UNCOMP 12 -#define SM7150_MASTER_CAMNOC_SF 13 -#define SM7150_MASTER_CAMNOC_SF_UNCOMP 14 -#define SM7150_MASTER_CNOC_A2NOC 15 -#define SM7150_MASTER_CNOC_DC_NOC 16 -#define SM7150_MASTER_CNOC_MNOC_CFG 17 -#define SM7150_MASTER_COMPUTE_NOC 18 -#define SM7150_MASTER_CRYPTO_CORE_0 19 -#define SM7150_MASTER_EMMC 20 -#define SM7150_MASTER_GEM_NOC_CFG 21 -#define SM7150_MASTER_GEM_NOC_PCIE_SNOC 22 -#define SM7150_MASTER_GEM_NOC_SNOC 23 -#define SM7150_MASTER_GIC 24 -#define SM7150_MASTER_GRAPHICS_3D 25 -#define SM7150_MASTER_IPA 26 -#define SM7150_MASTER_LLCC 27 -#define SM7150_MASTER_MDP_PORT0 28 -#define SM7150_MASTER_MDP_PORT1 29 -#define SM7150_MASTER_MNOC_HF_MEM_NOC 30 -#define SM7150_MASTER_MNOC_SF_MEM_NOC 31 -#define SM7150_MASTER_NPU 32 -#define SM7150_MASTER_PCIE 33 -#define SM7150_MASTER_PIMEM 34 -#define SM7150_MASTER_QDSS_BAM 35 -#define SM7150_MASTER_QDSS_DAP 36 -#define SM7150_MASTER_QDSS_ETR 37 -#define SM7150_MASTER_QUP_0 38 -#define SM7150_MASTER_QUP_1 39 -#define SM7150_MASTER_ROTATOR 40 -#define SM7150_MASTER_SDCC_2 41 -#define SM7150_MASTER_SDCC_4 42 -#define SM7150_MASTER_SNOC_CFG 43 -#define SM7150_MASTER_SNOC_GC_MEM_NOC 44 -#define SM7150_MASTER_SNOC_SF_MEM_NOC 45 -#define SM7150_MASTER_SPDM 46 -#define SM7150_MASTER_SYS_TCU 47 -#define SM7150_MASTER_TSIF 48 -#define SM7150_MASTER_UFS_MEM 49 -#define SM7150_MASTER_USB3 50 -#define SM7150_MASTER_VIDEO_P0 51 -#define SM7150_MASTER_VIDEO_P1 52 -#define SM7150_MASTER_VIDEO_PROC 53 -#define SM7150_SLAVE_A1NOC_CFG 54 -#define SM7150_SLAVE_A2NOC_CFG 55 -#define SM7150_SLAVE_AHB2PHY_NORTH 56 -#define SM7150_SLAVE_AHB2PHY_SOUTH 57 -#define SM7150_SLAVE_AHB2PHY_WEST 58 -#define SM7150_SLAVE_ANOC_PCIE_GEM_NOC 59 -#define SM7150_SLAVE_AOP 60 -#define SM7150_SLAVE_AOSS 61 -#define SM7150_SLAVE_APPSS 62 -#define SM7150_SLAVE_CAMERA_CFG 63 -#define SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG 64 -#define SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG 65 -#define SM7150_SLAVE_CAMNOC_UNCOMP 66 -#define SM7150_SLAVE_CDSP_CFG 67 -#define SM7150_SLAVE_CDSP_GEM_NOC 68 -#define SM7150_SLAVE_CLK_CTL 69 -#define SM7150_SLAVE_CNOC_A2NOC 70 -#define SM7150_SLAVE_CNOC_DDRSS 71 -#define SM7150_SLAVE_CNOC_MNOC_CFG 72 -#define SM7150_SLAVE_CRYPTO_0_CFG 73 -#define SM7150_SLAVE_DISPLAY_CFG 74 -#define SM7150_SLAVE_DISPLAY_THROTTLE_CFG 75 -#define SM7150_SLAVE_EBI_CH0 76 -#define SM7150_SLAVE_EMMC_CFG 77 -#define SM7150_SLAVE_GEM_NOC_CFG 78 -#define SM7150_SLAVE_GEM_NOC_SNOC 79 -#define SM7150_SLAVE_GLM 80 -#define SM7150_SLAVE_GRAPHICS_3D_CFG 81 -#define SM7150_SLAVE_IMEM_CFG 82 -#define SM7150_SLAVE_IPA_CFG 83 -#define SM7150_SLAVE_LLCC 84 -#define SM7150_SLAVE_LLCC_CFG 85 -#define SM7150_SLAVE_MNOC_HF_MEM_NOC 86 -#define SM7150_SLAVE_MNOC_SF_MEM_NOC 87 -#define SM7150_SLAVE_MSS_PROC_MS_MPU_CFG 88 -#define SM7150_SLAVE_OCIMEM 89 -#define SM7150_SLAVE_PCIE_CFG 90 -#define SM7150_SLAVE_PDM 91 -#define SM7150_SLAVE_PIMEM 92 -#define SM7150_SLAVE_PIMEM_CFG 93 -#define SM7150_SLAVE_PRNG 94 -#define SM7150_SLAVE_QDSS_CFG 95 -#define SM7150_SLAVE_QDSS_STM 96 -#define SM7150_SLAVE_QUP_0 97 -#define SM7150_SLAVE_QUP_1 98 -#define SM7150_SLAVE_RBCPR_CX_CFG 99 -#define SM7150_SLAVE_RBCPR_MX_CFG 100 -#define SM7150_SLAVE_SDCC_2 101 -#define SM7150_SLAVE_SDCC_4 102 -#define SM7150_SLAVE_SERVICE_A1NOC 103 -#define SM7150_SLAVE_SERVICE_A2NOC 104 -#define SM7150_SLAVE_SERVICE_CNOC 105 -#define SM7150_SLAVE_SERVICE_GEM_NOC 106 -#define SM7150_SLAVE_SERVICE_MNOC 107 -#define SM7150_SLAVE_SERVICE_SNOC 108 -#define SM7150_SLAVE_SNOC_CFG 109 -#define SM7150_SLAVE_SNOC_GEM_NOC_GC 110 -#define SM7150_SLAVE_SNOC_GEM_NOC_SF 111 -#define SM7150_SLAVE_SPDM_WRAPPER 112 -#define SM7150_SLAVE_TCSR 113 -#define SM7150_SLAVE_TCU 114 -#define SM7150_SLAVE_TLMM_NORTH 115 -#define SM7150_SLAVE_TLMM_SOUTH 116 -#define SM7150_SLAVE_TLMM_WEST 117 -#define SM7150_SLAVE_TSIF 118 -#define SM7150_SLAVE_UFS_MEM_CFG 119 -#define SM7150_SLAVE_USB3 120 -#define SM7150_SLAVE_VENUS_CFG 121 -#define SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG 122 -#define SM7150_SLAVE_VENUS_THROTTLE_CFG 123 -#define SM7150_SLAVE_VSENSE_CTRL_CFG 124 -#define SM7150_SNOC_CNOC_MAS 125 -#define SM7150_SNOC_CNOC_SLV 126 - -#endif diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom/sm8150.c index f29b77556a79..ae732afbd155 100644 --- a/drivers/interconnect/qcom/sm8150.c +++ b/drivers/interconnect/qcom/sm8150.c @@ -14,1268 +14,1252 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sm8150.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node xm_emac; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node xm_usb3_1; +static struct qcom_icc_node qhm_a2noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qhm_sensorss_ahb; +static struct qcom_icc_node qhm_tsif; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node qxm_camnoc_hf0_uncomp; +static struct qcom_icc_node qxm_camnoc_hf1_uncomp; +static struct qcom_icc_node qxm_camnoc_sf_uncomp; +static struct qcom_icc_node qnm_npu; +static struct qcom_icc_node qhm_spdm; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc_dc_noc; +static struct qcom_icc_node acm_apps; +static struct qcom_icc_node acm_gpu_tcu; +static struct qcom_icc_node acm_sys_tcu; +static struct qcom_icc_node qhm_gemnoc_cfg; +static struct qcom_icc_node qnm_cmpnoc; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_ecc; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qxm_camnoc_hf0; +static struct qcom_icc_node qxm_camnoc_hf1; +static struct qcom_icc_node qxm_camnoc_sf; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_mdp1; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qxm_venus0; +static struct qcom_icc_node qxm_venus1; +static struct qcom_icc_node qxm_venus_arm9; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gemnoc; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_camnoc_uncomp; +static struct qcom_icc_node qns_cdsp_mem_noc; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_a2_noc_cfg; +static struct qcom_icc_node qhs_ahb2phy_south; +static struct qcom_icc_node qhs_aop; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_dsp; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_emac_cfg; +static struct qcom_icc_node qhs_glm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_npu_cfg; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_phy_refgen_north; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qupv3_east; +static struct qcom_icc_node qhs_qupv3_north; +static struct qcom_icc_node qhs_qupv3_south; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_spdm; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_ssc_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm_east; +static struct qcom_icc_node qhs_tlmm_north; +static struct qcom_icc_node qhs_tlmm_south; +static struct qcom_icc_node qhs_tlmm_west; +static struct qcom_icc_node qhs_tsif; +static struct qcom_icc_node qhs_ufs_card_cfg; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_usb3_1; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_cnoc_a2noc; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_memnoc; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qns_ecc; +static struct qcom_icc_node qns_gem_noc_snoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node srvc_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns2_mem_noc; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; static struct qcom_icc_node qhm_a1noc_cfg = { .name = "qhm_a1noc_cfg", - .id = SM8150_MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_SLAVE_SERVICE_A1NOC }, + .link_nodes = { &srvc_aggre1_noc }, }; static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", - .id = SM8150_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_emac = { .name = "xm_emac", - .id = SM8150_MASTER_EMAC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SM8150_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SM8150_MASTER_USB3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_1 = { .name = "xm_usb3_1", - .id = SM8150_MASTER_USB3_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_a2noc_cfg = { .name = "qhm_a2noc_cfg", - .id = SM8150_MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_SLAVE_SERVICE_A2NOC }, + .link_nodes = { &srvc_aggre2_noc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SM8150_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = SM8150_MASTER_QSPI, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = SM8150_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", - .id = SM8150_MASTER_QUP_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_sensorss_ahb = { .name = "qhm_sensorss_ahb", - .id = SM8150_MASTER_SENSORS_AHB, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_tsif = { .name = "qhm_tsif", - .id = SM8150_MASTER_TSIF, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_cnoc = { .name = "qnm_cnoc", - .id = SM8150_MASTER_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SM8150_MASTER_CRYPTO_CORE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SM8150_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", - .id = SM8150_MASTER_PCIE, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", - .id = SM8150_MASTER_PCIE_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = SM8150_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SM8150_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SM8150_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { .name = "qxm_camnoc_hf0_uncomp", - .id = SM8150_MASTER_CAMNOC_HF0_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { .name = "qxm_camnoc_hf1_uncomp", - .id = SM8150_MASTER_CAMNOC_HF1_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qxm_camnoc_sf_uncomp = { .name = "qxm_camnoc_sf_uncomp", - .id = SM8150_MASTER_CAMNOC_SF_UNCOMP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_CAMNOC_UNCOMP }, + .link_nodes = { &qns_camnoc_uncomp }, }; static struct qcom_icc_node qnm_npu = { .name = "qnm_npu", - .id = SM8150_MASTER_NPU, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_CDSP_MEM_NOC }, + .link_nodes = { &qns_cdsp_mem_noc }, }; static struct qcom_icc_node qhm_spdm = { .name = "qhm_spdm", - .id = SM8150_MASTER_SPDM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_SLAVE_CNOC_A2NOC }, + .link_nodes = { &qns_cnoc_a2noc }, }; static struct qcom_icc_node qnm_snoc = { .name = "qnm_snoc", - .id = SM8150_SNOC_CNOC_MAS, .channels = 1, .buswidth = 8, .num_links = 50, - .links = { SM8150_SLAVE_TLMM_SOUTH, - SM8150_SLAVE_CDSP_CFG, - SM8150_SLAVE_SPSS_CFG, - SM8150_SLAVE_CAMERA_CFG, - SM8150_SLAVE_SDCC_4, - SM8150_SLAVE_SDCC_2, - SM8150_SLAVE_CNOC_MNOC_CFG, - SM8150_SLAVE_EMAC_CFG, - SM8150_SLAVE_UFS_MEM_CFG, - SM8150_SLAVE_TLMM_EAST, - SM8150_SLAVE_SSC_CFG, - SM8150_SLAVE_SNOC_CFG, - SM8150_SLAVE_NORTH_PHY_CFG, - SM8150_SLAVE_QUP_0, - SM8150_SLAVE_GLM, - SM8150_SLAVE_PCIE_1_CFG, - SM8150_SLAVE_A2NOC_CFG, - SM8150_SLAVE_QDSS_CFG, - SM8150_SLAVE_DISPLAY_CFG, - SM8150_SLAVE_TCSR, - SM8150_SLAVE_CNOC_DDRSS, - SM8150_SLAVE_RBCPR_MMCX_CFG, - SM8150_SLAVE_NPU_CFG, - SM8150_SLAVE_PCIE_0_CFG, - SM8150_SLAVE_GRAPHICS_3D_CFG, - SM8150_SLAVE_VENUS_CFG, - SM8150_SLAVE_TSIF, - SM8150_SLAVE_IPA_CFG, - SM8150_SLAVE_CLK_CTL, - SM8150_SLAVE_AOP, - SM8150_SLAVE_QUP_1, - SM8150_SLAVE_AHB2PHY_SOUTH, - SM8150_SLAVE_USB3_1, - SM8150_SLAVE_SERVICE_CNOC, - SM8150_SLAVE_UFS_CARD_CFG, - SM8150_SLAVE_QUP_2, - SM8150_SLAVE_RBCPR_CX_CFG, - SM8150_SLAVE_TLMM_WEST, - SM8150_SLAVE_A1NOC_CFG, - SM8150_SLAVE_AOSS, - SM8150_SLAVE_PRNG, - SM8150_SLAVE_VSENSE_CTRL_CFG, - SM8150_SLAVE_QSPI, - SM8150_SLAVE_USB3, - SM8150_SLAVE_SPDM_WRAPPER, - SM8150_SLAVE_CRYPTO_0_CFG, - SM8150_SLAVE_PIMEM_CFG, - SM8150_SLAVE_TLMM_NORTH, - SM8150_SLAVE_RBCPR_MX_CFG, - SM8150_SLAVE_IMEM_CFG - }, + .link_nodes = { &qhs_tlmm_south, + &qhs_compute_dsp, + &qhs_spss_cfg, + &qhs_camera_cfg, + &qhs_sdc4, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_emac_cfg, + &qhs_ufs_mem_cfg, + &qhs_tlmm_east, + &qhs_ssc_cfg, + &qhs_snoc_cfg, + &qhs_phy_refgen_north, + &qhs_qupv3_south, + &qhs_glm, + &qhs_pcie1_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_display_cfg, + &qhs_tcsr, + &qhs_ddrss_cfg, + &qhs_cpr_mmcx, + &qhs_npu_cfg, + &qhs_pcie0_cfg, + &qhs_gpuss_cfg, + &qhs_venus_cfg, + &qhs_tsif, + &qhs_ipa, + &qhs_clk_ctl, + &qhs_aop, + &qhs_qupv3_north, + &qhs_ahb2phy_south, + &qhs_usb3_1, + &srvc_cnoc, + &qhs_ufs_card_cfg, + &qhs_qupv3_east, + &qhs_cpr_cx, + &qhs_tlmm_west, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_vsense_ctrl_cfg, + &qhs_qspi, + &qhs_usb3_0, + &qhs_spdm, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_tlmm_north, + &qhs_cpr_mx, + &qhs_imem_cfg }, }; static struct qcom_icc_node xm_qdss_dap = { .name = "xm_qdss_dap", - .id = SM8150_MASTER_QDSS_DAP, .channels = 1, .buswidth = 8, .num_links = 51, - .links = { SM8150_SLAVE_TLMM_SOUTH, - SM8150_SLAVE_CDSP_CFG, - SM8150_SLAVE_SPSS_CFG, - SM8150_SLAVE_CAMERA_CFG, - SM8150_SLAVE_SDCC_4, - SM8150_SLAVE_SDCC_2, - SM8150_SLAVE_CNOC_MNOC_CFG, - SM8150_SLAVE_EMAC_CFG, - SM8150_SLAVE_UFS_MEM_CFG, - SM8150_SLAVE_TLMM_EAST, - SM8150_SLAVE_SSC_CFG, - SM8150_SLAVE_SNOC_CFG, - SM8150_SLAVE_NORTH_PHY_CFG, - SM8150_SLAVE_QUP_0, - SM8150_SLAVE_GLM, - SM8150_SLAVE_PCIE_1_CFG, - SM8150_SLAVE_A2NOC_CFG, - SM8150_SLAVE_QDSS_CFG, - SM8150_SLAVE_DISPLAY_CFG, - SM8150_SLAVE_TCSR, - SM8150_SLAVE_CNOC_DDRSS, - SM8150_SLAVE_CNOC_A2NOC, - SM8150_SLAVE_RBCPR_MMCX_CFG, - SM8150_SLAVE_NPU_CFG, - SM8150_SLAVE_PCIE_0_CFG, - SM8150_SLAVE_GRAPHICS_3D_CFG, - SM8150_SLAVE_VENUS_CFG, - SM8150_SLAVE_TSIF, - SM8150_SLAVE_IPA_CFG, - SM8150_SLAVE_CLK_CTL, - SM8150_SLAVE_AOP, - SM8150_SLAVE_QUP_1, - SM8150_SLAVE_AHB2PHY_SOUTH, - SM8150_SLAVE_USB3_1, - SM8150_SLAVE_SERVICE_CNOC, - SM8150_SLAVE_UFS_CARD_CFG, - SM8150_SLAVE_QUP_2, - SM8150_SLAVE_RBCPR_CX_CFG, - SM8150_SLAVE_TLMM_WEST, - SM8150_SLAVE_A1NOC_CFG, - SM8150_SLAVE_AOSS, - SM8150_SLAVE_PRNG, - SM8150_SLAVE_VSENSE_CTRL_CFG, - SM8150_SLAVE_QSPI, - SM8150_SLAVE_USB3, - SM8150_SLAVE_SPDM_WRAPPER, - SM8150_SLAVE_CRYPTO_0_CFG, - SM8150_SLAVE_PIMEM_CFG, - SM8150_SLAVE_TLMM_NORTH, - SM8150_SLAVE_RBCPR_MX_CFG, - SM8150_SLAVE_IMEM_CFG - }, + .link_nodes = { &qhs_tlmm_south, + &qhs_compute_dsp, + &qhs_spss_cfg, + &qhs_camera_cfg, + &qhs_sdc4, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_emac_cfg, + &qhs_ufs_mem_cfg, + &qhs_tlmm_east, + &qhs_ssc_cfg, + &qhs_snoc_cfg, + &qhs_phy_refgen_north, + &qhs_qupv3_south, + &qhs_glm, + &qhs_pcie1_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_display_cfg, + &qhs_tcsr, + &qhs_ddrss_cfg, + &qns_cnoc_a2noc, + &qhs_cpr_mmcx, + &qhs_npu_cfg, + &qhs_pcie0_cfg, + &qhs_gpuss_cfg, + &qhs_venus_cfg, + &qhs_tsif, + &qhs_ipa, + &qhs_clk_ctl, + &qhs_aop, + &qhs_qupv3_north, + &qhs_ahb2phy_south, + &qhs_usb3_1, + &srvc_cnoc, + &qhs_ufs_card_cfg, + &qhs_qupv3_east, + &qhs_cpr_cx, + &qhs_tlmm_west, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_vsense_ctrl_cfg, + &qhs_qspi, + &qhs_usb3_0, + &qhs_spdm, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_tlmm_north, + &qhs_cpr_mx, + &qhs_imem_cfg }, }; static struct qcom_icc_node qhm_cnoc_dc_noc = { .name = "qhm_cnoc_dc_noc", - .id = SM8150_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SM8150_SLAVE_GEM_NOC_CFG, - SM8150_SLAVE_LLCC_CFG - }, + .link_nodes = { &qhs_memnoc, + &qhs_llcc }, }; static struct qcom_icc_node acm_apps = { .name = "acm_apps", - .id = SM8150_MASTER_AMPSS_M0, .channels = 2, .buswidth = 32, .num_links = 3, - .links = { SM8150_SLAVE_ECC, - SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_ecc, + &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node acm_gpu_tcu = { .name = "acm_gpu_tcu", - .id = SM8150_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node acm_sys_tcu = { .name = "acm_sys_tcu", - .id = SM8150_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qhm_gemnoc_cfg = { .name = "qhm_gemnoc_cfg", - .id = SM8150_MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SM8150_SLAVE_SERVICE_GEM_NOC, - SM8150_SLAVE_MSS_PROC_MS_MPU_CFG - }, + .link_nodes = { &srvc_gemnoc, + &qhs_mdsp_ms_mpu_cfg }, }; static struct qcom_icc_node qnm_cmpnoc = { .name = "qnm_cmpnoc", - .id = SM8150_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, .num_links = 3, - .links = { SM8150_SLAVE_ECC, - SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_ecc, + &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", - .id = SM8150_MASTER_GRAPHICS_3D, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SM8150_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SM8150_MASTER_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 2, - .links = { SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = SM8150_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SM8150_SLAVE_LLCC, - SM8150_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SM8150_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SM8150_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8150_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qxm_ecc = { .name = "qxm_ecc", - .id = SM8150_MASTER_ECC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SM8150_MASTER_LLCC, .channels = 4, .buswidth = 4, .num_links = 1, - .links = { SM8150_SLAVE_EBI_CH0 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qhm_mnoc_cfg = { .name = "qhm_mnoc_cfg", - .id = SM8150_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qxm_camnoc_hf0 = { .name = "qxm_camnoc_hf0", - .id = SM8150_MASTER_CAMNOC_HF0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_hf1 = { .name = "qxm_camnoc_hf1", - .id = SM8150_MASTER_CAMNOC_HF1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_camnoc_sf = { .name = "qxm_camnoc_sf", - .id = SM8150_MASTER_CAMNOC_SF, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_mdp0 = { .name = "qxm_mdp0", - .id = SM8150_MASTER_MDP_PORT0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_mdp1 = { .name = "qxm_mdp1", - .id = SM8150_MASTER_MDP_PORT1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_rot = { .name = "qxm_rot", - .id = SM8150_MASTER_ROTATOR, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus0 = { .name = "qxm_venus0", - .id = SM8150_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus1 = { .name = "qxm_venus1", - .id = SM8150_MASTER_VIDEO_P1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qxm_venus_arm9 = { .name = "qxm_venus_arm9", - .id = SM8150_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns2_mem_noc }, }; static struct qcom_icc_node qhm_snoc_cfg = { .name = "qhm_snoc_cfg", - .id = SM8150_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SM8150_A1NOC_SNOC_MAS, .channels = 1, .buswidth = 16, .num_links = 6, - .links = { SM8150_SLAVE_SNOC_GEM_NOC_SF, - SM8150_SLAVE_PIMEM, - SM8150_SLAVE_OCIMEM, - SM8150_SLAVE_APPSS, - SM8150_SNOC_CNOC_SLV, - SM8150_SLAVE_QDSS_STM - }, + .link_nodes = { &qns_gemnoc_sf, + &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SM8150_A2NOC_SNOC_MAS, .channels = 1, .buswidth = 16, .num_links = 9, - .links = { SM8150_SLAVE_SNOC_GEM_NOC_SF, - SM8150_SLAVE_PIMEM, - SM8150_SLAVE_OCIMEM, - SM8150_SLAVE_APPSS, - SM8150_SNOC_CNOC_SLV, - SM8150_SLAVE_PCIE_0, - SM8150_SLAVE_PCIE_1, - SM8150_SLAVE_TCU, - SM8150_SLAVE_QDSS_STM - }, + .link_nodes = { &qns_gemnoc_sf, + &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_pcie_0, + &xs_pcie_1, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_gemnoc = { .name = "qnm_gemnoc", - .id = SM8150_MASTER_GEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 6, - .links = { SM8150_SLAVE_PIMEM, - SM8150_SLAVE_OCIMEM, - SM8150_SLAVE_APPSS, - SM8150_SNOC_CNOC_SLV, - SM8150_SLAVE_TCU, - SM8150_SLAVE_QDSS_STM - }, + .link_nodes = { &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = SM8150_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8150_SLAVE_SNOC_GEM_NOC_GC, - SM8150_SLAVE_OCIMEM - }, + .link_nodes = { &qns_gemnoc_gc, + &qxs_imem }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SM8150_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8150_SLAVE_SNOC_GEM_NOC_GC, - SM8150_SLAVE_OCIMEM - }, + .link_nodes = { &qns_gemnoc_gc, + &qxs_imem }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SM8150_A1NOC_SNOC_SLV, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8150_A1NOC_SNOC_MAS }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node srvc_aggre1_noc = { .name = "srvc_aggre1_noc", - .id = SM8150_SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SM8150_A2NOC_SNOC_SLV, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8150_A2NOC_SNOC_MAS }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qns_pcie_mem_noc = { .name = "qns_pcie_mem_noc", - .id = SM8150_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8150_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node srvc_aggre2_noc = { .name = "srvc_aggre2_noc", - .id = SM8150_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_camnoc_uncomp = { .name = "qns_camnoc_uncomp", - .id = SM8150_SLAVE_CAMNOC_UNCOMP, .channels = 1, .buswidth = 32, }; static struct qcom_icc_node qns_cdsp_mem_noc = { .name = "qns_cdsp_mem_noc", - .id = SM8150_SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8150_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_cmpnoc }, }; static struct qcom_icc_node qhs_a1_noc_cfg = { .name = "qhs_a1_noc_cfg", - .id = SM8150_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_MASTER_A1NOC_CFG }, + .link_nodes = { &qhm_a1noc_cfg }, }; static struct qcom_icc_node qhs_a2_noc_cfg = { .name = "qhs_a2_noc_cfg", - .id = SM8150_SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_MASTER_A2NOC_CFG }, + .link_nodes = { &qhm_a2noc_cfg }, }; static struct qcom_icc_node qhs_ahb2phy_south = { .name = "qhs_ahb2phy_south", - .id = SM8150_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aop = { .name = "qhs_aop", - .id = SM8150_SLAVE_AOP, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SM8150_SLAVE_AOSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SM8150_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SM8150_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_compute_dsp = { .name = "qhs_compute_dsp", - .id = SM8150_SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SM8150_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_mmcx = { .name = "qhs_cpr_mmcx", - .id = SM8150_SLAVE_RBCPR_MMCX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_mx = { .name = "qhs_cpr_mx", - .id = SM8150_SLAVE_RBCPR_MX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SM8150_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ddrss_cfg = { .name = "qhs_ddrss_cfg", - .id = SM8150_SLAVE_CNOC_DDRSS, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_MASTER_CNOC_DC_NOC }, + .link_nodes = { &qhm_cnoc_dc_noc }, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SM8150_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_emac_cfg = { .name = "qhs_emac_cfg", - .id = SM8150_SLAVE_EMAC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_glm = { .name = "qhs_glm", - .id = SM8150_SLAVE_GLM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SM8150_SLAVE_GRAPHICS_3D_CFG, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SM8150_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SM8150_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mnoc_cfg = { .name = "qhs_mnoc_cfg", - .id = SM8150_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qhm_mnoc_cfg }, }; static struct qcom_icc_node qhs_npu_cfg = { .name = "qhs_npu_cfg", - .id = SM8150_SLAVE_NPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = SM8150_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie1_cfg = { .name = "qhs_pcie1_cfg", - .id = SM8150_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_phy_refgen_north = { .name = "qhs_phy_refgen_north", - .id = SM8150_SLAVE_NORTH_PHY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SM8150_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SM8150_SLAVE_PRNG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SM8150_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = SM8150_SLAVE_QSPI, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qupv3_east = { .name = "qhs_qupv3_east", - .id = SM8150_SLAVE_QUP_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qupv3_north = { .name = "qhs_qupv3_north", - .id = SM8150_SLAVE_QUP_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qupv3_south = { .name = "qhs_qupv3_south", - .id = SM8150_SLAVE_QUP_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SM8150_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SM8150_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_snoc_cfg = { .name = "qhs_snoc_cfg", - .id = SM8150_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_MASTER_SNOC_CFG }, + .link_nodes = { &qhm_snoc_cfg }, }; static struct qcom_icc_node qhs_spdm = { .name = "qhs_spdm", - .id = SM8150_SLAVE_SPDM_WRAPPER, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_spss_cfg = { .name = "qhs_spss_cfg", - .id = SM8150_SLAVE_SPSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ssc_cfg = { .name = "qhs_ssc_cfg", - .id = SM8150_SLAVE_SSC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SM8150_SLAVE_TCSR, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_east = { .name = "qhs_tlmm_east", - .id = SM8150_SLAVE_TLMM_EAST, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_north = { .name = "qhs_tlmm_north", - .id = SM8150_SLAVE_TLMM_NORTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_south = { .name = "qhs_tlmm_south", - .id = SM8150_SLAVE_TLMM_SOUTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm_west = { .name = "qhs_tlmm_west", - .id = SM8150_SLAVE_TLMM_WEST, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tsif = { .name = "qhs_tsif", - .id = SM8150_SLAVE_TSIF, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_card_cfg = { .name = "qhs_ufs_card_cfg", - .id = SM8150_SLAVE_UFS_CARD_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SM8150_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SM8150_SLAVE_USB3, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_1 = { .name = "qhs_usb3_1", - .id = SM8150_SLAVE_USB3_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SM8150_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SM8150_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_cnoc_a2noc = { .name = "qns_cnoc_a2noc", - .id = SM8150_SLAVE_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_MASTER_CNOC_A2NOC }, + .link_nodes = { &qnm_cnoc }, }; static struct qcom_icc_node srvc_cnoc = { .name = "srvc_cnoc", - .id = SM8150_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_llcc = { .name = "qhs_llcc", - .id = SM8150_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_memnoc = { .name = "qhs_memnoc", - .id = SM8150_SLAVE_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8150_MASTER_GEM_NOC_CFG }, + .link_nodes = { &qhm_gemnoc_cfg }, }; static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { .name = "qhs_mdsp_ms_mpu_cfg", - .id = SM8150_SLAVE_MSS_PROC_MS_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_ecc = { .name = "qns_ecc", - .id = SM8150_SLAVE_ECC, .channels = 1, .buswidth = 32, }; static struct qcom_icc_node qns_gem_noc_snoc = { .name = "qns_gem_noc_snoc", - .id = SM8150_SLAVE_GEM_NOC_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_MASTER_GEM_NOC_SNOC }, + .link_nodes = { &qnm_gemnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SM8150_SLAVE_LLCC, .channels = 4, .buswidth = 16, .num_links = 1, - .links = { SM8150_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node srvc_gemnoc = { .name = "srvc_gemnoc", - .id = SM8150_SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SM8150_SLAVE_EBI_CH0, .channels = 4, .buswidth = 4, }; static struct qcom_icc_node qns2_mem_noc = { .name = "qns2_mem_noc", - .id = SM8150_SLAVE_MNOC_SF_MEM_NOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8150_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SM8150_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8150_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SM8150_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SM8150_SLAVE_APPSS, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qns_cnoc = { .name = "qns_cnoc", - .id = SM8150_SNOC_CNOC_SLV, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_SNOC_CNOC_MAS }, + .link_nodes = { &qnm_snoc }, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = SM8150_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8150_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SM8150_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8150_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SM8150_SLAVE_OCIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = SM8150_SLAVE_PIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SM8150_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_pcie_0 = { .name = "xs_pcie_0", - .id = SM8150_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_pcie_1 = { .name = "xs_pcie_1", - .id = SM8150_SLAVE_PCIE_1, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SM8150_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SM8150_SLAVE_TCU, .channels = 1, .buswidth = 8, }; @@ -1864,7 +1848,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove_new = qcom_icc_rpmh_remove, + .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sm8150", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sm8150.h b/drivers/interconnect/qcom/sm8150.h deleted file mode 100644 index 1d587c94eb06..000000000000 --- a/drivers/interconnect/qcom/sm8150.h +++ /dev/null @@ -1,152 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm #define SM8250 interconnect IDs - * - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8150_H -#define __DRIVERS_INTERCONNECT_QCOM_SM8150_H - -#define SM8150_A1NOC_SNOC_MAS 0 -#define SM8150_A1NOC_SNOC_SLV 1 -#define SM8150_A2NOC_SNOC_MAS 2 -#define SM8150_A2NOC_SNOC_SLV 3 -#define SM8150_MASTER_A1NOC_CFG 4 -#define SM8150_MASTER_A2NOC_CFG 5 -#define SM8150_MASTER_AMPSS_M0 6 -#define SM8150_MASTER_CAMNOC_HF0 7 -#define SM8150_MASTER_CAMNOC_HF0_UNCOMP 8 -#define SM8150_MASTER_CAMNOC_HF1 9 -#define SM8150_MASTER_CAMNOC_HF1_UNCOMP 10 -#define SM8150_MASTER_CAMNOC_SF 11 -#define SM8150_MASTER_CAMNOC_SF_UNCOMP 12 -#define SM8150_MASTER_CNOC_A2NOC 13 -#define SM8150_MASTER_CNOC_DC_NOC 14 -#define SM8150_MASTER_CNOC_MNOC_CFG 15 -#define SM8150_MASTER_COMPUTE_NOC 16 -#define SM8150_MASTER_CRYPTO_CORE_0 17 -#define SM8150_MASTER_ECC 18 -#define SM8150_MASTER_EMAC 19 -#define SM8150_MASTER_GEM_NOC_CFG 20 -#define SM8150_MASTER_GEM_NOC_PCIE_SNOC 21 -#define SM8150_MASTER_GEM_NOC_SNOC 22 -#define SM8150_MASTER_GIC 23 -#define SM8150_MASTER_GPU_TCU 24 -#define SM8150_MASTER_GRAPHICS_3D 25 -#define SM8150_MASTER_IPA 26 -/* 27 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SM8150_MASTER_LLCC 28 -#define SM8150_MASTER_MDP_PORT0 29 -#define SM8150_MASTER_MDP_PORT1 30 -#define SM8150_MASTER_MNOC_HF_MEM_NOC 31 -#define SM8150_MASTER_MNOC_SF_MEM_NOC 32 -#define SM8150_MASTER_NPU 33 -#define SM8150_MASTER_PCIE 34 -#define SM8150_MASTER_PCIE_1 35 -#define SM8150_MASTER_PIMEM 36 -#define SM8150_MASTER_QDSS_BAM 37 -#define SM8150_MASTER_QDSS_DAP 38 -#define SM8150_MASTER_QDSS_ETR 39 -#define SM8150_MASTER_QSPI 40 -#define SM8150_MASTER_QUP_0 41 -#define SM8150_MASTER_QUP_1 42 -#define SM8150_MASTER_QUP_2 43 -#define SM8150_MASTER_ROTATOR 44 -#define SM8150_MASTER_SDCC_2 45 -#define SM8150_MASTER_SDCC_4 46 -#define SM8150_MASTER_SENSORS_AHB 47 -#define SM8150_MASTER_SNOC_CFG 48 -#define SM8150_MASTER_SNOC_GC_MEM_NOC 49 -#define SM8150_MASTER_SNOC_SF_MEM_NOC 50 -#define SM8150_MASTER_SPDM 51 -#define SM8150_MASTER_SYS_TCU 52 -#define SM8150_MASTER_TSIF 53 -#define SM8150_MASTER_UFS_MEM 54 -#define SM8150_MASTER_USB3 55 -#define SM8150_MASTER_USB3_1 56 -#define SM8150_MASTER_VIDEO_P0 57 -#define SM8150_MASTER_VIDEO_P1 58 -#define SM8150_MASTER_VIDEO_PROC 59 -#define SM8150_SLAVE_A1NOC_CFG 60 -#define SM8150_SLAVE_A2NOC_CFG 61 -#define SM8150_SLAVE_AHB2PHY_SOUTH 62 -#define SM8150_SLAVE_ANOC_PCIE_GEM_NOC 63 -#define SM8150_SLAVE_AOP 64 -#define SM8150_SLAVE_AOSS 65 -#define SM8150_SLAVE_APPSS 66 -#define SM8150_SLAVE_CAMERA_CFG 67 -#define SM8150_SLAVE_CAMNOC_UNCOMP 68 -#define SM8150_SLAVE_CDSP_CFG 69 -#define SM8150_SLAVE_CDSP_MEM_NOC 70 -#define SM8150_SLAVE_CLK_CTL 71 -#define SM8150_SLAVE_CNOC_A2NOC 72 -#define SM8150_SLAVE_CNOC_DDRSS 73 -#define SM8150_SLAVE_CNOC_MNOC_CFG 74 -#define SM8150_SLAVE_CRYPTO_0_CFG 75 -#define SM8150_SLAVE_DISPLAY_CFG 76 -#define SM8150_SLAVE_EBI_CH0 77 -#define SM8150_SLAVE_ECC 78 -#define SM8150_SLAVE_EMAC_CFG 79 -#define SM8150_SLAVE_GEM_NOC_CFG 80 -#define SM8150_SLAVE_GEM_NOC_SNOC 81 -#define SM8150_SLAVE_GLM 82 -#define SM8150_SLAVE_GRAPHICS_3D_CFG 83 -#define SM8150_SLAVE_IMEM_CFG 84 -#define SM8150_SLAVE_IPA_CFG 85 -/* 86 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SM8150_SLAVE_LLCC 87 -#define SM8150_SLAVE_LLCC_CFG 88 -#define SM8150_SLAVE_MNOC_HF_MEM_NOC 89 -#define SM8150_SLAVE_MNOC_SF_MEM_NOC 90 -#define SM8150_SLAVE_MSS_PROC_MS_MPU_CFG 91 -#define SM8150_SLAVE_NORTH_PHY_CFG 92 -#define SM8150_SLAVE_NPU_CFG 93 -#define SM8150_SLAVE_OCIMEM 94 -#define SM8150_SLAVE_PCIE_0 95 -#define SM8150_SLAVE_PCIE_0_CFG 96 -#define SM8150_SLAVE_PCIE_1 97 -#define SM8150_SLAVE_PCIE_1_CFG 98 -#define SM8150_SLAVE_PIMEM 99 -#define SM8150_SLAVE_PIMEM_CFG 100 -#define SM8150_SLAVE_PRNG 101 -#define SM8150_SLAVE_QDSS_CFG 102 -#define SM8150_SLAVE_QDSS_STM 103 -#define SM8150_SLAVE_QSPI 104 -#define SM8150_SLAVE_QUP_0 105 -#define SM8150_SLAVE_QUP_1 106 -#define SM8150_SLAVE_QUP_2 107 -#define SM8150_SLAVE_RBCPR_CX_CFG 108 -#define SM8150_SLAVE_RBCPR_MMCX_CFG 109 -#define SM8150_SLAVE_RBCPR_MX_CFG 110 -#define SM8150_SLAVE_SDCC_2 111 -#define SM8150_SLAVE_SDCC_4 112 -#define SM8150_SLAVE_SERVICE_A1NOC 113 -#define SM8150_SLAVE_SERVICE_A2NOC 114 -#define SM8150_SLAVE_SERVICE_CNOC 115 -#define SM8150_SLAVE_SERVICE_GEM_NOC 116 -#define SM8150_SLAVE_SERVICE_MNOC 117 -#define SM8150_SLAVE_SERVICE_SNOC 118 -#define SM8150_SLAVE_SNOC_CFG 119 -#define SM8150_SLAVE_SNOC_GEM_NOC_GC 120 -#define SM8150_SLAVE_SNOC_GEM_NOC_SF 121 -#define SM8150_SLAVE_SPDM_WRAPPER 122 -#define SM8150_SLAVE_SPSS_CFG 123 -#define SM8150_SLAVE_SSC_CFG 124 -#define SM8150_SLAVE_TCSR 125 -#define SM8150_SLAVE_TCU 126 -#define SM8150_SLAVE_TLMM_EAST 127 -#define SM8150_SLAVE_TLMM_NORTH 128 -#define SM8150_SLAVE_TLMM_SOUTH 129 -#define SM8150_SLAVE_TLMM_WEST 130 -#define SM8150_SLAVE_TSIF 131 -#define SM8150_SLAVE_UFS_CARD_CFG 132 -#define SM8150_SLAVE_UFS_MEM_CFG 133 -#define SM8150_SLAVE_USB3 134 -#define SM8150_SLAVE_USB3_1 135 -#define SM8150_SLAVE_VENUS_CFG 136 -#define SM8150_SLAVE_VSENSE_CTRL_CFG 137 -#define SM8150_SNOC_CNOC_MAS 138 -#define SM8150_SNOC_CNOC_SLV 139 - -#endif diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom/sm8250.c index 1879fa15761f..2ed112eab155 100644 --- a/drivers/interconnect/qcom/sm8250.c +++ b/drivers/interconnect/qcom/sm8250.c @@ -14,1383 +14,1369 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sm8250.h" + +static struct qcom_icc_node qhm_a1noc_cfg; +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qhm_tsif; +static struct qcom_icc_node xm_pcie3_modem; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node xm_usb3_1; +static struct qcom_icc_node qhm_a2noc_cfg; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qnm_cnoc; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_ufs_card; +static struct qcom_icc_node qnm_npu; +static struct qcom_icc_node qnm_snoc; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qhm_cnoc_dc_noc; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qhm_gemnoc_cfg; +static struct qcom_icc_node qnm_cmpnoc; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qhm_mnoc_cfg; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_video0; +static struct qcom_icc_node qnm_video1; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_mdp1; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node amm_npu_sys; +static struct qcom_icc_node amm_npu_sys_cdp_w; +static struct qcom_icc_node qhm_cfg; +static struct qcom_icc_node qhm_snoc_cfg; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gemnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_pcie_modem_mem_noc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qns_cdsp_mem_noc; +static struct qcom_icc_node qhs_a1_noc_cfg; +static struct qcom_icc_node qhs_a2_noc_cfg; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_dsp; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_ddrss_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_lpass_cfg; +static struct qcom_icc_node qhs_mnoc_cfg; +static struct qcom_icc_node qhs_npu_cfg; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pcie_modem_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_snoc_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm0; +static struct qcom_icc_node qhs_tlmm1; +static struct qcom_icc_node qhs_tlmm2; +static struct qcom_icc_node qhs_tsif; +static struct qcom_icc_node qhs_ufs_card_cfg; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_usb3_1; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_cnoc_a2noc; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qhs_memnoc; +static struct qcom_icc_node qns_gem_noc_snoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_sys_pcie; +static struct qcom_icc_node srvc_even_gemnoc; +static struct qcom_icc_node srvc_odd_gemnoc; +static struct qcom_icc_node srvc_sys_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qhs_cal_dp0; +static struct qcom_icc_node qhs_cal_dp1; +static struct qcom_icc_node qhs_cp; +static struct qcom_icc_node qhs_dma_bwmon; +static struct qcom_icc_node qhs_dpm; +static struct qcom_icc_node qhs_isense; +static struct qcom_icc_node qhs_llm; +static struct qcom_icc_node qhs_tcm; +static struct qcom_icc_node qns_npu_sys; +static struct qcom_icc_node srvc_noc; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qns_cnoc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_pcie_modem; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup2_core_master; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup2_core_slave; static struct qcom_icc_node qhm_a1noc_cfg = { .name = "qhm_a1noc_cfg", - .id = SM8250_MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_SLAVE_SERVICE_A1NOC }, + .link_nodes = { &srvc_aggre1_noc }, }; static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = SM8250_MASTER_QSPI_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = SM8250_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", - .id = SM8250_MASTER_QUP_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_tsif = { .name = "qhm_tsif", - .id = SM8250_MASTER_TSIF, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_pcie3_modem = { .name = "xm_pcie3_modem", - .id = SM8250_MASTER_PCIE_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1 }, + .link_nodes = { &qns_pcie_modem_mem_noc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SM8250_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SM8250_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SM8250_MASTER_USB3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_1 = { .name = "xm_usb3_1", - .id = SM8250_MASTER_USB3_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_A1NOC_SNOC_SLV }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_a2noc_cfg = { .name = "qhm_a2noc_cfg", - .id = SM8250_MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_SLAVE_SERVICE_A2NOC }, + .link_nodes = { &srvc_aggre2_noc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SM8250_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", - .id = SM8250_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_cnoc = { .name = "qnm_cnoc", - .id = SM8250_MASTER_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SM8250_MASTER_CRYPTO_CORE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SM8250_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", - .id = SM8250_MASTER_PCIE, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", - .id = SM8250_MASTER_PCIE_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = SM8250_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SM8250_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_ufs_card = { .name = "xm_ufs_card", - .id = SM8250_MASTER_UFS_CARD, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_A2NOC_SNOC_SLV }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_npu = { .name = "qnm_npu", - .id = SM8250_MASTER_NPU, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8250_SLAVE_CDSP_MEM_NOC }, + .link_nodes = { &qns_cdsp_mem_noc }, }; static struct qcom_icc_node qnm_snoc = { .name = "qnm_snoc", - .id = SM8250_SNOC_CNOC_MAS, .channels = 1, .buswidth = 8, .num_links = 49, - .links = { SM8250_SLAVE_CDSP_CFG, - SM8250_SLAVE_CAMERA_CFG, - SM8250_SLAVE_TLMM_SOUTH, - SM8250_SLAVE_TLMM_NORTH, - SM8250_SLAVE_SDCC_4, - SM8250_SLAVE_TLMM_WEST, - SM8250_SLAVE_SDCC_2, - SM8250_SLAVE_CNOC_MNOC_CFG, - SM8250_SLAVE_UFS_MEM_CFG, - SM8250_SLAVE_SNOC_CFG, - SM8250_SLAVE_PDM, - SM8250_SLAVE_CX_RDPM, - SM8250_SLAVE_PCIE_1_CFG, - SM8250_SLAVE_A2NOC_CFG, - SM8250_SLAVE_QDSS_CFG, - SM8250_SLAVE_DISPLAY_CFG, - SM8250_SLAVE_PCIE_2_CFG, - SM8250_SLAVE_TCSR, - SM8250_SLAVE_DCC_CFG, - SM8250_SLAVE_CNOC_DDRSS, - SM8250_SLAVE_IPC_ROUTER_CFG, - SM8250_SLAVE_PCIE_0_CFG, - SM8250_SLAVE_RBCPR_MMCX_CFG, - SM8250_SLAVE_NPU_CFG, - SM8250_SLAVE_AHB2PHY_SOUTH, - SM8250_SLAVE_AHB2PHY_NORTH, - SM8250_SLAVE_GRAPHICS_3D_CFG, - SM8250_SLAVE_VENUS_CFG, - SM8250_SLAVE_TSIF, - SM8250_SLAVE_IPA_CFG, - SM8250_SLAVE_IMEM_CFG, - SM8250_SLAVE_USB3, - SM8250_SLAVE_SERVICE_CNOC, - SM8250_SLAVE_UFS_CARD_CFG, - SM8250_SLAVE_USB3_1, - SM8250_SLAVE_LPASS, - SM8250_SLAVE_RBCPR_CX_CFG, - SM8250_SLAVE_A1NOC_CFG, - SM8250_SLAVE_AOSS, - SM8250_SLAVE_PRNG, - SM8250_SLAVE_VSENSE_CTRL_CFG, - SM8250_SLAVE_QSPI_0, - SM8250_SLAVE_CRYPTO_0_CFG, - SM8250_SLAVE_PIMEM_CFG, - SM8250_SLAVE_RBCPR_MX_CFG, - SM8250_SLAVE_QUP_0, - SM8250_SLAVE_QUP_1, - SM8250_SLAVE_QUP_2, - SM8250_SLAVE_CLK_CTL - }, + .link_nodes = { &qhs_compute_dsp, + &qhs_camera_cfg, + &qhs_tlmm1, + &qhs_tlmm0, + &qhs_sdc4, + &qhs_tlmm2, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_ufs_mem_cfg, + &qhs_snoc_cfg, + &qhs_pdm, + &qhs_cx_rdpm, + &qhs_pcie1_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_display_cfg, + &qhs_pcie_modem_cfg, + &qhs_tcsr, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_ipc_router, + &qhs_pcie0_cfg, + &qhs_cpr_mmcx, + &qhs_npu_cfg, + &qhs_ahb2phy0, + &qhs_ahb2phy1, + &qhs_gpuss_cfg, + &qhs_venus_cfg, + &qhs_tsif, + &qhs_ipa, + &qhs_imem_cfg, + &qhs_usb3_0, + &srvc_cnoc, + &qhs_ufs_card_cfg, + &qhs_usb3_1, + &qhs_lpass_cfg, + &qhs_cpr_cx, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_vsense_ctrl_cfg, + &qhs_qspi, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_cpr_mx, + &qhs_qup0, + &qhs_qup1, + &qhs_qup2, + &qhs_clk_ctl }, }; static struct qcom_icc_node xm_qdss_dap = { .name = "xm_qdss_dap", - .id = SM8250_MASTER_QDSS_DAP, .channels = 1, .buswidth = 8, .num_links = 50, - .links = { SM8250_SLAVE_CDSP_CFG, - SM8250_SLAVE_CAMERA_CFG, - SM8250_SLAVE_TLMM_SOUTH, - SM8250_SLAVE_TLMM_NORTH, - SM8250_SLAVE_SDCC_4, - SM8250_SLAVE_TLMM_WEST, - SM8250_SLAVE_SDCC_2, - SM8250_SLAVE_CNOC_MNOC_CFG, - SM8250_SLAVE_UFS_MEM_CFG, - SM8250_SLAVE_SNOC_CFG, - SM8250_SLAVE_PDM, - SM8250_SLAVE_CX_RDPM, - SM8250_SLAVE_PCIE_1_CFG, - SM8250_SLAVE_A2NOC_CFG, - SM8250_SLAVE_QDSS_CFG, - SM8250_SLAVE_DISPLAY_CFG, - SM8250_SLAVE_PCIE_2_CFG, - SM8250_SLAVE_TCSR, - SM8250_SLAVE_DCC_CFG, - SM8250_SLAVE_CNOC_DDRSS, - SM8250_SLAVE_IPC_ROUTER_CFG, - SM8250_SLAVE_CNOC_A2NOC, - SM8250_SLAVE_PCIE_0_CFG, - SM8250_SLAVE_RBCPR_MMCX_CFG, - SM8250_SLAVE_NPU_CFG, - SM8250_SLAVE_AHB2PHY_SOUTH, - SM8250_SLAVE_AHB2PHY_NORTH, - SM8250_SLAVE_GRAPHICS_3D_CFG, - SM8250_SLAVE_VENUS_CFG, - SM8250_SLAVE_TSIF, - SM8250_SLAVE_IPA_CFG, - SM8250_SLAVE_IMEM_CFG, - SM8250_SLAVE_USB3, - SM8250_SLAVE_SERVICE_CNOC, - SM8250_SLAVE_UFS_CARD_CFG, - SM8250_SLAVE_USB3_1, - SM8250_SLAVE_LPASS, - SM8250_SLAVE_RBCPR_CX_CFG, - SM8250_SLAVE_A1NOC_CFG, - SM8250_SLAVE_AOSS, - SM8250_SLAVE_PRNG, - SM8250_SLAVE_VSENSE_CTRL_CFG, - SM8250_SLAVE_QSPI_0, - SM8250_SLAVE_CRYPTO_0_CFG, - SM8250_SLAVE_PIMEM_CFG, - SM8250_SLAVE_RBCPR_MX_CFG, - SM8250_SLAVE_QUP_0, - SM8250_SLAVE_QUP_1, - SM8250_SLAVE_QUP_2, - SM8250_SLAVE_CLK_CTL - }, + .link_nodes = { &qhs_compute_dsp, + &qhs_camera_cfg, + &qhs_tlmm1, + &qhs_tlmm0, + &qhs_sdc4, + &qhs_tlmm2, + &qhs_sdc2, + &qhs_mnoc_cfg, + &qhs_ufs_mem_cfg, + &qhs_snoc_cfg, + &qhs_pdm, + &qhs_cx_rdpm, + &qhs_pcie1_cfg, + &qhs_a2_noc_cfg, + &qhs_qdss_cfg, + &qhs_display_cfg, + &qhs_pcie_modem_cfg, + &qhs_tcsr, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_ipc_router, + &qns_cnoc_a2noc, + &qhs_pcie0_cfg, + &qhs_cpr_mmcx, + &qhs_npu_cfg, + &qhs_ahb2phy0, + &qhs_ahb2phy1, + &qhs_gpuss_cfg, + &qhs_venus_cfg, + &qhs_tsif, + &qhs_ipa, + &qhs_imem_cfg, + &qhs_usb3_0, + &srvc_cnoc, + &qhs_ufs_card_cfg, + &qhs_usb3_1, + &qhs_lpass_cfg, + &qhs_cpr_cx, + &qhs_a1_noc_cfg, + &qhs_aoss, + &qhs_prng, + &qhs_vsense_ctrl_cfg, + &qhs_qspi, + &qhs_crypto0_cfg, + &qhs_pimem_cfg, + &qhs_cpr_mx, + &qhs_qup0, + &qhs_qup1, + &qhs_qup2, + &qhs_clk_ctl }, }; static struct qcom_icc_node qhm_cnoc_dc_noc = { .name = "qhm_cnoc_dc_noc", - .id = SM8250_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SM8250_SLAVE_GEM_NOC_CFG, - SM8250_SLAVE_LLCC_CFG - }, + .link_nodes = { &qhs_memnoc, + &qhs_llcc }, }; static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", - .id = SM8250_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8250_SLAVE_LLCC, - SM8250_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", - .id = SM8250_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8250_SLAVE_LLCC, - SM8250_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", - .id = SM8250_MASTER_AMPSS_M0, .channels = 2, .buswidth = 32, .num_links = 3, - .links = { SM8250_SLAVE_LLCC, - SM8250_SLAVE_GEM_NOC_SNOC, - SM8250_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc, + &qns_sys_pcie }, }; static struct qcom_icc_node qhm_gemnoc_cfg = { .name = "qhm_gemnoc_cfg", - .id = SM8250_MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 3, - .links = { SM8250_SLAVE_SERVICE_GEM_NOC_2, - SM8250_SLAVE_SERVICE_GEM_NOC_1, - SM8250_SLAVE_SERVICE_GEM_NOC - }, + .link_nodes = { &srvc_odd_gemnoc, + &srvc_even_gemnoc, + &srvc_sys_gemnoc }, }; static struct qcom_icc_node qnm_cmpnoc = { .name = "qnm_cmpnoc", - .id = SM8250_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8250_SLAVE_LLCC, - SM8250_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", - .id = SM8250_MASTER_GRAPHICS_3D, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8250_SLAVE_LLCC, - SM8250_SLAVE_GEM_NOC_SNOC }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SM8250_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8250_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SM8250_MASTER_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8250_SLAVE_LLCC, - SM8250_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = SM8250_MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SM8250_SLAVE_LLCC, - SM8250_SLAVE_GEM_NOC_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SM8250_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SM8250_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SM8250_SLAVE_LLCC, - SM8250_SLAVE_GEM_NOC_SNOC, - SM8250_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes = { &qns_llcc, + &qns_gem_noc_snoc, + &qns_sys_pcie }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SM8250_MASTER_LLCC, .channels = 4, .buswidth = 4, .num_links = 1, - .links = { SM8250_SLAVE_EBI_CH0 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qhm_mnoc_cfg = { .name = "qhm_mnoc_cfg", - .id = SM8250_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qnm_camnoc_hf = { .name = "qnm_camnoc_hf", - .id = SM8250_MASTER_CAMNOC_HF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8250_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_camnoc_icp = { .name = "qnm_camnoc_icp", - .id = SM8250_MASTER_CAMNOC_ICP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_camnoc_sf = { .name = "qnm_camnoc_sf", - .id = SM8250_MASTER_CAMNOC_SF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video0 = { .name = "qnm_video0", - .id = SM8250_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video1 = { .name = "qnm_video1", - .id = SM8250_MASTER_VIDEO_P1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_cvp = { .name = "qnm_video_cvp", - .id = SM8250_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qxm_mdp0 = { .name = "qxm_mdp0", - .id = SM8250_MASTER_MDP_PORT0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8250_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_mdp1 = { .name = "qxm_mdp1", - .id = SM8250_MASTER_MDP_PORT1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8250_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_rot = { .name = "qxm_rot", - .id = SM8250_MASTER_ROTATOR, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node amm_npu_sys = { .name = "amm_npu_sys", - .id = SM8250_MASTER_NPU_SYS, .channels = 4, .buswidth = 32, .num_links = 1, - .links = { SM8250_SLAVE_NPU_COMPUTE_NOC }, + .link_nodes = { &qns_npu_sys }, }; static struct qcom_icc_node amm_npu_sys_cdp_w = { .name = "amm_npu_sys_cdp_w", - .id = SM8250_MASTER_NPU_CDP, .channels = 2, .buswidth = 16, .num_links = 1, - .links = { SM8250_SLAVE_NPU_COMPUTE_NOC }, + .link_nodes = { &qns_npu_sys }, }; static struct qcom_icc_node qhm_cfg = { .name = "qhm_cfg", - .id = SM8250_MASTER_NPU_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 9, - .links = { SM8250_SLAVE_SERVICE_NPU_NOC, - SM8250_SLAVE_ISENSE_CFG, - SM8250_SLAVE_NPU_LLM_CFG, - SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, - SM8250_SLAVE_NPU_CP, - SM8250_SLAVE_NPU_TCM, - SM8250_SLAVE_NPU_CAL_DP0, - SM8250_SLAVE_NPU_CAL_DP1, - SM8250_SLAVE_NPU_DPM - }, + .link_nodes = { &srvc_noc, + &qhs_isense, + &qhs_llm, + &qhs_dma_bwmon, + &qhs_cp, + &qhs_tcm, + &qhs_cal_dp0, + &qhs_cal_dp1, + &qhs_dpm }, }; static struct qcom_icc_node qhm_snoc_cfg = { .name = "qhm_snoc_cfg", - .id = SM8250_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SM8250_A1NOC_SNOC_MAS, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8250_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SM8250_A2NOC_SNOC_MAS, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8250_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_gemnoc = { .name = "qnm_gemnoc", - .id = SM8250_MASTER_GEM_NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 6, - .links = { SM8250_SLAVE_PIMEM, - SM8250_SLAVE_OCIMEM, - SM8250_SLAVE_APPSS, - SM8250_SNOC_CNOC_SLV, - SM8250_SLAVE_TCU, - SM8250_SLAVE_QDSS_STM - }, + .link_nodes = { &qxs_pimem, + &qxs_imem, + &qhs_apss, + &qns_cnoc, + &xs_sys_tcu_cfg, + &xs_qdss_stm }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = SM8250_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 3, - .links = { SM8250_SLAVE_PCIE_2, - SM8250_SLAVE_PCIE_0, - SM8250_SLAVE_PCIE_1 - }, + .link_nodes = { &xs_pcie_modem, + &xs_pcie_0, + &xs_pcie_1 }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = SM8250_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SM8250_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SM8250_A1NOC_SNOC_SLV, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8250_A1NOC_SNOC_MAS }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node qns_pcie_modem_mem_noc = { .name = "qns_pcie_modem_mem_noc", - .id = SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8250_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node srvc_aggre1_noc = { .name = "srvc_aggre1_noc", - .id = SM8250_SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SM8250_A2NOC_SNOC_SLV, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8250_A2NOC_SNOC_MAS }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qns_pcie_mem_noc = { .name = "qns_pcie_mem_noc", - .id = SM8250_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8250_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node srvc_aggre2_noc = { .name = "srvc_aggre2_noc", - .id = SM8250_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_cdsp_mem_noc = { .name = "qns_cdsp_mem_noc", - .id = SM8250_SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8250_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_cmpnoc }, }; static struct qcom_icc_node qhs_a1_noc_cfg = { .name = "qhs_a1_noc_cfg", - .id = SM8250_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_MASTER_A1NOC_CFG }, + .link_nodes = { &qhm_a1noc_cfg }, }; static struct qcom_icc_node qhs_a2_noc_cfg = { .name = "qhs_a2_noc_cfg", - .id = SM8250_SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_MASTER_A2NOC_CFG }, + .link_nodes = { &qhm_a2noc_cfg }, }; static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", - .id = SM8250_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ahb2phy1 = { .name = "qhs_ahb2phy1", - .id = SM8250_SLAVE_AHB2PHY_NORTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SM8250_SLAVE_AOSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SM8250_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SM8250_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_compute_dsp = { .name = "qhs_compute_dsp", - .id = SM8250_SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SM8250_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_mmcx = { .name = "qhs_cpr_mmcx", - .id = SM8250_SLAVE_RBCPR_MMCX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_mx = { .name = "qhs_cpr_mx", - .id = SM8250_SLAVE_RBCPR_MX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SM8250_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cx_rdpm = { .name = "qhs_cx_rdpm", - .id = SM8250_SLAVE_CX_RDPM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dcc_cfg = { .name = "qhs_dcc_cfg", - .id = SM8250_SLAVE_DCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ddrss_cfg = { .name = "qhs_ddrss_cfg", - .id = SM8250_SLAVE_CNOC_DDRSS, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_MASTER_CNOC_DC_NOC }, + .link_nodes = { &qhm_cnoc_dc_noc }, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SM8250_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SM8250_SLAVE_GRAPHICS_3D_CFG, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SM8250_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SM8250_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", - .id = SM8250_SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_cfg = { .name = "qhs_lpass_cfg", - .id = SM8250_SLAVE_LPASS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mnoc_cfg = { .name = "qhs_mnoc_cfg", - .id = SM8250_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qhm_mnoc_cfg }, }; static struct qcom_icc_node qhs_npu_cfg = { .name = "qhs_npu_cfg", - .id = SM8250_SLAVE_NPU_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_MASTER_NPU_NOC_CFG }, + .link_nodes = { &qhm_cfg }, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = SM8250_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie1_cfg = { .name = "qhs_pcie1_cfg", - .id = SM8250_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie_modem_cfg = { .name = "qhs_pcie_modem_cfg", - .id = SM8250_SLAVE_PCIE_2_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SM8250_SLAVE_PDM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SM8250_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SM8250_SLAVE_PRNG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SM8250_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = SM8250_SLAVE_QSPI_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", - .id = SM8250_SLAVE_QUP_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = SM8250_SLAVE_QUP_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup2 = { .name = "qhs_qup2", - .id = SM8250_SLAVE_QUP_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SM8250_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SM8250_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_snoc_cfg = { .name = "qhs_snoc_cfg", - .id = SM8250_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_MASTER_SNOC_CFG }, + .link_nodes = { &qhm_snoc_cfg }, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SM8250_SLAVE_TCSR, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm0 = { .name = "qhs_tlmm0", - .id = SM8250_SLAVE_TLMM_NORTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm1 = { .name = "qhs_tlmm1", - .id = SM8250_SLAVE_TLMM_SOUTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm2 = { .name = "qhs_tlmm2", - .id = SM8250_SLAVE_TLMM_WEST, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tsif = { .name = "qhs_tsif", - .id = SM8250_SLAVE_TSIF, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_card_cfg = { .name = "qhs_ufs_card_cfg", - .id = SM8250_SLAVE_UFS_CARD_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SM8250_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SM8250_SLAVE_USB3, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_1 = { .name = "qhs_usb3_1", - .id = SM8250_SLAVE_USB3_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SM8250_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SM8250_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_cnoc_a2noc = { .name = "qns_cnoc_a2noc", - .id = SM8250_SLAVE_CNOC_A2NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_MASTER_CNOC_A2NOC }, + .link_nodes = { &qnm_cnoc }, }; static struct qcom_icc_node srvc_cnoc = { .name = "srvc_cnoc", - .id = SM8250_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_llcc = { .name = "qhs_llcc", - .id = SM8250_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_memnoc = { .name = "qhs_memnoc", - .id = SM8250_SLAVE_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_MASTER_GEM_NOC_CFG }, + .link_nodes = { &qhm_gemnoc_cfg }, }; static struct qcom_icc_node qns_gem_noc_snoc = { .name = "qns_gem_noc_snoc", - .id = SM8250_SLAVE_GEM_NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8250_MASTER_GEM_NOC_SNOC }, + .link_nodes = { &qnm_gemnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SM8250_SLAVE_LLCC, .channels = 4, .buswidth = 16, .num_links = 1, - .links = { SM8250_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_sys_pcie = { .name = "qns_sys_pcie", - .id = SM8250_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node srvc_even_gemnoc = { .name = "srvc_even_gemnoc", - .id = SM8250_SLAVE_SERVICE_GEM_NOC_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_odd_gemnoc = { .name = "srvc_odd_gemnoc", - .id = SM8250_SLAVE_SERVICE_GEM_NOC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_sys_gemnoc = { .name = "srvc_sys_gemnoc", - .id = SM8250_SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SM8250_SLAVE_EBI_CH0, .channels = 4, .buswidth = 4, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SM8250_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8250_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", - .id = SM8250_SLAVE_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8250_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SM8250_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cal_dp0 = { .name = "qhs_cal_dp0", - .id = SM8250_SLAVE_NPU_CAL_DP0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cal_dp1 = { .name = "qhs_cal_dp1", - .id = SM8250_SLAVE_NPU_CAL_DP1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cp = { .name = "qhs_cp", - .id = SM8250_SLAVE_NPU_CP, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dma_bwmon = { .name = "qhs_dma_bwmon", - .id = SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dpm = { .name = "qhs_dpm", - .id = SM8250_SLAVE_NPU_DPM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_isense = { .name = "qhs_isense", - .id = SM8250_SLAVE_ISENSE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_llm = { .name = "qhs_llm", - .id = SM8250_SLAVE_NPU_LLM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tcm = { .name = "qhs_tcm", - .id = SM8250_SLAVE_NPU_TCM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_npu_sys = { .name = "qns_npu_sys", - .id = SM8250_SLAVE_NPU_COMPUTE_NOC, .channels = 2, .buswidth = 32, }; static struct qcom_icc_node srvc_noc = { .name = "srvc_noc", - .id = SM8250_SLAVE_SERVICE_NPU_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SM8250_SLAVE_APPSS, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qns_cnoc = { .name = "qns_cnoc", - .id = SM8250_SNOC_CNOC_SLV, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_SNOC_CNOC_MAS }, + .link_nodes = { &qnm_snoc }, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = SM8250_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8250_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SM8250_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8250_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SM8250_SLAVE_OCIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = SM8250_SLAVE_PIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SM8250_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_pcie_0 = { .name = "xs_pcie_0", - .id = SM8250_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_pcie_1 = { .name = "xs_pcie_1", - .id = SM8250_SLAVE_PCIE_1, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_pcie_modem = { .name = "xs_pcie_modem", - .id = SM8250_SLAVE_PCIE_2, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SM8250_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SM8250_SLAVE_TCU, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", - .id = SM8250_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { .name = "qup1_core_master", - .id = SM8250_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_SLAVE_QUP_CORE_1 }, + .link_nodes = { &qup1_core_slave }, }; static struct qcom_icc_node qup2_core_master = { .name = "qup2_core_master", - .id = SM8250_MASTER_QUP_CORE_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8250_SLAVE_QUP_CORE_2 }, + .link_nodes = { &qup2_core_slave }, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", - .id = SM8250_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qup1_core_slave = { .name = "qup1_core_slave", - .id = SM8250_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qup2_core_slave = { .name = "qup2_core_slave", - .id = SM8250_SLAVE_QUP_CORE_2, .channels = 1, .buswidth = 4, }; @@ -1991,7 +1977,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove_new = qcom_icc_rpmh_remove, + .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sm8250", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sm8250.h b/drivers/interconnect/qcom/sm8250.h deleted file mode 100644 index 032665093c5b..000000000000 --- a/drivers/interconnect/qcom/sm8250.h +++ /dev/null @@ -1,168 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm #define SM8250 interconnect IDs - * - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8250_H -#define __DRIVERS_INTERCONNECT_QCOM_SM8250_H - -#define SM8250_A1NOC_SNOC_MAS 0 -#define SM8250_A1NOC_SNOC_SLV 1 -#define SM8250_A2NOC_SNOC_MAS 2 -#define SM8250_A2NOC_SNOC_SLV 3 -#define SM8250_MASTER_A1NOC_CFG 4 -#define SM8250_MASTER_A2NOC_CFG 5 -#define SM8250_MASTER_AMPSS_M0 6 -#define SM8250_MASTER_ANOC_PCIE_GEM_NOC 7 -#define SM8250_MASTER_CAMNOC_HF 8 -#define SM8250_MASTER_CAMNOC_ICP 9 -#define SM8250_MASTER_CAMNOC_SF 10 -#define SM8250_MASTER_CNOC_A2NOC 11 -#define SM8250_MASTER_CNOC_DC_NOC 12 -#define SM8250_MASTER_CNOC_MNOC_CFG 13 -#define SM8250_MASTER_COMPUTE_NOC 14 -#define SM8250_MASTER_CRYPTO_CORE_0 15 -#define SM8250_MASTER_GEM_NOC_CFG 16 -#define SM8250_MASTER_GEM_NOC_PCIE_SNOC 17 -#define SM8250_MASTER_GEM_NOC_SNOC 18 -#define SM8250_MASTER_GIC 19 -#define SM8250_MASTER_GPU_TCU 20 -#define SM8250_MASTER_GRAPHICS_3D 21 -#define SM8250_MASTER_IPA 22 -/* 23 was used by MASTER_IPA_CORE, now represented as RPMh clock */ -#define SM8250_MASTER_LLCC 24 -#define SM8250_MASTER_MDP_PORT0 25 -#define SM8250_MASTER_MDP_PORT1 26 -#define SM8250_MASTER_MNOC_HF_MEM_NOC 27 -#define SM8250_MASTER_MNOC_SF_MEM_NOC 28 -#define SM8250_MASTER_NPU 29 -#define SM8250_MASTER_NPU_CDP 30 -#define SM8250_MASTER_NPU_NOC_CFG 31 -#define SM8250_MASTER_NPU_SYS 32 -#define SM8250_MASTER_PCIE 33 -#define SM8250_MASTER_PCIE_1 34 -#define SM8250_MASTER_PCIE_2 35 -#define SM8250_MASTER_PIMEM 36 -#define SM8250_MASTER_QDSS_BAM 37 -#define SM8250_MASTER_QDSS_DAP 38 -#define SM8250_MASTER_QDSS_ETR 39 -#define SM8250_MASTER_QSPI_0 40 -#define SM8250_MASTER_QUP_0 41 -#define SM8250_MASTER_QUP_1 42 -#define SM8250_MASTER_QUP_2 43 -#define SM8250_MASTER_ROTATOR 44 -#define SM8250_MASTER_SDCC_2 45 -#define SM8250_MASTER_SDCC_4 46 -#define SM8250_MASTER_SNOC_CFG 47 -#define SM8250_MASTER_SNOC_GC_MEM_NOC 48 -#define SM8250_MASTER_SNOC_SF_MEM_NOC 49 -#define SM8250_MASTER_SYS_TCU 50 -#define SM8250_MASTER_TSIF 51 -#define SM8250_MASTER_UFS_CARD 52 -#define SM8250_MASTER_UFS_MEM 53 -#define SM8250_MASTER_USB3 54 -#define SM8250_MASTER_USB3_1 55 -#define SM8250_MASTER_VIDEO_P0 56 -#define SM8250_MASTER_VIDEO_P1 57 -#define SM8250_MASTER_VIDEO_PROC 58 -#define SM8250_SLAVE_A1NOC_CFG 59 -#define SM8250_SLAVE_A2NOC_CFG 60 -#define SM8250_SLAVE_AHB2PHY_NORTH 61 -#define SM8250_SLAVE_AHB2PHY_SOUTH 62 -#define SM8250_SLAVE_ANOC_PCIE_GEM_NOC 63 -#define SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1 64 -#define SM8250_SLAVE_AOSS 65 -#define SM8250_SLAVE_APPSS 66 -#define SM8250_SLAVE_CAMERA_CFG 67 -#define SM8250_SLAVE_CDSP_CFG 68 -#define SM8250_SLAVE_CDSP_MEM_NOC 69 -#define SM8250_SLAVE_CLK_CTL 70 -#define SM8250_SLAVE_CNOC_A2NOC 71 -#define SM8250_SLAVE_CNOC_DDRSS 72 -#define SM8250_SLAVE_CNOC_MNOC_CFG 73 -#define SM8250_SLAVE_CRYPTO_0_CFG 74 -#define SM8250_SLAVE_CX_RDPM 75 -#define SM8250_SLAVE_DCC_CFG 76 -#define SM8250_SLAVE_DISPLAY_CFG 77 -#define SM8250_SLAVE_EBI_CH0 78 -#define SM8250_SLAVE_GEM_NOC_CFG 79 -#define SM8250_SLAVE_GEM_NOC_SNOC 80 -#define SM8250_SLAVE_GRAPHICS_3D_CFG 81 -#define SM8250_SLAVE_IMEM_CFG 82 -#define SM8250_SLAVE_IPA_CFG 83 -/* 84 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ -#define SM8250_SLAVE_IPC_ROUTER_CFG 85 -#define SM8250_SLAVE_ISENSE_CFG 86 -#define SM8250_SLAVE_LLCC 87 -#define SM8250_SLAVE_LLCC_CFG 88 -#define SM8250_SLAVE_LPASS 89 -#define SM8250_SLAVE_MEM_NOC_PCIE_SNOC 90 -#define SM8250_SLAVE_MNOC_HF_MEM_NOC 91 -#define SM8250_SLAVE_MNOC_SF_MEM_NOC 92 -#define SM8250_SLAVE_NPU_CAL_DP0 93 -#define SM8250_SLAVE_NPU_CAL_DP1 94 -#define SM8250_SLAVE_NPU_CFG 95 -#define SM8250_SLAVE_NPU_COMPUTE_NOC 96 -#define SM8250_SLAVE_NPU_CP 97 -#define SM8250_SLAVE_NPU_DPM 98 -#define SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG 99 -#define SM8250_SLAVE_NPU_LLM_CFG 100 -#define SM8250_SLAVE_NPU_TCM 101 -#define SM8250_SLAVE_OCIMEM 102 -#define SM8250_SLAVE_PCIE_0 103 -#define SM8250_SLAVE_PCIE_0_CFG 104 -#define SM8250_SLAVE_PCIE_1 105 -#define SM8250_SLAVE_PCIE_1_CFG 106 -#define SM8250_SLAVE_PCIE_2 107 -#define SM8250_SLAVE_PCIE_2_CFG 108 -#define SM8250_SLAVE_PDM 109 -#define SM8250_SLAVE_PIMEM 110 -#define SM8250_SLAVE_PIMEM_CFG 111 -#define SM8250_SLAVE_PRNG 112 -#define SM8250_SLAVE_QDSS_CFG 113 -#define SM8250_SLAVE_QDSS_STM 114 -#define SM8250_SLAVE_QSPI_0 115 -#define SM8250_SLAVE_QUP_0 116 -#define SM8250_SLAVE_QUP_1 117 -#define SM8250_SLAVE_QUP_2 118 -#define SM8250_SLAVE_RBCPR_CX_CFG 119 -#define SM8250_SLAVE_RBCPR_MMCX_CFG 120 -#define SM8250_SLAVE_RBCPR_MX_CFG 121 -#define SM8250_SLAVE_SDCC_2 122 -#define SM8250_SLAVE_SDCC_4 123 -#define SM8250_SLAVE_SERVICE_A1NOC 124 -#define SM8250_SLAVE_SERVICE_A2NOC 125 -#define SM8250_SLAVE_SERVICE_CNOC 126 -#define SM8250_SLAVE_SERVICE_GEM_NOC 127 -#define SM8250_SLAVE_SERVICE_GEM_NOC_1 128 -#define SM8250_SLAVE_SERVICE_GEM_NOC_2 129 -#define SM8250_SLAVE_SERVICE_MNOC 130 -#define SM8250_SLAVE_SERVICE_NPU_NOC 131 -#define SM8250_SLAVE_SERVICE_SNOC 132 -#define SM8250_SLAVE_SNOC_CFG 133 -#define SM8250_SLAVE_SNOC_GEM_NOC_GC 134 -#define SM8250_SLAVE_SNOC_GEM_NOC_SF 135 -#define SM8250_SLAVE_TCSR 136 -#define SM8250_SLAVE_TCU 137 -#define SM8250_SLAVE_TLMM_NORTH 138 -#define SM8250_SLAVE_TLMM_SOUTH 139 -#define SM8250_SLAVE_TLMM_WEST 140 -#define SM8250_SLAVE_TSIF 141 -#define SM8250_SLAVE_UFS_CARD_CFG 142 -#define SM8250_SLAVE_UFS_MEM_CFG 143 -#define SM8250_SLAVE_USB3 144 -#define SM8250_SLAVE_USB3_1 145 -#define SM8250_SLAVE_VENUS_CFG 146 -#define SM8250_SLAVE_VSENSE_CTRL_CFG 147 -#define SM8250_SNOC_CNOC_MAS 148 -#define SM8250_SNOC_CNOC_SLV 149 -#define SM8250_MASTER_QUP_CORE_0 150 -#define SM8250_MASTER_QUP_CORE_1 151 -#define SM8250_MASTER_QUP_CORE_2 152 -#define SM8250_SLAVE_QUP_CORE_0 153 -#define SM8250_SLAVE_QUP_CORE_1 154 -#define SM8250_SLAVE_QUP_CORE_2 155 - -#endif diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom/sm8350.c index 4236a43dc256..bb793d724893 100644 --- a/drivers/interconnect/qcom/sm8350.c +++ b/drivers/interconnect/qcom/sm8350.c @@ -13,1255 +13,1241 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -#include "sm8350.h" + +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qnm_a1noc_cfg; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node xm_usb3_1; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qnm_a2noc_cfg; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node xm_qdss_etr; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node xm_ufs_card; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node xm_qdss_dap; +static struct qcom_icc_node qnm_cnoc_dc_noc; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_cmpnoc; +static struct qcom_icc_node qnm_gemnoc_cfg; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qhm_config_noc; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_mnoc_cfg; +static struct qcom_icc_node qnm_video0; +static struct qcom_icc_node qnm_video1; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qxm_mdp0; +static struct qcom_icc_node qxm_mdp1; +static struct qcom_icc_node qxm_rot; +static struct qcom_icc_node qhm_nsp_noc_config; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_snoc_cfg; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_dcc_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_hwkm; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_lpass_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_pka_wrapper_cfg; +static struct qcom_icc_node qhs_pmu_wrapper_cfg; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_security; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_ufs_card_cfg; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_usb3_1; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_a1_noc_cfg; +static struct qcom_icc_node qns_a2_noc_cfg; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qns_mnoc_cfg; +static struct qcom_icc_node qns_snoc_cfg; +static struct qcom_icc_node qxs_boot_imem; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_llcc; +static struct qcom_icc_node qns_gemnoc; +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; +static struct qcom_icc_node qhs_modem_ms_mpu_cfg; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node srvc_even_gemnoc; +static struct qcom_icc_node srvc_odd_gemnoc; +static struct qcom_icc_node srvc_sys_gemnoc; +static struct qcom_icc_node qhs_lpass_core; +static struct qcom_icc_node qhs_lpass_lpi; +static struct qcom_icc_node qhs_lpass_mpu; +static struct qcom_icc_node qhs_lpass_top; +static struct qcom_icc_node srvc_niu_aml_noc; +static struct qcom_icc_node srvc_niu_lpass_agnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node service_nsp_noc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node srvc_snoc; static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = SM8350_MASTER_QSPI_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8350_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", - .id = SM8350_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8350_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = SM8350_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8350_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", - .id = SM8350_MASTER_QUP_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8350_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_a1noc_cfg = { .name = "qnm_a1noc_cfg", - .id = SM8350_MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8350_SLAVE_SERVICE_A1NOC }, + .link_nodes = { &srvc_aggre1_noc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SM8350_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SM8350_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SM8350_MASTER_USB3_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_1 = { .name = "xm_usb3_1", - .id = SM8350_MASTER_USB3_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SM8350_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8350_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_a2noc_cfg = { .name = "qnm_a2noc_cfg", - .id = SM8350_MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8350_SLAVE_SERVICE_A2NOC }, + .link_nodes = { &srvc_aggre2_noc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SM8350_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SM8350_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", - .id = SM8350_MASTER_PCIE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", - .id = SM8350_MASTER_PCIE_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_qdss_etr = { .name = "xm_qdss_etr", - .id = SM8350_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SM8350_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_ufs_card = { .name = "xm_ufs_card", - .id = SM8350_MASTER_UFS_CARD, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", - .id = SM8350_MASTER_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 56, - .links = { SM8350_SLAVE_AHB2PHY_SOUTH, - SM8350_SLAVE_AHB2PHY_NORTH, - SM8350_SLAVE_AOSS, - SM8350_SLAVE_APPSS, - SM8350_SLAVE_CAMERA_CFG, - SM8350_SLAVE_CLK_CTL, - SM8350_SLAVE_CDSP_CFG, - SM8350_SLAVE_RBCPR_CX_CFG, - SM8350_SLAVE_RBCPR_MMCX_CFG, - SM8350_SLAVE_RBCPR_MX_CFG, - SM8350_SLAVE_CRYPTO_0_CFG, - SM8350_SLAVE_CX_RDPM, - SM8350_SLAVE_DCC_CFG, - SM8350_SLAVE_DISPLAY_CFG, - SM8350_SLAVE_GFX3D_CFG, - SM8350_SLAVE_HWKM, - SM8350_SLAVE_IMEM_CFG, - SM8350_SLAVE_IPA_CFG, - SM8350_SLAVE_IPC_ROUTER_CFG, - SM8350_SLAVE_LPASS, - SM8350_SLAVE_CNOC_MSS, - SM8350_SLAVE_MX_RDPM, - SM8350_SLAVE_PCIE_0_CFG, - SM8350_SLAVE_PCIE_1_CFG, - SM8350_SLAVE_PDM, - SM8350_SLAVE_PIMEM_CFG, - SM8350_SLAVE_PKA_WRAPPER_CFG, - SM8350_SLAVE_PMU_WRAPPER_CFG, - SM8350_SLAVE_QDSS_CFG, - SM8350_SLAVE_QSPI_0, - SM8350_SLAVE_QUP_0, - SM8350_SLAVE_QUP_1, - SM8350_SLAVE_QUP_2, - SM8350_SLAVE_SDCC_2, - SM8350_SLAVE_SDCC_4, - SM8350_SLAVE_SECURITY, - SM8350_SLAVE_SPSS_CFG, - SM8350_SLAVE_TCSR, - SM8350_SLAVE_TLMM, - SM8350_SLAVE_UFS_CARD_CFG, - SM8350_SLAVE_UFS_MEM_CFG, - SM8350_SLAVE_USB3_0, - SM8350_SLAVE_USB3_1, - SM8350_SLAVE_VENUS_CFG, - SM8350_SLAVE_VSENSE_CTRL_CFG, - SM8350_SLAVE_A1NOC_CFG, - SM8350_SLAVE_A2NOC_CFG, - SM8350_SLAVE_DDRSS_CFG, - SM8350_SLAVE_CNOC_MNOC_CFG, - SM8350_SLAVE_SNOC_CFG, - SM8350_SLAVE_BOOT_IMEM, - SM8350_SLAVE_IMEM, - SM8350_SLAVE_PIMEM, - SM8350_SLAVE_SERVICE_CNOC, - SM8350_SLAVE_QDSS_STM, - SM8350_SLAVE_TCU - }, + .link_nodes = { &qhs_ahb2phy0, + &qhs_ahb2phy1, + &qhs_aoss, + &qhs_apss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_cfg, + &qhs_cpr_cx, + &qhs_cpr_mmcx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_cx_rdpm, + &qhs_dcc_cfg, + &qhs_display_cfg, + &qhs_gpuss_cfg, + &qhs_hwkm, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_ipc_router, + &qhs_lpass_cfg, + &qhs_mss_cfg, + &qhs_mx_rdpm, + &qhs_pcie0_cfg, + &qhs_pcie1_cfg, + &qhs_pdm, + &qhs_pimem_cfg, + &qhs_pka_wrapper_cfg, + &qhs_pmu_wrapper_cfg, + &qhs_qdss_cfg, + &qhs_qspi, + &qhs_qup0, + &qhs_qup1, + &qhs_qup2, + &qhs_sdc2, + &qhs_sdc4, + &qhs_security, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_a1_noc_cfg, + &qns_a2_noc_cfg, + &qns_ddrss_cfg, + &qns_mnoc_cfg, + &qns_snoc_cfg, + &qxs_boot_imem, + &qxs_imem, + &qxs_pimem, + &srvc_cnoc, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = SM8350_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8350_SLAVE_PCIE_0, - SM8350_SLAVE_PCIE_1 - }, + .link_nodes = { &xs_pcie_0, + &xs_pcie_1 }, }; static struct qcom_icc_node xm_qdss_dap = { .name = "xm_qdss_dap", - .id = SM8350_MASTER_QDSS_DAP, .channels = 1, .buswidth = 8, .num_links = 56, - .links = { SM8350_SLAVE_AHB2PHY_SOUTH, - SM8350_SLAVE_AHB2PHY_NORTH, - SM8350_SLAVE_AOSS, - SM8350_SLAVE_APPSS, - SM8350_SLAVE_CAMERA_CFG, - SM8350_SLAVE_CLK_CTL, - SM8350_SLAVE_CDSP_CFG, - SM8350_SLAVE_RBCPR_CX_CFG, - SM8350_SLAVE_RBCPR_MMCX_CFG, - SM8350_SLAVE_RBCPR_MX_CFG, - SM8350_SLAVE_CRYPTO_0_CFG, - SM8350_SLAVE_CX_RDPM, - SM8350_SLAVE_DCC_CFG, - SM8350_SLAVE_DISPLAY_CFG, - SM8350_SLAVE_GFX3D_CFG, - SM8350_SLAVE_HWKM, - SM8350_SLAVE_IMEM_CFG, - SM8350_SLAVE_IPA_CFG, - SM8350_SLAVE_IPC_ROUTER_CFG, - SM8350_SLAVE_LPASS, - SM8350_SLAVE_CNOC_MSS, - SM8350_SLAVE_MX_RDPM, - SM8350_SLAVE_PCIE_0_CFG, - SM8350_SLAVE_PCIE_1_CFG, - SM8350_SLAVE_PDM, - SM8350_SLAVE_PIMEM_CFG, - SM8350_SLAVE_PKA_WRAPPER_CFG, - SM8350_SLAVE_PMU_WRAPPER_CFG, - SM8350_SLAVE_QDSS_CFG, - SM8350_SLAVE_QSPI_0, - SM8350_SLAVE_QUP_0, - SM8350_SLAVE_QUP_1, - SM8350_SLAVE_QUP_2, - SM8350_SLAVE_SDCC_2, - SM8350_SLAVE_SDCC_4, - SM8350_SLAVE_SECURITY, - SM8350_SLAVE_SPSS_CFG, - SM8350_SLAVE_TCSR, - SM8350_SLAVE_TLMM, - SM8350_SLAVE_UFS_CARD_CFG, - SM8350_SLAVE_UFS_MEM_CFG, - SM8350_SLAVE_USB3_0, - SM8350_SLAVE_USB3_1, - SM8350_SLAVE_VENUS_CFG, - SM8350_SLAVE_VSENSE_CTRL_CFG, - SM8350_SLAVE_A1NOC_CFG, - SM8350_SLAVE_A2NOC_CFG, - SM8350_SLAVE_DDRSS_CFG, - SM8350_SLAVE_CNOC_MNOC_CFG, - SM8350_SLAVE_SNOC_CFG, - SM8350_SLAVE_BOOT_IMEM, - SM8350_SLAVE_IMEM, - SM8350_SLAVE_PIMEM, - SM8350_SLAVE_SERVICE_CNOC, - SM8350_SLAVE_QDSS_STM, - SM8350_SLAVE_TCU - }, + .link_nodes = { &qhs_ahb2phy0, + &qhs_ahb2phy1, + &qhs_aoss, + &qhs_apss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_cfg, + &qhs_cpr_cx, + &qhs_cpr_mmcx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_cx_rdpm, + &qhs_dcc_cfg, + &qhs_display_cfg, + &qhs_gpuss_cfg, + &qhs_hwkm, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_ipc_router, + &qhs_lpass_cfg, + &qhs_mss_cfg, + &qhs_mx_rdpm, + &qhs_pcie0_cfg, + &qhs_pcie1_cfg, + &qhs_pdm, + &qhs_pimem_cfg, + &qhs_pka_wrapper_cfg, + &qhs_pmu_wrapper_cfg, + &qhs_qdss_cfg, + &qhs_qspi, + &qhs_qup0, + &qhs_qup1, + &qhs_qup2, + &qhs_sdc2, + &qhs_sdc4, + &qhs_security, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_a1_noc_cfg, + &qns_a2_noc_cfg, + &qns_ddrss_cfg, + &qns_mnoc_cfg, + &qns_snoc_cfg, + &qxs_boot_imem, + &qxs_imem, + &qxs_pimem, + &srvc_cnoc, + &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_cnoc_dc_noc = { .name = "qnm_cnoc_dc_noc", - .id = SM8350_MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .num_links = 2, - .links = { SM8350_SLAVE_LLCC_CFG, - SM8350_SLAVE_GEM_NOC_CFG - }, + .link_nodes = { &qhs_llcc, + &qns_gemnoc }, }; static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", - .id = SM8350_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8350_SLAVE_GEM_NOC_CNOC, - SM8350_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", - .id = SM8350_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8350_SLAVE_GEM_NOC_CNOC, - SM8350_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", - .id = SM8350_MASTER_APPSS_PROC, .channels = 2, .buswidth = 32, .num_links = 3, - .links = { SM8350_SLAVE_GEM_NOC_CNOC, - SM8350_SLAVE_LLCC, - SM8350_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_cmpnoc = { .name = "qnm_cmpnoc", - .id = SM8350_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8350_SLAVE_GEM_NOC_CNOC, - SM8350_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node qnm_gemnoc_cfg = { .name = "qnm_gemnoc_cfg", - .id = SM8350_MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 5, - .links = { SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, - SM8350_SLAVE_MCDMA_MS_MPU_CFG, - SM8350_SLAVE_SERVICE_GEM_NOC_1, - SM8350_SLAVE_SERVICE_GEM_NOC_2, - SM8350_SLAVE_SERVICE_GEM_NOC - }, + .link_nodes = { &qhs_mdsp_ms_mpu_cfg, + &qhs_modem_ms_mpu_cfg, + &srvc_even_gemnoc, + &srvc_odd_gemnoc, + &srvc_sys_gemnoc }, }; static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", - .id = SM8350_MASTER_GFX3D, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8350_SLAVE_GEM_NOC_CNOC, - SM8350_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SM8350_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8350_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SM8350_MASTER_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8350_SLAVE_GEM_NOC_CNOC, - SM8350_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = SM8350_MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SM8350_SLAVE_GEM_NOC_CNOC, - SM8350_SLAVE_LLCC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SM8350_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SM8350_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SM8350_SLAVE_GEM_NOC_CNOC, - SM8350_SLAVE_LLCC, - SM8350_SLAVE_MEM_NOC_PCIE_SNOC - }, + .link_nodes = { &qns_gem_noc_cnoc, + &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qhm_config_noc = { .name = "qhm_config_noc", - .id = SM8350_MASTER_CNOC_LPASS_AG_NOC, .channels = 1, .buswidth = 4, .num_links = 6, - .links = { SM8350_SLAVE_LPASS_CORE_CFG, - SM8350_SLAVE_LPASS_LPI_CFG, - SM8350_SLAVE_LPASS_MPU_CFG, - SM8350_SLAVE_LPASS_TOP_CFG, - SM8350_SLAVE_SERVICES_LPASS_AML_NOC, - SM8350_SLAVE_SERVICE_LPASS_AG_NOC - }, + .link_nodes = { &qhs_lpass_core, + &qhs_lpass_lpi, + &qhs_lpass_mpu, + &qhs_lpass_top, + &srvc_niu_aml_noc, + &srvc_niu_lpass_agnoc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SM8350_MASTER_LLCC, .channels = 4, .buswidth = 4, .num_links = 1, - .links = { SM8350_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qnm_camnoc_hf = { .name = "qnm_camnoc_hf", - .id = SM8350_MASTER_CAMNOC_HF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_camnoc_icp = { .name = "qnm_camnoc_icp", - .id = SM8350_MASTER_CAMNOC_ICP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_camnoc_sf = { .name = "qnm_camnoc_sf", - .id = SM8350_MASTER_CAMNOC_SF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_mnoc_cfg = { .name = "qnm_mnoc_cfg", - .id = SM8350_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8350_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qnm_video0 = { .name = "qnm_video0", - .id = SM8350_MASTER_VIDEO_P0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video1 = { .name = "qnm_video1", - .id = SM8350_MASTER_VIDEO_P1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_cvp = { .name = "qnm_video_cvp", - .id = SM8350_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qxm_mdp0 = { .name = "qxm_mdp0", - .id = SM8350_MASTER_MDP0, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_mdp1 = { .name = "qxm_mdp1", - .id = SM8350_MASTER_MDP1, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qxm_rot = { .name = "qxm_rot", - .id = SM8350_MASTER_ROTATOR, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qhm_nsp_noc_config = { .name = "qhm_nsp_noc_config", - .id = SM8350_MASTER_CDSP_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8350_SLAVE_SERVICE_NSP_NOC }, + .link_nodes = { &service_nsp_noc }, }; static struct qcom_icc_node qxm_nsp = { .name = "qxm_nsp", - .id = SM8350_MASTER_CDSP_PROC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8350_SLAVE_CDSP_MEM_NOC }, + .link_nodes = { &qns_nsp_gemnoc }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SM8350_MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8350_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SM8350_MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8350_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_snoc_cfg = { .name = "qnm_snoc_cfg", - .id = SM8350_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8350_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = SM8350_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SM8350_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SM8350_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8350_MASTER_A1NOC_SNOC }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node srvc_aggre1_noc = { .name = "srvc_aggre1_noc", - .id = SM8350_SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SM8350_SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8350_MASTER_A2NOC_SNOC }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qns_pcie_mem_noc = { .name = "qns_pcie_mem_noc", - .id = SM8350_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8350_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node srvc_aggre2_noc = { .name = "srvc_aggre2_noc", - .id = SM8350_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", - .id = SM8350_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ahb2phy1 = { .name = "qhs_ahb2phy1", - .id = SM8350_SLAVE_AHB2PHY_NORTH, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SM8350_SLAVE_AOSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SM8350_SLAVE_APPSS, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SM8350_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SM8350_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_compute_cfg = { .name = "qhs_compute_cfg", - .id = SM8350_SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SM8350_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_mmcx = { .name = "qhs_cpr_mmcx", - .id = SM8350_SLAVE_RBCPR_MMCX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cpr_mx = { .name = "qhs_cpr_mx", - .id = SM8350_SLAVE_RBCPR_MX_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SM8350_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_cx_rdpm = { .name = "qhs_cx_rdpm", - .id = SM8350_SLAVE_CX_RDPM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_dcc_cfg = { .name = "qhs_dcc_cfg", - .id = SM8350_SLAVE_DCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SM8350_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SM8350_SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_hwkm = { .name = "qhs_hwkm", - .id = SM8350_SLAVE_HWKM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SM8350_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SM8350_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", - .id = SM8350_SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_cfg = { .name = "qhs_lpass_cfg", - .id = SM8350_SLAVE_LPASS, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8350_MASTER_CNOC_LPASS_AG_NOC }, + .link_nodes = { &qhm_config_noc }, }; static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", - .id = SM8350_SLAVE_CNOC_MSS, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mx_rdpm = { .name = "qhs_mx_rdpm", - .id = SM8350_SLAVE_MX_RDPM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = SM8350_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pcie1_cfg = { .name = "qhs_pcie1_cfg", - .id = SM8350_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SM8350_SLAVE_PDM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SM8350_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pka_wrapper_cfg = { .name = "qhs_pka_wrapper_cfg", - .id = SM8350_SLAVE_PKA_WRAPPER_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_pmu_wrapper_cfg = { .name = "qhs_pmu_wrapper_cfg", - .id = SM8350_SLAVE_PMU_WRAPPER_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SM8350_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = SM8350_SLAVE_QSPI_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", - .id = SM8350_SLAVE_QUP_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = SM8350_SLAVE_QUP_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_qup2 = { .name = "qhs_qup2", - .id = SM8350_SLAVE_QUP_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SM8350_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SM8350_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_security = { .name = "qhs_security", - .id = SM8350_SLAVE_SECURITY, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_spss_cfg = { .name = "qhs_spss_cfg", - .id = SM8350_SLAVE_SPSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SM8350_SLAVE_TCSR, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = SM8350_SLAVE_TLMM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_card_cfg = { .name = "qhs_ufs_card_cfg", - .id = SM8350_SLAVE_UFS_CARD_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SM8350_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SM8350_SLAVE_USB3_0, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_usb3_1 = { .name = "qhs_usb3_1", - .id = SM8350_SLAVE_USB3_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SM8350_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SM8350_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_a1_noc_cfg = { .name = "qns_a1_noc_cfg", - .id = SM8350_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_a2_noc_cfg = { .name = "qns_a2_noc_cfg", - .id = SM8350_SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_ddrss_cfg = { .name = "qns_ddrss_cfg", - .id = SM8350_SLAVE_DDRSS_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_mnoc_cfg = { .name = "qns_mnoc_cfg", - .id = SM8350_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_snoc_cfg = { .name = "qns_snoc_cfg", - .id = SM8350_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qxs_boot_imem = { .name = "qxs_boot_imem", - .id = SM8350_SLAVE_BOOT_IMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SM8350_SLAVE_IMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = SM8350_SLAVE_PIMEM, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node srvc_cnoc = { .name = "srvc_cnoc", - .id = SM8350_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_pcie_0 = { .name = "xs_pcie_0", - .id = SM8350_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_pcie_1 = { .name = "xs_pcie_1", - .id = SM8350_SLAVE_PCIE_1, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SM8350_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SM8350_SLAVE_TCU, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node qhs_llcc = { .name = "qhs_llcc", - .id = SM8350_SLAVE_LLCC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_gemnoc = { .name = "qns_gemnoc", - .id = SM8350_SLAVE_GEM_NOC_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { .name = "qhs_mdsp_ms_mpu_cfg", - .id = SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_modem_ms_mpu_cfg = { .name = "qhs_modem_ms_mpu_cfg", - .id = SM8350_SLAVE_MCDMA_MS_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_gem_noc_cnoc = { .name = "qns_gem_noc_cnoc", - .id = SM8350_SLAVE_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8350_MASTER_GEM_NOC_CNOC }, + .link_nodes = { &qnm_gemnoc_cnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SM8350_SLAVE_LLCC, .channels = 4, .buswidth = 16, .num_links = 1, - .links = { SM8350_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_pcie = { .name = "qns_pcie", - .id = SM8350_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, }; static struct qcom_icc_node srvc_even_gemnoc = { .name = "srvc_even_gemnoc", - .id = SM8350_SLAVE_SERVICE_GEM_NOC_1, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_odd_gemnoc = { .name = "srvc_odd_gemnoc", - .id = SM8350_SLAVE_SERVICE_GEM_NOC_2, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_sys_gemnoc = { .name = "srvc_sys_gemnoc", - .id = SM8350_SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_core = { .name = "qhs_lpass_core", - .id = SM8350_SLAVE_LPASS_CORE_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_lpi = { .name = "qhs_lpass_lpi", - .id = SM8350_SLAVE_LPASS_LPI_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_mpu = { .name = "qhs_lpass_mpu", - .id = SM8350_SLAVE_LPASS_MPU_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qhs_lpass_top = { .name = "qhs_lpass_top", - .id = SM8350_SLAVE_LPASS_TOP_CFG, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_niu_aml_noc = { .name = "srvc_niu_aml_noc", - .id = SM8350_SLAVE_SERVICES_LPASS_AML_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node srvc_niu_lpass_agnoc = { .name = "srvc_niu_lpass_agnoc", - .id = SM8350_SLAVE_SERVICE_LPASS_AG_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SM8350_SLAVE_EBI1, .channels = 4, .buswidth = 4, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SM8350_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8350_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", - .id = SM8350_SLAVE_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8350_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SM8350_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_nsp_gemnoc = { .name = "qns_nsp_gemnoc", - .id = SM8350_SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8350_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_cmpnoc }, }; static struct qcom_icc_node service_nsp_noc = { .name = "service_nsp_noc", - .id = SM8350_SLAVE_SERVICE_NSP_NOC, .channels = 1, .buswidth = 4, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = SM8350_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8350_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SM8350_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8350_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SM8350_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, }; @@ -1807,7 +1793,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove_new = qcom_icc_rpmh_remove, + .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sm8350", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sm8350.h b/drivers/interconnect/qcom/sm8350.h deleted file mode 100644 index 074c6131ab36..000000000000 --- a/drivers/interconnect/qcom/sm8350.h +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm SM8350 interconnect IDs - * - * Copyright (c) 2021, Linaro Limited - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8350_H -#define __DRIVERS_INTERCONNECT_QCOM_SM8350_H - -#define SM8350_MASTER_GPU_TCU 0 -#define SM8350_MASTER_SYS_TCU 1 -#define SM8350_MASTER_APPSS_PROC 2 -#define SM8350_MASTER_LLCC 3 -#define SM8350_MASTER_CNOC_LPASS_AG_NOC 4 -#define SM8350_MASTER_CDSP_NOC_CFG 5 -#define SM8350_MASTER_QDSS_BAM 6 -#define SM8350_MASTER_QSPI_0 7 -#define SM8350_MASTER_QUP_0 8 -#define SM8350_MASTER_QUP_1 9 -#define SM8350_MASTER_QUP_2 10 -#define SM8350_MASTER_A1NOC_CFG 11 -#define SM8350_MASTER_A2NOC_CFG 12 -#define SM8350_MASTER_A1NOC_SNOC 13 -#define SM8350_MASTER_A2NOC_SNOC 14 -#define SM8350_MASTER_CAMNOC_HF 15 -#define SM8350_MASTER_CAMNOC_ICP 16 -#define SM8350_MASTER_CAMNOC_SF 17 -#define SM8350_MASTER_COMPUTE_NOC 18 -#define SM8350_MASTER_CNOC_DC_NOC 19 -#define SM8350_MASTER_GEM_NOC_CFG 20 -#define SM8350_MASTER_GEM_NOC_CNOC 21 -#define SM8350_MASTER_GEM_NOC_PCIE_SNOC 22 -#define SM8350_MASTER_GFX3D 23 -#define SM8350_MASTER_CNOC_MNOC_CFG 24 -#define SM8350_MASTER_MNOC_HF_MEM_NOC 25 -#define SM8350_MASTER_MNOC_SF_MEM_NOC 26 -#define SM8350_MASTER_ANOC_PCIE_GEM_NOC 27 -#define SM8350_MASTER_SNOC_CFG 28 -#define SM8350_MASTER_SNOC_GC_MEM_NOC 29 -#define SM8350_MASTER_SNOC_SF_MEM_NOC 30 -#define SM8350_MASTER_VIDEO_P0 31 -#define SM8350_MASTER_VIDEO_P1 32 -#define SM8350_MASTER_VIDEO_PROC 33 -#define SM8350_MASTER_QUP_CORE_0 34 -#define SM8350_MASTER_QUP_CORE_1 35 -#define SM8350_MASTER_QUP_CORE_2 36 -#define SM8350_MASTER_CRYPTO 37 -#define SM8350_MASTER_IPA 38 -#define SM8350_MASTER_MDP0 39 -#define SM8350_MASTER_MDP1 40 -#define SM8350_MASTER_CDSP_PROC 41 -#define SM8350_MASTER_PIMEM 42 -#define SM8350_MASTER_ROTATOR 43 -#define SM8350_MASTER_GIC 44 -#define SM8350_MASTER_PCIE_0 45 -#define SM8350_MASTER_PCIE_1 46 -#define SM8350_MASTER_QDSS_DAP 47 -#define SM8350_MASTER_QDSS_ETR 48 -#define SM8350_MASTER_SDCC_2 49 -#define SM8350_MASTER_SDCC_4 50 -#define SM8350_MASTER_UFS_CARD 51 -#define SM8350_MASTER_UFS_MEM 52 -#define SM8350_MASTER_USB3_0 53 -#define SM8350_MASTER_USB3_1 54 -#define SM8350_SLAVE_EBI1 55 -#define SM8350_SLAVE_AHB2PHY_SOUTH 56 -#define SM8350_SLAVE_AHB2PHY_NORTH 57 -#define SM8350_SLAVE_AOSS 58 -#define SM8350_SLAVE_APPSS 59 -#define SM8350_SLAVE_CAMERA_CFG 60 -#define SM8350_SLAVE_CLK_CTL 61 -#define SM8350_SLAVE_CDSP_CFG 62 -#define SM8350_SLAVE_RBCPR_CX_CFG 63 -#define SM8350_SLAVE_RBCPR_MMCX_CFG 64 -#define SM8350_SLAVE_RBCPR_MX_CFG 65 -#define SM8350_SLAVE_CRYPTO_0_CFG 66 -#define SM8350_SLAVE_CX_RDPM 67 -#define SM8350_SLAVE_DCC_CFG 68 -#define SM8350_SLAVE_DISPLAY_CFG 69 -#define SM8350_SLAVE_GFX3D_CFG 70 -#define SM8350_SLAVE_HWKM 71 -#define SM8350_SLAVE_IMEM_CFG 72 -#define SM8350_SLAVE_IPA_CFG 73 -#define SM8350_SLAVE_IPC_ROUTER_CFG 74 -#define SM8350_SLAVE_LLCC_CFG 75 -#define SM8350_SLAVE_LPASS 76 -#define SM8350_SLAVE_LPASS_CORE_CFG 77 -#define SM8350_SLAVE_LPASS_LPI_CFG 78 -#define SM8350_SLAVE_LPASS_MPU_CFG 79 -#define SM8350_SLAVE_LPASS_TOP_CFG 80 -#define SM8350_SLAVE_MSS_PROC_MS_MPU_CFG 81 -#define SM8350_SLAVE_MCDMA_MS_MPU_CFG 82 -#define SM8350_SLAVE_CNOC_MSS 83 -#define SM8350_SLAVE_MX_RDPM 84 -#define SM8350_SLAVE_PCIE_0_CFG 85 -#define SM8350_SLAVE_PCIE_1_CFG 86 -#define SM8350_SLAVE_PDM 87 -#define SM8350_SLAVE_PIMEM_CFG 88 -#define SM8350_SLAVE_PKA_WRAPPER_CFG 89 -#define SM8350_SLAVE_PMU_WRAPPER_CFG 90 -#define SM8350_SLAVE_QDSS_CFG 91 -#define SM8350_SLAVE_QSPI_0 92 -#define SM8350_SLAVE_QUP_0 93 -#define SM8350_SLAVE_QUP_1 94 -#define SM8350_SLAVE_QUP_2 95 -#define SM8350_SLAVE_SDCC_2 96 -#define SM8350_SLAVE_SDCC_4 97 -#define SM8350_SLAVE_SECURITY 98 -#define SM8350_SLAVE_SPSS_CFG 99 -#define SM8350_SLAVE_TCSR 100 -#define SM8350_SLAVE_TLMM 101 -#define SM8350_SLAVE_UFS_CARD_CFG 102 -#define SM8350_SLAVE_UFS_MEM_CFG 103 -#define SM8350_SLAVE_USB3_0 104 -#define SM8350_SLAVE_USB3_1 105 -#define SM8350_SLAVE_VENUS_CFG 106 -#define SM8350_SLAVE_VSENSE_CTRL_CFG 107 -#define SM8350_SLAVE_A1NOC_CFG 108 -#define SM8350_SLAVE_A1NOC_SNOC 109 -#define SM8350_SLAVE_A2NOC_CFG 110 -#define SM8350_SLAVE_A2NOC_SNOC 111 -#define SM8350_SLAVE_DDRSS_CFG 112 -#define SM8350_SLAVE_GEM_NOC_CNOC 113 -#define SM8350_SLAVE_GEM_NOC_CFG 114 -#define SM8350_SLAVE_SNOC_GEM_NOC_GC 115 -#define SM8350_SLAVE_SNOC_GEM_NOC_SF 116 -#define SM8350_SLAVE_LLCC 117 -#define SM8350_SLAVE_MNOC_HF_MEM_NOC 118 -#define SM8350_SLAVE_MNOC_SF_MEM_NOC 119 -#define SM8350_SLAVE_CNOC_MNOC_CFG 120 -#define SM8350_SLAVE_CDSP_MEM_NOC 121 -#define SM8350_SLAVE_MEM_NOC_PCIE_SNOC 122 -#define SM8350_SLAVE_ANOC_PCIE_GEM_NOC 123 -#define SM8350_SLAVE_SNOC_CFG 124 -#define SM8350_SLAVE_QUP_CORE_0 125 -#define SM8350_SLAVE_QUP_CORE_1 126 -#define SM8350_SLAVE_QUP_CORE_2 127 -#define SM8350_SLAVE_BOOT_IMEM 128 -#define SM8350_SLAVE_IMEM 129 -#define SM8350_SLAVE_PIMEM 130 -#define SM8350_SLAVE_SERVICE_NSP_NOC 131 -#define SM8350_SLAVE_SERVICE_A1NOC 132 -#define SM8350_SLAVE_SERVICE_A2NOC 133 -#define SM8350_SLAVE_SERVICE_CNOC 134 -#define SM8350_SLAVE_SERVICE_GEM_NOC_1 135 -#define SM8350_SLAVE_SERVICE_MNOC 136 -#define SM8350_SLAVE_SERVICES_LPASS_AML_NOC 137 -#define SM8350_SLAVE_SERVICE_LPASS_AG_NOC 138 -#define SM8350_SLAVE_SERVICE_GEM_NOC_2 139 -#define SM8350_SLAVE_SERVICE_SNOC 140 -#define SM8350_SLAVE_SERVICE_GEM_NOC 141 -#define SM8350_SLAVE_PCIE_0 142 -#define SM8350_SLAVE_PCIE_1 143 -#define SM8350_SLAVE_QDSS_STM 144 -#define SM8350_SLAVE_TCU 145 - -#endif diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom/sm8450.c index b3cd0087377c..669a638bf3ef 100644 --- a/drivers/interconnect/qcom/sm8450.c +++ b/drivers/interconnect/qcom/sm8450.c @@ -16,1325 +16,1262 @@ #include "bcm-voter.h" #include "icc-common.h" #include "icc-rpmh.h" -#include "sm8450.h" + +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qnm_a1noc_cfg; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qnm_a2noc_cfg; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node qxm_sensorss_q6; +static struct qcom_icc_node qxm_sp; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup2_core_master; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_mdsp; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_nsp_gemnoc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qhm_config_noc; +static struct qcom_icc_node qxm_lpass_dsp; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_mdp; +static struct qcom_icc_node qnm_mnoc_cfg; +static struct qcom_icc_node qnm_rot; +static struct qcom_icc_node qnm_vapss_hcp; +static struct qcom_icc_node qnm_video; +static struct qcom_icc_node qnm_video_cv_cpu; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qnm_video_v_cpu; +static struct qcom_icc_node qhm_nsp_noc_config; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node qnm_pcie_anoc_cfg; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node qhm_gic; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_lpass_noc; +static struct qcom_icc_node qnm_snoc_cfg; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qnm_mnoc_hf_disp; +static struct qcom_icc_node qnm_mnoc_sf_disp; +static struct qcom_icc_node qnm_pcie_disp; +static struct qcom_icc_node llcc_mc_disp; +static struct qcom_icc_node qnm_mdp_disp; +static struct qcom_icc_node qnm_rot_disp; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node srvc_aggre1_noc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node srvc_aggre2_noc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup2_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_compute_cfg; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mxa; +static struct qcom_icc_node qhs_cpr_mxc; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_lpass_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qns_a1_noc_cfg; +static struct qcom_icc_node qns_a2_noc_cfg; +static struct qcom_icc_node qns_ddrss_cfg; +static struct qcom_icc_node qns_mnoc_cfg; +static struct qcom_icc_node qns_pcie_anoc_cfg; +static struct qcom_icc_node qns_snoc_cfg; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_cnoc; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node qhs_lpass_core; +static struct qcom_icc_node qhs_lpass_lpi; +static struct qcom_icc_node qhs_lpass_mpu; +static struct qcom_icc_node qhs_lpass_top; +static struct qcom_icc_node qns_sysnoc; +static struct qcom_icc_node srvc_niu_aml_noc; +static struct qcom_icc_node srvc_niu_lpass_agnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node service_nsp_noc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_pcie_aggre_noc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node srvc_snoc; +static struct qcom_icc_node qns_llcc_disp; +static struct qcom_icc_node ebi_disp; +static struct qcom_icc_node qns_mem_noc_hf_disp; +static struct qcom_icc_node qns_mem_noc_sf_disp; static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = SM8450_MASTER_QSPI_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = SM8450_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qnm_a1noc_cfg = { .name = "qnm_a1noc_cfg", - .id = SM8450_MASTER_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_SERVICE_A1NOC }, + .link_nodes = { &srvc_aggre1_noc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SM8450_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SM8450_MASTER_UFS_MEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SM8450_MASTER_USB3_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SM8450_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", - .id = SM8450_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", - .id = SM8450_MASTER_QUP_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qnm_a2noc_cfg = { .name = "qnm_a2noc_cfg", - .id = SM8450_MASTER_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_SERVICE_A2NOC }, + .link_nodes = { &srvc_aggre2_noc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SM8450_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SM8450_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_sensorss_q6 = { .name = "qxm_sensorss_q6", - .id = SM8450_MASTER_SENSORS_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_sp = { .name = "qxm_sp", - .id = SM8450_MASTER_SP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr_0 = { .name = "xm_qdss_etr_0", - .id = SM8450_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr_1 = { .name = "xm_qdss_etr_1", - .id = SM8450_MASTER_QDSS_ETR_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SM8450_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", - .id = SM8450_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { .name = "qup1_core_master", - .id = SM8450_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_QUP_CORE_1 }, + .link_nodes = { &qup1_core_slave }, }; static struct qcom_icc_node qup2_core_master = { .name = "qup2_core_master", - .id = SM8450_MASTER_QUP_CORE_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_QUP_CORE_2 }, + .link_nodes = { &qup2_core_slave }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", - .id = SM8450_MASTER_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 51, - .links = { SM8450_SLAVE_AHB2PHY_SOUTH, SM8450_SLAVE_AHB2PHY_NORTH, - SM8450_SLAVE_AOSS, SM8450_SLAVE_CAMERA_CFG, - SM8450_SLAVE_CLK_CTL, SM8450_SLAVE_CDSP_CFG, - SM8450_SLAVE_RBCPR_CX_CFG, SM8450_SLAVE_RBCPR_MMCX_CFG, - SM8450_SLAVE_RBCPR_MXA_CFG, SM8450_SLAVE_RBCPR_MXC_CFG, - SM8450_SLAVE_CRYPTO_0_CFG, SM8450_SLAVE_CX_RDPM, - SM8450_SLAVE_DISPLAY_CFG, SM8450_SLAVE_GFX3D_CFG, - SM8450_SLAVE_IMEM_CFG, SM8450_SLAVE_IPA_CFG, - SM8450_SLAVE_IPC_ROUTER_CFG, SM8450_SLAVE_LPASS, - SM8450_SLAVE_CNOC_MSS, SM8450_SLAVE_MX_RDPM, - SM8450_SLAVE_PCIE_0_CFG, SM8450_SLAVE_PCIE_1_CFG, - SM8450_SLAVE_PDM, SM8450_SLAVE_PIMEM_CFG, - SM8450_SLAVE_PRNG, SM8450_SLAVE_QDSS_CFG, - SM8450_SLAVE_QSPI_0, SM8450_SLAVE_QUP_0, - SM8450_SLAVE_QUP_1, SM8450_SLAVE_QUP_2, - SM8450_SLAVE_SDCC_2, SM8450_SLAVE_SDCC_4, - SM8450_SLAVE_SPSS_CFG, SM8450_SLAVE_TCSR, - SM8450_SLAVE_TLMM, SM8450_SLAVE_TME_CFG, - SM8450_SLAVE_UFS_MEM_CFG, SM8450_SLAVE_USB3_0, - SM8450_SLAVE_VENUS_CFG, SM8450_SLAVE_VSENSE_CTRL_CFG, - SM8450_SLAVE_A1NOC_CFG, SM8450_SLAVE_A2NOC_CFG, - SM8450_SLAVE_DDRSS_CFG, SM8450_SLAVE_CNOC_MNOC_CFG, - SM8450_SLAVE_PCIE_ANOC_CFG, SM8450_SLAVE_SNOC_CFG, - SM8450_SLAVE_IMEM, SM8450_SLAVE_PIMEM, - SM8450_SLAVE_SERVICE_CNOC, SM8450_SLAVE_QDSS_STM, - SM8450_SLAVE_TCU }, + .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_aoss, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_compute_cfg, + &qhs_cpr_cx, &qhs_cpr_mmcx, + &qhs_cpr_mxa, &qhs_cpr_mxc, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_imem_cfg, &qhs_ipa, + &qhs_ipc_router, &qhs_lpass_cfg, + &qhs_mss_cfg, &qhs_mx_rdpm, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pdm, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_qup2, + &qhs_sdc2, &qhs_sdc4, + &qhs_spss_cfg, &qhs_tcsr, + &qhs_tlmm, &qhs_tme_cfg, + &qhs_ufs_mem_cfg, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qns_a1_noc_cfg, &qns_a2_noc_cfg, + &qns_ddrss_cfg, &qns_mnoc_cfg, + &qns_pcie_anoc_cfg, &qns_snoc_cfg, + &qxs_imem, &qxs_pimem, + &srvc_cnoc, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = SM8450_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8450_SLAVE_PCIE_0, SM8450_SLAVE_PCIE_1 }, + .link_nodes = { &xs_pcie_0, &xs_pcie_1 }, }; static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", - .id = SM8450_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", - .id = SM8450_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", - .id = SM8450_MASTER_APPSS_PROC, .channels = 3, .buswidth = 32, .num_links = 3, - .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC, - SM8450_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", - .id = SM8450_MASTER_GFX3D, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_mdsp = { .name = "qnm_mdsp", - .id = SM8450_MASTER_MSS_PROC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC, - SM8450_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SM8450_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SM8450_MASTER_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_nsp_gemnoc = { .name = "qnm_nsp_gemnoc", - .id = SM8450_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = SM8450_MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SM8450_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SM8450_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC, - SM8450_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qhm_config_noc = { .name = "qhm_config_noc", - .id = SM8450_MASTER_CNOC_LPASS_AG_NOC, .channels = 1, .buswidth = 4, .num_links = 6, - .links = { SM8450_SLAVE_LPASS_CORE_CFG, SM8450_SLAVE_LPASS_LPI_CFG, - SM8450_SLAVE_LPASS_MPU_CFG, SM8450_SLAVE_LPASS_TOP_CFG, - SM8450_SLAVE_SERVICES_LPASS_AML_NOC, SM8450_SLAVE_SERVICE_LPASS_AG_NOC }, + .link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi, + &qhs_lpass_mpu, &qhs_lpass_top, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; static struct qcom_icc_node qxm_lpass_dsp = { .name = "qxm_lpass_dsp", - .id = SM8450_MASTER_LPASS_PROC, .channels = 1, .buswidth = 8, .num_links = 4, - .links = { SM8450_SLAVE_LPASS_TOP_CFG, SM8450_SLAVE_LPASS_SNOC, - SM8450_SLAVE_SERVICES_LPASS_AML_NOC, SM8450_SLAVE_SERVICE_LPASS_AG_NOC }, + .link_nodes = { &qhs_lpass_top, &qns_sysnoc, + &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SM8450_MASTER_LLCC, .channels = 4, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qnm_camnoc_hf = { .name = "qnm_camnoc_hf", - .id = SM8450_MASTER_CAMNOC_HF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_camnoc_icp = { .name = "qnm_camnoc_icp", - .id = SM8450_MASTER_CAMNOC_ICP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_camnoc_sf = { .name = "qnm_camnoc_sf", - .id = SM8450_MASTER_CAMNOC_SF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_mdp = { .name = "qnm_mdp", - .id = SM8450_MASTER_MDP, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_mnoc_cfg = { .name = "qnm_mnoc_cfg", - .id = SM8450_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qnm_rot = { .name = "qnm_rot", - .id = SM8450_MASTER_ROTATOR, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_vapss_hcp = { .name = "qnm_vapss_hcp", - .id = SM8450_MASTER_CDSP_HCP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video = { .name = "qnm_video", - .id = SM8450_MASTER_VIDEO, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_cv_cpu = { .name = "qnm_video_cv_cpu", - .id = SM8450_MASTER_VIDEO_CV_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_cvp = { .name = "qnm_video_cvp", - .id = SM8450_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_v_cpu = { .name = "qnm_video_v_cpu", - .id = SM8450_MASTER_VIDEO_V_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qhm_nsp_noc_config = { .name = "qhm_nsp_noc_config", - .id = SM8450_MASTER_CDSP_NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_SERVICE_NSP_NOC }, + .link_nodes = { &service_nsp_noc }, }; static struct qcom_icc_node qxm_nsp = { .name = "qxm_nsp", - .id = SM8450_MASTER_CDSP_PROC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_CDSP_MEM_NOC }, + .link_nodes = { &qns_nsp_gemnoc }, }; static struct qcom_icc_node qnm_pcie_anoc_cfg = { .name = "qnm_pcie_anoc_cfg", - .id = SM8450_MASTER_PCIE_ANOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_SERVICE_PCIE_ANOC }, + .link_nodes = { &srvc_pcie_aggre_noc }, }; static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", - .id = SM8450_MASTER_PCIE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", - .id = SM8450_MASTER_PCIE_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node qhm_gic = { .name = "qhm_gic", - .id = SM8450_MASTER_GIC_AHB, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SM8450_MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8450_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SM8450_MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8450_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_lpass_noc = { .name = "qnm_lpass_noc", - .id = SM8450_MASTER_LPASS_ANOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8450_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_snoc_cfg = { .name = "qnm_snoc_cfg", - .id = SM8450_MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_SERVICE_SNOC }, + .link_nodes = { &srvc_snoc }, }; static struct qcom_icc_node qxm_pimem = { .name = "qxm_pimem", - .id = SM8450_MASTER_PIMEM, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SM8450_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node qnm_mnoc_hf_disp = { .name = "qnm_mnoc_hf_disp", - .id = SM8450_MASTER_MNOC_HF_MEM_NOC_DISP, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_LLCC_DISP }, + .link_nodes = { &qns_llcc_disp }, }; static struct qcom_icc_node qnm_mnoc_sf_disp = { .name = "qnm_mnoc_sf_disp", - .id = SM8450_MASTER_MNOC_SF_MEM_NOC_DISP, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_LLCC_DISP }, + .link_nodes = { &qns_llcc_disp }, }; static struct qcom_icc_node qnm_pcie_disp = { .name = "qnm_pcie_disp", - .id = SM8450_MASTER_ANOC_PCIE_GEM_NOC_DISP, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8450_SLAVE_LLCC_DISP }, + .link_nodes = { &qns_llcc_disp }, }; static struct qcom_icc_node llcc_mc_disp = { .name = "llcc_mc_disp", - .id = SM8450_MASTER_LLCC_DISP, .channels = 4, .buswidth = 4, .num_links = 1, - .links = { SM8450_SLAVE_EBI1_DISP }, + .link_nodes = { &ebi_disp }, }; static struct qcom_icc_node qnm_mdp_disp = { .name = "qnm_mdp_disp", - .id = SM8450_MASTER_MDP_DISP, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_MNOC_HF_MEM_NOC_DISP }, + .link_nodes = { &qns_mem_noc_hf_disp }, }; static struct qcom_icc_node qnm_rot_disp = { .name = "qnm_rot_disp", - .id = SM8450_MASTER_ROTATOR_DISP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC_DISP }, + .link_nodes = { &qns_mem_noc_sf_disp }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SM8450_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8450_MASTER_A1NOC_SNOC }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node srvc_aggre1_noc = { .name = "srvc_aggre1_noc", - .id = SM8450_SLAVE_SERVICE_A1NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SM8450_SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8450_MASTER_A2NOC_SNOC }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node srvc_aggre2_noc = { .name = "srvc_aggre2_noc", - .id = SM8450_SLAVE_SERVICE_A2NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", - .id = SM8450_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup1_core_slave = { .name = "qup1_core_slave", - .id = SM8450_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup2_core_slave = { .name = "qup2_core_slave", - .id = SM8450_SLAVE_QUP_CORE_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", - .id = SM8450_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy1 = { .name = "qhs_ahb2phy1", - .id = SM8450_SLAVE_AHB2PHY_NORTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SM8450_SLAVE_AOSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SM8450_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SM8450_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_compute_cfg = { .name = "qhs_compute_cfg", - .id = SM8450_SLAVE_CDSP_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { MASTER_CDSP_NOC_CFG }, + .link_nodes = { MASTER_CDSP_NOC_CFG }, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SM8450_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mmcx = { .name = "qhs_cpr_mmcx", - .id = SM8450_SLAVE_RBCPR_MMCX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mxa = { .name = "qhs_cpr_mxa", - .id = SM8450_SLAVE_RBCPR_MXA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mxc = { .name = "qhs_cpr_mxc", - .id = SM8450_SLAVE_RBCPR_MXC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SM8450_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cx_rdpm = { .name = "qhs_cx_rdpm", - .id = SM8450_SLAVE_CX_RDPM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SM8450_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SM8450_SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SM8450_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SM8450_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", - .id = SM8450_SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_cfg = { .name = "qhs_lpass_cfg", - .id = SM8450_SLAVE_LPASS, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { MASTER_CNOC_LPASS_AG_NOC }, + .link_nodes = { MASTER_CNOC_LPASS_AG_NOC }, }; static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", - .id = SM8450_SLAVE_CNOC_MSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mx_rdpm = { .name = "qhs_mx_rdpm", - .id = SM8450_SLAVE_MX_RDPM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = SM8450_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie1_cfg = { .name = "qhs_pcie1_cfg", - .id = SM8450_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SM8450_SLAVE_PDM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SM8450_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SM8450_SLAVE_PRNG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SM8450_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = SM8450_SLAVE_QSPI_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", - .id = SM8450_SLAVE_QUP_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = SM8450_SLAVE_QUP_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup2 = { .name = "qhs_qup2", - .id = SM8450_SLAVE_QUP_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SM8450_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SM8450_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_spss_cfg = { .name = "qhs_spss_cfg", - .id = SM8450_SLAVE_SPSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SM8450_SLAVE_TCSR, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = SM8450_SLAVE_TLMM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tme_cfg = { .name = "qhs_tme_cfg", - .id = SM8450_SLAVE_TME_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SM8450_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SM8450_SLAVE_USB3_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SM8450_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SM8450_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_a1_noc_cfg = { .name = "qns_a1_noc_cfg", - .id = SM8450_SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_MASTER_A1NOC_CFG }, + .link_nodes = { &qnm_a1noc_cfg }, }; static struct qcom_icc_node qns_a2_noc_cfg = { .name = "qns_a2_noc_cfg", - .id = SM8450_SLAVE_A2NOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_MASTER_A2NOC_CFG }, + .link_nodes = { &qnm_a2noc_cfg }, }; static struct qcom_icc_node qns_ddrss_cfg = { .name = "qns_ddrss_cfg", - .id = SM8450_SLAVE_DDRSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 1, //FIXME where is link }; static struct qcom_icc_node qns_mnoc_cfg = { .name = "qns_mnoc_cfg", - .id = SM8450_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qnm_mnoc_cfg }, }; static struct qcom_icc_node qns_pcie_anoc_cfg = { .name = "qns_pcie_anoc_cfg", - .id = SM8450_SLAVE_PCIE_ANOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_MASTER_PCIE_ANOC_CFG }, + .link_nodes = { &qnm_pcie_anoc_cfg }, }; static struct qcom_icc_node qns_snoc_cfg = { .name = "qns_snoc_cfg", - .id = SM8450_SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8450_MASTER_SNOC_CFG }, + .link_nodes = { &qnm_snoc_cfg }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SM8450_SLAVE_IMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qxs_pimem = { .name = "qxs_pimem", - .id = SM8450_SLAVE_PIMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node srvc_cnoc = { .name = "srvc_cnoc", - .id = SM8450_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_0 = { .name = "xs_pcie_0", - .id = SM8450_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_1 = { .name = "xs_pcie_1", - .id = SM8450_SLAVE_PCIE_1, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SM8450_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SM8450_SLAVE_TCU, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qns_gem_noc_cnoc = { .name = "qns_gem_noc_cnoc", - .id = SM8450_SLAVE_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8450_MASTER_GEM_NOC_CNOC }, + .link_nodes = { &qnm_gemnoc_cnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SM8450_SLAVE_LLCC, .channels = 4, .buswidth = 16, .num_links = 1, - .links = { SM8450_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_pcie = { .name = "qns_pcie", - .id = SM8450_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node qhs_lpass_core = { .name = "qhs_lpass_core", - .id = SM8450_SLAVE_LPASS_CORE_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_lpi = { .name = "qhs_lpass_lpi", - .id = SM8450_SLAVE_LPASS_LPI_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_mpu = { .name = "qhs_lpass_mpu", - .id = SM8450_SLAVE_LPASS_MPU_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_lpass_top = { .name = "qhs_lpass_top", - .id = SM8450_SLAVE_LPASS_TOP_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_sysnoc = { .name = "qns_sysnoc", - .id = SM8450_SLAVE_LPASS_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8450_MASTER_LPASS_ANOC }, + .link_nodes = { &qnm_lpass_noc }, }; static struct qcom_icc_node srvc_niu_aml_noc = { .name = "srvc_niu_aml_noc", - .id = SM8450_SLAVE_SERVICES_LPASS_AML_NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node srvc_niu_lpass_agnoc = { .name = "srvc_niu_lpass_agnoc", - .id = SM8450_SLAVE_SERVICE_LPASS_AG_NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SM8450_SLAVE_EBI1, .channels = 4, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SM8450_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", - .id = SM8450_SLAVE_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SM8450_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_nsp_gemnoc = { .name = "qns_nsp_gemnoc", - .id = SM8450_SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_nsp_gemnoc }, }; static struct qcom_icc_node service_nsp_noc = { .name = "service_nsp_noc", - .id = SM8450_SLAVE_SERVICE_NSP_NOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_pcie_mem_noc = { .name = "qns_pcie_mem_noc", - .id = SM8450_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8450_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node srvc_pcie_aggre_noc = { .name = "srvc_pcie_aggre_noc", - .id = SM8450_SLAVE_SERVICE_PCIE_ANOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = SM8450_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8450_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SM8450_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8450_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node srvc_snoc = { .name = "srvc_snoc", - .id = SM8450_SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_llcc_disp = { .name = "qns_llcc_disp", - .id = SM8450_SLAVE_LLCC_DISP, .channels = 4, .buswidth = 16, .num_links = 1, - .links = { SM8450_MASTER_LLCC_DISP }, + .link_nodes = { &llcc_mc_disp }, }; static struct qcom_icc_node ebi_disp = { .name = "ebi_disp", - .id = SM8450_SLAVE_EBI1_DISP, .channels = 4, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_mem_noc_hf_disp = { .name = "qns_mem_noc_hf_disp", - .id = SM8450_SLAVE_MNOC_HF_MEM_NOC_DISP, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_MASTER_MNOC_HF_MEM_NOC_DISP }, + .link_nodes = { &qnm_mnoc_hf_disp }, }; static struct qcom_icc_node qns_mem_noc_sf_disp = { .name = "qns_mem_noc_sf_disp", - .id = SM8450_SLAVE_MNOC_SF_MEM_NOC_DISP, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8450_MASTER_MNOC_SF_MEM_NOC_DISP }, + .link_nodes = { &qnm_mnoc_sf_disp }, }; static struct qcom_icc_bcm bcm_acv = { @@ -1884,7 +1821,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove_new = qcom_icc_rpmh_remove, + .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sm8450", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sm8450.h b/drivers/interconnect/qcom/sm8450.h deleted file mode 100644 index a5790ec6767b..000000000000 --- a/drivers/interconnect/qcom/sm8450.h +++ /dev/null @@ -1,169 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * SM8450 interconnect IDs - * - * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2021, Linaro Limited - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8450_H -#define __DRIVERS_INTERCONNECT_QCOM_SM8450_H - -#define SM8450_MASTER_GPU_TCU 0 -#define SM8450_MASTER_SYS_TCU 1 -#define SM8450_MASTER_APPSS_PROC 2 -#define SM8450_MASTER_LLCC 3 -#define SM8450_MASTER_CNOC_LPASS_AG_NOC 4 -#define SM8450_MASTER_GIC_AHB 5 -#define SM8450_MASTER_CDSP_NOC_CFG 6 -#define SM8450_MASTER_QDSS_BAM 7 -#define SM8450_MASTER_QSPI_0 8 -#define SM8450_MASTER_QUP_0 9 -#define SM8450_MASTER_QUP_1 10 -#define SM8450_MASTER_QUP_2 11 -#define SM8450_MASTER_A1NOC_CFG 12 -#define SM8450_MASTER_A2NOC_CFG 13 -#define SM8450_MASTER_A1NOC_SNOC 14 -#define SM8450_MASTER_A2NOC_SNOC 15 -#define SM8450_MASTER_CAMNOC_HF 16 -#define SM8450_MASTER_CAMNOC_ICP 17 -#define SM8450_MASTER_CAMNOC_SF 18 -#define SM8450_MASTER_GEM_NOC_CNOC 19 -#define SM8450_MASTER_GEM_NOC_PCIE_SNOC 20 -#define SM8450_MASTER_GFX3D 21 -#define SM8450_MASTER_LPASS_ANOC 22 -#define SM8450_MASTER_MDP 23 -#define SM8450_MASTER_MDP0 SM8450_MASTER_MDP -#define SM8450_MASTER_MDP1 SM8450_MASTER_MDP -#define SM8450_MASTER_MSS_PROC 24 -#define SM8450_MASTER_CNOC_MNOC_CFG 25 -#define SM8450_MASTER_MNOC_HF_MEM_NOC 26 -#define SM8450_MASTER_MNOC_SF_MEM_NOC 27 -#define SM8450_MASTER_COMPUTE_NOC 28 -#define SM8450_MASTER_ANOC_PCIE_GEM_NOC 29 -#define SM8450_MASTER_PCIE_ANOC_CFG 30 -#define SM8450_MASTER_ROTATOR 31 -#define SM8450_MASTER_SNOC_CFG 32 -#define SM8450_MASTER_SNOC_GC_MEM_NOC 33 -#define SM8450_MASTER_SNOC_SF_MEM_NOC 34 -#define SM8450_MASTER_CDSP_HCP 35 -#define SM8450_MASTER_VIDEO 36 -#define SM8450_MASTER_VIDEO_P0 SM8450_MASTER_VIDEO -#define SM8450_MASTER_VIDEO_P1 SM8450_MASTER_VIDEO -#define SM8450_MASTER_VIDEO_CV_PROC 37 -#define SM8450_MASTER_VIDEO_PROC 38 -#define SM8450_MASTER_VIDEO_V_PROC 39 -#define SM8450_MASTER_QUP_CORE_0 40 -#define SM8450_MASTER_QUP_CORE_1 41 -#define SM8450_MASTER_QUP_CORE_2 42 -#define SM8450_MASTER_CRYPTO 43 -#define SM8450_MASTER_IPA 44 -#define SM8450_MASTER_LPASS_PROC 45 -#define SM8450_MASTER_CDSP_PROC 46 -#define SM8450_MASTER_PIMEM 47 -#define SM8450_MASTER_SENSORS_PROC 48 -#define SM8450_MASTER_SP 49 -#define SM8450_MASTER_GIC 50 -#define SM8450_MASTER_PCIE_0 51 -#define SM8450_MASTER_PCIE_1 52 -#define SM8450_MASTER_QDSS_ETR 53 -#define SM8450_MASTER_QDSS_ETR_1 54 -#define SM8450_MASTER_SDCC_2 55 -#define SM8450_MASTER_SDCC_4 56 -#define SM8450_MASTER_UFS_MEM 57 -#define SM8450_MASTER_USB3_0 58 -#define SM8450_SLAVE_EBI1 512 -#define SM8450_SLAVE_AHB2PHY_SOUTH 513 -#define SM8450_SLAVE_AHB2PHY_NORTH 514 -#define SM8450_SLAVE_AOSS 515 -#define SM8450_SLAVE_CAMERA_CFG 516 -#define SM8450_SLAVE_CLK_CTL 517 -#define SM8450_SLAVE_CDSP_CFG 518 -#define SM8450_SLAVE_RBCPR_CX_CFG 519 -#define SM8450_SLAVE_RBCPR_MMCX_CFG 520 -#define SM8450_SLAVE_RBCPR_MXA_CFG 521 -#define SM8450_SLAVE_RBCPR_MXC_CFG 522 -#define SM8450_SLAVE_CRYPTO_0_CFG 523 -#define SM8450_SLAVE_CX_RDPM 524 -#define SM8450_SLAVE_DISPLAY_CFG 525 -#define SM8450_SLAVE_GFX3D_CFG 526 -#define SM8450_SLAVE_IMEM_CFG 527 -#define SM8450_SLAVE_IPA_CFG 528 -#define SM8450_SLAVE_IPC_ROUTER_CFG 529 -#define SM8450_SLAVE_LPASS 530 -#define SM8450_SLAVE_LPASS_CORE_CFG 531 -#define SM8450_SLAVE_LPASS_LPI_CFG 532 -#define SM8450_SLAVE_LPASS_MPU_CFG 533 -#define SM8450_SLAVE_LPASS_TOP_CFG 534 -#define SM8450_SLAVE_CNOC_MSS 535 -#define SM8450_SLAVE_MX_RDPM 536 -#define SM8450_SLAVE_PCIE_0_CFG 537 -#define SM8450_SLAVE_PCIE_1_CFG 538 -#define SM8450_SLAVE_PDM 539 -#define SM8450_SLAVE_PIMEM_CFG 540 -#define SM8450_SLAVE_PRNG 541 -#define SM8450_SLAVE_QDSS_CFG 542 -#define SM8450_SLAVE_QSPI_0 543 -#define SM8450_SLAVE_QUP_0 544 -#define SM8450_SLAVE_QUP_1 545 -#define SM8450_SLAVE_QUP_2 546 -#define SM8450_SLAVE_SDCC_2 547 -#define SM8450_SLAVE_SDCC_4 548 -#define SM8450_SLAVE_SPSS_CFG 549 -#define SM8450_SLAVE_TCSR 550 -#define SM8450_SLAVE_TLMM 551 -#define SM8450_SLAVE_TME_CFG 552 -#define SM8450_SLAVE_UFS_MEM_CFG 553 -#define SM8450_SLAVE_USB3_0 554 -#define SM8450_SLAVE_VENUS_CFG 555 -#define SM8450_SLAVE_VSENSE_CTRL_CFG 556 -#define SM8450_SLAVE_A1NOC_CFG 557 -#define SM8450_SLAVE_A1NOC_SNOC 558 -#define SM8450_SLAVE_A2NOC_CFG 559 -#define SM8450_SLAVE_A2NOC_SNOC 560 -#define SM8450_SLAVE_DDRSS_CFG 561 -#define SM8450_SLAVE_GEM_NOC_CNOC 562 -#define SM8450_SLAVE_SNOC_GEM_NOC_GC 563 -#define SM8450_SLAVE_SNOC_GEM_NOC_SF 564 -#define SM8450_SLAVE_LLCC 565 -#define SM8450_SLAVE_MNOC_HF_MEM_NOC 566 -#define SM8450_SLAVE_MNOC_SF_MEM_NOC 567 -#define SM8450_SLAVE_CNOC_MNOC_CFG 568 -#define SM8450_SLAVE_CDSP_MEM_NOC 569 -#define SM8450_SLAVE_MEM_NOC_PCIE_SNOC 570 -#define SM8450_SLAVE_PCIE_ANOC_CFG 571 -#define SM8450_SLAVE_ANOC_PCIE_GEM_NOC 572 -#define SM8450_SLAVE_SNOC_CFG 573 -#define SM8450_SLAVE_LPASS_SNOC 574 -#define SM8450_SLAVE_QUP_CORE_0 575 -#define SM8450_SLAVE_QUP_CORE_1 576 -#define SM8450_SLAVE_QUP_CORE_2 577 -#define SM8450_SLAVE_IMEM 578 -#define SM8450_SLAVE_PIMEM 579 -#define SM8450_SLAVE_SERVICE_NSP_NOC 580 -#define SM8450_SLAVE_SERVICE_A1NOC 581 -#define SM8450_SLAVE_SERVICE_A2NOC 582 -#define SM8450_SLAVE_SERVICE_CNOC 583 -#define SM8450_SLAVE_SERVICE_MNOC 584 -#define SM8450_SLAVE_SERVICES_LPASS_AML_NOC 585 -#define SM8450_SLAVE_SERVICE_LPASS_AG_NOC 586 -#define SM8450_SLAVE_SERVICE_PCIE_ANOC 587 -#define SM8450_SLAVE_SERVICE_SNOC 588 -#define SM8450_SLAVE_PCIE_0 589 -#define SM8450_SLAVE_PCIE_1 590 -#define SM8450_SLAVE_QDSS_STM 591 -#define SM8450_SLAVE_TCU 592 -#define SM8450_MASTER_LLCC_DISP 1000 -#define SM8450_MASTER_MDP_DISP 1001 -#define SM8450_MASTER_MDP0_DISP SM8450_MASTER_MDP_DISP -#define SM8450_MASTER_MDP1_DISP SM8450_MASTER_MDP_DISP -#define SM8450_MASTER_MNOC_HF_MEM_NOC_DISP 1002 -#define SM8450_MASTER_MNOC_SF_MEM_NOC_DISP 1003 -#define SM8450_MASTER_ANOC_PCIE_GEM_NOC_DISP 1004 -#define SM8450_MASTER_ROTATOR_DISP 1005 -#define SM8450_SLAVE_EBI1_DISP 1512 -#define SM8450_SLAVE_LLCC_DISP 1513 -#define SM8450_SLAVE_MNOC_HF_MEM_NOC_DISP 1514 -#define SM8450_SLAVE_MNOC_SF_MEM_NOC_DISP 1515 - -#endif diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom/sm8550.c index 4d0e6fa9e003..d01762e13272 100644 --- a/drivers/interconnect/qcom/sm8550.c +++ b/drivers/interconnect/qcom/sm8550.c @@ -18,1103 +18,1048 @@ #include "bcm-voter.h" #include "icc-common.h" #include "icc-rpmh.h" -#include "sm8550.h" + +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node qxm_sp; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup2_core_master; +static struct qcom_icc_node qsm_cfg; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_lpass_gemnoc; +static struct qcom_icc_node qnm_mdsp; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_nsp_gemnoc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qnm_lpiaon_noc; +static struct qcom_icc_node qnm_lpass_lpinoc; +static struct qcom_icc_node qxm_lpinoc_dsp_axim; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_mdp; +static struct qcom_icc_node qnm_vapss_hcp; +static struct qcom_icc_node qnm_video; +static struct qcom_icc_node qnm_video_cv_cpu; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qnm_video_v_cpu; +static struct qcom_icc_node qsm_mnoc_cfg; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node qsm_pcie_anoc_cfg; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node qhm_gic; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup2_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_apss; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mxa; +static struct qcom_icc_node qhs_cpr_mxc; +static struct qcom_icc_node qhs_cpr_nspcx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_i2c; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_pimem_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qss_lpass_qtb_cfg; +static struct qcom_icc_node qss_mnoc_cfg; +static struct qcom_icc_node qss_nsp_qtb_cfg; +static struct qcom_icc_node qss_pcie_anoc_cfg; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qss_cfg; +static struct qcom_icc_node qss_ddrss_cfg; +static struct qcom_icc_node qxs_boot_imem; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc; +static struct qcom_icc_node qns_lpass_aggnoc; +static struct qcom_icc_node qns_lpi_aon_noc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_pcie_aggre_noc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = SM8550_MASTER_QSPI_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = SM8550_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SM8550_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SM8550_MASTER_UFS_MEM, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SM8550_MASTER_USB3_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SM8550_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", - .id = SM8550_MASTER_QUP_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SM8550_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SM8550_MASTER_IPA, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_sp = { .name = "qxm_sp", - .id = SM8550_MASTER_SP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr_0 = { .name = "xm_qdss_etr_0", - .id = SM8550_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr_1 = { .name = "xm_qdss_etr_1", - .id = SM8550_MASTER_QDSS_ETR_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SM8550_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", - .id = SM8550_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { .name = "qup1_core_master", - .id = SM8550_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_SLAVE_QUP_CORE_1 }, + .link_nodes = { &qup1_core_slave }, }; static struct qcom_icc_node qup2_core_master = { .name = "qup2_core_master", - .id = SM8550_MASTER_QUP_CORE_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_SLAVE_QUP_CORE_2 }, + .link_nodes = { &qup2_core_slave }, }; static struct qcom_icc_node qsm_cfg = { .name = "qsm_cfg", - .id = SM8550_MASTER_CNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 44, - .links = { SM8550_SLAVE_AHB2PHY_SOUTH, SM8550_SLAVE_AHB2PHY_NORTH, - SM8550_SLAVE_APPSS, SM8550_SLAVE_CAMERA_CFG, - SM8550_SLAVE_CLK_CTL, SM8550_SLAVE_RBCPR_CX_CFG, - SM8550_SLAVE_RBCPR_MMCX_CFG, SM8550_SLAVE_RBCPR_MXA_CFG, - SM8550_SLAVE_RBCPR_MXC_CFG, SM8550_SLAVE_CPR_NSPCX, - SM8550_SLAVE_CRYPTO_0_CFG, SM8550_SLAVE_CX_RDPM, - SM8550_SLAVE_DISPLAY_CFG, SM8550_SLAVE_GFX3D_CFG, - SM8550_SLAVE_I2C, SM8550_SLAVE_IMEM_CFG, - SM8550_SLAVE_IPA_CFG, SM8550_SLAVE_IPC_ROUTER_CFG, - SM8550_SLAVE_CNOC_MSS, SM8550_SLAVE_MX_RDPM, - SM8550_SLAVE_PCIE_0_CFG, SM8550_SLAVE_PCIE_1_CFG, - SM8550_SLAVE_PDM, SM8550_SLAVE_PIMEM_CFG, - SM8550_SLAVE_PRNG, SM8550_SLAVE_QDSS_CFG, - SM8550_SLAVE_QSPI_0, SM8550_SLAVE_QUP_1, - SM8550_SLAVE_QUP_2, SM8550_SLAVE_SDCC_2, - SM8550_SLAVE_SDCC_4, SM8550_SLAVE_SPSS_CFG, - SM8550_SLAVE_TCSR, SM8550_SLAVE_TLMM, - SM8550_SLAVE_UFS_MEM_CFG, SM8550_SLAVE_USB3_0, - SM8550_SLAVE_VENUS_CFG, SM8550_SLAVE_VSENSE_CTRL_CFG, - SM8550_SLAVE_LPASS_QTB_CFG, SM8550_SLAVE_CNOC_MNOC_CFG, - SM8550_SLAVE_NSP_QTB_CFG, SM8550_SLAVE_PCIE_ANOC_CFG, - SM8550_SLAVE_QDSS_STM, SM8550_SLAVE_TCU }, + .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_apss, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_cpr_cx, + &qhs_cpr_mmcx, &qhs_cpr_mxa, + &qhs_cpr_mxc, &qhs_cpr_nspcx, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_i2c, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_mss_cfg, &qhs_mx_rdpm, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pdm, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup1, + &qhs_qup2, &qhs_sdc2, + &qhs_sdc4, &qhs_spss_cfg, + &qhs_tcsr, &qhs_tlmm, + &qhs_ufs_mem_cfg, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qss_lpass_qtb_cfg, &qss_mnoc_cfg, + &qss_nsp_qtb_cfg, &qss_pcie_anoc_cfg, + &xs_qdss_stm, &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", - .id = SM8550_MASTER_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 6, - .links = { SM8550_SLAVE_AOSS, SM8550_SLAVE_TME_CFG, - SM8550_SLAVE_CNOC_CFG, SM8550_SLAVE_DDRSS_CFG, - SM8550_SLAVE_BOOT_IMEM, SM8550_SLAVE_IMEM }, + .link_nodes = { &qhs_aoss, &qhs_tme_cfg, + &qss_cfg, &qss_ddrss_cfg, + &qxs_boot_imem, &qxs_imem }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = SM8550_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8550_SLAVE_PCIE_0, SM8550_SLAVE_PCIE_1 }, + .link_nodes = { &xs_pcie_0, &xs_pcie_1 }, }; static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", - .id = SM8550_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", - .id = SM8550_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", - .id = SM8550_MASTER_APPSS_PROC, .channels = 3, .buswidth = 32, .num_links = 3, - .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC, - SM8550_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", - .id = SM8550_MASTER_GFX3D, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_lpass_gemnoc = { .name = "qnm_lpass_gemnoc", - .id = SM8550_MASTER_LPASS_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC, - SM8550_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_mdsp = { .name = "qnm_mdsp", - .id = SM8550_MASTER_MSS_PROC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC, - SM8550_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SM8550_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SM8550_MASTER_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_nsp_gemnoc = { .name = "qnm_nsp_gemnoc", - .id = SM8550_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = SM8550_MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_gc = { .name = "qnm_snoc_gc", - .id = SM8550_MASTER_SNOC_GC_MEM_NOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SM8550_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SM8550_SLAVE_GEM_NOC_CNOC, SM8550_SLAVE_LLCC, - SM8550_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_lpiaon_noc = { .name = "qnm_lpiaon_noc", - .id = SM8550_MASTER_LPIAON_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_SLAVE_LPASS_GEM_NOC }, + .link_nodes = { &qns_lpass_ag_noc_gemnoc }, }; static struct qcom_icc_node qnm_lpass_lpinoc = { .name = "qnm_lpass_lpinoc", - .id = SM8550_MASTER_LPASS_LPINOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC }, + .link_nodes = { &qns_lpass_aggnoc }, }; static struct qcom_icc_node qxm_lpinoc_dsp_axim = { .name = "qxm_lpinoc_dsp_axim", - .id = SM8550_MASTER_LPASS_PROC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_SLAVE_LPICX_NOC_LPIAON_NOC }, + .link_nodes = { &qns_lpi_aon_noc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SM8550_MASTER_LLCC, .channels = 4, .buswidth = 4, .num_links = 1, - .links = { SM8550_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qnm_camnoc_hf = { .name = "qnm_camnoc_hf", - .id = SM8550_MASTER_CAMNOC_HF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8550_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_camnoc_icp = { .name = "qnm_camnoc_icp", - .id = SM8550_MASTER_CAMNOC_ICP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_camnoc_sf = { .name = "qnm_camnoc_sf", - .id = SM8550_MASTER_CAMNOC_SF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_mdp = { .name = "qnm_mdp", - .id = SM8550_MASTER_MDP, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8550_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_vapss_hcp = { .name = "qnm_vapss_hcp", - .id = SM8550_MASTER_CDSP_HCP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video = { .name = "qnm_video", - .id = SM8550_MASTER_VIDEO, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_cv_cpu = { .name = "qnm_video_cv_cpu", - .id = SM8550_MASTER_VIDEO_CV_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_cvp = { .name = "qnm_video_cvp", - .id = SM8550_MASTER_VIDEO_PROC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_v_cpu = { .name = "qnm_video_v_cpu", - .id = SM8550_MASTER_VIDEO_V_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qsm_mnoc_cfg = { .name = "qsm_mnoc_cfg", - .id = SM8550_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qxm_nsp = { .name = "qxm_nsp", - .id = SM8550_MASTER_CDSP_PROC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8550_SLAVE_CDSP_MEM_NOC }, + .link_nodes = { &qns_nsp_gemnoc }, }; static struct qcom_icc_node qsm_pcie_anoc_cfg = { .name = "qsm_pcie_anoc_cfg", - .id = SM8550_MASTER_PCIE_ANOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_SLAVE_SERVICE_PCIE_ANOC }, + .link_nodes = { &srvc_pcie_aggre_noc }, }; static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", - .id = SM8550_MASTER_PCIE_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", - .id = SM8550_MASTER_PCIE_1, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node qhm_gic = { .name = "qhm_gic", - .id = SM8550_MASTER_GIC_AHB, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SM8550_MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SM8550_MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SM8550_MASTER_GIC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_SLAVE_SNOC_GEM_NOC_GC }, + .link_nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SM8550_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_MASTER_A1NOC_SNOC }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SM8550_SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_MASTER_A2NOC_SNOC }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", - .id = SM8550_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup1_core_slave = { .name = "qup1_core_slave", - .id = SM8550_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup2_core_slave = { .name = "qup2_core_slave", - .id = SM8550_SLAVE_QUP_CORE_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", - .id = SM8550_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy1 = { .name = "qhs_ahb2phy1", - .id = SM8550_SLAVE_AHB2PHY_NORTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_apss = { .name = "qhs_apss", - .id = SM8550_SLAVE_APPSS, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SM8550_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SM8550_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SM8550_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mmcx = { .name = "qhs_cpr_mmcx", - .id = SM8550_SLAVE_RBCPR_MMCX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mxa = { .name = "qhs_cpr_mxa", - .id = SM8550_SLAVE_RBCPR_MXA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mxc = { .name = "qhs_cpr_mxc", - .id = SM8550_SLAVE_RBCPR_MXC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_nspcx = { .name = "qhs_cpr_nspcx", - .id = SM8550_SLAVE_CPR_NSPCX, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SM8550_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cx_rdpm = { .name = "qhs_cx_rdpm", - .id = SM8550_SLAVE_CX_RDPM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SM8550_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SM8550_SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_i2c = { .name = "qhs_i2c", - .id = SM8550_SLAVE_I2C, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SM8550_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SM8550_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", - .id = SM8550_SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", - .id = SM8550_SLAVE_CNOC_MSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mx_rdpm = { .name = "qhs_mx_rdpm", - .id = SM8550_SLAVE_MX_RDPM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = SM8550_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie1_cfg = { .name = "qhs_pcie1_cfg", - .id = SM8550_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SM8550_SLAVE_PDM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pimem_cfg = { .name = "qhs_pimem_cfg", - .id = SM8550_SLAVE_PIMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SM8550_SLAVE_PRNG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SM8550_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = SM8550_SLAVE_QSPI_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = SM8550_SLAVE_QUP_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup2 = { .name = "qhs_qup2", - .id = SM8550_SLAVE_QUP_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SM8550_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SM8550_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_spss_cfg = { .name = "qhs_spss_cfg", - .id = SM8550_SLAVE_SPSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SM8550_SLAVE_TCSR, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = SM8550_SLAVE_TLMM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SM8550_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SM8550_SLAVE_USB3_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SM8550_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SM8550_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qss_lpass_qtb_cfg = { .name = "qss_lpass_qtb_cfg", - .id = SM8550_SLAVE_LPASS_QTB_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qss_mnoc_cfg = { .name = "qss_mnoc_cfg", - .id = SM8550_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qsm_mnoc_cfg }, }; static struct qcom_icc_node qss_nsp_qtb_cfg = { .name = "qss_nsp_qtb_cfg", - .id = SM8550_SLAVE_NSP_QTB_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qss_pcie_anoc_cfg = { .name = "qss_pcie_anoc_cfg", - .id = SM8550_SLAVE_PCIE_ANOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_MASTER_PCIE_ANOC_CFG }, + .link_nodes = { &qsm_pcie_anoc_cfg }, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SM8550_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SM8550_SLAVE_TCU, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SM8550_SLAVE_AOSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tme_cfg = { .name = "qhs_tme_cfg", - .id = SM8550_SLAVE_TME_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qss_cfg = { .name = "qss_cfg", - .id = SM8550_SLAVE_CNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8550_MASTER_CNOC_CFG }, + .link_nodes = { &qsm_cfg }, }; static struct qcom_icc_node qss_ddrss_cfg = { .name = "qss_ddrss_cfg", - .id = SM8550_SLAVE_DDRSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qxs_boot_imem = { .name = "qxs_boot_imem", - .id = SM8550_SLAVE_BOOT_IMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SM8550_SLAVE_IMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_0 = { .name = "xs_pcie_0", - .id = SM8550_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_1 = { .name = "xs_pcie_1", - .id = SM8550_SLAVE_PCIE_1, .channels = 1, .buswidth = 16, - .num_links = 0, }; static struct qcom_icc_node qns_gem_noc_cnoc = { .name = "qns_gem_noc_cnoc", - .id = SM8550_SLAVE_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_MASTER_GEM_NOC_CNOC }, + .link_nodes = { &qnm_gemnoc_cnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SM8550_SLAVE_LLCC, .channels = 4, .buswidth = 16, .num_links = 1, - .links = { SM8550_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_pcie = { .name = "qns_pcie", - .id = SM8550_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { .name = "qns_lpass_ag_noc_gemnoc", - .id = SM8550_SLAVE_LPASS_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_MASTER_LPASS_GEM_NOC }, + .link_nodes = { &qnm_lpass_gemnoc }, }; static struct qcom_icc_node qns_lpass_aggnoc = { .name = "qns_lpass_aggnoc", - .id = SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_MASTER_LPIAON_NOC }, + .link_nodes = { &qnm_lpiaon_noc }, }; static struct qcom_icc_node qns_lpi_aon_noc = { .name = "qns_lpi_aon_noc", - .id = SM8550_SLAVE_LPICX_NOC_LPIAON_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_MASTER_LPASS_LPINOC }, + .link_nodes = { &qnm_lpass_lpinoc }, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SM8550_SLAVE_EBI1, .channels = 4, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SM8550_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8550_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", - .id = SM8550_SLAVE_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8550_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SM8550_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_nsp_gemnoc = { .name = "qns_nsp_gemnoc", - .id = SM8550_SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8550_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_nsp_gemnoc }, }; static struct qcom_icc_node qns_pcie_mem_noc = { .name = "qns_pcie_mem_noc", - .id = SM8550_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node srvc_pcie_aggre_noc = { .name = "srvc_pcie_aggre_noc", - .id = SM8550_SLAVE_SERVICE_PCIE_ANOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_gemnoc_gc = { .name = "qns_gemnoc_gc", - .id = SM8550_SLAVE_SNOC_GEM_NOC_GC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8550_MASTER_SNOC_GC_MEM_NOC }, + .link_nodes = { &qnm_snoc_gc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SM8550_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8550_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_bcm bcm_acv = { @@ -1645,7 +1590,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove_new = qcom_icc_rpmh_remove, + .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sm8550", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sm8550.h b/drivers/interconnect/qcom/sm8550.h deleted file mode 100644 index c9b2986e1293..000000000000 --- a/drivers/interconnect/qcom/sm8550.h +++ /dev/null @@ -1,138 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * SM8450 interconnect IDs - * - * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2021, Linaro Limited - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8450_H -#define __DRIVERS_INTERCONNECT_QCOM_SM8450_H - -#define SM8550_MASTER_A1NOC_SNOC 0 -#define SM8550_MASTER_A2NOC_SNOC 1 -#define SM8550_MASTER_ANOC_PCIE_GEM_NOC 2 -#define SM8550_MASTER_APPSS_PROC 3 -#define SM8550_MASTER_CAMNOC_HF 4 -#define SM8550_MASTER_CAMNOC_ICP 5 -#define SM8550_MASTER_CAMNOC_SF 6 -#define SM8550_MASTER_CDSP_HCP 7 -#define SM8550_MASTER_CDSP_PROC 8 -#define SM8550_MASTER_CNOC_CFG 9 -#define SM8550_MASTER_CNOC_MNOC_CFG 10 -#define SM8550_MASTER_COMPUTE_NOC 11 -#define SM8550_MASTER_CRYPTO 12 -#define SM8550_MASTER_GEM_NOC_CNOC 13 -#define SM8550_MASTER_GEM_NOC_PCIE_SNOC 14 -#define SM8550_MASTER_GFX3D 15 -#define SM8550_MASTER_GIC 16 -#define SM8550_MASTER_GIC_AHB 17 -#define SM8550_MASTER_GPU_TCU 18 -#define SM8550_MASTER_IPA 19 -#define SM8550_MASTER_LLCC 20 -#define SM8550_MASTER_LPASS_GEM_NOC 21 -#define SM8550_MASTER_LPASS_LPINOC 22 -#define SM8550_MASTER_LPASS_PROC 23 -#define SM8550_MASTER_LPIAON_NOC 24 -#define SM8550_MASTER_MDP 25 -#define SM8550_MASTER_MNOC_HF_MEM_NOC 26 -#define SM8550_MASTER_MNOC_SF_MEM_NOC 27 -#define SM8550_MASTER_MSS_PROC 28 -#define SM8550_MASTER_PCIE_0 29 -#define SM8550_MASTER_PCIE_1 30 -#define SM8550_MASTER_PCIE_ANOC_CFG 31 -#define SM8550_MASTER_QDSS_BAM 32 -#define SM8550_MASTER_QDSS_ETR 33 -#define SM8550_MASTER_QDSS_ETR_1 34 -#define SM8550_MASTER_QSPI_0 35 -#define SM8550_MASTER_QUP_1 36 -#define SM8550_MASTER_QUP_2 37 -#define SM8550_MASTER_QUP_CORE_0 38 -#define SM8550_MASTER_QUP_CORE_1 39 -#define SM8550_MASTER_QUP_CORE_2 40 -#define SM8550_MASTER_SDCC_2 41 -#define SM8550_MASTER_SDCC_4 42 -#define SM8550_MASTER_SNOC_GC_MEM_NOC 43 -#define SM8550_MASTER_SNOC_SF_MEM_NOC 44 -#define SM8550_MASTER_SP 45 -#define SM8550_MASTER_SYS_TCU 46 -#define SM8550_MASTER_UFS_MEM 47 -#define SM8550_MASTER_USB3_0 48 -#define SM8550_MASTER_VIDEO 49 -#define SM8550_MASTER_VIDEO_CV_PROC 50 -#define SM8550_MASTER_VIDEO_PROC 51 -#define SM8550_MASTER_VIDEO_V_PROC 52 -#define SM8550_SLAVE_A1NOC_SNOC 53 -#define SM8550_SLAVE_A2NOC_SNOC 54 -#define SM8550_SLAVE_AHB2PHY_NORTH 55 -#define SM8550_SLAVE_AHB2PHY_SOUTH 56 -#define SM8550_SLAVE_ANOC_PCIE_GEM_NOC 57 -#define SM8550_SLAVE_AOSS 58 -#define SM8550_SLAVE_APPSS 59 -#define SM8550_SLAVE_BOOT_IMEM 60 -#define SM8550_SLAVE_CAMERA_CFG 61 -#define SM8550_SLAVE_CDSP_MEM_NOC 62 -#define SM8550_SLAVE_CLK_CTL 63 -#define SM8550_SLAVE_CNOC_CFG 64 -#define SM8550_SLAVE_CNOC_MNOC_CFG 65 -#define SM8550_SLAVE_CNOC_MSS 66 -#define SM8550_SLAVE_CPR_NSPCX 67 -#define SM8550_SLAVE_CRYPTO_0_CFG 68 -#define SM8550_SLAVE_CX_RDPM 69 -#define SM8550_SLAVE_DDRSS_CFG 70 -#define SM8550_SLAVE_DISPLAY_CFG 71 -#define SM8550_SLAVE_EBI1 72 -#define SM8550_SLAVE_GEM_NOC_CNOC 73 -#define SM8550_SLAVE_GFX3D_CFG 74 -#define SM8550_SLAVE_I2C 75 -#define SM8550_SLAVE_IMEM 76 -#define SM8550_SLAVE_IMEM_CFG 77 -#define SM8550_SLAVE_IPA_CFG 78 -#define SM8550_SLAVE_IPC_ROUTER_CFG 79 -#define SM8550_SLAVE_LLCC 80 -#define SM8550_SLAVE_LPASS_GEM_NOC 81 -#define SM8550_SLAVE_LPASS_QTB_CFG 82 -#define SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC 83 -#define SM8550_SLAVE_LPICX_NOC_LPIAON_NOC 84 -#define SM8550_SLAVE_MEM_NOC_PCIE_SNOC 85 -#define SM8550_SLAVE_MNOC_HF_MEM_NOC 86 -#define SM8550_SLAVE_MNOC_SF_MEM_NOC 87 -#define SM8550_SLAVE_MX_RDPM 88 -#define SM8550_SLAVE_NSP_QTB_CFG 89 -#define SM8550_SLAVE_PCIE_0 90 -#define SM8550_SLAVE_PCIE_0_CFG 91 -#define SM8550_SLAVE_PCIE_1 92 -#define SM8550_SLAVE_PCIE_1_CFG 93 -#define SM8550_SLAVE_PCIE_ANOC_CFG 94 -#define SM8550_SLAVE_PDM 95 -#define SM8550_SLAVE_PIMEM_CFG 96 -#define SM8550_SLAVE_PRNG 97 -#define SM8550_SLAVE_QDSS_CFG 98 -#define SM8550_SLAVE_QDSS_STM 99 -#define SM8550_SLAVE_QSPI_0 100 -#define SM8550_SLAVE_QUP_1 101 -#define SM8550_SLAVE_QUP_2 102 -#define SM8550_SLAVE_QUP_CORE_0 103 -#define SM8550_SLAVE_QUP_CORE_1 104 -#define SM8550_SLAVE_QUP_CORE_2 105 -#define SM8550_SLAVE_RBCPR_CX_CFG 106 -#define SM8550_SLAVE_RBCPR_MMCX_CFG 107 -#define SM8550_SLAVE_RBCPR_MXA_CFG 108 -#define SM8550_SLAVE_RBCPR_MXC_CFG 109 -#define SM8550_SLAVE_SDCC_2 110 -#define SM8550_SLAVE_SDCC_4 111 -#define SM8550_SLAVE_SERVICE_MNOC 112 -#define SM8550_SLAVE_SERVICE_PCIE_ANOC 113 -#define SM8550_SLAVE_SNOC_GEM_NOC_GC 114 -#define SM8550_SLAVE_SNOC_GEM_NOC_SF 115 -#define SM8550_SLAVE_SPSS_CFG 116 -#define SM8550_SLAVE_TCSR 117 -#define SM8550_SLAVE_TCU 118 -#define SM8550_SLAVE_TLMM 119 -#define SM8550_SLAVE_TME_CFG 120 -#define SM8550_SLAVE_UFS_MEM_CFG 121 -#define SM8550_SLAVE_USB3_0 122 -#define SM8550_SLAVE_VENUS_CFG 123 -#define SM8550_SLAVE_VSENSE_CTRL_CFG 124 - -#endif diff --git a/drivers/interconnect/qcom/sm8650.c b/drivers/interconnect/qcom/sm8650.c index b962e6c233ef..cf3ae734d4c3 100644 --- a/drivers/interconnect/qcom/sm8650.c +++ b/drivers/interconnect/qcom/sm8650.c @@ -15,1147 +15,1417 @@ #include "bcm-voter.h" #include "icc-common.h" #include "icc-rpmh.h" -#include "sm8650.h" + +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qxm_qup02; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node qxm_sp; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup2_core_master; +static struct qcom_icc_node qsm_cfg; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node alm_ubwc_p_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_lpass_gemnoc; +static struct qcom_icc_node qnm_mdsp; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_nsp_gemnoc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qnm_ubwc_p; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qnm_lpiaon_noc; +static struct qcom_icc_node qnm_lpass_lpinoc; +static struct qcom_icc_node qxm_lpinoc_dsp_axim; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_mdp; +static struct qcom_icc_node qnm_vapss_hcp; +static struct qcom_icc_node qnm_video; +static struct qcom_icc_node qnm_video_cv_cpu; +static struct qcom_icc_node qnm_video_cvp; +static struct qcom_icc_node qnm_video_v_cpu; +static struct qcom_icc_node qsm_mnoc_cfg; +static struct qcom_icc_node qnm_nsp; +static struct qcom_icc_node qsm_pcie_anoc_cfg; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_apss_noc; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup2_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_hmx; +static struct qcom_icc_node qhs_cpr_mmcx; +static struct qcom_icc_node qhs_cpr_mxa; +static struct qcom_icc_node qhs_cpr_mxc; +static struct qcom_icc_node qhs_cpr_nspcx; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_i2c; +static struct qcom_icc_node qhs_i3c_ibi0_cfg; +static struct qcom_icc_node qhs_i3c_ibi1_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_mx_2_rdpm; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pcie_rscc; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup02; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qss_mnoc_cfg; +static struct qcom_icc_node qss_nsp_qtb_cfg; +static struct qcom_icc_node qss_pcie_anoc_cfg; +static struct qcom_icc_node srvc_cnoc_cfg; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qss_apss; +static struct qcom_icc_node qss_cfg; +static struct qcom_icc_node qss_ddrss_cfg; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node srvc_cnoc_main; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc; +static struct qcom_icc_node qns_lpass_aggnoc; +static struct qcom_icc_node qns_lpi_aon_noc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_pcie_aggre_noc; +static struct qcom_icc_node qns_gemnoc_sf; +static const struct regmap_config icc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .fast_io = true, +}; + +static struct qcom_icc_qosbox qhm_qspi_qos = { + .num_ports = 1, + .port_offsets = { 0xc000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 0, +}; static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = SM8650_MASTER_QSPI_0, .channels = 1, .buswidth = 4, + .qosbox = &qhm_qspi_qos, .num_links = 1, - .links = { SM8650_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_qosbox qhm_qup1_qos = { + .num_ports = 1, + .port_offsets = { 0xd000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 0, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = SM8650_MASTER_QUP_1, .channels = 1, .buswidth = 4, + .qosbox = &qhm_qup1_qos, .num_links = 1, - .links = { SM8650_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qxm_qup02 = { .name = "qxm_qup02", - .id = SM8650_MASTER_QUP_3, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8650_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_qosbox xm_sdc4_qos = { + .num_ports = 1, + .port_offsets = { 0xe000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 0, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = SM8650_MASTER_SDCC_4, .channels = 1, .buswidth = 8, + .qosbox = &xm_sdc4_qos, .num_links = 1, - .links = { SM8650_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_qosbox xm_ufs_mem_qos = { + .num_ports = 1, + .port_offsets = { 0xf000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 0, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = SM8650_MASTER_UFS_MEM, .channels = 1, .buswidth = 16, + .qosbox = &xm_ufs_mem_qos, .num_links = 1, - .links = { SM8650_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_qosbox xm_usb3_0_qos = { + .num_ports = 1, + .port_offsets = { 0x10000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 0, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = SM8650_MASTER_USB3_0, .channels = 1, .buswidth = 8, + .qosbox = &xm_usb3_0_qos, .num_links = 1, - .links = { SM8650_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_qosbox qhm_qdss_bam_qos = { + .num_ports = 1, + .port_offsets = { 0x12000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 0, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", - .id = SM8650_MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, + .qosbox = &qhm_qdss_bam_qos, .num_links = 1, - .links = { SM8650_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_qosbox qhm_qup2_qos = { + .num_ports = 1, + .port_offsets = { 0x13000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 0, }; static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", - .id = SM8650_MASTER_QUP_2, .channels = 1, .buswidth = 4, + .qosbox = &qhm_qup2_qos, .num_links = 1, - .links = { SM8650_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_qosbox qxm_crypto_qos = { + .num_ports = 1, + .port_offsets = { 0x15000 }, + .prio = 2, + .urg_fwd = 1, + .prio_fwd_disable = 0, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = SM8650_MASTER_CRYPTO, .channels = 1, .buswidth = 8, + .qosbox = &qxm_crypto_qos, .num_links = 1, - .links = { SM8650_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_qosbox qxm_ipa_qos = { + .num_ports = 1, + .port_offsets = { 0x16000 }, + .prio = 2, + .urg_fwd = 1, + .prio_fwd_disable = 0, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", - .id = SM8650_MASTER_IPA, .channels = 1, .buswidth = 8, + .qosbox = &qxm_ipa_qos, .num_links = 1, - .links = { SM8650_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_sp = { .name = "qxm_sp", - .id = SM8650_MASTER_SP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8650_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_qosbox xm_qdss_etr_0_qos = { + .num_ports = 1, + .port_offsets = { 0x17000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 0, }; static struct qcom_icc_node xm_qdss_etr_0 = { .name = "xm_qdss_etr_0", - .id = SM8650_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, + .qosbox = &xm_qdss_etr_0_qos, .num_links = 1, - .links = { SM8650_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_qosbox xm_qdss_etr_1_qos = { + .num_ports = 1, + .port_offsets = { 0x18000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 0, }; static struct qcom_icc_node xm_qdss_etr_1 = { .name = "xm_qdss_etr_1", - .id = SM8650_MASTER_QDSS_ETR_1, .channels = 1, .buswidth = 8, + .qosbox = &xm_qdss_etr_1_qos, .num_links = 1, - .links = { SM8650_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_qosbox xm_sdc2_qos = { + .num_ports = 1, + .port_offsets = { 0x19000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 0, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = SM8650_MASTER_SDCC_2, .channels = 1, .buswidth = 8, + .qosbox = &xm_sdc2_qos, .num_links = 1, - .links = { SM8650_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", - .id = SM8650_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8650_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { .name = "qup1_core_master", - .id = SM8650_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8650_SLAVE_QUP_CORE_1 }, + .link_nodes = { &qup1_core_slave }, }; static struct qcom_icc_node qup2_core_master = { .name = "qup2_core_master", - .id = SM8650_MASTER_QUP_CORE_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8650_SLAVE_QUP_CORE_2 }, + .link_nodes = { &qup2_core_slave }, }; static struct qcom_icc_node qsm_cfg = { .name = "qsm_cfg", - .id = SM8650_MASTER_CNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 46, - .links = { SM8650_SLAVE_AHB2PHY_SOUTH, SM8650_SLAVE_AHB2PHY_NORTH, - SM8650_SLAVE_CAMERA_CFG, SM8650_SLAVE_CLK_CTL, - SM8650_SLAVE_RBCPR_CX_CFG, SM8650_SLAVE_CPR_HMX, - SM8650_SLAVE_RBCPR_MMCX_CFG, SM8650_SLAVE_RBCPR_MXA_CFG, - SM8650_SLAVE_RBCPR_MXC_CFG, SM8650_SLAVE_CPR_NSPCX, - SM8650_SLAVE_CRYPTO_0_CFG, SM8650_SLAVE_CX_RDPM, - SM8650_SLAVE_DISPLAY_CFG, SM8650_SLAVE_GFX3D_CFG, - SM8650_SLAVE_I2C, SM8650_SLAVE_I3C_IBI0_CFG, - SM8650_SLAVE_I3C_IBI1_CFG, SM8650_SLAVE_IMEM_CFG, - SM8650_SLAVE_CNOC_MSS, SM8650_SLAVE_MX_2_RDPM, - SM8650_SLAVE_MX_RDPM, SM8650_SLAVE_PCIE_0_CFG, - SM8650_SLAVE_PCIE_1_CFG, SM8650_SLAVE_PCIE_RSCC, - SM8650_SLAVE_PDM, SM8650_SLAVE_PRNG, - SM8650_SLAVE_QDSS_CFG, SM8650_SLAVE_QSPI_0, - SM8650_SLAVE_QUP_3, SM8650_SLAVE_QUP_1, - SM8650_SLAVE_QUP_2, SM8650_SLAVE_SDCC_2, - SM8650_SLAVE_SDCC_4, SM8650_SLAVE_SPSS_CFG, - SM8650_SLAVE_TCSR, SM8650_SLAVE_TLMM, - SM8650_SLAVE_UFS_MEM_CFG, SM8650_SLAVE_USB3_0, - SM8650_SLAVE_VENUS_CFG, SM8650_SLAVE_VSENSE_CTRL_CFG, - SM8650_SLAVE_CNOC_MNOC_CFG, SM8650_SLAVE_NSP_QTB_CFG, - SM8650_SLAVE_PCIE_ANOC_CFG, SM8650_SLAVE_SERVICE_CNOC_CFG, - SM8650_SLAVE_QDSS_STM, SM8650_SLAVE_TCU }, + .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_cpr_cx, &qhs_cpr_hmx, + &qhs_cpr_mmcx, &qhs_cpr_mxa, + &qhs_cpr_mxc, &qhs_cpr_nspcx, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_i2c, &qhs_i3c_ibi0_cfg, + &qhs_i3c_ibi1_cfg, &qhs_imem_cfg, + &qhs_mss_cfg, &qhs_mx_2_rdpm, + &qhs_mx_rdpm, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_pcie_rscc, + &qhs_pdm, &qhs_prng, + &qhs_qdss_cfg, &qhs_qspi, + &qhs_qup02, &qhs_qup1, + &qhs_qup2, &qhs_sdc2, + &qhs_sdc4, &qhs_spss_cfg, + &qhs_tcsr, &qhs_tlmm, + &qhs_ufs_mem_cfg, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qss_mnoc_cfg, &qss_nsp_qtb_cfg, + &qss_pcie_anoc_cfg, &srvc_cnoc_cfg, + &xs_qdss_stm, &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", - .id = SM8650_MASTER_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 9, - .links = { SM8650_SLAVE_AOSS, SM8650_SLAVE_IPA_CFG, - SM8650_SLAVE_IPC_ROUTER_CFG, SM8650_SLAVE_TME_CFG, - SM8650_SLAVE_APPSS, SM8650_SLAVE_CNOC_CFG, - SM8650_SLAVE_DDRSS_CFG, SM8650_SLAVE_IMEM, - SM8650_SLAVE_SERVICE_CNOC }, + .link_nodes = { &qhs_aoss, &qhs_ipa, + &qhs_ipc_router, &qhs_tme_cfg, + &qss_apss, &qss_cfg, + &qss_ddrss_cfg, &qxs_imem, + &srvc_cnoc_main }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = SM8650_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 16, .num_links = 2, - .links = { SM8650_SLAVE_PCIE_0, SM8650_SLAVE_PCIE_1 }, + .link_nodes = { &xs_pcie_0, &xs_pcie_1 }, +}; + +static struct qcom_icc_qosbox alm_gpu_tcu_qos = { + .num_ports = 1, + .port_offsets = { 0xbf000 }, + .prio = 1, + .urg_fwd = 0, + .prio_fwd_disable = 1, }; static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", - .id = SM8650_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, + .qosbox = &alm_gpu_tcu_qos, .num_links = 2, - .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_qosbox alm_sys_tcu_qos = { + .num_ports = 1, + .port_offsets = { 0xc1000 }, + .prio = 6, + .urg_fwd = 0, + .prio_fwd_disable = 1, }; static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", - .id = SM8650_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, + .qosbox = &alm_sys_tcu_qos, .num_links = 2, - .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_qosbox alm_ubwc_p_tcu_qos = { + .num_ports = 1, + .port_offsets = { 0xc5000 }, + .prio = 1, + .urg_fwd = 0, + .prio_fwd_disable = 1, }; static struct qcom_icc_node alm_ubwc_p_tcu = { .name = "alm_ubwc_p_tcu", - .id = SM8650_MASTER_UBWC_P_TCU, .channels = 1, .buswidth = 8, + .qosbox = &alm_ubwc_p_tcu_qos, .num_links = 2, - .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", - .id = SM8650_MASTER_APPSS_PROC, .channels = 3, .buswidth = 32, .num_links = 3, - .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, - SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_qosbox qnm_gpu_qos = { + .num_ports = 2, + .port_offsets = { 0x31000, 0x71000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 1, }; static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", - .id = SM8650_MASTER_GFX3D, .channels = 2, .buswidth = 32, + .qosbox = &qnm_gpu_qos, .num_links = 2, - .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = { + .num_ports = 1, + .port_offsets = { 0xb5000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, }; static struct qcom_icc_node qnm_lpass_gemnoc = { .name = "qnm_lpass_gemnoc", - .id = SM8650_MASTER_LPASS_GEM_NOC, .channels = 1, .buswidth = 16, + .qosbox = &qnm_lpass_gemnoc_qos, .num_links = 3, - .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, - SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_mdsp = { .name = "qnm_mdsp", - .id = SM8650_MASTER_MSS_PROC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, - SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_qosbox qnm_mnoc_hf_qos = { + .num_ports = 2, + .port_offsets = { 0x33000, 0x73000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = SM8650_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, + .qosbox = &qnm_mnoc_hf_qos, .num_links = 2, - .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_qosbox qnm_mnoc_sf_qos = { + .num_ports = 2, + .port_offsets = { 0x35000, 0x75000 }, + .prio = 0, + .urg_fwd = 0, + .prio_fwd_disable = 0, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = SM8650_MASTER_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, + .qosbox = &qnm_mnoc_sf_qos, .num_links = 2, - .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = { + .num_ports = 2, + .port_offsets = { 0x37000, 0x77000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 1, }; static struct qcom_icc_node qnm_nsp_gemnoc = { .name = "qnm_nsp_gemnoc", - .id = SM8650_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, + .qosbox = &qnm_nsp_gemnoc_qos, .num_links = 3, - .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, - SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_qosbox qnm_pcie_qos = { + .num_ports = 1, + .port_offsets = { 0xb7000 }, + .prio = 2, + .urg_fwd = 1, + .prio_fwd_disable = 0, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = SM8650_MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, + .qosbox = &qnm_pcie_qos, .num_links = 2, - .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_qosbox qnm_snoc_sf_qos = { + .num_ports = 1, + .port_offsets = { 0xbb000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = SM8650_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, + .qosbox = &qnm_snoc_sf_qos, .num_links = 3, - .links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, - SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_qosbox qnm_ubwc_p_qos = { + .num_ports = 1, + .port_offsets = { 0xc3000 }, + .prio = 1, + .urg_fwd = 1, + .prio_fwd_disable = 1, }; static struct qcom_icc_node qnm_ubwc_p = { .name = "qnm_ubwc_p", - .id = SM8650_MASTER_UBWC_P, .channels = 1, .buswidth = 32, + .qosbox = &qnm_ubwc_p_qos, .num_links = 1, - .links = { SM8650_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, +}; + +static struct qcom_icc_qosbox xm_gic_qos = { + .num_ports = 1, + .port_offsets = { 0xb9000 }, + .prio = 4, + .urg_fwd = 0, + .prio_fwd_disable = 1, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = SM8650_MASTER_GIC, .channels = 1, .buswidth = 8, + .qosbox = &xm_gic_qos, .num_links = 1, - .links = { SM8650_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_lpiaon_noc = { .name = "qnm_lpiaon_noc", - .id = SM8650_MASTER_LPIAON_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_SLAVE_LPASS_GEM_NOC }, + .link_nodes = { &qns_lpass_ag_noc_gemnoc }, }; static struct qcom_icc_node qnm_lpass_lpinoc = { .name = "qnm_lpass_lpinoc", - .id = SM8650_MASTER_LPASS_LPINOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC }, + .link_nodes = { &qns_lpass_aggnoc }, }; static struct qcom_icc_node qxm_lpinoc_dsp_axim = { .name = "qxm_lpinoc_dsp_axim", - .id = SM8650_MASTER_LPASS_PROC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_SLAVE_LPICX_NOC_LPIAON_NOC }, + .link_nodes = { &qns_lpi_aon_noc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = SM8650_MASTER_LLCC, .channels = 4, .buswidth = 4, .num_links = 1, - .links = { SM8650_SLAVE_EBI1 }, + .link_nodes = { &ebi }, +}; + +static struct qcom_icc_qosbox qnm_camnoc_hf_qos = { + .num_ports = 2, + .port_offsets = { 0x28000, 0x29000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, }; static struct qcom_icc_node qnm_camnoc_hf = { .name = "qnm_camnoc_hf", - .id = SM8650_MASTER_CAMNOC_HF, .channels = 2, .buswidth = 32, + .qosbox = &qnm_camnoc_hf_qos, .num_links = 1, - .links = { SM8650_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_qosbox qnm_camnoc_icp_qos = { + .num_ports = 1, + .port_offsets = { 0x2a000 }, + .prio = 4, + .urg_fwd = 1, + .prio_fwd_disable = 0, }; static struct qcom_icc_node qnm_camnoc_icp = { .name = "qnm_camnoc_icp", - .id = SM8650_MASTER_CAMNOC_ICP, .channels = 1, .buswidth = 8, + .qosbox = &qnm_camnoc_icp_qos, .num_links = 1, - .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_qosbox qnm_camnoc_sf_qos = { + .num_ports = 2, + .port_offsets = { 0x2b000, 0x2c000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, }; static struct qcom_icc_node qnm_camnoc_sf = { .name = "qnm_camnoc_sf", - .id = SM8650_MASTER_CAMNOC_SF, .channels = 2, .buswidth = 32, + .qosbox = &qnm_camnoc_sf_qos, .num_links = 1, - .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_qosbox qnm_mdp_qos = { + .num_ports = 2, + .port_offsets = { 0x2d000, 0x2e000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, }; static struct qcom_icc_node qnm_mdp = { .name = "qnm_mdp", - .id = SM8650_MASTER_MDP, .channels = 2, .buswidth = 32, + .qosbox = &qnm_mdp_qos, .num_links = 1, - .links = { SM8650_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_vapss_hcp = { .name = "qnm_vapss_hcp", - .id = SM8650_MASTER_CDSP_HCP, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_qosbox qnm_video_qos = { + .num_ports = 2, + .port_offsets = { 0x30000, 0x31000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, }; static struct qcom_icc_node qnm_video = { .name = "qnm_video", - .id = SM8650_MASTER_VIDEO, .channels = 2, .buswidth = 32, + .qosbox = &qnm_video_qos, .num_links = 1, - .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_qosbox qnm_video_cv_cpu_qos = { + .num_ports = 1, + .port_offsets = { 0x32000 }, + .prio = 4, + .urg_fwd = 1, + .prio_fwd_disable = 0, }; static struct qcom_icc_node qnm_video_cv_cpu = { .name = "qnm_video_cv_cpu", - .id = SM8650_MASTER_VIDEO_CV_PROC, .channels = 1, .buswidth = 8, + .qosbox = &qnm_video_cv_cpu_qos, .num_links = 1, - .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_qosbox qnm_video_cvp_qos = { + .num_ports = 2, + .port_offsets = { 0x33000, 0x34000 }, + .prio = 0, + .urg_fwd = 1, + .prio_fwd_disable = 0, }; static struct qcom_icc_node qnm_video_cvp = { .name = "qnm_video_cvp", - .id = SM8650_MASTER_VIDEO_PROC, .channels = 2, .buswidth = 32, + .qosbox = &qnm_video_cvp_qos, .num_links = 1, - .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_qosbox qnm_video_v_cpu_qos = { + .num_ports = 1, + .port_offsets = { 0x35000 }, + .prio = 4, + .urg_fwd = 1, + .prio_fwd_disable = 0, }; static struct qcom_icc_node qnm_video_v_cpu = { .name = "qnm_video_v_cpu", - .id = SM8650_MASTER_VIDEO_V_PROC, .channels = 1, .buswidth = 8, + .qosbox = &qnm_video_v_cpu_qos, .num_links = 1, - .links = { SM8650_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qsm_mnoc_cfg = { .name = "qsm_mnoc_cfg", - .id = SM8650_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8650_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qnm_nsp = { .name = "qnm_nsp", - .id = SM8650_MASTER_CDSP_PROC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8650_SLAVE_CDSP_MEM_NOC }, + .link_nodes = { &qns_nsp_gemnoc }, }; static struct qcom_icc_node qsm_pcie_anoc_cfg = { .name = "qsm_pcie_anoc_cfg", - .id = SM8650_MASTER_PCIE_ANOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8650_SLAVE_SERVICE_PCIE_ANOC }, + .link_nodes = { &srvc_pcie_aggre_noc }, +}; + +static struct qcom_icc_qosbox xm_pcie3_0_qos = { + .num_ports = 1, + .port_offsets = { 0xb000 }, + .prio = 3, + .urg_fwd = 0, + .prio_fwd_disable = 0, }; static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", - .id = SM8650_MASTER_PCIE_0, .channels = 1, .buswidth = 8, + .qosbox = &xm_pcie3_0_qos, .num_links = 1, - .links = { SM8650_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, +}; + +static struct qcom_icc_qosbox xm_pcie3_1_qos = { + .num_ports = 1, + .port_offsets = { 0xc000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 0, }; static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", - .id = SM8650_MASTER_PCIE_1, .channels = 1, .buswidth = 16, + .qosbox = &xm_pcie3_1_qos, .num_links = 1, - .links = { SM8650_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = SM8650_MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = SM8650_MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_qosbox qnm_apss_noc_qos = { + .num_ports = 1, + .port_offsets = { 0x1c000 }, + .prio = 2, + .urg_fwd = 0, + .prio_fwd_disable = 1, +}; + +static struct qcom_icc_node qnm_apss_noc = { + .name = "qnm_apss_noc", + .channels = 1, + .buswidth = 4, + .qosbox = &qnm_apss_noc_qos, + .num_links = 1, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = SM8650_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_MASTER_A1NOC_SNOC }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = SM8650_SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_MASTER_A2NOC_SNOC }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", - .id = SM8650_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup1_core_slave = { .name = "qup1_core_slave", - .id = SM8650_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup2_core_slave = { .name = "qup2_core_slave", - .id = SM8650_SLAVE_QUP_CORE_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", - .id = SM8650_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy1 = { .name = "qhs_ahb2phy1", - .id = SM8650_SLAVE_AHB2PHY_NORTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = SM8650_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = SM8650_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_cx = { .name = "qhs_cpr_cx", - .id = SM8650_SLAVE_RBCPR_CX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_hmx = { .name = "qhs_cpr_hmx", - .id = SM8650_SLAVE_CPR_HMX, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mmcx = { .name = "qhs_cpr_mmcx", - .id = SM8650_SLAVE_RBCPR_MMCX_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mxa = { .name = "qhs_cpr_mxa", - .id = SM8650_SLAVE_RBCPR_MXA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_mxc = { .name = "qhs_cpr_mxc", - .id = SM8650_SLAVE_RBCPR_MXC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cpr_nspcx = { .name = "qhs_cpr_nspcx", - .id = SM8650_SLAVE_CPR_NSPCX, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = SM8650_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_cx_rdpm = { .name = "qhs_cx_rdpm", - .id = SM8650_SLAVE_CX_RDPM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = SM8650_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = SM8650_SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_i2c = { .name = "qhs_i2c", - .id = SM8650_SLAVE_I2C, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_i3c_ibi0_cfg = { .name = "qhs_i3c_ibi0_cfg", - .id = SM8650_SLAVE_I3C_IBI0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_i3c_ibi1_cfg = { .name = "qhs_i3c_ibi1_cfg", - .id = SM8650_SLAVE_I3C_IBI1_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = SM8650_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", - .id = SM8650_SLAVE_CNOC_MSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mx_2_rdpm = { .name = "qhs_mx_2_rdpm", - .id = SM8650_SLAVE_MX_2_RDPM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_mx_rdpm = { .name = "qhs_mx_rdpm", - .id = SM8650_SLAVE_MX_RDPM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = SM8650_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie1_cfg = { .name = "qhs_pcie1_cfg", - .id = SM8650_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie_rscc = { .name = "qhs_pcie_rscc", - .id = SM8650_SLAVE_PCIE_RSCC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = SM8650_SLAVE_PDM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = SM8650_SLAVE_PRNG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = SM8650_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = SM8650_SLAVE_QSPI_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup02 = { .name = "qhs_qup02", - .id = SM8650_SLAVE_QUP_3, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = SM8650_SLAVE_QUP_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup2 = { .name = "qhs_qup2", - .id = SM8650_SLAVE_QUP_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = SM8650_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = SM8650_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_spss_cfg = { .name = "qhs_spss_cfg", - .id = SM8650_SLAVE_SPSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = SM8650_SLAVE_TCSR, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = SM8650_SLAVE_TLMM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = SM8650_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3_0 = { .name = "qhs_usb3_0", - .id = SM8650_SLAVE_USB3_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = SM8650_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", - .id = SM8650_SLAVE_VSENSE_CTRL_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qss_mnoc_cfg = { .name = "qss_mnoc_cfg", - .id = SM8650_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8650_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qsm_mnoc_cfg }, }; static struct qcom_icc_node qss_nsp_qtb_cfg = { .name = "qss_nsp_qtb_cfg", - .id = SM8650_SLAVE_NSP_QTB_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qss_pcie_anoc_cfg = { .name = "qss_pcie_anoc_cfg", - .id = SM8650_SLAVE_PCIE_ANOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8650_MASTER_PCIE_ANOC_CFG }, + .link_nodes = { &qsm_pcie_anoc_cfg }, }; static struct qcom_icc_node srvc_cnoc_cfg = { .name = "srvc_cnoc_cfg", - .id = SM8650_SLAVE_SERVICE_CNOC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = SM8650_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = SM8650_SLAVE_TCU, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = SM8650_SLAVE_AOSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", - .id = SM8650_SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", - .id = SM8650_SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tme_cfg = { .name = "qhs_tme_cfg", - .id = SM8650_SLAVE_TME_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qss_apss = { .name = "qss_apss", - .id = SM8650_SLAVE_APPSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qss_cfg = { .name = "qss_cfg", - .id = SM8650_SLAVE_CNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { SM8650_MASTER_CNOC_CFG }, + .link_nodes = { &qsm_cfg }, }; static struct qcom_icc_node qss_ddrss_cfg = { .name = "qss_ddrss_cfg", - .id = SM8650_SLAVE_DDRSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = SM8650_SLAVE_IMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node srvc_cnoc_main = { .name = "srvc_cnoc_main", - .id = SM8650_SLAVE_SERVICE_CNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_0 = { .name = "xs_pcie_0", - .id = SM8650_SLAVE_PCIE_0, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_1 = { .name = "xs_pcie_1", - .id = SM8650_SLAVE_PCIE_1, .channels = 1, .buswidth = 16, - .num_links = 0, }; static struct qcom_icc_node qns_gem_noc_cnoc = { .name = "qns_gem_noc_cnoc", - .id = SM8650_SLAVE_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_MASTER_GEM_NOC_CNOC }, + .link_nodes = { &qnm_gemnoc_cnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = SM8650_SLAVE_LLCC, .channels = 4, .buswidth = 16, .num_links = 1, - .links = { SM8650_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_pcie = { .name = "qns_pcie", - .id = SM8650_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { SM8650_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { .name = "qns_lpass_ag_noc_gemnoc", - .id = SM8650_SLAVE_LPASS_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_MASTER_LPASS_GEM_NOC }, + .link_nodes = { &qnm_lpass_gemnoc }, }; static struct qcom_icc_node qns_lpass_aggnoc = { .name = "qns_lpass_aggnoc", - .id = SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_MASTER_LPIAON_NOC }, + .link_nodes = { &qnm_lpiaon_noc }, }; static struct qcom_icc_node qns_lpi_aon_noc = { .name = "qns_lpi_aon_noc", - .id = SM8650_SLAVE_LPICX_NOC_LPIAON_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_MASTER_LPASS_LPINOC }, + .link_nodes = { &qnm_lpass_lpinoc }, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = SM8650_SLAVE_EBI1, .channels = 4, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = SM8650_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8650_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", - .id = SM8650_SLAVE_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8650_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = SM8650_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_nsp_gemnoc = { .name = "qns_nsp_gemnoc", - .id = SM8650_SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { SM8650_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_nsp_gemnoc }, }; static struct qcom_icc_node qns_pcie_mem_noc = { .name = "qns_pcie_mem_noc", - .id = SM8650_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node srvc_pcie_aggre_noc = { .name = "srvc_pcie_aggre_noc", - .id = SM8650_SLAVE_SERVICE_PCIE_ANOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = SM8650_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { SM8650_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_bcm bcm_acv = { @@ -1325,6 +1595,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_aggre1_noc = { + .config = &icc_regmap_config, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), }; @@ -1346,6 +1617,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_aggre2_noc = { + .config = &icc_regmap_config, .nodes = aggre2_noc_nodes, .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), .bcms = aggre2_noc_bcms, @@ -1429,6 +1701,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_config_noc = { + .config = &icc_regmap_config, .nodes = config_noc_nodes, .num_nodes = ARRAY_SIZE(config_noc_nodes), .bcms = config_noc_bcms, @@ -1456,6 +1729,7 @@ static struct qcom_icc_node * const cnoc_main_nodes[] = { }; static const struct qcom_icc_desc sm8650_cnoc_main = { + .config = &icc_regmap_config, .nodes = cnoc_main_nodes, .num_nodes = ARRAY_SIZE(cnoc_main_nodes), .bcms = cnoc_main_bcms, @@ -1488,6 +1762,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_gem_noc = { + .config = &icc_regmap_config, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, @@ -1500,6 +1775,7 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_lpass_ag_noc = { + .config = &icc_regmap_config, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), }; @@ -1514,6 +1790,7 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_lpass_lpiaon_noc = { + .config = &icc_regmap_config, .nodes = lpass_lpiaon_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), .bcms = lpass_lpiaon_noc_bcms, @@ -1526,6 +1803,7 @@ static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_lpass_lpicx_noc = { + .config = &icc_regmap_config, .nodes = lpass_lpicx_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), }; @@ -1569,6 +1847,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_mmss_noc = { + .config = &icc_regmap_config, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, @@ -1585,6 +1864,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = { }; static const struct qcom_icc_desc sm8650_nsp_noc = { + .config = &icc_regmap_config, .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), .bcms = nsp_noc_bcms, @@ -1604,6 +1884,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = { }; static const struct qcom_icc_desc sm8650_pcie_anoc = { + .config = &icc_regmap_config, .nodes = pcie_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), .bcms = pcie_anoc_bcms, @@ -1620,9 +1901,11 @@ static struct qcom_icc_node * const system_noc_nodes[] = { [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, + [MASTER_APSS_NOC] = &qnm_apss_noc, }; static const struct qcom_icc_desc sm8650_system_noc = { + .config = &icc_regmap_config, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, @@ -1650,7 +1933,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove_new = qcom_icc_rpmh_remove, + .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sm8650", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/sm8650.h b/drivers/interconnect/qcom/sm8650.h deleted file mode 100644 index de35c956fe49..000000000000 --- a/drivers/interconnect/qcom/sm8650.h +++ /dev/null @@ -1,143 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * SM8650 interconnect IDs - * - * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Linaro Limited - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8650_H -#define __DRIVERS_INTERCONNECT_QCOM_SM8650_H - -#define SM8650_MASTER_A1NOC_SNOC 0 -#define SM8650_MASTER_A2NOC_SNOC 1 -#define SM8650_MASTER_ANOC_PCIE_GEM_NOC 2 -#define SM8650_MASTER_APPSS_PROC 3 -#define SM8650_MASTER_CAMNOC_HF 4 -#define SM8650_MASTER_CAMNOC_ICP 5 -#define SM8650_MASTER_CAMNOC_SF 6 -#define SM8650_MASTER_CDSP_HCP 7 -#define SM8650_MASTER_CDSP_PROC 8 -#define SM8650_MASTER_CNOC_CFG 9 -#define SM8650_MASTER_CNOC_MNOC_CFG 10 -#define SM8650_MASTER_COMPUTE_NOC 11 -#define SM8650_MASTER_CRYPTO 12 -#define SM8650_MASTER_GEM_NOC_CNOC 13 -#define SM8650_MASTER_GEM_NOC_PCIE_SNOC 14 -#define SM8650_MASTER_GFX3D 15 -#define SM8650_MASTER_GIC 16 -#define SM8650_MASTER_GPU_TCU 17 -#define SM8650_MASTER_IPA 18 -#define SM8650_MASTER_LLCC 19 -#define SM8650_MASTER_LPASS_GEM_NOC 20 -#define SM8650_MASTER_LPASS_LPINOC 21 -#define SM8650_MASTER_LPASS_PROC 22 -#define SM8650_MASTER_LPIAON_NOC 23 -#define SM8650_MASTER_MDP 24 -#define SM8650_MASTER_MNOC_HF_MEM_NOC 25 -#define SM8650_MASTER_MNOC_SF_MEM_NOC 26 -#define SM8650_MASTER_MSS_PROC 27 -#define SM8650_MASTER_PCIE_0 28 -#define SM8650_MASTER_PCIE_1 29 -#define SM8650_MASTER_PCIE_ANOC_CFG 30 -#define SM8650_MASTER_QDSS_BAM 31 -#define SM8650_MASTER_QDSS_ETR 32 -#define SM8650_MASTER_QDSS_ETR_1 33 -#define SM8650_MASTER_QSPI_0 34 -#define SM8650_MASTER_QUP_1 35 -#define SM8650_MASTER_QUP_2 36 -#define SM8650_MASTER_QUP_3 37 -#define SM8650_MASTER_QUP_CORE_0 38 -#define SM8650_MASTER_QUP_CORE_1 39 -#define SM8650_MASTER_QUP_CORE_2 40 -#define SM8650_MASTER_SDCC_2 41 -#define SM8650_MASTER_SDCC_4 42 -#define SM8650_MASTER_SNOC_SF_MEM_NOC 43 -#define SM8650_MASTER_SP 44 -#define SM8650_MASTER_SYS_TCU 45 -#define SM8650_MASTER_UBWC_P 46 -#define SM8650_MASTER_UBWC_P_TCU 47 -#define SM8650_MASTER_UFS_MEM 48 -#define SM8650_MASTER_USB3_0 49 -#define SM8650_MASTER_VIDEO 50 -#define SM8650_MASTER_VIDEO_CV_PROC 51 -#define SM8650_MASTER_VIDEO_PROC 52 -#define SM8650_MASTER_VIDEO_V_PROC 53 -#define SM8650_SLAVE_A1NOC_SNOC 54 -#define SM8650_SLAVE_A2NOC_SNOC 55 -#define SM8650_SLAVE_AHB2PHY_NORTH 56 -#define SM8650_SLAVE_AHB2PHY_SOUTH 57 -#define SM8650_SLAVE_ANOC_PCIE_GEM_NOC 58 -#define SM8650_SLAVE_AOSS 59 -#define SM8650_SLAVE_APPSS 60 -#define SM8650_SLAVE_CAMERA_CFG 61 -#define SM8650_SLAVE_CDSP_MEM_NOC 62 -#define SM8650_SLAVE_CLK_CTL 63 -#define SM8650_SLAVE_CNOC_CFG 64 -#define SM8650_SLAVE_CNOC_MNOC_CFG 65 -#define SM8650_SLAVE_CNOC_MSS 66 -#define SM8650_SLAVE_CPR_HMX 67 -#define SM8650_SLAVE_CPR_NSPCX 68 -#define SM8650_SLAVE_CRYPTO_0_CFG 69 -#define SM8650_SLAVE_CX_RDPM 70 -#define SM8650_SLAVE_DDRSS_CFG 71 -#define SM8650_SLAVE_DISPLAY_CFG 72 -#define SM8650_SLAVE_EBI1 73 -#define SM8650_SLAVE_GEM_NOC_CNOC 74 -#define SM8650_SLAVE_GFX3D_CFG 75 -#define SM8650_SLAVE_I2C 76 -#define SM8650_SLAVE_I3C_IBI0_CFG 77 -#define SM8650_SLAVE_I3C_IBI1_CFG 78 -#define SM8650_SLAVE_IMEM 79 -#define SM8650_SLAVE_IMEM_CFG 80 -#define SM8650_SLAVE_IPA_CFG 81 -#define SM8650_SLAVE_IPC_ROUTER_CFG 82 -#define SM8650_SLAVE_LLCC 83 -#define SM8650_SLAVE_LPASS_GEM_NOC 84 -#define SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC 85 -#define SM8650_SLAVE_LPICX_NOC_LPIAON_NOC 86 -#define SM8650_SLAVE_MEM_NOC_PCIE_SNOC 87 -#define SM8650_SLAVE_MNOC_HF_MEM_NOC 88 -#define SM8650_SLAVE_MNOC_SF_MEM_NOC 89 -#define SM8650_SLAVE_MX_2_RDPM 90 -#define SM8650_SLAVE_MX_RDPM 91 -#define SM8650_SLAVE_NSP_QTB_CFG 92 -#define SM8650_SLAVE_PCIE_0 93 -#define SM8650_SLAVE_PCIE_1 94 -#define SM8650_SLAVE_PCIE_0_CFG 95 -#define SM8650_SLAVE_PCIE_1_CFG 96 -#define SM8650_SLAVE_PCIE_ANOC_CFG 97 -#define SM8650_SLAVE_PCIE_RSCC 98 -#define SM8650_SLAVE_PDM 99 -#define SM8650_SLAVE_PRNG 100 -#define SM8650_SLAVE_QDSS_CFG 101 -#define SM8650_SLAVE_QDSS_STM 102 -#define SM8650_SLAVE_QSPI_0 103 -#define SM8650_SLAVE_QUP_1 104 -#define SM8650_SLAVE_QUP_2 105 -#define SM8650_SLAVE_QUP_3 106 -#define SM8650_SLAVE_QUP_CORE_0 107 -#define SM8650_SLAVE_QUP_CORE_1 108 -#define SM8650_SLAVE_QUP_CORE_2 109 -#define SM8650_SLAVE_RBCPR_CX_CFG 110 -#define SM8650_SLAVE_RBCPR_MMCX_CFG 111 -#define SM8650_SLAVE_RBCPR_MXA_CFG 112 -#define SM8650_SLAVE_RBCPR_MXC_CFG 113 -#define SM8650_SLAVE_SDCC_2 114 -#define SM8650_SLAVE_SDCC_4 115 -#define SM8650_SLAVE_SERVICE_CNOC 116 -#define SM8650_SLAVE_SERVICE_CNOC_CFG 117 -#define SM8650_SLAVE_SERVICE_MNOC 118 -#define SM8650_SLAVE_SERVICE_PCIE_ANOC 119 -#define SM8650_SLAVE_SNOC_GEM_NOC_SF 120 -#define SM8650_SLAVE_SPSS_CFG 121 -#define SM8650_SLAVE_TCSR 122 -#define SM8650_SLAVE_TCU 123 -#define SM8650_SLAVE_TLMM 124 -#define SM8650_SLAVE_TME_CFG 125 -#define SM8650_SLAVE_UFS_MEM_CFG 126 -#define SM8650_SLAVE_USB3_0 127 -#define SM8650_SLAVE_VENUS_CFG 128 -#define SM8650_SLAVE_VSENSE_CTRL_CFG 129 - -#endif diff --git a/drivers/interconnect/qcom/sm8750.c b/drivers/interconnect/qcom/sm8750.c new file mode 100644 index 000000000000..1486c0b8f4c1 --- /dev/null +++ b/drivers/interconnect/qcom/sm8750.c @@ -0,0 +1,1535 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + * + */ + +#include <linux/device.h> +#include <linux/interconnect.h> +#include <linux/interconnect-provider.h> +#include <linux/module.h> +#include <linux/of_platform.h> +#include <dt-bindings/interconnect/qcom,sm8750-rpmh.h> + +#include "bcm-voter.h" +#include "icc-rpmh.h" + +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node qxm_qup02; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node qxm_soccp; +static struct qcom_icc_node qxm_sp; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup2_core_master; +static struct qcom_icc_node qsm_cfg; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_lpass_gemnoc; +static struct qcom_icc_node qnm_mdsp; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_nsp_gemnoc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qnm_ubwc_p; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qnm_lpiaon_noc; +static struct qcom_icc_node qnm_lpass_lpinoc; +static struct qcom_icc_node qnm_lpinoc_dsp_qns4m; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_nrt_icp_sf; +static struct qcom_icc_node qnm_camnoc_rt_cdm_sf; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_mdp; +static struct qcom_icc_node qnm_vapss_hcp; +static struct qcom_icc_node qnm_video_cv_cpu; +static struct qcom_icc_node qnm_video_eva; +static struct qcom_icc_node qnm_video_mvp; +static struct qcom_icc_node qnm_video_v_cpu; +static struct qcom_icc_node qsm_mnoc_cfg; +static struct qcom_icc_node qnm_nsp; +static struct qcom_icc_node qsm_pcie_anoc_cfg; +static struct qcom_icc_node xm_pcie3; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup2_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_eva_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_i2c; +static struct qcom_icc_node qhs_i3c_ibi0_cfg; +static struct qcom_icc_node qhs_i3c_ibi1_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_pcie_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup02; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_spss_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qss_mnoc_cfg; +static struct qcom_icc_node qss_pcie_anoc_cfg; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_soccp; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qns_apss; +static struct qcom_icc_node qss_cfg; +static struct qcom_icc_node qss_ddrss_cfg; +static struct qcom_icc_node qxs_boot_imem; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_modem_boot_imem; +static struct qcom_icc_node srvc_cnoc_main; +static struct qcom_icc_node xs_pcie; +static struct qcom_icc_node chs_ubwc_p; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc; +static struct qcom_icc_node qns_lpass_aggnoc; +static struct qcom_icc_node qns_lpi_aon_noc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_pcie_aggre_noc; +static struct qcom_icc_node qns_gemnoc_sf; + +static struct qcom_icc_node qhm_qspi = { + .name = "qhm_qspi", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qhm_qup1 = { + .name = "qhm_qup1", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qxm_qup02 = { + .name = "qxm_qup02", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_sdc4 = { + .name = "xm_sdc4", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node xm_usb3_0 = { + .name = "xm_usb3_0", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qhm_qup2 = { + .name = "qhm_qup2", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qxm_soccp = { + .name = "qxm_soccp", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qxm_sp = { + .name = "qxm_sp", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node xm_qdss_etr_0 = { + .name = "xm_qdss_etr_0", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node xm_qdss_etr_1 = { + .name = "xm_qdss_etr_1", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node xm_sdc2 = { + .name = "xm_sdc2", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qup0_core_master = { + .name = "qup0_core_master", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qup0_core_slave }, +}; + +static struct qcom_icc_node qup1_core_master = { + .name = "qup1_core_master", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qup1_core_slave }, +}; + +static struct qcom_icc_node qup2_core_master = { + .name = "qup2_core_master", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qup2_core_slave }, +}; + +static struct qcom_icc_node qsm_cfg = { + .name = "qsm_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 33, + .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_crypto0_cfg, &qhs_display_cfg, + &qhs_eva_cfg, &qhs_gpuss_cfg, + &qhs_i2c, &qhs_i3c_ibi0_cfg, + &qhs_i3c_ibi1_cfg, &qhs_imem_cfg, + &qhs_mss_cfg, &qhs_pcie_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup02, + &qhs_qup1, &qhs_qup2, + &qhs_sdc2, &qhs_sdc4, + &qhs_spss_cfg, &qhs_tcsr, + &qhs_tlmm, &qhs_ufs_mem_cfg, + &qhs_usb3_0, &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, &qss_mnoc_cfg, + &qss_pcie_anoc_cfg, &xs_qdss_stm, + &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_node qnm_gemnoc_cnoc = { + .name = "qnm_gemnoc_cnoc", + .channels = 1, + .buswidth = 16, + .num_links = 12, + .link_nodes = { &qhs_aoss, &qhs_ipa, + &qhs_ipc_router, &qhs_soccp, + &qhs_tme_cfg, &qns_apss, + &qss_cfg, &qss_ddrss_cfg, + &qxs_boot_imem, &qxs_imem, + &qxs_modem_boot_imem, &srvc_cnoc_main }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie = { + .name = "qnm_gemnoc_pcie", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &xs_pcie }, +}; + +static struct qcom_icc_node alm_gpu_tcu = { + .name = "alm_gpu_tcu", + .channels = 1, + .buswidth = 8, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node alm_sys_tcu = { + .name = "alm_sys_tcu", + .channels = 1, + .buswidth = 8, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node chm_apps = { + .name = "chm_apps", + .channels = 4, + .buswidth = 32, + .num_links = 4, + .link_nodes = { &chs_ubwc_p, &qns_gem_noc_cnoc, + &qns_llcc, &qns_pcie }, +}; + +static struct qcom_icc_node qnm_gpu = { + .name = "qnm_gpu", + .channels = 2, + .buswidth = 32, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node qnm_lpass_gemnoc = { + .name = "qnm_lpass_gemnoc", + .channels = 1, + .buswidth = 16, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_mdsp = { + .name = "qnm_mdsp", + .channels = 1, + .buswidth = 16, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .channels = 2, + .buswidth = 32, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .channels = 2, + .buswidth = 32, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node qnm_nsp_gemnoc = { + .name = "qnm_nsp_gemnoc", + .channels = 2, + .buswidth = 32, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_pcie = { + .name = "qnm_pcie", + .channels = 1, + .buswidth = 8, + .num_links = 2, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .channels = 1, + .buswidth = 16, + .num_links = 3, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_ubwc_p = { + .name = "qnm_ubwc_p", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_llcc }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_llcc }, +}; + +static struct qcom_icc_node qnm_lpiaon_noc = { + .name = "qnm_lpiaon_noc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_lpass_ag_noc_gemnoc }, +}; + +static struct qcom_icc_node qnm_lpass_lpinoc = { + .name = "qnm_lpass_lpinoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_lpass_aggnoc }, +}; + +static struct qcom_icc_node qnm_lpinoc_dsp_qns4m = { + .name = "qnm_lpinoc_dsp_qns4m", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_lpi_aon_noc }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .channels = 4, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &ebi }, +}; + +static struct qcom_icc_node qnm_camnoc_hf = { + .name = "qnm_camnoc_hf", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qnm_camnoc_nrt_icp_sf = { + .name = "qnm_camnoc_nrt_icp_sf", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_camnoc_rt_cdm_sf = { + .name = "qnm_camnoc_rt_cdm_sf", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_camnoc_sf = { + .name = "qnm_camnoc_sf", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_mdp = { + .name = "qnm_mdp", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qnm_vapss_hcp = { + .name = "qnm_vapss_hcp", + .channels = 1, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_cv_cpu = { + .name = "qnm_video_cv_cpu", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_eva = { + .name = "qnm_video_eva", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_mvp = { + .name = "qnm_video_mvp", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_v_cpu = { + .name = "qnm_video_v_cpu", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qsm_mnoc_cfg = { + .name = "qsm_mnoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &srvc_mnoc }, +}; + +static struct qcom_icc_node qnm_nsp = { + .name = "qnm_nsp", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qns_nsp_gemnoc }, +}; + +static struct qcom_icc_node qsm_pcie_anoc_cfg = { + .name = "qsm_pcie_anoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &srvc_pcie_aggre_noc }, +}; + +static struct qcom_icc_node xm_pcie3 = { + .name = "xm_pcie3", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qns_pcie_mem_noc }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_node qup0_core_slave = { + .name = "qup0_core_slave", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup1_core_slave = { + .name = "qup1_core_slave", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup2_core_slave = { + .name = "qup2_core_slave", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy0 = { + .name = "qhs_ahb2phy0", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy1 = { + .name = "qhs_ahb2phy1", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display_cfg = { + .name = "qhs_display_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_eva_cfg = { + .name = "qhs_eva_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_i2c = { + .name = "qhs_i2c", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_i3c_ibi0_cfg = { + .name = "qhs_i3c_ibi0_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_i3c_ibi1_cfg = { + .name = "qhs_i3c_ibi1_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mss_cfg = { + .name = "qhs_mss_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie_cfg = { + .name = "qhs_pcie_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qspi = { + .name = "qhs_qspi", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup02 = { + .name = "qhs_qup02", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup1 = { + .name = "qhs_qup1", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup2 = { + .name = "qhs_qup2", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .name = "qhs_sdc2", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc4 = { + .name = "qhs_sdc4", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_spss_cfg = { + .name = "qhs_spss_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm = { + .name = "qhs_tlmm", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_0 = { + .name = "qhs_usb3_0", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .name = "qhs_vsense_ctrl_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qss_mnoc_cfg = { + .name = "qss_mnoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qsm_mnoc_cfg }, +}; + +static struct qcom_icc_node qss_pcie_anoc_cfg = { + .name = "qss_pcie_anoc_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qsm_pcie_anoc_cfg }, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipc_router = { + .name = "qhs_ipc_router", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_soccp = { + .name = "qhs_soccp", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tme_cfg = { + .name = "qhs_tme_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_apss = { + .name = "qns_apss", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qss_cfg = { + .name = "qss_cfg", + .channels = 1, + .buswidth = 4, + .num_links = 1, + .link_nodes = { &qsm_cfg }, +}; + +static struct qcom_icc_node qss_ddrss_cfg = { + .name = "qss_ddrss_cfg", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qxs_boot_imem = { + .name = "qxs_boot_imem", + .channels = 1, + .buswidth = 16, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_modem_boot_imem = { + .name = "qxs_modem_boot_imem", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node srvc_cnoc_main = { + .name = "srvc_cnoc_main", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_pcie = { + .name = "xs_pcie", + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node chs_ubwc_p = { + .name = "chs_ubwc_p", + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node qns_gem_noc_cnoc = { + .name = "qns_gem_noc_cnoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_gemnoc_cnoc }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .channels = 4, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &llcc_mc }, +}; + +static struct qcom_icc_node qns_pcie = { + .name = "qns_pcie", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qnm_gemnoc_pcie }, +}; + +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { + .name = "qns_lpass_ag_noc_gemnoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_lpass_gemnoc }, +}; + +static struct qcom_icc_node qns_lpass_aggnoc = { + .name = "qns_lpass_aggnoc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_lpiaon_noc }, +}; + +static struct qcom_icc_node qns_lpi_aon_noc = { + .name = "qns_lpi_aon_noc", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_lpass_lpinoc }, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .channels = 4, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_mnoc_hf }, +}; + +static struct qcom_icc_node qns_mem_noc_sf = { + .name = "qns_mem_noc_sf", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_mnoc_sf }, +}; + +static struct qcom_icc_node srvc_mnoc = { + .name = "srvc_mnoc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_nsp_gemnoc = { + .name = "qns_nsp_gemnoc", + .channels = 2, + .buswidth = 32, + .num_links = 1, + .link_nodes = { &qnm_nsp_gemnoc }, +}; + +static struct qcom_icc_node qns_pcie_mem_noc = { + .name = "qns_pcie_mem_noc", + .channels = 1, + .buswidth = 8, + .num_links = 1, + .link_nodes = { &qnm_pcie }, +}; + +static struct qcom_icc_node srvc_pcie_aggre_noc = { + .name = "srvc_pcie_aggre_noc", + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .channels = 1, + .buswidth = 16, + .num_links = 1, + .link_nodes = { &qnm_snoc_sf }, +}; + +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .enable_mask = BIT(0), + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .enable_mask = BIT(0), + .keepalive = true, + .num_nodes = 44, + .nodes = { &qsm_cfg, &qhs_ahb2phy0, + &qhs_ahb2phy1, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_crypto0_cfg, + &qhs_eva_cfg, &qhs_gpuss_cfg, + &qhs_i3c_ibi0_cfg, &qhs_i3c_ibi1_cfg, + &qhs_imem_cfg, &qhs_mss_cfg, + &qhs_pcie_cfg, &qhs_prng, + &qhs_qdss_cfg, &qhs_qspi, + &qhs_sdc2, &qhs_sdc4, + &qhs_spss_cfg, &qhs_tcsr, + &qhs_tlmm, &qhs_ufs_mem_cfg, + &qhs_usb3_0, &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, &qss_mnoc_cfg, + &qss_pcie_anoc_cfg, &xs_qdss_stm, + &xs_sys_tcu_cfg, &qnm_gemnoc_cnoc, + &qnm_gemnoc_pcie, &qhs_aoss, + &qhs_ipa, &qhs_ipc_router, + &qhs_soccp, &qhs_tme_cfg, + &qns_apss, &qss_cfg, + &qss_ddrss_cfg, &qxs_boot_imem, + &qxs_imem, &qxs_modem_boot_imem, + &srvc_cnoc_main, &xs_pcie }, +}; + +static struct qcom_icc_bcm bcm_cn1 = { + .name = "CN1", + .num_nodes = 5, + .nodes = { &qhs_display_cfg, &qhs_i2c, + &qhs_qup02, &qhs_qup1, + &qhs_qup2 }, +}; + +static struct qcom_icc_bcm bcm_co0 = { + .name = "CO0", + .enable_mask = BIT(0), + .num_nodes = 2, + .nodes = { &qnm_nsp, &qns_nsp_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_lp0 = { + .name = "LP0", + .num_nodes = 2, + .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .enable_mask = BIT(0), + .num_nodes = 9, + .nodes = { &qnm_camnoc_hf, &qnm_camnoc_nrt_icp_sf, + &qnm_camnoc_rt_cdm_sf, &qnm_camnoc_sf, + &qnm_vapss_hcp, &qnm_video_cv_cpu, + &qnm_video_mvp, &qnm_video_v_cpu, + &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .keepalive = true, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup0_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup1 = { + .name = "QUP1", + .keepalive = true, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup1_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup2 = { + .name = "QUP2", + .keepalive = true, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup2_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh1 = { + .name = "SH1", + .enable_mask = BIT(0), + .num_nodes = 14, + .nodes = { &alm_gpu_tcu, &alm_sys_tcu, + &chm_apps, &qnm_gpu, + &qnm_mdsp, &qnm_mnoc_hf, + &qnm_mnoc_sf, &qnm_nsp_gemnoc, + &qnm_pcie, &qnm_snoc_sf, + &xm_gic, &chs_ubwc_p, + &qns_gem_noc_cnoc, &qns_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .num_nodes = 1, + .nodes = { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .num_nodes = 1, + .nodes = { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .num_nodes = 1, + .nodes = { &qns_pcie_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_ubw0 = { + .name = "UBW0", + .num_nodes = 1, + .nodes = { &qnm_ubwc_p }, +}; + +static struct qcom_icc_node * const aggre1_noc_nodes[] = { + [MASTER_QSPI_0] = &qhm_qspi, + [MASTER_QUP_1] = &qhm_qup1, + [MASTER_QUP_3] = &qxm_qup02, + [MASTER_SDCC_4] = &xm_sdc4, + [MASTER_UFS_MEM] = &xm_ufs_mem, + [MASTER_USB3_0] = &xm_usb3_0, + [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, +}; + +static const struct qcom_icc_desc sm8750_aggre1_noc = { + .nodes = aggre1_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), +}; + +static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { + &bcm_ce0, +}; + +static struct qcom_icc_node * const aggre2_noc_nodes[] = { + [MASTER_QDSS_BAM] = &qhm_qdss_bam, + [MASTER_QUP_2] = &qhm_qup2, + [MASTER_CRYPTO] = &qxm_crypto, + [MASTER_IPA] = &qxm_ipa, + [MASTER_SOCCP_AGGR_NOC] = &qxm_soccp, + [MASTER_SP] = &qxm_sp, + [MASTER_QDSS_ETR] = &xm_qdss_etr_0, + [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, + [MASTER_SDCC_2] = &xm_sdc2, + [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, +}; + +static const struct qcom_icc_desc sm8750_aggre2_noc = { + .nodes = aggre2_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), + .bcms = aggre2_noc_bcms, + .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), +}; + +static struct qcom_icc_bcm * const clk_virt_bcms[] = { + &bcm_qup0, + &bcm_qup1, + &bcm_qup2, +}; + +static struct qcom_icc_node * const clk_virt_nodes[] = { + [MASTER_QUP_CORE_0] = &qup0_core_master, + [MASTER_QUP_CORE_1] = &qup1_core_master, + [MASTER_QUP_CORE_2] = &qup2_core_master, + [SLAVE_QUP_CORE_0] = &qup0_core_slave, + [SLAVE_QUP_CORE_1] = &qup1_core_slave, + [SLAVE_QUP_CORE_2] = &qup2_core_slave, +}; + +static const struct qcom_icc_desc sm8750_clk_virt = { + .nodes = clk_virt_nodes, + .num_nodes = ARRAY_SIZE(clk_virt_nodes), + .bcms = clk_virt_bcms, + .num_bcms = ARRAY_SIZE(clk_virt_bcms), +}; + +static struct qcom_icc_bcm * const config_noc_bcms[] = { + &bcm_cn0, + &bcm_cn1, +}; + +static struct qcom_icc_node * const config_noc_nodes[] = { + [MASTER_CNOC_CFG] = &qsm_cfg, + [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, + [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, + [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, + [SLAVE_CLK_CTL] = &qhs_clk_ctl, + [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, + [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, + [SLAVE_EVA_CFG] = &qhs_eva_cfg, + [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, + [SLAVE_I2C] = &qhs_i2c, + [SLAVE_I3C_IBI0_CFG] = &qhs_i3c_ibi0_cfg, + [SLAVE_I3C_IBI1_CFG] = &qhs_i3c_ibi1_cfg, + [SLAVE_IMEM_CFG] = &qhs_imem_cfg, + [SLAVE_CNOC_MSS] = &qhs_mss_cfg, + [SLAVE_PCIE_CFG] = &qhs_pcie_cfg, + [SLAVE_PRNG] = &qhs_prng, + [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, + [SLAVE_QSPI_0] = &qhs_qspi, + [SLAVE_QUP_3] = &qhs_qup02, + [SLAVE_QUP_1] = &qhs_qup1, + [SLAVE_QUP_2] = &qhs_qup2, + [SLAVE_SDCC_2] = &qhs_sdc2, + [SLAVE_SDCC_4] = &qhs_sdc4, + [SLAVE_SPSS_CFG] = &qhs_spss_cfg, + [SLAVE_TCSR] = &qhs_tcsr, + [SLAVE_TLMM] = &qhs_tlmm, + [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, + [SLAVE_USB3_0] = &qhs_usb3_0, + [SLAVE_VENUS_CFG] = &qhs_venus_cfg, + [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, + [SLAVE_CNOC_MNOC_CFG] = &qss_mnoc_cfg, + [SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg, + [SLAVE_QDSS_STM] = &xs_qdss_stm, + [SLAVE_TCU] = &xs_sys_tcu_cfg, +}; + +static const struct qcom_icc_desc sm8750_config_noc = { + .nodes = config_noc_nodes, + .num_nodes = ARRAY_SIZE(config_noc_nodes), + .bcms = config_noc_bcms, + .num_bcms = ARRAY_SIZE(config_noc_bcms), +}; + +static struct qcom_icc_bcm * const cnoc_main_bcms[] = { + &bcm_cn0, +}; + +static struct qcom_icc_node * const cnoc_main_nodes[] = { + [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, + [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, + [SLAVE_AOSS] = &qhs_aoss, + [SLAVE_IPA_CFG] = &qhs_ipa, + [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, + [SLAVE_SOCCP] = &qhs_soccp, + [SLAVE_TME_CFG] = &qhs_tme_cfg, + [SLAVE_APPSS] = &qns_apss, + [SLAVE_CNOC_CFG] = &qss_cfg, + [SLAVE_DDRSS_CFG] = &qss_ddrss_cfg, + [SLAVE_BOOT_IMEM] = &qxs_boot_imem, + [SLAVE_IMEM] = &qxs_imem, + [SLAVE_BOOT_IMEM_2] = &qxs_modem_boot_imem, + [SLAVE_SERVICE_CNOC] = &srvc_cnoc_main, + [SLAVE_PCIE_0] = &xs_pcie, +}; + +static const struct qcom_icc_desc sm8750_cnoc_main = { + .nodes = cnoc_main_nodes, + .num_nodes = ARRAY_SIZE(cnoc_main_nodes), + .bcms = cnoc_main_bcms, + .num_bcms = ARRAY_SIZE(cnoc_main_bcms), +}; + +static struct qcom_icc_bcm * const gem_noc_bcms[] = { + &bcm_sh0, + &bcm_sh1, + &bcm_ubw0, +}; + +static struct qcom_icc_node * const gem_noc_nodes[] = { + [MASTER_GPU_TCU] = &alm_gpu_tcu, + [MASTER_SYS_TCU] = &alm_sys_tcu, + [MASTER_APPSS_PROC] = &chm_apps, + [MASTER_GFX3D] = &qnm_gpu, + [MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc, + [MASTER_MSS_PROC] = &qnm_mdsp, + [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, + [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, + [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc, + [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, + [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, + [MASTER_UBWC_P] = &qnm_ubwc_p, + [MASTER_GIC] = &xm_gic, + [SLAVE_UBWC_P] = &chs_ubwc_p, + [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, + [SLAVE_LLCC] = &qns_llcc, + [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, +}; + +static const struct qcom_icc_desc sm8750_gem_noc = { + .nodes = gem_noc_nodes, + .num_nodes = ARRAY_SIZE(gem_noc_nodes), + .bcms = gem_noc_bcms, + .num_bcms = ARRAY_SIZE(gem_noc_bcms), +}; + +static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { + [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc, + [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc, +}; + +static const struct qcom_icc_desc sm8750_lpass_ag_noc = { + .nodes = lpass_ag_noc_nodes, + .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), +}; + +static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = { + &bcm_lp0, +}; + +static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { + [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc, + [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc, +}; + +static const struct qcom_icc_desc sm8750_lpass_lpiaon_noc = { + .nodes = lpass_lpiaon_noc_nodes, + .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), + .bcms = lpass_lpiaon_noc_bcms, + .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms), +}; + +static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { + [MASTER_LPASS_PROC] = &qnm_lpinoc_dsp_qns4m, + [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc, +}; + +static const struct qcom_icc_desc sm8750_lpass_lpicx_noc = { + .nodes = lpass_lpicx_noc_nodes, + .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), +}; + +static struct qcom_icc_bcm * const mc_virt_bcms[] = { + &bcm_acv, + &bcm_mc0, +}; + +static struct qcom_icc_node * const mc_virt_nodes[] = { + [MASTER_LLCC] = &llcc_mc, + [SLAVE_EBI1] = &ebi, +}; + +static const struct qcom_icc_desc sm8750_mc_virt = { + .nodes = mc_virt_nodes, + .num_nodes = ARRAY_SIZE(mc_virt_nodes), + .bcms = mc_virt_bcms, + .num_bcms = ARRAY_SIZE(mc_virt_bcms), +}; + +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { + &bcm_mm0, + &bcm_mm1, +}; + +static struct qcom_icc_node * const mmss_noc_nodes[] = { + [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, + [MASTER_CAMNOC_NRT_ICP_SF] = &qnm_camnoc_nrt_icp_sf, + [MASTER_CAMNOC_RT_CDM_SF] = &qnm_camnoc_rt_cdm_sf, + [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, + [MASTER_MDP] = &qnm_mdp, + [MASTER_CDSP_HCP] = &qnm_vapss_hcp, + [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu, + [MASTER_VIDEO_EVA] = &qnm_video_eva, + [MASTER_VIDEO_MVP] = &qnm_video_mvp, + [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, + [MASTER_CNOC_MNOC_CFG] = &qsm_mnoc_cfg, + [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, + [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, + [SLAVE_SERVICE_MNOC] = &srvc_mnoc, +}; + +static const struct qcom_icc_desc sm8750_mmss_noc = { + .nodes = mmss_noc_nodes, + .num_nodes = ARRAY_SIZE(mmss_noc_nodes), + .bcms = mmss_noc_bcms, + .num_bcms = ARRAY_SIZE(mmss_noc_bcms), +}; + +static struct qcom_icc_bcm * const nsp_noc_bcms[] = { + &bcm_co0, +}; + +static struct qcom_icc_node * const nsp_noc_nodes[] = { + [MASTER_CDSP_PROC] = &qnm_nsp, + [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, +}; + +static const struct qcom_icc_desc sm8750_nsp_noc = { + .nodes = nsp_noc_nodes, + .num_nodes = ARRAY_SIZE(nsp_noc_nodes), + .bcms = nsp_noc_bcms, + .num_bcms = ARRAY_SIZE(nsp_noc_bcms), +}; + +static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { + &bcm_sn4, +}; + +static struct qcom_icc_node * const pcie_anoc_nodes[] = { + [MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg, + [MASTER_PCIE_0] = &xm_pcie3, + [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, + [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc, +}; + +static const struct qcom_icc_desc sm8750_pcie_anoc = { + .nodes = pcie_anoc_nodes, + .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), + .bcms = pcie_anoc_bcms, + .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), +}; + +static struct qcom_icc_bcm * const system_noc_bcms[] = { + &bcm_sn0, + &bcm_sn2, + &bcm_sn3, +}; + +static struct qcom_icc_node * const system_noc_nodes[] = { + [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, + [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, + [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, +}; + +static const struct qcom_icc_desc sm8750_system_noc = { + .nodes = system_noc_nodes, + .num_nodes = ARRAY_SIZE(system_noc_nodes), + .bcms = system_noc_bcms, + .num_bcms = ARRAY_SIZE(system_noc_bcms), +}; + +static const struct of_device_id qnoc_of_match[] = { + { .compatible = "qcom,sm8750-aggre1-noc", .data = &sm8750_aggre1_noc}, + { .compatible = "qcom,sm8750-aggre2-noc", .data = &sm8750_aggre2_noc}, + { .compatible = "qcom,sm8750-clk-virt", .data = &sm8750_clk_virt}, + { .compatible = "qcom,sm8750-config-noc", .data = &sm8750_config_noc}, + { .compatible = "qcom,sm8750-cnoc-main", .data = &sm8750_cnoc_main}, + { .compatible = "qcom,sm8750-gem-noc", .data = &sm8750_gem_noc}, + { .compatible = "qcom,sm8750-lpass-ag-noc", .data = &sm8750_lpass_ag_noc}, + { .compatible = "qcom,sm8750-lpass-lpiaon-noc", .data = &sm8750_lpass_lpiaon_noc}, + { .compatible = "qcom,sm8750-lpass-lpicx-noc", .data = &sm8750_lpass_lpicx_noc}, + { .compatible = "qcom,sm8750-mc-virt", .data = &sm8750_mc_virt}, + { .compatible = "qcom,sm8750-mmss-noc", .data = &sm8750_mmss_noc}, + { .compatible = "qcom,sm8750-nsp-noc", .data = &sm8750_nsp_noc}, + { .compatible = "qcom,sm8750-pcie-anoc", .data = &sm8750_pcie_anoc}, + { .compatible = "qcom,sm8750-system-noc", .data = &sm8750_system_noc}, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver = { + .probe = qcom_icc_rpmh_probe, + .remove = qcom_icc_rpmh_remove, + .driver = { + .name = "qnoc-sm8750", + .of_match_table = qnoc_of_match, + .sync_state = icc_sync_state, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION("SM8750 NoC driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/interconnect/qcom/smd-rpm.c b/drivers/interconnect/qcom/smd-rpm.c index 3816bfb4e2f3..8316c87a2c60 100644 --- a/drivers/interconnect/qcom/smd-rpm.c +++ b/drivers/interconnect/qcom/smd-rpm.c @@ -85,7 +85,7 @@ static struct platform_driver qcom_interconnect_rpm_smd_driver = { .name = "icc_smd_rpm", }, .probe = qcom_icc_rpm_smd_probe, - .remove_new = qcom_icc_rpm_smd_remove, + .remove = qcom_icc_rpm_smd_remove, }; module_platform_driver(qcom_interconnect_rpm_smd_driver); MODULE_AUTHOR("Georgi Djakov <georgi.djakov@linaro.org>"); diff --git a/drivers/interconnect/qcom/x1e80100.c b/drivers/interconnect/qcom/x1e80100.c index 654abb9ce08e..2ba2823c7860 100644 --- a/drivers/interconnect/qcom/x1e80100.c +++ b/drivers/interconnect/qcom/x1e80100.c @@ -15,1342 +15,1278 @@ #include "bcm-voter.h" #include "icc-common.h" #include "icc-rpmh.h" -#include "x1e80100.h" + +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node xm_sdc4; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qhm_qup2; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_sp; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qup2_core_master; +static struct qcom_icc_node qsm_cfg; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_pcie_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_lpass; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_nsp_noc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qnm_lpiaon_noc; +static struct qcom_icc_node qnm_lpass_lpinoc; +static struct qcom_icc_node qxm_lpinoc_dsp_axim; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_av1_enc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_eva; +static struct qcom_icc_node qnm_mdp; +static struct qcom_icc_node qnm_video; +static struct qcom_icc_node qnm_video_cv_cpu; +static struct qcom_icc_node qnm_video_v_cpu; +static struct qcom_icc_node qsm_mnoc_cfg; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node qnm_pcie_north_gem_noc; +static struct qcom_icc_node qnm_pcie_south_gem_noc; +static struct qcom_icc_node xm_pcie_3; +static struct qcom_icc_node xm_pcie_4; +static struct qcom_icc_node xm_pcie_5; +static struct qcom_icc_node xm_pcie_0; +static struct qcom_icc_node xm_pcie_1; +static struct qcom_icc_node xm_pcie_2; +static struct qcom_icc_node xm_pcie_6a; +static struct qcom_icc_node xm_pcie_6b; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_gic; +static struct qcom_icc_node qnm_usb_anoc; +static struct qcom_icc_node qnm_aggre_usb_north_snoc; +static struct qcom_icc_node qnm_aggre_usb_south_snoc; +static struct qcom_icc_node xm_usb2_0; +static struct qcom_icc_node xm_usb3_mp; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node xm_usb3_1; +static struct qcom_icc_node xm_usb3_2; +static struct qcom_icc_node xm_usb4_0; +static struct qcom_icc_node xm_usb4_1; +static struct qcom_icc_node xm_usb4_2; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qup2_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_ahb2phy2; +static struct qcom_icc_node qhs_av1_enc_cfg; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_pcie2_cfg; +static struct qcom_icc_node qhs_pcie3_cfg; +static struct qcom_icc_node qhs_pcie4_cfg; +static struct qcom_icc_node qhs_pcie5_cfg; +static struct qcom_icc_node qhs_pcie6a_cfg; +static struct qcom_icc_node qhs_pcie6b_cfg; +static struct qcom_icc_node qhs_pcie_rsc_cfg; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_qup2; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_sdc4; +static struct qcom_icc_node qhs_smmuv3_cfg; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb2_0_cfg; +static struct qcom_icc_node qhs_usb3_0_cfg; +static struct qcom_icc_node qhs_usb3_1_cfg; +static struct qcom_icc_node qhs_usb3_2_cfg; +static struct qcom_icc_node qhs_usb3_mp_cfg; +static struct qcom_icc_node qhs_usb4_0_cfg; +static struct qcom_icc_node qhs_usb4_1_cfg; +static struct qcom_icc_node qhs_usb4_2_cfg; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qss_lpass_qtb_cfg; +static struct qcom_icc_node qss_mnoc_cfg; +static struct qcom_icc_node qss_nsp_qtb_cfg; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qns_apss; +static struct qcom_icc_node qss_cfg; +static struct qcom_icc_node qxs_boot_imem; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node xs_pcie_2; +static struct qcom_icc_node xs_pcie_3; +static struct qcom_icc_node xs_pcie_4; +static struct qcom_icc_node xs_pcie_5; +static struct qcom_icc_node xs_pcie_6a; +static struct qcom_icc_node xs_pcie_6b; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc; +static struct qcom_icc_node qns_lpass_aggnoc; +static struct qcom_icc_node qns_lpi_aon_noc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node qns_pcie_north_gem_noc; +static struct qcom_icc_node qns_pcie_south_gem_noc; +static struct qcom_icc_node qns_gemnoc_sf; +static struct qcom_icc_node qns_aggre_usb_snoc; +static struct qcom_icc_node qns_aggre_usb_north_snoc; +static struct qcom_icc_node qns_aggre_usb_south_snoc; static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", - .id = X1E80100_MASTER_QSPI_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { X1E80100_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup1 = { .name = "qhm_qup1", - .id = X1E80100_MASTER_QUP_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { X1E80100_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", - .id = X1E80100_MASTER_SDCC_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", - .id = X1E80100_MASTER_UFS_MEM, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_A1NOC_SNOC }, + .link_nodes = { &qns_a1noc_snoc }, }; static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", - .id = X1E80100_MASTER_QUP_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { X1E80100_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", - .id = X1E80100_MASTER_QUP_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { X1E80100_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", - .id = X1E80100_MASTER_CRYPTO, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qxm_sp = { .name = "qxm_sp", - .id = X1E80100_MASTER_SP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr_0 = { .name = "xm_qdss_etr_0", - .id = X1E80100_MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_qdss_etr_1 = { .name = "xm_qdss_etr_1", - .id = X1E80100_MASTER_QDSS_ETR_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", - .id = X1E80100_MASTER_SDCC_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_A2NOC_SNOC }, + .link_nodes = { &qns_a2noc_snoc }, }; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", - .id = X1E80100_MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { X1E80100_SLAVE_QUP_CORE_0 }, + .link_nodes = { &qup0_core_slave }, }; static struct qcom_icc_node qup1_core_master = { .name = "qup1_core_master", - .id = X1E80100_MASTER_QUP_CORE_1, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { X1E80100_SLAVE_QUP_CORE_1 }, + .link_nodes = { &qup1_core_slave }, }; static struct qcom_icc_node qup2_core_master = { .name = "qup2_core_master", - .id = X1E80100_MASTER_QUP_CORE_2, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { X1E80100_SLAVE_QUP_CORE_2 }, + .link_nodes = { &qup2_core_slave }, }; static struct qcom_icc_node qsm_cfg = { .name = "qsm_cfg", - .id = X1E80100_MASTER_CNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 47, - .links = { X1E80100_SLAVE_AHB2PHY_SOUTH, X1E80100_SLAVE_AHB2PHY_NORTH, - X1E80100_SLAVE_AHB2PHY_2, X1E80100_SLAVE_AV1_ENC_CFG, - X1E80100_SLAVE_CAMERA_CFG, X1E80100_SLAVE_CLK_CTL, - X1E80100_SLAVE_CRYPTO_0_CFG, X1E80100_SLAVE_DISPLAY_CFG, - X1E80100_SLAVE_GFX3D_CFG, X1E80100_SLAVE_IMEM_CFG, - X1E80100_SLAVE_IPC_ROUTER_CFG, X1E80100_SLAVE_PCIE_0_CFG, - X1E80100_SLAVE_PCIE_1_CFG, X1E80100_SLAVE_PCIE_2_CFG, - X1E80100_SLAVE_PCIE_3_CFG, X1E80100_SLAVE_PCIE_4_CFG, - X1E80100_SLAVE_PCIE_5_CFG, X1E80100_SLAVE_PCIE_6A_CFG, - X1E80100_SLAVE_PCIE_6B_CFG, X1E80100_SLAVE_PCIE_RSC_CFG, - X1E80100_SLAVE_PDM, X1E80100_SLAVE_PRNG, - X1E80100_SLAVE_QDSS_CFG, X1E80100_SLAVE_QSPI_0, - X1E80100_SLAVE_QUP_0, X1E80100_SLAVE_QUP_1, - X1E80100_SLAVE_QUP_2, X1E80100_SLAVE_SDCC_2, - X1E80100_SLAVE_SDCC_4, X1E80100_SLAVE_SMMUV3_CFG, - X1E80100_SLAVE_TCSR, X1E80100_SLAVE_TLMM, - X1E80100_SLAVE_UFS_MEM_CFG, X1E80100_SLAVE_USB2, - X1E80100_SLAVE_USB3_0, X1E80100_SLAVE_USB3_1, - X1E80100_SLAVE_USB3_2, X1E80100_SLAVE_USB3_MP, - X1E80100_SLAVE_USB4_0, X1E80100_SLAVE_USB4_1, - X1E80100_SLAVE_USB4_2, X1E80100_SLAVE_VENUS_CFG, - X1E80100_SLAVE_LPASS_QTB_CFG, X1E80100_SLAVE_CNOC_MNOC_CFG, - X1E80100_SLAVE_NSP_QTB_CFG, X1E80100_SLAVE_QDSS_STM, - X1E80100_SLAVE_TCU }, + .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_ahb2phy2, &qhs_av1_enc_cfg, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_crypto0_cfg, &qhs_display_cfg, + &qhs_gpuss_cfg, &qhs_imem_cfg, + &qhs_ipc_router, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_pcie2_cfg, + &qhs_pcie3_cfg, &qhs_pcie4_cfg, + &qhs_pcie5_cfg, &qhs_pcie6a_cfg, + &qhs_pcie6b_cfg, &qhs_pcie_rsc_cfg, + &qhs_pdm, &qhs_prng, + &qhs_qdss_cfg, &qhs_qspi, + &qhs_qup0, &qhs_qup1, + &qhs_qup2, &qhs_sdc2, + &qhs_sdc4, &qhs_smmuv3_cfg, + &qhs_tcsr, &qhs_tlmm, + &qhs_ufs_mem_cfg, &qhs_usb2_0_cfg, + &qhs_usb3_0_cfg, &qhs_usb3_1_cfg, + &qhs_usb3_2_cfg, &qhs_usb3_mp_cfg, + &qhs_usb4_0_cfg, &qhs_usb4_1_cfg, + &qhs_usb4_2_cfg, &qhs_venus_cfg, + &qss_lpass_qtb_cfg, &qss_mnoc_cfg, + &qss_nsp_qtb_cfg, &xs_qdss_stm, + &xs_sys_tcu_cfg }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", - .id = X1E80100_MASTER_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 6, - .links = { X1E80100_SLAVE_AOSS, X1E80100_SLAVE_TME_CFG, - X1E80100_SLAVE_APPSS, X1E80100_SLAVE_CNOC_CFG, - X1E80100_SLAVE_BOOT_IMEM, X1E80100_SLAVE_IMEM }, + .link_nodes = { &qhs_aoss, &qhs_tme_cfg, + &qns_apss, &qss_cfg, + &qxs_boot_imem, &qxs_imem }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", - .id = X1E80100_MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 32, .num_links = 8, - .links = { X1E80100_SLAVE_PCIE_0, X1E80100_SLAVE_PCIE_1, - X1E80100_SLAVE_PCIE_2, X1E80100_SLAVE_PCIE_3, - X1E80100_SLAVE_PCIE_4, X1E80100_SLAVE_PCIE_5, - X1E80100_SLAVE_PCIE_6A, X1E80100_SLAVE_PCIE_6B }, + .link_nodes = { &xs_pcie_0, &xs_pcie_1, + &xs_pcie_2, &xs_pcie_3, + &xs_pcie_4, &xs_pcie_5, + &xs_pcie_6a, &xs_pcie_6b }, }; static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", - .id = X1E80100_MASTER_GPU_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node alm_pcie_tcu = { .name = "alm_pcie_tcu", - .id = X1E80100_MASTER_PCIE_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", - .id = X1E80100_MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .num_links = 2, - .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", - .id = X1E80100_MASTER_APPSS_PROC, .channels = 6, .buswidth = 32, .num_links = 3, - .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC, - X1E80100_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", - .id = X1E80100_MASTER_GFX3D, .channels = 4, .buswidth = 32, .num_links = 2, - .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_lpass = { .name = "qnm_lpass", - .id = X1E80100_MASTER_LPASS_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 3, - .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC, - X1E80100_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", - .id = X1E80100_MASTER_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", - .id = X1E80100_MASTER_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 2, - .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_nsp_noc = { .name = "qnm_nsp_noc", - .id = X1E80100_MASTER_COMPUTE_NOC, .channels = 2, .buswidth = 32, .num_links = 3, - .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC, - X1E80100_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", - .id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 64, .num_links = 2, - .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", - .id = X1E80100_MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 64, .num_links = 3, - .links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC, - X1E80100_SLAVE_MEM_NOC_PCIE_SNOC }, + .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", - .id = X1E80100_MASTER_GIC2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_LLCC }, + .link_nodes = { &qns_llcc }, }; static struct qcom_icc_node qnm_lpiaon_noc = { .name = "qnm_lpiaon_noc", - .id = X1E80100_MASTER_LPIAON_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_LPASS_GEM_NOC }, + .link_nodes = { &qns_lpass_ag_noc_gemnoc }, }; static struct qcom_icc_node qnm_lpass_lpinoc = { .name = "qnm_lpass_lpinoc", - .id = X1E80100_MASTER_LPASS_LPINOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_LPIAON_NOC_LPASS_AG_NOC }, + .link_nodes = { &qns_lpass_aggnoc }, }; static struct qcom_icc_node qxm_lpinoc_dsp_axim = { .name = "qxm_lpinoc_dsp_axim", - .id = X1E80100_MASTER_LPASS_PROC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_LPICX_NOC_LPIAON_NOC }, + .link_nodes = { &qns_lpi_aon_noc }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", - .id = X1E80100_MASTER_LLCC, .channels = 8, .buswidth = 4, .num_links = 1, - .links = { X1E80100_SLAVE_EBI1 }, + .link_nodes = { &ebi }, }; static struct qcom_icc_node qnm_av1_enc = { .name = "qnm_av1_enc", - .id = X1E80100_MASTER_AV1_ENC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_camnoc_hf = { .name = "qnm_camnoc_hf", - .id = X1E80100_MASTER_CAMNOC_HF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { X1E80100_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_camnoc_icp = { .name = "qnm_camnoc_icp", - .id = X1E80100_MASTER_CAMNOC_ICP, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_camnoc_sf = { .name = "qnm_camnoc_sf", - .id = X1E80100_MASTER_CAMNOC_SF, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_eva = { .name = "qnm_eva", - .id = X1E80100_MASTER_EVA, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_mdp = { .name = "qnm_mdp", - .id = X1E80100_MASTER_MDP, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { X1E80100_SLAVE_MNOC_HF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_node qnm_video = { .name = "qnm_video", - .id = X1E80100_MASTER_VIDEO, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_cv_cpu = { .name = "qnm_video_cv_cpu", - .id = X1E80100_MASTER_VIDEO_CV_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qnm_video_v_cpu = { .name = "qnm_video_v_cpu", - .id = X1E80100_MASTER_VIDEO_V_PROC, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC }, + .link_nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_node qsm_mnoc_cfg = { .name = "qsm_mnoc_cfg", - .id = X1E80100_MASTER_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { X1E80100_SLAVE_SERVICE_MNOC }, + .link_nodes = { &srvc_mnoc }, }; static struct qcom_icc_node qxm_nsp = { .name = "qxm_nsp", - .id = X1E80100_MASTER_CDSP_PROC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { X1E80100_SLAVE_CDSP_MEM_NOC }, + .link_nodes = { &qns_nsp_gemnoc }, }; static struct qcom_icc_node qnm_pcie_north_gem_noc = { .name = "qnm_pcie_north_gem_noc", - .id = X1E80100_MASTER_PCIE_NORTH, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node qnm_pcie_south_gem_noc = { .name = "qnm_pcie_south_gem_noc", - .id = X1E80100_MASTER_PCIE_SOUTH, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qns_pcie_mem_noc }, }; static struct qcom_icc_node xm_pcie_3 = { .name = "xm_pcie_3", - .id = X1E80100_MASTER_PCIE_3, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_SLAVE_PCIE_NORTH }, + .link_nodes = { &qns_pcie_north_gem_noc }, }; static struct qcom_icc_node xm_pcie_4 = { .name = "xm_pcie_4", - .id = X1E80100_MASTER_PCIE_4, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_PCIE_NORTH }, + .link_nodes = { &qns_pcie_north_gem_noc }, }; static struct qcom_icc_node xm_pcie_5 = { .name = "xm_pcie_5", - .id = X1E80100_MASTER_PCIE_5, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_PCIE_NORTH }, + .link_nodes = { &qns_pcie_north_gem_noc }, }; static struct qcom_icc_node xm_pcie_0 = { .name = "xm_pcie_0", - .id = X1E80100_MASTER_PCIE_0, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_PCIE_SOUTH }, + .link_nodes = { &qns_pcie_south_gem_noc }, }; static struct qcom_icc_node xm_pcie_1 = { .name = "xm_pcie_1", - .id = X1E80100_MASTER_PCIE_1, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_PCIE_SOUTH }, + .link_nodes = { &qns_pcie_south_gem_noc }, }; static struct qcom_icc_node xm_pcie_2 = { .name = "xm_pcie_2", - .id = X1E80100_MASTER_PCIE_2, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_PCIE_SOUTH }, + .link_nodes = { &qns_pcie_south_gem_noc }, }; static struct qcom_icc_node xm_pcie_6a = { .name = "xm_pcie_6a", - .id = X1E80100_MASTER_PCIE_6A, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { X1E80100_SLAVE_PCIE_SOUTH }, + .link_nodes = { &qns_pcie_south_gem_noc }, }; static struct qcom_icc_node xm_pcie_6b = { .name = "xm_pcie_6b", - .id = X1E80100_MASTER_PCIE_6B, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_PCIE_SOUTH }, + .link_nodes = { &qns_pcie_south_gem_noc }, }; static struct qcom_icc_node qnm_aggre1_noc = { .name = "qnm_aggre1_noc", - .id = X1E80100_MASTER_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre2_noc = { .name = "qnm_aggre2_noc", - .id = X1E80100_MASTER_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_gic = { .name = "qnm_gic", - .id = X1E80100_MASTER_GIC1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_usb_anoc = { .name = "qnm_usb_anoc", - .id = X1E80100_MASTER_USB_NOC_SNOC, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF }, + .link_nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_node qnm_aggre_usb_north_snoc = { .name = "qnm_aggre_usb_north_snoc", - .id = X1E80100_MASTER_AGGRE_USB_NORTH, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_SLAVE_USB_NOC_SNOC }, + .link_nodes = { &qns_aggre_usb_snoc }, }; static struct qcom_icc_node qnm_aggre_usb_south_snoc = { .name = "qnm_aggre_usb_south_snoc", - .id = X1E80100_MASTER_AGGRE_USB_SOUTH, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_SLAVE_USB_NOC_SNOC }, + .link_nodes = { &qns_aggre_usb_snoc }, }; static struct qcom_icc_node xm_usb2_0 = { .name = "xm_usb2_0", - .id = X1E80100_MASTER_USB2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_AGGRE_USB_NORTH }, + .link_nodes = { &qns_aggre_usb_north_snoc }, }; static struct qcom_icc_node xm_usb3_mp = { .name = "xm_usb3_mp", - .id = X1E80100_MASTER_USB3_MP, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_AGGRE_USB_NORTH }, + .link_nodes = { &qns_aggre_usb_north_snoc }, }; static struct qcom_icc_node xm_usb3_0 = { .name = "xm_usb3_0", - .id = X1E80100_MASTER_USB3_0, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, + .link_nodes = { &qns_aggre_usb_south_snoc }, }; static struct qcom_icc_node xm_usb3_1 = { .name = "xm_usb3_1", - .id = X1E80100_MASTER_USB3_1, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, + .link_nodes = { &qns_aggre_usb_south_snoc }, }; static struct qcom_icc_node xm_usb3_2 = { .name = "xm_usb3_2", - .id = X1E80100_MASTER_USB3_2, .channels = 1, .buswidth = 8, .num_links = 1, - .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, + .link_nodes = { &qns_aggre_usb_south_snoc }, }; static struct qcom_icc_node xm_usb4_0 = { .name = "xm_usb4_0", - .id = X1E80100_MASTER_USB4_0, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, + .link_nodes = { &qns_aggre_usb_south_snoc }, }; static struct qcom_icc_node xm_usb4_1 = { .name = "xm_usb4_1", - .id = X1E80100_MASTER_USB4_1, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, + .link_nodes = { &qns_aggre_usb_south_snoc }, }; static struct qcom_icc_node xm_usb4_2 = { .name = "xm_usb4_2", - .id = X1E80100_MASTER_USB4_2, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, + .link_nodes = { &qns_aggre_usb_south_snoc }, }; static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", - .id = X1E80100_SLAVE_A1NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_MASTER_A1NOC_SNOC }, + .link_nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_node qns_a2noc_snoc = { .name = "qns_a2noc_snoc", - .id = X1E80100_SLAVE_A2NOC_SNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_MASTER_A2NOC_SNOC }, + .link_nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", - .id = X1E80100_SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup1_core_slave = { .name = "qup1_core_slave", - .id = X1E80100_SLAVE_QUP_CORE_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qup2_core_slave = { .name = "qup2_core_slave", - .id = X1E80100_SLAVE_QUP_CORE_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", - .id = X1E80100_SLAVE_AHB2PHY_SOUTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy1 = { .name = "qhs_ahb2phy1", - .id = X1E80100_SLAVE_AHB2PHY_NORTH, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ahb2phy2 = { .name = "qhs_ahb2phy2", - .id = X1E80100_SLAVE_AHB2PHY_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_av1_enc_cfg = { .name = "qhs_av1_enc_cfg", - .id = X1E80100_SLAVE_AV1_ENC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", - .id = X1E80100_SLAVE_CAMERA_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", - .id = X1E80100_SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_crypto0_cfg = { .name = "qhs_crypto0_cfg", - .id = X1E80100_SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", - .id = X1E80100_SLAVE_DISPLAY_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", - .id = X1E80100_SLAVE_GFX3D_CFG, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", - .id = X1E80100_SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", - .id = X1E80100_SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", - .id = X1E80100_SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie1_cfg = { .name = "qhs_pcie1_cfg", - .id = X1E80100_SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie2_cfg = { .name = "qhs_pcie2_cfg", - .id = X1E80100_SLAVE_PCIE_2_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie3_cfg = { .name = "qhs_pcie3_cfg", - .id = X1E80100_SLAVE_PCIE_3_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie4_cfg = { .name = "qhs_pcie4_cfg", - .id = X1E80100_SLAVE_PCIE_4_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie5_cfg = { .name = "qhs_pcie5_cfg", - .id = X1E80100_SLAVE_PCIE_5_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie6a_cfg = { .name = "qhs_pcie6a_cfg", - .id = X1E80100_SLAVE_PCIE_6A_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie6b_cfg = { .name = "qhs_pcie6b_cfg", - .id = X1E80100_SLAVE_PCIE_6B_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pcie_rsc_cfg = { .name = "qhs_pcie_rsc_cfg", - .id = X1E80100_SLAVE_PCIE_RSC_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", - .id = X1E80100_SLAVE_PDM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", - .id = X1E80100_SLAVE_PRNG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", - .id = X1E80100_SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", - .id = X1E80100_SLAVE_QSPI_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", - .id = X1E80100_SLAVE_QUP_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", - .id = X1E80100_SLAVE_QUP_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_qup2 = { .name = "qhs_qup2", - .id = X1E80100_SLAVE_QUP_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", - .id = X1E80100_SLAVE_SDCC_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", - .id = X1E80100_SLAVE_SDCC_4, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_smmuv3_cfg = { .name = "qhs_smmuv3_cfg", - .id = X1E80100_SLAVE_SMMUV3_CFG, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", - .id = X1E80100_SLAVE_TCSR, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", - .id = X1E80100_SLAVE_TLMM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", - .id = X1E80100_SLAVE_UFS_MEM_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb2_0_cfg = { .name = "qhs_usb2_0_cfg", - .id = X1E80100_SLAVE_USB2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3_0_cfg = { .name = "qhs_usb3_0_cfg", - .id = X1E80100_SLAVE_USB3_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3_1_cfg = { .name = "qhs_usb3_1_cfg", - .id = X1E80100_SLAVE_USB3_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3_2_cfg = { .name = "qhs_usb3_2_cfg", - .id = X1E80100_SLAVE_USB3_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb3_mp_cfg = { .name = "qhs_usb3_mp_cfg", - .id = X1E80100_SLAVE_USB3_MP, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb4_0_cfg = { .name = "qhs_usb4_0_cfg", - .id = X1E80100_SLAVE_USB4_0, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb4_1_cfg = { .name = "qhs_usb4_1_cfg", - .id = X1E80100_SLAVE_USB4_1, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_usb4_2_cfg = { .name = "qhs_usb4_2_cfg", - .id = X1E80100_SLAVE_USB4_2, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_venus_cfg = { .name = "qhs_venus_cfg", - .id = X1E80100_SLAVE_VENUS_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qss_lpass_qtb_cfg = { .name = "qss_lpass_qtb_cfg", - .id = X1E80100_SLAVE_LPASS_QTB_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qss_mnoc_cfg = { .name = "qss_mnoc_cfg", - .id = X1E80100_SLAVE_CNOC_MNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { X1E80100_MASTER_CNOC_MNOC_CFG }, + .link_nodes = { &qsm_mnoc_cfg }, }; static struct qcom_icc_node qss_nsp_qtb_cfg = { .name = "qss_nsp_qtb_cfg", - .id = X1E80100_SLAVE_NSP_QTB_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", - .id = X1E80100_SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", - .id = X1E80100_SLAVE_TCU, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", - .id = X1E80100_SLAVE_AOSS, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qhs_tme_cfg = { .name = "qhs_tme_cfg", - .id = X1E80100_SLAVE_TME_CFG, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_apss = { .name = "qns_apss", - .id = X1E80100_SLAVE_APPSS, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node qss_cfg = { .name = "qss_cfg", - .id = X1E80100_SLAVE_CNOC_CFG, .channels = 1, .buswidth = 4, .num_links = 1, - .links = { X1E80100_MASTER_CNOC_CFG }, + .link_nodes = { &qsm_cfg }, }; static struct qcom_icc_node qxs_boot_imem = { .name = "qxs_boot_imem", - .id = X1E80100_SLAVE_BOOT_IMEM, .channels = 1, .buswidth = 16, - .num_links = 0, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", - .id = X1E80100_SLAVE_IMEM, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_0 = { .name = "xs_pcie_0", - .id = X1E80100_SLAVE_PCIE_0, .channels = 1, .buswidth = 16, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_1 = { .name = "xs_pcie_1", - .id = X1E80100_SLAVE_PCIE_1, .channels = 1, .buswidth = 16, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_2 = { .name = "xs_pcie_2", - .id = X1E80100_SLAVE_PCIE_2, .channels = 1, .buswidth = 16, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_3 = { .name = "xs_pcie_3", - .id = X1E80100_SLAVE_PCIE_3, .channels = 1, .buswidth = 64, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_4 = { .name = "xs_pcie_4", - .id = X1E80100_SLAVE_PCIE_4, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_5 = { .name = "xs_pcie_5", - .id = X1E80100_SLAVE_PCIE_5, .channels = 1, .buswidth = 8, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_6a = { .name = "xs_pcie_6a", - .id = X1E80100_SLAVE_PCIE_6A, .channels = 1, .buswidth = 32, - .num_links = 0, }; static struct qcom_icc_node xs_pcie_6b = { .name = "xs_pcie_6b", - .id = X1E80100_SLAVE_PCIE_6B, .channels = 1, .buswidth = 16, - .num_links = 0, }; static struct qcom_icc_node qns_gem_noc_cnoc = { .name = "qns_gem_noc_cnoc", - .id = X1E80100_SLAVE_GEM_NOC_CNOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_MASTER_GEM_NOC_CNOC }, + .link_nodes = { &qnm_gemnoc_cnoc }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", - .id = X1E80100_SLAVE_LLCC, .channels = 8, .buswidth = 16, .num_links = 1, - .links = { X1E80100_MASTER_LLCC }, + .link_nodes = { &llcc_mc }, }; static struct qcom_icc_node qns_pcie = { .name = "qns_pcie", - .id = X1E80100_SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 32, .num_links = 1, - .links = { X1E80100_MASTER_GEM_NOC_PCIE_SNOC }, + .link_nodes = { &qnm_gemnoc_pcie }, }; static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { .name = "qns_lpass_ag_noc_gemnoc", - .id = X1E80100_SLAVE_LPASS_GEM_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_MASTER_LPASS_GEM_NOC }, + .link_nodes = { &qnm_lpass }, }; static struct qcom_icc_node qns_lpass_aggnoc = { .name = "qns_lpass_aggnoc", - .id = X1E80100_SLAVE_LPIAON_NOC_LPASS_AG_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_MASTER_LPIAON_NOC }, + .link_nodes = { &qnm_lpiaon_noc }, }; static struct qcom_icc_node qns_lpi_aon_noc = { .name = "qns_lpi_aon_noc", - .id = X1E80100_SLAVE_LPICX_NOC_LPIAON_NOC, .channels = 1, .buswidth = 16, .num_links = 1, - .links = { X1E80100_MASTER_LPASS_LPINOC }, + .link_nodes = { &qnm_lpass_lpinoc }, }; static struct qcom_icc_node ebi = { .name = "ebi", - .id = X1E80100_SLAVE_EBI1, .channels = 8, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", - .id = X1E80100_SLAVE_MNOC_HF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { X1E80100_MASTER_MNOC_HF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_hf }, }; static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", - .id = X1E80100_SLAVE_MNOC_SF_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { X1E80100_MASTER_MNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_mnoc_sf }, }; static struct qcom_icc_node srvc_mnoc = { .name = "srvc_mnoc", - .id = X1E80100_SLAVE_SERVICE_MNOC, .channels = 1, .buswidth = 4, - .num_links = 0, }; static struct qcom_icc_node qns_nsp_gemnoc = { .name = "qns_nsp_gemnoc", - .id = X1E80100_SLAVE_CDSP_MEM_NOC, .channels = 2, .buswidth = 32, .num_links = 1, - .links = { X1E80100_MASTER_COMPUTE_NOC }, + .link_nodes = { &qnm_nsp_noc }, }; static struct qcom_icc_node qns_pcie_mem_noc = { .name = "qns_pcie_mem_noc", - .id = X1E80100_SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_MASTER_ANOC_PCIE_GEM_NOC }, + .link_nodes = { &qnm_pcie }, }; static struct qcom_icc_node qns_pcie_north_gem_noc = { .name = "qns_pcie_north_gem_noc", - .id = X1E80100_SLAVE_PCIE_NORTH, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_MASTER_PCIE_NORTH }, + .link_nodes = { &qnm_pcie_north_gem_noc }, }; static struct qcom_icc_node qns_pcie_south_gem_noc = { .name = "qns_pcie_south_gem_noc", - .id = X1E80100_SLAVE_PCIE_SOUTH, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_MASTER_PCIE_SOUTH }, + .link_nodes = { &qnm_pcie_south_gem_noc }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", - .id = X1E80100_SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_MASTER_SNOC_SF_MEM_NOC }, + .link_nodes = { &qnm_snoc_sf }, }; static struct qcom_icc_node qns_aggre_usb_snoc = { .name = "qns_aggre_usb_snoc", - .id = X1E80100_SLAVE_USB_NOC_SNOC, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_MASTER_USB_NOC_SNOC }, + .link_nodes = { &qnm_usb_anoc }, }; static struct qcom_icc_node qns_aggre_usb_north_snoc = { .name = "qns_aggre_usb_north_snoc", - .id = X1E80100_SLAVE_AGGRE_USB_NORTH, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_MASTER_AGGRE_USB_NORTH }, + .link_nodes = { &qnm_aggre_usb_north_snoc }, }; static struct qcom_icc_node qns_aggre_usb_south_snoc = { .name = "qns_aggre_usb_south_snoc", - .id = X1E80100_SLAVE_AGGRE_USB_SOUTH, .channels = 1, .buswidth = 64, .num_links = 1, - .links = { X1E80100_MASTER_AGGRE_USB_SOUTH }, + .link_nodes = { &qnm_aggre_usb_south_snoc }, }; static struct qcom_icc_bcm bcm_acv = { @@ -1964,7 +1900,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, - .remove_new = qcom_icc_rpmh_remove, + .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-x1e80100", .of_match_table = qnoc_of_match, diff --git a/drivers/interconnect/qcom/x1e80100.h b/drivers/interconnect/qcom/x1e80100.h deleted file mode 100644 index 2e14264f4c2b..000000000000 --- a/drivers/interconnect/qcom/x1e80100.h +++ /dev/null @@ -1,192 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * X1E80100 interconnect IDs - * - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. - * Copyright (c) 2023, Linaro Limited - */ - -#ifndef __DRIVERS_INTERCONNECT_QCOM_X1E80100_H -#define __DRIVERS_INTERCONNECT_QCOM_X1E80100_H - -#define X1E80100_MASTER_A1NOC_SNOC 0 -#define X1E80100_MASTER_A2NOC_SNOC 1 -#define X1E80100_MASTER_ANOC_PCIE_GEM_NOC 2 -#define X1E80100_MASTER_ANOC_PCIE_GEM_NOC_DISP 3 -#define X1E80100_MASTER_APPSS_PROC 4 -#define X1E80100_MASTER_CAMNOC_HF 5 -#define X1E80100_MASTER_CAMNOC_ICP 6 -#define X1E80100_MASTER_CAMNOC_SF 7 -#define X1E80100_MASTER_CDSP_PROC 8 -#define X1E80100_MASTER_CNOC_CFG 9 -#define X1E80100_MASTER_CNOC_MNOC_CFG 10 -#define X1E80100_MASTER_COMPUTE_NOC 11 -#define X1E80100_MASTER_CRYPTO 12 -#define X1E80100_MASTER_GEM_NOC_CNOC 13 -#define X1E80100_MASTER_GEM_NOC_PCIE_SNOC 14 -#define X1E80100_MASTER_GFX3D 15 -#define X1E80100_MASTER_GPU_TCU 16 -#define X1E80100_MASTER_IPA 17 -#define X1E80100_MASTER_LLCC 18 -#define X1E80100_MASTER_LLCC_DISP 19 -#define X1E80100_MASTER_LPASS_GEM_NOC 20 -#define X1E80100_MASTER_LPASS_LPINOC 21 -#define X1E80100_MASTER_LPASS_PROC 22 -#define X1E80100_MASTER_LPIAON_NOC 23 -#define X1E80100_MASTER_MDP 24 -#define X1E80100_MASTER_MDP_DISP 25 -#define X1E80100_MASTER_MNOC_HF_MEM_NOC 26 -#define X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP 27 -#define X1E80100_MASTER_MNOC_SF_MEM_NOC 28 -#define X1E80100_MASTER_PCIE_0 29 -#define X1E80100_MASTER_PCIE_1 30 -#define X1E80100_MASTER_QDSS_ETR 31 -#define X1E80100_MASTER_QDSS_ETR_1 32 -#define X1E80100_MASTER_QSPI_0 33 -#define X1E80100_MASTER_QUP_0 34 -#define X1E80100_MASTER_QUP_1 35 -#define X1E80100_MASTER_QUP_2 36 -#define X1E80100_MASTER_QUP_CORE_0 37 -#define X1E80100_MASTER_QUP_CORE_1 38 -#define X1E80100_MASTER_SDCC_2 39 -#define X1E80100_MASTER_SDCC_4 40 -#define X1E80100_MASTER_SNOC_SF_MEM_NOC 41 -#define X1E80100_MASTER_SP 42 -#define X1E80100_MASTER_SYS_TCU 43 -#define X1E80100_MASTER_UFS_MEM 44 -#define X1E80100_MASTER_USB3_0 45 -#define X1E80100_MASTER_VIDEO 46 -#define X1E80100_MASTER_VIDEO_CV_PROC 47 -#define X1E80100_MASTER_VIDEO_V_PROC 48 -#define X1E80100_SLAVE_A1NOC_SNOC 49 -#define X1E80100_SLAVE_A2NOC_SNOC 50 -#define X1E80100_SLAVE_AHB2PHY_NORTH 51 -#define X1E80100_SLAVE_AHB2PHY_SOUTH 52 -#define X1E80100_SLAVE_ANOC_PCIE_GEM_NOC 53 -#define X1E80100_SLAVE_AOSS 54 -#define X1E80100_SLAVE_APPSS 55 -#define X1E80100_SLAVE_BOOT_IMEM 56 -#define X1E80100_SLAVE_CAMERA_CFG 57 -#define X1E80100_SLAVE_CDSP_MEM_NOC 58 -#define X1E80100_SLAVE_CLK_CTL 59 -#define X1E80100_SLAVE_CNOC_CFG 60 -#define X1E80100_SLAVE_CNOC_MNOC_CFG 61 -#define X1E80100_SLAVE_CRYPTO_0_CFG 62 -#define X1E80100_SLAVE_DISPLAY_CFG 63 -#define X1E80100_SLAVE_EBI1 64 -#define X1E80100_SLAVE_EBI1_DISP 65 -#define X1E80100_SLAVE_GEM_NOC_CNOC 66 -#define X1E80100_SLAVE_GFX3D_CFG 67 -#define X1E80100_SLAVE_IMEM 68 -#define X1E80100_SLAVE_IMEM_CFG 69 -#define X1E80100_SLAVE_IPC_ROUTER_CFG 70 -#define X1E80100_SLAVE_LLCC 71 -#define X1E80100_SLAVE_LLCC_DISP 72 -#define X1E80100_SLAVE_LPASS_GEM_NOC 73 -#define X1E80100_SLAVE_LPASS_QTB_CFG 74 -#define X1E80100_SLAVE_LPIAON_NOC_LPASS_AG_NOC 75 -#define X1E80100_SLAVE_LPICX_NOC_LPIAON_NOC 76 -#define X1E80100_SLAVE_MEM_NOC_PCIE_SNOC 77 -#define X1E80100_SLAVE_MNOC_HF_MEM_NOC 78 -#define X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP 79 -#define X1E80100_SLAVE_MNOC_SF_MEM_NOC 80 -#define X1E80100_SLAVE_NSP_QTB_CFG 81 -#define X1E80100_SLAVE_PCIE_0 82 -#define X1E80100_SLAVE_PCIE_0_CFG 83 -#define X1E80100_SLAVE_PCIE_1 84 -#define X1E80100_SLAVE_PCIE_1_CFG 85 -#define X1E80100_SLAVE_PDM 86 -#define X1E80100_SLAVE_PRNG 87 -#define X1E80100_SLAVE_QDSS_CFG 88 -#define X1E80100_SLAVE_QDSS_STM 89 -#define X1E80100_SLAVE_QSPI_0 90 -#define X1E80100_SLAVE_QUP_1 91 -#define X1E80100_SLAVE_QUP_2 92 -#define X1E80100_SLAVE_QUP_CORE_0 93 -#define X1E80100_SLAVE_QUP_CORE_1 94 -#define X1E80100_SLAVE_QUP_CORE_2 95 -#define X1E80100_SLAVE_SDCC_2 96 -#define X1E80100_SLAVE_SDCC_4 97 -#define X1E80100_SLAVE_SERVICE_MNOC 98 -#define X1E80100_SLAVE_SNOC_GEM_NOC_SF 99 -#define X1E80100_SLAVE_TCSR 100 -#define X1E80100_SLAVE_TCU 101 -#define X1E80100_SLAVE_TLMM 102 -#define X1E80100_SLAVE_TME_CFG 103 -#define X1E80100_SLAVE_UFS_MEM_CFG 104 -#define X1E80100_SLAVE_USB3_0 105 -#define X1E80100_SLAVE_VENUS_CFG 106 -#define X1E80100_MASTER_DDR_PERF_MODE 107 -#define X1E80100_MASTER_QUP_CORE_2 108 -#define X1E80100_MASTER_PCIE_TCU 109 -#define X1E80100_MASTER_GIC2 110 -#define X1E80100_MASTER_AV1_ENC 111 -#define X1E80100_MASTER_EVA 112 -#define X1E80100_MASTER_PCIE_NORTH 113 -#define X1E80100_MASTER_PCIE_SOUTH 114 -#define X1E80100_MASTER_PCIE_3 115 -#define X1E80100_MASTER_PCIE_4 116 -#define X1E80100_MASTER_PCIE_5 117 -#define X1E80100_MASTER_PCIE_2 118 -#define X1E80100_MASTER_PCIE_6A 119 -#define X1E80100_MASTER_PCIE_6B 120 -#define X1E80100_MASTER_GIC1 121 -#define X1E80100_MASTER_USB_NOC_SNOC 122 -#define X1E80100_MASTER_AGGRE_USB_NORTH 123 -#define X1E80100_MASTER_AGGRE_USB_SOUTH 124 -#define X1E80100_MASTER_USB2 125 -#define X1E80100_MASTER_USB3_MP 126 -#define X1E80100_MASTER_USB3_1 127 -#define X1E80100_MASTER_USB3_2 128 -#define X1E80100_MASTER_USB4_0 129 -#define X1E80100_MASTER_USB4_1 130 -#define X1E80100_MASTER_USB4_2 131 -#define X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE 132 -#define X1E80100_MASTER_LLCC_PCIE 133 -#define X1E80100_MASTER_PCIE_NORTH_PCIE 134 -#define X1E80100_MASTER_PCIE_SOUTH_PCIE 135 -#define X1E80100_MASTER_PCIE_3_PCIE 136 -#define X1E80100_MASTER_PCIE_4_PCIE 137 -#define X1E80100_MASTER_PCIE_5_PCIE 138 -#define X1E80100_MASTER_PCIE_0_PCIE 139 -#define X1E80100_MASTER_PCIE_1_PCIE 140 -#define X1E80100_MASTER_PCIE_2_PCIE 141 -#define X1E80100_MASTER_PCIE_6A_PCIE 142 -#define X1E80100_MASTER_PCIE_6B_PCIE 143 -#define X1E80100_SLAVE_AHB2PHY_2 144 -#define X1E80100_SLAVE_AV1_ENC_CFG 145 -#define X1E80100_SLAVE_PCIE_2_CFG 146 -#define X1E80100_SLAVE_PCIE_3_CFG 147 -#define X1E80100_SLAVE_PCIE_4_CFG 148 -#define X1E80100_SLAVE_PCIE_5_CFG 149 -#define X1E80100_SLAVE_PCIE_6A_CFG 150 -#define X1E80100_SLAVE_PCIE_6B_CFG 151 -#define X1E80100_SLAVE_PCIE_RSC_CFG 152 -#define X1E80100_SLAVE_QUP_0 153 -#define X1E80100_SLAVE_SMMUV3_CFG 154 -#define X1E80100_SLAVE_USB2 155 -#define X1E80100_SLAVE_USB3_1 156 -#define X1E80100_SLAVE_USB3_2 157 -#define X1E80100_SLAVE_USB3_MP 158 -#define X1E80100_SLAVE_USB4_0 159 -#define X1E80100_SLAVE_USB4_1 160 -#define X1E80100_SLAVE_USB4_2 161 -#define X1E80100_SLAVE_PCIE_2 162 -#define X1E80100_SLAVE_PCIE_3 163 -#define X1E80100_SLAVE_PCIE_4 164 -#define X1E80100_SLAVE_PCIE_5 165 -#define X1E80100_SLAVE_PCIE_6A 166 -#define X1E80100_SLAVE_PCIE_6B 167 -#define X1E80100_SLAVE_DDR_PERF_MODE 168 -#define X1E80100_SLAVE_PCIE_NORTH 169 -#define X1E80100_SLAVE_PCIE_SOUTH 170 -#define X1E80100_SLAVE_USB_NOC_SNOC 171 -#define X1E80100_SLAVE_AGGRE_USB_NORTH 172 -#define X1E80100_SLAVE_AGGRE_USB_SOUTH 173 -#define X1E80100_SLAVE_LLCC_PCIE 174 -#define X1E80100_SLAVE_EBI1_PCIE 175 -#define X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE 176 -#define X1E80100_SLAVE_PCIE_NORTH_PCIE 177 -#define X1E80100_SLAVE_PCIE_SOUTH_PCIE 178 - -#endif diff --git a/drivers/interconnect/samsung/exynos.c b/drivers/interconnect/samsung/exynos.c index c9e5361e17c5..8e8f56186a36 100644 --- a/drivers/interconnect/samsung/exynos.c +++ b/drivers/interconnect/samsung/exynos.c @@ -134,6 +134,11 @@ static int exynos_generic_icc_probe(struct platform_device *pdev) priv->node = icc_node; icc_node->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%pOFn", bus_dev->of_node); + if (!icc_node->name) { + icc_node_destroy(pdev->id); + return -ENOMEM; + } + if (of_property_read_u32(bus_dev->of_node, "samsung,data-clock-ratio", &priv->bus_clk_ratio)) priv->bus_clk_ratio = EXYNOS_ICC_DEFAULT_BUS_CLK_RATIO; @@ -180,7 +185,7 @@ static struct platform_driver exynos_generic_icc_driver = { .sync_state = icc_sync_state, }, .probe = exynos_generic_icc_probe, - .remove_new = exynos_generic_icc_remove, + .remove = exynos_generic_icc_remove, }; module_platform_driver(exynos_generic_icc_driver); |