summaryrefslogtreecommitdiff
path: root/drivers/media/tuners/mxl5005s.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/media/tuners/mxl5005s.c')
-rw-r--r--drivers/media/tuners/mxl5005s.c87
1 files changed, 49 insertions, 38 deletions
diff --git a/drivers/media/tuners/mxl5005s.c b/drivers/media/tuners/mxl5005s.c
index dd59c2c0e4a5..0e811c5eae6c 100644
--- a/drivers/media/tuners/mxl5005s.c
+++ b/drivers/media/tuners/mxl5005s.c
@@ -63,7 +63,7 @@
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/delay.h>
-#include "dvb_frontend.h"
+#include <media/dvb_frontend.h>
#include "mxl5005s.h"
static int debug;
@@ -1677,10 +1677,10 @@ static u16 MXL5005_TunerConfig(struct dvb_frontend *fe,
u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */
u16 TOP, /* 0: Dual AGC; Value: take over point */
u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */
- u8 CLOCK_OUT, /* 0: turn off clk out; 1: turn on clock out */
+ u8 CLOCK_OUT, /* 0: turn off clk out; 1: turn on clock out */
u8 DIV_OUT, /* 0: Div-1; 1: Div-4 */
- u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */
- u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */
+ u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */
+ u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */
/* Modulation Type; */
/* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
@@ -2639,7 +2639,7 @@ static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
E5A = (((Fmax - state->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ;
status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A);
- /* Euqation E5B CHCAL_EN_INIT_RF */
+ /* Equation E5B CHCAL_EN_INIT_RF */
status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0));
/*if (E5 == 0)
* status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1);
@@ -3414,9 +3414,8 @@ static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum,
u32 value, u16 controlGroup)
{
struct mxl5005s_state *state = fe->tuner_priv;
- u16 i, j, k;
+ u16 i, j;
u32 highLimit;
- u32 ctrlVal;
if (controlGroup == 1) /* Initial Control */ {
@@ -3424,17 +3423,16 @@ static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum,
if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
- highLimit = 1 << state->Init_Ctrl[i].size;
+ u16 size = min_t(u16, state->Init_Ctrl[i].size,
+ ARRAY_SIZE(state->Init_Ctrl[i].val));
+ highLimit = 1 << size;
if (value < highLimit) {
- for (j = 0; j < state->Init_Ctrl[i].size; j++) {
+ for (j = 0; j < size; j++) {
state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]),
(u8)(state->Init_Ctrl[i].bit[j]),
(u8)((value>>j) & 0x01));
}
- ctrlVal = 0;
- for (k = 0; k < state->Init_Ctrl[i].size; k++)
- ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k);
} else
return -1;
}
@@ -3446,17 +3444,16 @@ static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum,
if (controlNum == state->CH_Ctrl[i].Ctrl_Num) {
- highLimit = 1 << state->CH_Ctrl[i].size;
+ u16 size = min_t(u16, state->CH_Ctrl[i].size,
+ ARRAY_SIZE(state->CH_Ctrl[i].val));
+ highLimit = 1 << size;
if (value < highLimit) {
- for (j = 0; j < state->CH_Ctrl[i].size; j++) {
+ for (j = 0; j < size; j++) {
state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]),
(u8)(state->CH_Ctrl[i].bit[j]),
(u8)((value>>j) & 0x01));
}
- ctrlVal = 0;
- for (k = 0; k < state->CH_Ctrl[i].size; k++)
- ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k);
} else
return -1;
}
@@ -3477,11 +3474,6 @@ static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum,
(u8)(state->MXL_Ctrl[i].bit[j]),
(u8)((value>>j) & 0x01));
}
- ctrlVal = 0;
- for (k = 0; k < state->MXL_Ctrl[i].size; k++)
- ctrlVal += state->
- MXL_Ctrl[i].val[k] *
- (1 << k);
} else
return -1;
}
@@ -3584,17 +3576,18 @@ static u32 MXL_Ceiling(u32 value, u32 resolution)
return value / resolution + (value % resolution > 0 ? 1 : 0);
}
-/* Retrieve the Initialzation Registers */
+/* Retrieve the Initialization Registers */
static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum,
u8 *RegVal, int *count)
{
u16 status = 0;
int i ;
- u8 RegAddr[] = {
+ static const u8 RegAddr[] = {
11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73,
76, 77, 91, 134, 135, 137, 147,
- 156, 166, 167, 168, 25 };
+ 156, 166, 167, 168, 25
+ };
*count = ARRAY_SIZE(RegAddr);
@@ -3616,11 +3609,15 @@ static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal,
/* add 77, 166, 167, 168 register for 2.6.12 */
#ifdef _MXL_PRODUCTION
- u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106,
- 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ;
+ static const u8 RegAddr[] = {
+ 14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106,
+ 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168
+ };
#else
- u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106,
- 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ;
+ static const u8 RegAddr[] = {
+ 14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106,
+ 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168
+ };
/*
u8 RegAddr[171];
for (i = 0; i <= 170; i++)
@@ -3644,7 +3641,7 @@ static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum,
u16 status = 0;
int i;
- u8 RegAddr[] = {43, 136};
+ static const u8 RegAddr[] = {43, 136};
*count = ARRAY_SIZE(RegAddr);
@@ -3921,15 +3918,26 @@ static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type,
u32 bandwidth)
{
struct mxl5005s_state *state = fe->tuner_priv;
-
- u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
- u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
+ u8 *AddrTable;
+ u8 *ByteTable;
int TableLen;
dprintk(1, "%s(type=%d, bw=%d)\n", __func__, mod_type, bandwidth);
mxl5005s_reset(fe);
+ AddrTable = kcalloc(MXL5005S_REG_WRITING_TABLE_LEN_MAX, sizeof(u8),
+ GFP_KERNEL);
+ if (!AddrTable)
+ return -ENOMEM;
+
+ ByteTable = kcalloc(MXL5005S_REG_WRITING_TABLE_LEN_MAX, sizeof(u8),
+ GFP_KERNEL);
+ if (!ByteTable) {
+ kfree(AddrTable);
+ return -ENOMEM;
+ }
+
/* Tuner initialization stage 0 */
MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
AddrTable[0] = MASTER_CONTROL_ADDR;
@@ -3944,6 +3952,9 @@ static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type,
mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
+ kfree(AddrTable);
+ kfree(ByteTable);
+
return 0;
}
@@ -4070,10 +4081,10 @@ static void mxl5005s_release(struct dvb_frontend *fe)
static const struct dvb_tuner_ops mxl5005s_tuner_ops = {
.info = {
- .name = "MaxLinear MXL5005S",
- .frequency_min = 48000000,
- .frequency_max = 860000000,
- .frequency_step = 50000,
+ .name = "MaxLinear MXL5005S",
+ .frequency_min_hz = 48 * MHz,
+ .frequency_max_hz = 860 * MHz,
+ .frequency_step_hz = 50 * kHz,
},
.release = mxl5005s_release,
@@ -4109,7 +4120,7 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
fe->tuner_priv = state;
return fe;
}
-EXPORT_SYMBOL(mxl5005s_attach);
+EXPORT_SYMBOL_GPL(mxl5005s_attach);
MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver");
MODULE_AUTHOR("Steven Toth");
generated by cgit (git 2.34.1) at 2025-12-30 04:31:05 +0000