diff options
Diffstat (limited to 'drivers/mmc/host/sdhci-omap.c')
| -rw-r--r-- | drivers/mmc/host/sdhci-omap.c | 511 |
1 files changed, 415 insertions, 96 deletions
diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c index c11c18a9aacb..b5d7c1a80a92 100644 --- a/drivers/mmc/host/sdhci-omap.c +++ b/drivers/mmc/host/sdhci-omap.c @@ -1,29 +1,20 @@ -/** +// SPDX-License-Identifier: GPL-2.0-only +/* * SDHCI Controller driver for TI's OMAP SoCs * * Copyright (C) 2017 Texas Instruments * Author: Kishon Vijay Abraham I <kishon@ti.com> - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 of - * the License as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <linux/delay.h> +#include <linux/mmc/mmc.h> #include <linux/mmc/slot-gpio.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> +#include <linux/of_irq.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> +#include <linux/pm_wakeirq.h> #include <linux/regulator/consumer.h> #include <linux/pinctrl/consumer.h> #include <linux/sys_soc.h> @@ -31,7 +22,14 @@ #include "sdhci-pltfm.h" -#define SDHCI_OMAP_CON 0x12c +/* + * Note that the register offsets used here are from omap_regs + * base which is 0x100 for omap4 and later, and 0 for omap3 and + * earlier. + */ +#define SDHCI_OMAP_SYSCONFIG 0x10 + +#define SDHCI_OMAP_CON 0x2c #define CON_DW8 BIT(5) #define CON_DMA_MASTER BIT(20) #define CON_DDR BIT(19) @@ -41,20 +39,20 @@ #define CON_INIT BIT(1) #define CON_OD BIT(0) -#define SDHCI_OMAP_DLL 0x0134 +#define SDHCI_OMAP_DLL 0x34 #define DLL_SWT BIT(20) #define DLL_FORCE_SR_C_SHIFT 13 #define DLL_FORCE_SR_C_MASK (0x7f << DLL_FORCE_SR_C_SHIFT) #define DLL_FORCE_VALUE BIT(12) #define DLL_CALIB BIT(1) -#define SDHCI_OMAP_CMD 0x20c +#define SDHCI_OMAP_CMD 0x10c -#define SDHCI_OMAP_PSTATE 0x0224 +#define SDHCI_OMAP_PSTATE 0x124 #define PSTATE_DLEV_DAT0 BIT(20) #define PSTATE_DATI BIT(1) -#define SDHCI_OMAP_HCTL 0x228 +#define SDHCI_OMAP_HCTL 0x128 #define HCTL_SDBP BIT(8) #define HCTL_SDVS_SHIFT 9 #define HCTL_SDVS_MASK (0x7 << HCTL_SDVS_SHIFT) @@ -62,26 +60,28 @@ #define HCTL_SDVS_30 (0x6 << HCTL_SDVS_SHIFT) #define HCTL_SDVS_18 (0x5 << HCTL_SDVS_SHIFT) -#define SDHCI_OMAP_SYSCTL 0x22c +#define SDHCI_OMAP_SYSCTL 0x12c #define SYSCTL_CEN BIT(2) #define SYSCTL_CLKD_SHIFT 6 #define SYSCTL_CLKD_MASK 0x3ff -#define SDHCI_OMAP_STAT 0x230 +#define SDHCI_OMAP_STAT 0x130 -#define SDHCI_OMAP_IE 0x234 +#define SDHCI_OMAP_IE 0x134 #define INT_CC_EN BIT(0) -#define SDHCI_OMAP_AC12 0x23c +#define SDHCI_OMAP_ISE 0x138 + +#define SDHCI_OMAP_AC12 0x13c #define AC12_V1V8_SIGEN BIT(19) #define AC12_SCLK_SEL BIT(23) -#define SDHCI_OMAP_CAPA 0x240 +#define SDHCI_OMAP_CAPA 0x140 #define CAPA_VS33 BIT(24) #define CAPA_VS30 BIT(25) #define CAPA_VS18 BIT(26) -#define SDHCI_OMAP_CAPA2 0x0244 +#define SDHCI_OMAP_CAPA2 0x144 #define CAPA2_TSDR50 BIT(13) #define SDHCI_OMAP_TIMEOUT 1 /* 1 msec */ @@ -96,9 +96,11 @@ /* sdhci-omap controller flags */ #define SDHCI_OMAP_REQUIRE_IODELAY BIT(0) +#define SDHCI_OMAP_SPECIAL_RESET BIT(1) struct sdhci_omap_data { - u32 offset; + int omap_offset; /* Offset for omap regs from base */ + u32 offset; /* Offset for SDHCI regs from base */ u8 flags; }; @@ -116,7 +118,19 @@ struct sdhci_omap_host { struct pinctrl *pinctrl; struct pinctrl_state **pinctrl_state; + int wakeirq; bool is_tuning; + + /* Offset for omap specific registers from base */ + int omap_offset; + + /* Omap specific context save */ + u32 con; + u32 hctl; + u32 sysctl; + u32 capa; + u32 ie; + u32 ise; }; static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host); @@ -125,13 +139,13 @@ static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host); static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host, unsigned int offset) { - return readl(host->base + offset); + return readl(host->base + host->omap_offset + offset); } static inline void sdhci_omap_writel(struct sdhci_omap_host *host, unsigned int offset, u32 data) { - writel(data, host->base + offset); + writel(data, host->base + host->omap_offset + offset); } static int sdhci_omap_set_pbias(struct sdhci_omap_host *omap_host, @@ -176,7 +190,7 @@ static int sdhci_omap_set_pbias(struct sdhci_omap_host *omap_host, } static int sdhci_omap_enable_iov(struct sdhci_omap_host *omap_host, - unsigned int iov) + unsigned int iov_pbias) { int ret; struct sdhci_host *host = omap_host->host; @@ -187,14 +201,15 @@ static int sdhci_omap_enable_iov(struct sdhci_omap_host *omap_host, return ret; if (!IS_ERR(mmc->supply.vqmmc)) { - ret = regulator_set_voltage(mmc->supply.vqmmc, iov, iov); - if (ret) { + /* Pick the right voltage to allow 3.0V for 3.3V nominal PBIAS */ + ret = mmc_regulator_set_vqmmc(mmc, &mmc->ios); + if (ret < 0) { dev_err(mmc_dev(mmc), "vqmmc set voltage failed\n"); return ret; } } - ret = sdhci_omap_set_pbias(omap_host, true, iov); + ret = sdhci_omap_set_pbias(omap_host, true, iov_pbias); if (ret) return ret; @@ -204,16 +219,28 @@ static int sdhci_omap_enable_iov(struct sdhci_omap_host *omap_host, static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host, unsigned char signal_voltage) { - u32 reg; + u32 reg, capa; ktime_t timeout; reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL); reg &= ~HCTL_SDVS_MASK; - if (signal_voltage == MMC_SIGNAL_VOLTAGE_330) - reg |= HCTL_SDVS_33; - else + switch (signal_voltage) { + case MMC_SIGNAL_VOLTAGE_330: + capa = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA); + if (capa & CAPA_VS33) + reg |= HCTL_SDVS_33; + else if (capa & CAPA_VS30) + reg |= HCTL_SDVS_30; + else + dev_warn(omap_host->dev, "misconfigured CAPA: %08x\n", + capa); + break; + case MMC_SIGNAL_VOLTAGE_180: + default: reg |= HCTL_SDVS_18; + break; + } sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg); @@ -342,7 +369,7 @@ static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode) /* * Stage 1: Search for a maximum pass window ignoring any - * any single point failures. If the tuning value ends up + * single point failures. If the tuning value ends up * near it, move away from it in stage 2 below */ while (phase_delay <= MAX_PHASE_DELAY) { @@ -383,7 +410,7 @@ static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode) * on temperature */ if (temperature < -20000) - phase_delay = min(max_window + 4 * max_len - 24, + phase_delay = min(max_window + 4 * (max_len - 1) - 24, max_window + DIV_ROUND_UP(13 * max_len, 16) * 4); else if (temperature < 20000) @@ -531,28 +558,32 @@ static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc, if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA); - if (!(reg & CAPA_VS33)) + if (!(reg & (CAPA_VS30 | CAPA_VS33))) return -EOPNOTSUPP; + if (reg & CAPA_VS30) + iov = IOV_3V0; + else + iov = IOV_3V3; + sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage); reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12); reg &= ~AC12_V1V8_SIGEN; sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg); - iov = IOV_3V3; } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA); if (!(reg & CAPA_VS18)) return -EOPNOTSUPP; + iov = IOV_1V8; + sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage); reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12); reg |= AC12_V1V8_SIGEN; sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg); - - iov = IOV_1V8; } else { return -EOPNOTSUPP; } @@ -686,7 +717,24 @@ static void sdhci_omap_set_power(struct sdhci_host *host, unsigned char mode, { struct mmc_host *mmc = host->mmc; - mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); + if (!IS_ERR(mmc->supply.vmmc)) + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); +} + +/* + * MMCHS_HL_HWINFO has the MADMA_EN bit set if the controller instance + * is connected to L3 interconnect and is bus master capable. Note that + * the MMCHS_HL_HWINFO register is in the module registers before the + * omap registers and sdhci registers. The offset can vary for omap + * registers depending on the SoC. Do not use sdhci_omap_readl() here. + */ +static bool sdhci_omap_has_adma(struct sdhci_omap_host *omap_host, int offset) +{ + /* MMCHS_HL_HWINFO register is only available on omap4 and later */ + if (offset < 0x200) + return false; + + return readl(omap_host->base + 4) & 1; } static int sdhci_omap_enable_dma(struct sdhci_host *host) @@ -696,7 +744,11 @@ static int sdhci_omap_enable_dma(struct sdhci_host *host) struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); - reg |= CON_DMA_MASTER; + reg &= ~CON_DMA_MASTER; + /* Switch to DMA slave mode when using external DMA */ + if (!host->use_external_dma) + reg |= CON_DMA_MASTER; + sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); return 0; @@ -785,19 +837,95 @@ static void sdhci_omap_set_uhs_signaling(struct sdhci_host *host, sdhci_omap_start_clock(omap_host); } -void sdhci_omap_reset(struct sdhci_host *host, u8 mask) +#define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ +static void sdhci_omap_reset(struct sdhci_host *host, u8 mask) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); + unsigned long limit = MMC_TIMEOUT_US; + unsigned long i = 0; + u32 sysc; + + /* Save target module sysconfig configured by SoC PM layer */ + if (mask & SDHCI_RESET_ALL) + sysc = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCONFIG); /* Don't reset data lines during tuning operation */ if (omap_host->is_tuning) mask &= ~SDHCI_RESET_DATA; + if (omap_host->flags & SDHCI_OMAP_SPECIAL_RESET) { + sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); + while ((!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)) && + (i++ < limit)) + udelay(1); + i = 0; + while ((sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) && + (i++ < limit)) + udelay(1); + + if (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) + dev_err(mmc_dev(host->mmc), + "Timeout waiting on controller reset in %s\n", + __func__); + + goto restore_sysc; + } + sdhci_reset(host, mask); + +restore_sysc: + if (mask & SDHCI_RESET_ALL) + sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCONFIG, sysc); +} + +#define CMD_ERR_MASK (SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX |\ + SDHCI_INT_TIMEOUT) +#define CMD_MASK (CMD_ERR_MASK | SDHCI_INT_RESPONSE) + +static u32 sdhci_omap_irq(struct sdhci_host *host, u32 intmask) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); + + if (omap_host->is_tuning && host->cmd && !host->data_early && + (intmask & CMD_ERR_MASK)) { + + /* + * Since we are not resetting data lines during tuning + * operation, data error or data complete interrupts + * might still arrive. Mark this request as a failure + * but still wait for the data interrupt + */ + if (intmask & SDHCI_INT_TIMEOUT) + host->cmd->error = -ETIMEDOUT; + else + host->cmd->error = -EILSEQ; + + host->cmd = NULL; + + /* + * Sometimes command error interrupts and command complete + * interrupt will arrive together. Clear all command related + * interrupts here. + */ + sdhci_writel(host, intmask & CMD_MASK, SDHCI_INT_STATUS); + intmask &= ~CMD_MASK; + } + + return intmask; } -static struct sdhci_ops sdhci_omap_ops = { +static void sdhci_omap_set_timeout(struct sdhci_host *host, + struct mmc_command *cmd) +{ + if (cmd->opcode == MMC_ERASE) + sdhci_set_data_timeout_irq(host, false); + + __sdhci_set_timeout(host, cmd); +} + +static const struct sdhci_ops sdhci_omap_ops = { .set_clock = sdhci_omap_set_clock, .set_power = sdhci_omap_set_power, .enable_dma = sdhci_omap_enable_dma, @@ -807,36 +935,77 @@ static struct sdhci_ops sdhci_omap_ops = { .platform_send_init_74_clocks = sdhci_omap_init_74_clocks, .reset = sdhci_omap_reset, .set_uhs_signaling = sdhci_omap_set_uhs_signaling, + .irq = sdhci_omap_irq, + .set_timeout = sdhci_omap_set_timeout, }; -static int sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host) +static unsigned int sdhci_omap_regulator_get_caps(struct device *dev, + const char *name) { - u32 reg; - int ret = 0; + struct regulator *reg; + unsigned int caps = 0; + + reg = regulator_get(dev, name); + if (IS_ERR(reg)) + return ~0U; + + if (regulator_is_supported_voltage(reg, 1700000, 1950000)) + caps |= SDHCI_CAN_VDD_180; + if (regulator_is_supported_voltage(reg, 2700000, 3150000)) + caps |= SDHCI_CAN_VDD_300; + if (regulator_is_supported_voltage(reg, 3150000, 3600000)) + caps |= SDHCI_CAN_VDD_330; + + regulator_put(reg); + + return caps; +} + +static int sdhci_omap_set_capabilities(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); struct device *dev = omap_host->dev; - struct regulator *vqmmc; + const u32 mask = SDHCI_CAN_VDD_180 | SDHCI_CAN_VDD_300 | SDHCI_CAN_VDD_330; + unsigned int pbias, vqmmc, caps = 0; + u32 reg; - vqmmc = regulator_get(dev, "vqmmc"); - if (IS_ERR(vqmmc)) { - ret = PTR_ERR(vqmmc); - goto reg_put; - } + pbias = sdhci_omap_regulator_get_caps(dev, "pbias"); + vqmmc = sdhci_omap_regulator_get_caps(dev, "vqmmc"); + caps = pbias & vqmmc; + + if (pbias != ~0U && vqmmc == ~0U) + dev_warn(dev, "vqmmc regulator missing for pbias\n"); + else if (caps == ~0U) + return 0; + + /* + * Quirk handling to allow 3.0V vqmmc with a valid 3.3V PBIAS. This is + * needed for 3.0V ldo9_reg on omap5 at least. + */ + if (pbias != ~0U && (pbias & SDHCI_CAN_VDD_330) && + (vqmmc & SDHCI_CAN_VDD_300)) + caps |= SDHCI_CAN_VDD_330; /* voltage capabilities might be set by boot loader, clear it */ reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA); reg &= ~(CAPA_VS18 | CAPA_VS30 | CAPA_VS33); - if (regulator_is_supported_voltage(vqmmc, IOV_3V3, IOV_3V3)) - reg |= CAPA_VS33; - if (regulator_is_supported_voltage(vqmmc, IOV_1V8, IOV_1V8)) + if (caps & SDHCI_CAN_VDD_180) reg |= CAPA_VS18; + if (caps & SDHCI_CAN_VDD_300) + reg |= CAPA_VS30; + + if (caps & SDHCI_CAN_VDD_330) + reg |= CAPA_VS33; + sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, reg); -reg_put: - regulator_put(vqmmc); + host->caps &= ~mask; + host->caps |= caps; - return ret; + return 0; } static const struct sdhci_pltfm_data sdhci_omap_pdata = { @@ -852,18 +1021,60 @@ static const struct sdhci_pltfm_data sdhci_omap_pdata = { .ops = &sdhci_omap_ops, }; +static const struct sdhci_omap_data omap2430_data = { + .omap_offset = 0, + .offset = 0x100, +}; + +static const struct sdhci_omap_data omap3_data = { + .omap_offset = 0, + .offset = 0x100, +}; + +static const struct sdhci_omap_data omap4_data = { + .omap_offset = 0x100, + .offset = 0x200, + .flags = SDHCI_OMAP_SPECIAL_RESET, +}; + +static const struct sdhci_omap_data omap5_data = { + .omap_offset = 0x100, + .offset = 0x200, + .flags = SDHCI_OMAP_SPECIAL_RESET, +}; + static const struct sdhci_omap_data k2g_data = { + .omap_offset = 0x100, + .offset = 0x200, +}; + +static const struct sdhci_omap_data am335_data = { + .omap_offset = 0x100, + .offset = 0x200, + .flags = SDHCI_OMAP_SPECIAL_RESET, +}; + +static const struct sdhci_omap_data am437_data = { + .omap_offset = 0x100, .offset = 0x200, + .flags = SDHCI_OMAP_SPECIAL_RESET, }; static const struct sdhci_omap_data dra7_data = { + .omap_offset = 0x100, .offset = 0x200, .flags = SDHCI_OMAP_REQUIRE_IODELAY, }; static const struct of_device_id omap_sdhci_match[] = { + { .compatible = "ti,omap2430-sdhci", .data = &omap2430_data }, + { .compatible = "ti,omap3-sdhci", .data = &omap3_data }, + { .compatible = "ti,omap4-sdhci", .data = &omap4_data }, + { .compatible = "ti,omap5-sdhci", .data = &omap5_data }, { .compatible = "ti,dra7-sdhci", .data = &dra7_data }, { .compatible = "ti,k2g-sdhci", .data = &k2g_data }, + { .compatible = "ti,am335-sdhci", .data = &am335_data }, + { .compatible = "ti,am437-sdhci", .data = &am437_data }, {}, }; MODULE_DEVICE_TABLE(of, omap_sdhci_match); @@ -1007,21 +1218,21 @@ static int sdhci_omap_probe(struct platform_device *pdev) struct sdhci_pltfm_host *pltfm_host; struct sdhci_omap_host *omap_host; struct mmc_host *mmc; - const struct of_device_id *match; - struct sdhci_omap_data *data; + const struct sdhci_omap_data *data; const struct soc_device_attribute *soc; + struct resource *regs; - match = of_match_device(omap_sdhci_match, dev); - if (!match) - return -EINVAL; - - data = (struct sdhci_omap_data *)match->data; + data = of_device_get_match_data(&pdev->dev); if (!data) { dev_err(dev, "no sdhci omap data\n"); return -EINVAL; } offset = data->offset; + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!regs) + return -ENXIO; + host = sdhci_pltfm_init(pdev, &sdhci_omap_pdata, sizeof(*omap_host)); if (IS_ERR(host)) { @@ -1037,13 +1248,16 @@ static int sdhci_omap_probe(struct platform_device *pdev) omap_host->power_mode = MMC_POWER_UNDEFINED; omap_host->timing = MMC_TIMING_LEGACY; omap_host->flags = data->flags; + omap_host->omap_offset = data->omap_offset; + omap_host->con = -EINVAL; /* Prevent invalid restore on first resume */ host->ioaddr += offset; + host->mapbase = regs->start + offset; mmc = host->mmc; sdhci_get_of_property(pdev); ret = mmc_of_parse(mmc); if (ret) - goto err_pltfm_free; + return ret; soc = soc_device_match(sdhci_omap_soc_devices); if (soc) { @@ -1056,23 +1270,23 @@ static int sdhci_omap_probe(struct platform_device *pdev) mmc->f_max = 48000000; } + if (!mmc_host_can_gpio_ro(mmc)) + mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT; + pltfm_host->clk = devm_clk_get(dev, "fck"); - if (IS_ERR(pltfm_host->clk)) { - ret = PTR_ERR(pltfm_host->clk); - goto err_pltfm_free; - } + if (IS_ERR(pltfm_host->clk)) + return PTR_ERR(pltfm_host->clk); ret = clk_set_rate(pltfm_host->clk, mmc->f_max); - if (ret) { - dev_err(dev, "failed to set clock to %d\n", mmc->f_max); - goto err_pltfm_free; - } + if (ret) + return dev_err_probe(dev, ret, + "failed to set clock to %d\n", mmc->f_max); omap_host->pbias = devm_regulator_get_optional(dev, "pbias"); if (IS_ERR(omap_host->pbias)) { ret = PTR_ERR(omap_host->pbias); if (ret != -ENODEV) - goto err_pltfm_free; + return ret; dev_dbg(dev, "unable to get pbias regulator %d\n", ret); } omap_host->pbias_enabled = false; @@ -1080,24 +1294,25 @@ static int sdhci_omap_probe(struct platform_device *pdev) /* * omap_device_pm_domain has callbacks to enable the main * functional clock, interface clock and also configure the - * SYSCONFIG register of omap devices. The callback will be invoked - * as part of pm_runtime_get_sync. + * SYSCONFIG register to clear any boot loader set voltage + * capabilities before calling sdhci_setup_host(). The + * callback will be invoked as part of pm_runtime_get_sync. */ + pm_runtime_use_autosuspend(dev); + pm_runtime_set_autosuspend_delay(dev, 50); pm_runtime_enable(dev); - ret = pm_runtime_get_sync(dev); - if (ret < 0) { + ret = pm_runtime_resume_and_get(dev); + if (ret) { dev_err(dev, "pm_runtime_get_sync failed\n"); - pm_runtime_put_noidle(dev); goto err_rpm_disable; } - ret = sdhci_omap_set_capabilities(omap_host); + ret = sdhci_omap_set_capabilities(host); if (ret) { dev_err(dev, "failed to set system capabilities\n"); - goto err_put_sync; + goto err_rpm_put; } - host->mmc_host_ops.get_ro = mmc_gpio_get_ro; host->mmc_host_ops.start_signal_voltage_switch = sdhci_omap_start_signal_voltage_switch; host->mmc_host_ops.set_ios = sdhci_omap_set_ios; @@ -1105,9 +1320,28 @@ static int sdhci_omap_probe(struct platform_device *pdev) host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning; host->mmc_host_ops.enable_sdio_irq = sdhci_omap_enable_sdio_irq; + /* + * Switch to external DMA only if there is the "dmas" property and + * ADMA is not available on the controller instance. + */ + if (device_property_present(dev, "dmas") && + !sdhci_omap_has_adma(omap_host, offset)) + sdhci_switch_external_dma(host, true); + + if (device_property_read_bool(dev, "ti,non-removable")) { + dev_warn_once(dev, "using old ti,non-removable property\n"); + mmc->caps |= MMC_CAP_NONREMOVABLE; + } + + /* R1B responses is required to properly manage HW busy detection. */ + mmc->caps |= MMC_CAP_NEED_RSP_BUSY; + + /* Enable SDIO card power off. */ + mmc->caps |= MMC_CAP_POWER_OFF_CARD; + ret = sdhci_setup_host(host); if (ret) - goto err_put_sync; + goto err_rpm_put; ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host); if (ret) @@ -1117,40 +1351,125 @@ static int sdhci_omap_probe(struct platform_device *pdev) if (ret) goto err_cleanup_host; + /* + * SDIO devices can use the dat1 pin as a wake-up interrupt. Some + * devices like wl1xxx, use an out-of-band GPIO interrupt instead. + */ + omap_host->wakeirq = of_irq_get_byname(dev->of_node, "wakeup"); + if (omap_host->wakeirq == -EPROBE_DEFER) { + ret = -EPROBE_DEFER; + goto err_cleanup_host; + } + if (omap_host->wakeirq > 0) { + device_init_wakeup(dev, true); + ret = dev_pm_set_dedicated_wake_irq(dev, omap_host->wakeirq); + if (ret) { + device_init_wakeup(dev, false); + goto err_cleanup_host; + } + host->mmc->pm_caps |= MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; + } + + pm_runtime_put_autosuspend(dev); + return 0; err_cleanup_host: sdhci_cleanup_host(host); -err_put_sync: - pm_runtime_put_sync(dev); - +err_rpm_put: + pm_runtime_put_autosuspend(dev); err_rpm_disable: + pm_runtime_dont_use_autosuspend(dev); pm_runtime_disable(dev); - -err_pltfm_free: - sdhci_pltfm_free(pdev); return ret; } -static int sdhci_omap_remove(struct platform_device *pdev) +static void sdhci_omap_remove(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct sdhci_host *host = platform_get_drvdata(pdev); + pm_runtime_get_sync(dev); sdhci_remove_host(host, true); + device_init_wakeup(dev, false); + dev_pm_clear_wake_irq(dev); + pm_runtime_dont_use_autosuspend(dev); pm_runtime_put_sync(dev); - pm_runtime_disable(dev); - sdhci_pltfm_free(pdev); + /* Ensure device gets disabled despite userspace sysfs config */ + pm_runtime_force_suspend(dev); +} + +static void sdhci_omap_context_save(struct sdhci_omap_host *omap_host) +{ + omap_host->con = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); + omap_host->hctl = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL); + omap_host->sysctl = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL); + omap_host->capa = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA); + omap_host->ie = sdhci_omap_readl(omap_host, SDHCI_OMAP_IE); + omap_host->ise = sdhci_omap_readl(omap_host, SDHCI_OMAP_ISE); +} + +/* Order matters here, HCTL must be restored in two phases */ +static void sdhci_omap_context_restore(struct sdhci_omap_host *omap_host) +{ + sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, omap_host->hctl); + sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, omap_host->capa); + sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, omap_host->hctl); + + sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, omap_host->sysctl); + sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, omap_host->con); + sdhci_omap_writel(omap_host, SDHCI_OMAP_IE, omap_host->ie); + sdhci_omap_writel(omap_host, SDHCI_OMAP_ISE, omap_host->ise); +} + +static int sdhci_omap_runtime_suspend(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); + + if (host->tuning_mode != SDHCI_TUNING_MODE_3) + mmc_retune_needed(host->mmc); + + if (omap_host->con != -EINVAL) + sdhci_runtime_suspend_host(host); + + sdhci_omap_context_save(omap_host); + + pinctrl_pm_select_idle_state(dev); return 0; } +static int sdhci_omap_runtime_resume(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host); + + pinctrl_pm_select_default_state(dev); + + if (omap_host->con != -EINVAL) { + sdhci_omap_context_restore(omap_host); + sdhci_runtime_resume_host(host, 0); + } + + return 0; +} + +static const struct dev_pm_ops sdhci_omap_dev_pm_ops = { + RUNTIME_PM_OPS(sdhci_omap_runtime_suspend, sdhci_omap_runtime_resume, NULL) + SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) +}; + static struct platform_driver sdhci_omap_driver = { .probe = sdhci_omap_probe, .remove = sdhci_omap_remove, .driver = { .name = "sdhci-omap", + .probe_type = PROBE_PREFER_ASYNCHRONOUS, + .pm = pm_ptr(&sdhci_omap_dev_pm_ops), .of_match_table = omap_sdhci_match, }, }; |