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path: root/drivers/mtd/spi-nor/everspin.c
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Diffstat (limited to 'drivers/mtd/spi-nor/everspin.c')
-rw-r--r--drivers/mtd/spi-nor/everspin.c49
1 files changed, 37 insertions, 12 deletions
diff --git a/drivers/mtd/spi-nor/everspin.c b/drivers/mtd/spi-nor/everspin.c
index 04a177a32283..add37104d673 100644
--- a/drivers/mtd/spi-nor/everspin.c
+++ b/drivers/mtd/spi-nor/everspin.c
@@ -8,20 +8,45 @@
#include "core.h"
-static const struct flash_info everspin_parts[] = {
- /* Everspin */
- { "mr25h128", CAT25_INFO(16 * 1024, 1, 256, 2,
- SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
- { "mr25h256", CAT25_INFO(32 * 1024, 1, 256, 2,
- SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
- { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3,
- SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
- { "mr25h40", CAT25_INFO(512 * 1024, 1, 256, 3,
- SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
+static const struct flash_info everspin_nor_parts[] = {
+ {
+ .name = "mr25h128",
+ .size = SZ_16K,
+ .sector_size = SZ_16K,
+ .addr_nbytes = 2,
+ .flags = SPI_NOR_NO_ERASE,
+ }, {
+ .name = "mr25h256",
+ .size = SZ_32K,
+ .sector_size = SZ_32K,
+ .addr_nbytes = 2,
+ .flags = SPI_NOR_NO_ERASE,
+ }, {
+ .name = "mr25h10",
+ .size = SZ_128K,
+ .sector_size = SZ_128K,
+ .flags = SPI_NOR_NO_ERASE,
+ }, {
+ .name = "mr25h40",
+ .size = SZ_512K,
+ .sector_size = SZ_512K,
+ .flags = SPI_NOR_NO_ERASE,
+ }
+};
+
+static void everspin_nor_default_init(struct spi_nor *nor)
+{
+ /* Everspin FRAMs don't support the fast read opcode. */
+ nor->params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
+}
+
+static const struct spi_nor_fixups everspin_nor_fixups = {
+ .default_init = everspin_nor_default_init,
};
const struct spi_nor_manufacturer spi_nor_everspin = {
.name = "everspin",
- .parts = everspin_parts,
- .nparts = ARRAY_SIZE(everspin_parts),
+ .parts = everspin_nor_parts,
+ .nparts = ARRAY_SIZE(everspin_nor_parts),
+ .fixups = &everspin_nor_fixups,
};