diff options
Diffstat (limited to 'drivers/net/dsa/microchip/ksz9477_reg.h')
| -rw-r--r-- | drivers/net/dsa/microchip/ksz9477_reg.h | 138 |
1 files changed, 22 insertions, 116 deletions
diff --git a/drivers/net/dsa/microchip/ksz9477_reg.h b/drivers/net/dsa/microchip/ksz9477_reg.h index 2938e892b631..61ea11e3338e 100644 --- a/drivers/net/dsa/microchip/ksz9477_reg.h +++ b/drivers/net/dsa/microchip/ksz9477_reg.h @@ -1,8 +1,8 @@ -/* SPDX-License-Identifier: GPL-2.0 - * +/* SPDX-License-Identifier: GPL-2.0 */ +/* * Microchip KSZ9477 register definitions * - * Copyright (C) 2017-2018 Microchip Technology Inc. + * Copyright (C) 2017-2025 Microchip Technology Inc. */ #ifndef __KSZ9477_REGS_H @@ -25,7 +25,6 @@ #define REG_CHIP_ID2__1 0x0002 -#define CHIP_ID_63 0x63 #define CHIP_ID_66 0x66 #define CHIP_ID_67 0x67 #define CHIP_ID_77 0x77 @@ -39,11 +38,6 @@ #define SWITCH_REVISION_S 4 #define SWITCH_RESET 0x01 -#define REG_SW_PME_CTRL 0x0006 - -#define PME_ENABLE BIT(1) -#define PME_POLARITY BIT(0) - #define REG_GLOBAL_OPTIONS 0x000F #define SW_GIGABIT_ABLE BIT(6) @@ -113,19 +107,6 @@ #define REG_SW_IBA_SYNC__1 0x010C -#define REG_SW_IO_STRENGTH__1 0x010D -#define SW_DRIVE_STRENGTH_M 0x7 -#define SW_DRIVE_STRENGTH_2MA 0 -#define SW_DRIVE_STRENGTH_4MA 1 -#define SW_DRIVE_STRENGTH_8MA 2 -#define SW_DRIVE_STRENGTH_12MA 3 -#define SW_DRIVE_STRENGTH_16MA 4 -#define SW_DRIVE_STRENGTH_20MA 5 -#define SW_DRIVE_STRENGTH_24MA 6 -#define SW_DRIVE_STRENGTH_28MA 7 -#define SW_HI_SPEED_DRIVE_STRENGTH_S 4 -#define SW_LO_SPEED_DRIVE_STRENGTH_S 0 - #define REG_SW_IBA_STATUS__4 0x0110 #define SW_IBA_REQ BIT(31) @@ -166,16 +147,9 @@ #define SW_DOUBLE_TAG BIT(7) #define SW_RESET BIT(1) -#define SW_START BIT(0) - -#define REG_SW_MAC_ADDR_0 0x0302 -#define REG_SW_MAC_ADDR_1 0x0303 -#define REG_SW_MAC_ADDR_2 0x0304 -#define REG_SW_MAC_ADDR_3 0x0305 -#define REG_SW_MAC_ADDR_4 0x0306 -#define REG_SW_MAC_ADDR_5 0x0307 #define REG_SW_MTU__2 0x0308 +#define REG_SW_MTU_MASK GENMASK(13, 0) #define REG_SW_ISP_TPID__2 0x030A @@ -190,8 +164,7 @@ #define SW_VLAN_ENABLE BIT(7) #define SW_DROP_INVALID_VID BIT(6) -#define SW_AGE_CNT_M 0x7 -#define SW_AGE_CNT_S 3 +#define SW_AGE_CNT_M GENMASK(5, 3) #define SW_RESV_MCAST_ENABLE BIT(2) #define SW_HASH_OPTION_M 0x03 #define SW_HASH_OPTION_CRC 1 @@ -226,6 +199,7 @@ #define SW_PRIO_LOWEST_DA_SA 3 #define REG_SW_LUE_CTRL_3 0x0313 +#define SW_AGE_PERIOD_7_0_M GENMASK(7, 0) #define REG_SW_LUE_INT_STATUS 0x0314 #define REG_SW_LUE_INT_ENABLE 0x0315 @@ -265,8 +239,8 @@ #define REG_SW_MAC_CTRL_1 0x0331 -#define MULTICAST_STORM_DISABLE BIT(6) #define SW_BACK_PRESSURE BIT(5) +#define SW_BACK_PRESSURE_COLLISION 0 #define FAIR_FLOW_CTRL BIT(4) #define NO_EXC_COLLISION_DROP BIT(3) #define SW_JUMBO_PACKET BIT(2) @@ -276,13 +250,9 @@ #define REG_SW_MAC_CTRL_2 0x0332 #define SW_REPLACE_VID BIT(3) -#define BROADCAST_STORM_RATE_HI 0x07 #define REG_SW_MAC_CTRL_3 0x0333 -#define BROADCAST_STORM_RATE_LO 0xFF -#define BROADCAST_STORM_RATE 0x07FF - #define REG_SW_MAC_CTRL_4 0x0334 #define SW_PASS_PAUSE BIT(3) @@ -425,12 +395,8 @@ #define REG_SW_ALU_STAT_CTRL__4 0x041C -#define ALU_STAT_INDEX_M (BIT(4) - 1) -#define ALU_STAT_INDEX_S 16 #define ALU_RESV_MCAST_INDEX_M (BIT(6) - 1) #define ALU_STAT_START BIT(7) -#define ALU_RESV_MCAST_ADDR BIT(1) -#define ALU_STAT_READ BIT(0) #define REG_SW_ALU_VAL_A 0x0420 @@ -833,13 +799,6 @@ #define REG_PORT_AVB_SR_1_TYPE 0x0008 #define REG_PORT_AVB_SR_2_TYPE 0x000A -#define REG_PORT_PME_STATUS 0x0013 -#define REG_PORT_PME_CTRL 0x0017 - -#define PME_WOL_MAGICPKT BIT(2) -#define PME_WOL_LINKUP BIT(1) -#define PME_WOL_ENERGY BIT(0) - #define REG_PORT_INT_STATUS 0x001B #define REG_PORT_INT_MASK 0x001F @@ -857,7 +816,11 @@ #define PORT_FORCE_TX_FLOW_CTRL BIT(4) #define PORT_FORCE_RX_FLOW_CTRL BIT(3) #define PORT_TAIL_TAG_ENABLE BIT(2) -#define PORT_QUEUE_SPLIT_ENABLE 0x3 +#define PORT_QUEUE_SPLIT_MASK GENMASK(1, 0) +#define PORT_EIGHT_QUEUE 0x3 +#define PORT_FOUR_QUEUE 0x2 +#define PORT_TWO_QUEUE 0x1 +#define PORT_SINGLE_QUEUE 0x0 #define REG_PORT_CTRL_1 0x0021 @@ -865,8 +828,8 @@ #define REG_PORT_STATUS_0 0x0030 -#define PORT_INTF_SPEED_M 0x3 -#define PORT_INTF_SPEED_S 3 +#define PORT_INTF_SPEED_MASK GENMASK(4, 3) +#define PORT_INTF_SPEED_NONE GENMASK(1, 0) #define PORT_INTF_FULL_DUPLEX BIT(2) #define PORT_TX_FLOW_CTRL BIT(1) #define PORT_RX_FLOW_CTRL BIT(0) @@ -1184,35 +1147,16 @@ #define PORT_LINK_STATUS_FAIL BIT(0) /* 3 - xMII */ -#define REG_PORT_XMII_CTRL_0 0x0300 - #define PORT_SGMII_SEL BIT(7) -#define PORT_MII_FULL_DUPLEX BIT(6) -#define PORT_MII_100MBIT BIT(4) #define PORT_GRXC_ENABLE BIT(0) -#define REG_PORT_XMII_CTRL_1 0x0301 - #define PORT_RMII_CLK_SEL BIT(7) -/* S1 */ -#define PORT_MII_1000MBIT_S1 BIT(6) -/* S2 */ -#define PORT_MII_NOT_1GBIT BIT(6) #define PORT_MII_SEL_EDGE BIT(5) -#define PORT_RGMII_ID_IG_ENABLE BIT(4) -#define PORT_RGMII_ID_EG_ENABLE BIT(3) -#define PORT_MII_MAC_MODE BIT(2) -#define PORT_MII_SEL_M 0x3 -/* S1 */ -#define PORT_MII_SEL_S1 0x0 -#define PORT_RMII_SEL_S1 0x1 -#define PORT_GMII_SEL_S1 0x2 -#define PORT_RGMII_SEL_S1 0x3 -/* S2 */ -#define PORT_RGMII_SEL 0x0 -#define PORT_RMII_SEL 0x1 -#define PORT_GMII_SEL 0x2 -#define PORT_MII_SEL 0x3 + +#define REG_PMAVBC 0x03AC + +#define PMAVBC_MASK GENMASK(26, 16) +#define PMAVBC_MIN 0x580 /* 4 - MAC */ #define REG_PORT_MAC_CTRL_0 0x0400 @@ -1268,8 +1212,6 @@ /* 5 - MIB Counters */ #define REG_PORT_MIB_CTRL_STAT__4 0x0500 -#define MIB_COUNTER_OVERFLOW BIT(31) -#define MIB_COUNTER_VALID BIT(30) #define MIB_COUNTER_READ BIT(25) #define MIB_COUNTER_FLUSH_FREEZE BIT(24) #define MIB_COUNTER_INDEX_M (BIT(8) - 1) @@ -1513,33 +1455,10 @@ /* 9 - Shaping */ -#define REG_PORT_MTI_QUEUE_INDEX__4 0x0900 - -#define REG_PORT_MTI_QUEUE_CTRL_0__4 0x0904 - -#define MTI_PVID_REPLACE BIT(0) - -#define REG_PORT_MTI_QUEUE_CTRL_0 0x0914 +#define REG_PORT_MTI_QUEUE_CTRL_0__4 0x0904 -#define MTI_SCHEDULE_MODE_M 0x3 -#define MTI_SCHEDULE_MODE_S 6 -#define MTI_SCHEDULE_STRICT_PRIO 0 -#define MTI_SCHEDULE_WRR 2 -#define MTI_SHAPING_M 0x3 -#define MTI_SHAPING_S 4 -#define MTI_SHAPING_OFF 0 -#define MTI_SHAPING_SRP 1 -#define MTI_SHAPING_TIME_AWARE 2 +#define MTI_PVID_REPLACE BIT(0) -#define REG_PORT_MTI_QUEUE_CTRL_1 0x0915 - -#define MTI_TX_RATIO_M (BIT(7) - 1) - -#define REG_PORT_MTI_QUEUE_CTRL_2__2 0x0916 -#define REG_PORT_MTI_HI_WATER_MARK 0x0916 -#define REG_PORT_MTI_QUEUE_CTRL_3__2 0x0918 -#define REG_PORT_MTI_LO_WATER_MARK 0x0918 -#define REG_PORT_MTI_QUEUE_CTRL_4__2 0x091A #define REG_PORT_MTI_CREDIT_INCREMENT 0x091A /* A - QM */ @@ -1566,6 +1485,7 @@ #define PORT_QM_TX_CNT_USED_S 0 #define PORT_QM_TX_CNT_M (BIT(11) - 1) +#define PORT_QM_TX_CNT_MAX 0x200 #define REG_PORT_QM_TX_CNT_1__4 0x0A14 @@ -1585,10 +1505,6 @@ #define REG_PORT_LUE_MSTP_STATE 0x0B04 -#define PORT_TX_ENABLE BIT(2) -#define PORT_RX_ENABLE BIT(1) -#define PORT_LEARN_DISABLE BIT(0) - /* C - PTP */ #define REG_PTP_PORT_RX_DELAY__2 0x0C00 @@ -1632,11 +1548,7 @@ #define P_BCAST_STORM_CTRL REG_PORT_MAC_CTRL_0 #define P_PRIO_CTRL REG_PORT_MRI_PRIO_CTRL #define P_MIRROR_CTRL REG_PORT_MRI_MIRROR_CTRL -#define P_STP_CTRL REG_PORT_LUE_MSTP_STATE #define P_PHY_CTRL REG_PORT_PHY_CTRL -#define P_NEG_RESTART_CTRL REG_PORT_PHY_CTRL -#define P_LINK_STATUS REG_PORT_PHY_STATUS -#define P_SPEED_STATUS REG_PORT_PHY_PHY_CTRL #define P_RATE_LIMIT_CTRL REG_PORT_MAC_IN_RATE_LIMIT #define S_LINK_AGING_CTRL REG_SW_LUE_CTRL_1 @@ -1656,10 +1568,4 @@ #define PTP_TRIG_UNIT_M (BIT(MAX_TRIG_UNIT) - 1) #define PTP_TS_UNIT_M (BIT(MAX_TIMESTAMP_UNIT) - 1) -/* Driver set switch broadcast storm protection at 10% rate. */ -#define BROADCAST_STORM_PROT_RATE 10 - -/* 148,800 frames * 67 ms / 100 */ -#define BROADCAST_STORM_VALUE 9969 - #endif /* KSZ9477_REGS_H */ |