diff options
Diffstat (limited to 'drivers/net/dsa/sja1105/sja1105.h')
| -rw-r--r-- | drivers/net/dsa/sja1105/sja1105.h | 222 |
1 files changed, 155 insertions, 67 deletions
diff --git a/drivers/net/dsa/sja1105/sja1105.h b/drivers/net/dsa/sja1105/sja1105.h index 29ed21687295..dceb96ae9c83 100644 --- a/drivers/net/dsa/sja1105/sja1105.h +++ b/drivers/net/dsa/sja1105/sja1105.h @@ -13,14 +13,33 @@ #include <linux/mutex.h> #include "sja1105_static_config.h" -#define SJA1105_NUM_PORTS 5 -#define SJA1105_NUM_TC 8 #define SJA1105ET_FDB_BIN_SIZE 4 /* The hardware value is in multiples of 10 ms. * The passed parameter is in multiples of 1 ms. */ #define SJA1105_AGEING_TIME_MS(ms) ((ms) / 10) -#define SJA1105_NUM_L2_POLICERS 45 +#define SJA1105_NUM_L2_POLICERS SJA1110_MAX_L2_POLICING_COUNT + +/* Calculated assuming 1Gbps, where the clock has 125 MHz (8 ns period) + * To avoid floating point operations, we'll multiply the degrees by 10 + * to get a "phase" and get 1 decimal point precision. + */ +#define SJA1105_RGMII_DELAY_PS_TO_PHASE(ps) \ + (((ps) * 360) / 800) +#define SJA1105_RGMII_DELAY_PHASE_TO_PS(phase) \ + ((800 * (phase)) / 360) +#define SJA1105_RGMII_DELAY_PHASE_TO_HW(phase) \ + (((phase) - 738) / 9) +#define SJA1105_RGMII_DELAY_PS_TO_HW(ps) \ + SJA1105_RGMII_DELAY_PHASE_TO_HW(SJA1105_RGMII_DELAY_PS_TO_PHASE(ps)) + +/* Valid range in degrees is a value between 73.8 and 101.7 + * in 0.9 degree increments + */ +#define SJA1105_RGMII_DELAY_MIN_PS \ + SJA1105_RGMII_DELAY_PHASE_TO_PS(738) +#define SJA1105_RGMII_DELAY_MAX_PS \ + SJA1105_RGMII_DELAY_PHASE_TO_PS(1017) typedef enum { SPI_READ = 0, @@ -30,6 +49,14 @@ typedef enum { #include "sja1105_tas.h" #include "sja1105_ptp.h" +enum sja1105_stats_area { + MAC, + HL1, + HL2, + ETHER, + __MAX_SJA1105_STATS_AREA, +}; + /* Keeps the different addresses between E/T and P/Q/R/S */ struct sja1105_regs { u64 device_id; @@ -39,7 +66,6 @@ struct sja1105_regs { u64 rgu; u64 vl_status; u64 config; - u64 sgmii; u64 rmii_pll1; u64 ptppinst; u64 ptppindur; @@ -49,23 +75,41 @@ struct sja1105_regs { u64 ptpclkcorp; u64 ptpsyncts; u64 ptpschtm; - u64 ptpegr_ts[SJA1105_NUM_PORTS]; - u64 pad_mii_tx[SJA1105_NUM_PORTS]; - u64 pad_mii_rx[SJA1105_NUM_PORTS]; - u64 pad_mii_id[SJA1105_NUM_PORTS]; - u64 cgu_idiv[SJA1105_NUM_PORTS]; - u64 mii_tx_clk[SJA1105_NUM_PORTS]; - u64 mii_rx_clk[SJA1105_NUM_PORTS]; - u64 mii_ext_tx_clk[SJA1105_NUM_PORTS]; - u64 mii_ext_rx_clk[SJA1105_NUM_PORTS]; - u64 rgmii_tx_clk[SJA1105_NUM_PORTS]; - u64 rmii_ref_clk[SJA1105_NUM_PORTS]; - u64 rmii_ext_tx_clk[SJA1105_NUM_PORTS]; - u64 mac[SJA1105_NUM_PORTS]; - u64 mac_hl1[SJA1105_NUM_PORTS]; - u64 mac_hl2[SJA1105_NUM_PORTS]; - u64 ether_stats[SJA1105_NUM_PORTS]; - u64 qlevel[SJA1105_NUM_PORTS]; + u64 ptpegr_ts[SJA1105_MAX_NUM_PORTS]; + u64 pad_mii_tx[SJA1105_MAX_NUM_PORTS]; + u64 pad_mii_rx[SJA1105_MAX_NUM_PORTS]; + u64 pad_mii_id[SJA1105_MAX_NUM_PORTS]; + u64 cgu_idiv[SJA1105_MAX_NUM_PORTS]; + u64 mii_tx_clk[SJA1105_MAX_NUM_PORTS]; + u64 mii_rx_clk[SJA1105_MAX_NUM_PORTS]; + u64 mii_ext_tx_clk[SJA1105_MAX_NUM_PORTS]; + u64 mii_ext_rx_clk[SJA1105_MAX_NUM_PORTS]; + u64 rgmii_tx_clk[SJA1105_MAX_NUM_PORTS]; + u64 rmii_ref_clk[SJA1105_MAX_NUM_PORTS]; + u64 rmii_ext_tx_clk[SJA1105_MAX_NUM_PORTS]; + u64 stats[__MAX_SJA1105_STATS_AREA][SJA1105_MAX_NUM_PORTS]; + u64 mdio_100base_tx; + u64 mdio_100base_t1; + u64 pcs_base[SJA1105_MAX_NUM_PORTS]; +}; + +struct sja1105_mdio_private { + struct sja1105_private *priv; +}; + +enum { + SJA1105_SPEED_AUTO, + SJA1105_SPEED_10MBPS, + SJA1105_SPEED_100MBPS, + SJA1105_SPEED_1000MBPS, + SJA1105_SPEED_2500MBPS, + SJA1105_SPEED_MAX, +}; + +enum sja1105_internal_phy_t { + SJA1105_NO_PHY = 0, + SJA1105_PHY_BASE_TX, + SJA1105_PHY_BASE_T1, }; struct sja1105_info { @@ -85,15 +129,16 @@ struct sja1105_info { */ int ptpegr_ts_bytes; int num_cbs_shapers; + int max_frame_mem; + int num_ports; + bool multiple_cascade_ports; + /* Every {port, TXQ} has its own CBS shaper */ + bool fixed_cbs_mapping; + enum dsa_tag_protocol tag_proto; const struct sja1105_dynamic_table_ops *dyn_ops; const struct sja1105_table_ops *static_ops; const struct sja1105_regs *regs; - /* Both E/T and P/Q/R/S have quirks when it comes to popping the S-Tag - * from double-tagged frames. E/T will pop it only when it's equal to - * TPID from the General Parameters Table, while P/Q/R/S will only - * pop it when it's equal to TPID2. - */ - u16 qinq_tpid; + bool can_limit_mcast_flood; int (*reset_cmd)(struct dsa_switch *ds); int (*setup_rgmii_delay)(const void *ctx, int port); /* Prototypes from include/net/dsa.h */ @@ -103,7 +148,22 @@ struct sja1105_info { const unsigned char *addr, u16 vid); void (*ptp_cmd_packing)(u8 *buf, struct sja1105_ptp_cmd *cmd, enum packing_op op); + bool (*rxtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb); + void (*txtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb); + int (*clocking_setup)(struct sja1105_private *priv); + int (*pcs_mdio_read_c45)(struct mii_bus *bus, int phy, int mmd, + int reg); + int (*pcs_mdio_write_c45)(struct mii_bus *bus, int phy, int mmd, + int reg, u16 val); + int (*disable_microcontroller)(struct sja1105_private *priv); const char *name; + bool supports_mii[SJA1105_MAX_NUM_PORTS]; + bool supports_rmii[SJA1105_MAX_NUM_PORTS]; + bool supports_rgmii[SJA1105_MAX_NUM_PORTS]; + bool supports_sgmii[SJA1105_MAX_NUM_PORTS]; + bool supports_2500basex[SJA1105_MAX_NUM_PORTS]; + enum sja1105_internal_phy_t internal_phy[SJA1105_MAX_NUM_PORTS]; + const u64 port_speed[SJA1105_SPEED_MAX]; }; enum sja1105_key_type { @@ -185,42 +245,40 @@ struct sja1105_flow_block { int num_virtual_links; }; -struct sja1105_bridge_vlan { - struct list_head list; - int port; - u16 vid; - bool pvid; - bool untagged; -}; - -enum sja1105_vlan_state { - SJA1105_VLAN_UNAWARE, - SJA1105_VLAN_BEST_EFFORT, - SJA1105_VLAN_FILTERING_FULL, -}; - struct sja1105_private { struct sja1105_static_config static_config; - bool rgmii_rx_delay[SJA1105_NUM_PORTS]; - bool rgmii_tx_delay[SJA1105_NUM_PORTS]; - bool best_effort_vlan_filtering; + int rgmii_rx_delay_ps[SJA1105_MAX_NUM_PORTS]; + int rgmii_tx_delay_ps[SJA1105_MAX_NUM_PORTS]; + phy_interface_t phy_mode[SJA1105_MAX_NUM_PORTS]; + bool fixed_link[SJA1105_MAX_NUM_PORTS]; + unsigned long ucast_egress_floods; + unsigned long bcast_egress_floods; + unsigned long hwts_tx_en; + unsigned long hwts_rx_en; const struct sja1105_info *info; - struct gpio_desc *reset_gpio; + size_t max_xfer_len; struct spi_device *spidev; struct dsa_switch *ds; - struct list_head dsa_8021q_vlans; - struct list_head bridge_vlans; - struct list_head crosschip_links; + u16 bridge_pvid[SJA1105_MAX_NUM_PORTS]; + u16 tag_8021q_pvid[SJA1105_MAX_NUM_PORTS]; struct sja1105_flow_block flow_block; - struct sja1105_port ports[SJA1105_NUM_PORTS]; /* Serializes transmission of management frames so that * the switch doesn't confuse them with one another. */ struct mutex mgmt_lock; - bool expect_dsa_8021q; - enum sja1105_vlan_state vlan_state; + /* Serializes accesses to the FDB */ + struct mutex fdb_lock; + /* PTP two-step TX timestamp ID, and its serialization lock */ + spinlock_t ts_id_lock; + u8 ts_id; + /* Serializes access to the dynamic config interface */ + struct mutex dynamic_config_lock; + struct devlink_region **regions; struct sja1105_cbs_entry *cbs; - struct sja1105_tagger_data tagger_data; + struct mii_bus *mdio_base_t1; + struct mii_bus *mdio_base_tx; + struct mii_bus *mdio_pcs; + struct phylink_pcs *pcs[SJA1105_MAX_NUM_PORTS]; struct sja1105_ptp_data ptp_data; struct sja1105_tas_data tas_data; }; @@ -236,7 +294,6 @@ struct sja1105_spi_message { /* From sja1105_main.c */ enum sja1105_reset_reason { SJA1105_VLAN_FILTERING = 0, - SJA1105_RX_HWTSTAMPING, SJA1105_AGEING_TIME, SJA1105_SCHEDULING, SJA1105_BEST_EFFORT_POLICING, @@ -245,9 +302,27 @@ enum sja1105_reset_reason { int sja1105_static_config_reload(struct sja1105_private *priv, enum sja1105_reset_reason reason); - +int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled, + struct netlink_ext_ack *extack); void sja1105_frame_memory_partitioning(struct sja1105_private *priv); +/* From sja1105_mdio.c */ +int sja1105_mdiobus_register(struct dsa_switch *ds); +void sja1105_mdiobus_unregister(struct dsa_switch *ds); +int sja1105_pcs_mdio_read_c45(struct mii_bus *bus, int phy, int mmd, int reg); +int sja1105_pcs_mdio_write_c45(struct mii_bus *bus, int phy, int mmd, int reg, + u16 val); +int sja1110_pcs_mdio_read_c45(struct mii_bus *bus, int phy, int mmd, int reg); +int sja1110_pcs_mdio_write_c45(struct mii_bus *bus, int phy, int mmd, int reg, + u16 val); + +/* From sja1105_devlink.c */ +int sja1105_devlink_setup(struct dsa_switch *ds); +void sja1105_devlink_teardown(struct dsa_switch *ds); +int sja1105_devlink_info_get(struct dsa_switch *ds, + struct devlink_info_req *req, + struct netlink_ext_ack *extack); + /* From sja1105_spi.c */ int sja1105_xfer_buf(const struct sja1105_private *priv, sja1105_spi_rw_mode_t rw, u64 reg_addr, @@ -258,16 +333,22 @@ int sja1105_xfer_u32(const struct sja1105_private *priv, int sja1105_xfer_u64(const struct sja1105_private *priv, sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value, struct ptp_system_timestamp *ptp_sts); +int static_config_buf_prepare_for_upload(struct sja1105_private *priv, + void *config_buf, int buf_len); int sja1105_static_config_upload(struct sja1105_private *priv); int sja1105_inhibit_tx(const struct sja1105_private *priv, unsigned long port_bitmap, bool tx_inhibited); -extern struct sja1105_info sja1105e_info; -extern struct sja1105_info sja1105t_info; -extern struct sja1105_info sja1105p_info; -extern struct sja1105_info sja1105q_info; -extern struct sja1105_info sja1105r_info; -extern struct sja1105_info sja1105s_info; +extern const struct sja1105_info sja1105e_info; +extern const struct sja1105_info sja1105t_info; +extern const struct sja1105_info sja1105p_info; +extern const struct sja1105_info sja1105q_info; +extern const struct sja1105_info sja1105r_info; +extern const struct sja1105_info sja1105s_info; +extern const struct sja1105_info sja1110a_info; +extern const struct sja1105_info sja1110b_info; +extern const struct sja1105_info sja1110c_info; +extern const struct sja1105_info sja1110d_info; /* From sja1105_clocking.c */ @@ -283,16 +364,11 @@ typedef enum { XMII_MODE_SGMII = 3, } sja1105_phy_interface_t; -typedef enum { - SJA1105_SPEED_10MBPS = 3, - SJA1105_SPEED_100MBPS = 2, - SJA1105_SPEED_1000MBPS = 1, - SJA1105_SPEED_AUTO = 0, -} sja1105_speed_t; - int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port); +int sja1110_setup_rgmii_delay(const void *ctx, int port); int sja1105_clocking_setup_port(struct sja1105_private *priv, int port); int sja1105_clocking_setup(struct sja1105_private *priv); +int sja1110_disable_microcontroller(struct sja1105_private *priv); /* From sja1105_ethtool.c */ void sja1105_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data); @@ -313,6 +389,18 @@ enum sja1105_iotag { SJA1105_S_TAG = 1, /* Outer VLAN header */ }; +enum sja1110_vlan_type { + SJA1110_VLAN_INVALID = 0, + SJA1110_VLAN_C_TAG = 1, /* Single inner VLAN tag */ + SJA1110_VLAN_S_TAG = 2, /* Single outer VLAN tag */ + SJA1110_VLAN_D_TAG = 3, /* Double tagged, use outer tag for lookup */ +}; + +enum sja1110_shaper_type { + SJA1110_LEAKY_BUCKET_SHAPER = 0, + SJA1110_CBS_SHAPER = 1, +}; + u8 sja1105et_fdb_hash(struct sja1105_private *priv, const u8 *addr, u16 vid); int sja1105et_fdb_add(struct dsa_switch *ds, int port, const unsigned char *addr, u16 vid); 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