diff options
Diffstat (limited to 'drivers/net/ipa/ipa_reg.h')
| -rw-r--r-- | drivers/net/ipa/ipa_reg.h | 1045 |
1 files changed, 607 insertions, 438 deletions
diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h index 0a688d8c1d7c..61b7c441ae95 100644 --- a/drivers/net/ipa/ipa_reg.h +++ b/drivers/net/ipa/ipa_reg.h @@ -1,14 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. - * Copyright (C) 2018-2020 Linaro Ltd. + * Copyright (C) 2018-2024 Linaro Ltd. */ #ifndef _IPA_REG_H_ #define _IPA_REG_H_ -#include <linux/bitfield.h> +#include "reg.h" -#include "ipa_version.h" +struct platform_device; struct ipa; @@ -16,463 +16,632 @@ struct ipa; * DOC: IPA Registers * * IPA registers are located within the "ipa-reg" address space defined by - * Device Tree. The offset of each register within that space is specified - * by symbols defined below. The address space is mapped to virtual memory - * space in ipa_mem_init(). All IPA registers are 32 bits wide. + * Device Tree. Each register has a specified offset within that space, + * which is mapped into virtual memory space in ipa_mem_init(). Each + * has a unique identifer, taken from the ipa_reg_id enumerated type. + * All IPA registers are 32 bits wide. * - * Certain register types are duplicated for a number of instances of - * something. For example, each IPA endpoint has an set of registers - * defining its configuration. The offset to an endpoint's set of registers - * is computed based on an "base" offset, plus an endpoint's ID multiplied - * and a "stride" value for the register. For such registers, the offset is - * computed by a function-like macro that takes a parameter used in the - * computation. + * Certain "parameterized" register types are duplicated for a number of + * instances of something. For example, each IPA endpoint has an set of + * registers defining its configuration. The offset to an endpoint's set + * of registers is computed based on an "base" offset, plus an endpoint's + * ID multiplied and a "stride" value for the register. Similarly, some + * registers have an offset that depends on execution environment. In + * this case, the stride is multiplied by a member of the gsi_ee_id + * enumerated type. * - * Some register offsets depend on execution environment. For these an "ee" - * parameter is supplied to the offset macro. The "ee" value is a member of - * the gsi_ee enumerated type. + * Each version of IPA implements an array of ipa_reg structures indexed + * by register ID. Each entry in the array specifies the base offset and + * (for parameterized registers) a non-zero stride value. Not all versions + * of IPA define all registers. The offset for a register is returned by + * reg_offset() when the register's ipa_reg structure is supplied; + * zero is returned for an undefined register (this should never happen). * - * The offset of a register dependent on endpoint id is computed by a macro - * that is supplied a parameter "ep". The "ep" value is assumed to be less - * than the maximum endpoint value for the current hardware, and that will - * not exceed IPA_ENDPOINT_MAX. - * - * The offset of registers related to filter and route tables is computed - * by a macro that is supplied a parameter "er". The "er" represents an - * endpoint ID for filters, or a route ID for routes. For filters, the - * endpoint ID must be less than IPA_ENDPOINT_MAX, but is further restricted - * because not all endpoints support filtering. For routes, the route ID - * must be less than IPA_ROUTE_MAX. - * - * The offset of registers related to resource types is computed by a macro - * that is supplied a parameter "rt". The "rt" represents a resource type, - * which is is a member of the ipa_resource_type_src enumerated type for - * source endpoint resources or the ipa_resource_type_dst enumerated type - * for destination endpoint resources. - * - * Some registers encode multiple fields within them. For these, each field - * has a symbol below defining a field mask that encodes both the position - * and width of the field within its register. - * - * In some cases, different versions of IPA hardware use different offset or - * field mask values. In such cases an inline_function(ipa) is used rather - * than a MACRO to define the offset or field mask to use. - * - * Finally, some registers hold bitmasks representing endpoints. In such - * cases the @available field in the @ipa structure defines the "full" set - * of valid bits for the register. + * Some registers encode multiple fields within them. Each field in + * such a register has a unique identifier (from an enumerated type). + * The position and width of the fields in a register are defined by + * an array of field masks, indexed by field ID. Two functions are + * used to access register fields; both take an ipa_reg structure as + * argument. To encode a value to be represented in a register field, + * the value and field ID are passed to reg_encode(). To extract + * a value encoded in a register field, the field ID is passed to + * reg_decode(). In addition, for single-bit fields, reg_bit() + * can be used to either encode the bit value, or to generate a mask + * used to extract the bit value. */ -#define IPA_REG_ENABLED_PIPES_OFFSET 0x00000038 - -#define IPA_REG_COMP_CFG_OFFSET 0x0000003c -#define ENABLE_FMASK GENMASK(0, 0) -#define GSI_SNOC_BYPASS_DIS_FMASK GENMASK(1, 1) -#define GEN_QMB_0_SNOC_BYPASS_DIS_FMASK GENMASK(2, 2) -#define GEN_QMB_1_SNOC_BYPASS_DIS_FMASK GENMASK(3, 3) -#define IPA_DCMP_FAST_CLK_EN_FMASK GENMASK(4, 4) -#define IPA_QMB_SELECT_CONS_EN_FMASK GENMASK(5, 5) -#define IPA_QMB_SELECT_PROD_EN_FMASK GENMASK(6, 6) -#define GSI_MULTI_INORDER_RD_DIS_FMASK GENMASK(7, 7) -#define GSI_MULTI_INORDER_WR_DIS_FMASK GENMASK(8, 8) -#define GEN_QMB_0_MULTI_INORDER_RD_DIS_FMASK GENMASK(9, 9) -#define GEN_QMB_1_MULTI_INORDER_RD_DIS_FMASK GENMASK(10, 10) -#define GEN_QMB_0_MULTI_INORDER_WR_DIS_FMASK GENMASK(11, 11) -#define GEN_QMB_1_MULTI_INORDER_WR_DIS_FMASK GENMASK(12, 12) -#define GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS_FMASK GENMASK(13, 13) -#define GSI_SNOC_CNOC_LOOP_PROT_DISABLE_FMASK GENMASK(14, 14) -#define GSI_MULTI_AXI_MASTERS_DIS_FMASK GENMASK(15, 15) -#define IPA_QMB_SELECT_GLOBAL_EN_FMASK GENMASK(16, 16) -#define IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_FMASK GENMASK(20, 17) - -#define IPA_REG_CLKON_CFG_OFFSET 0x00000044 -#define RX_FMASK GENMASK(0, 0) -#define PROC_FMASK GENMASK(1, 1) -#define TX_WRAPPER_FMASK GENMASK(2, 2) -#define MISC_FMASK GENMASK(3, 3) -#define RAM_ARB_FMASK GENMASK(4, 4) -#define FTCH_HPS_FMASK GENMASK(5, 5) -#define FTCH_DPS_FMASK GENMASK(6, 6) -#define HPS_FMASK GENMASK(7, 7) -#define DPS_FMASK GENMASK(8, 8) -#define RX_HPS_CMDQS_FMASK GENMASK(9, 9) -#define HPS_DPS_CMDQS_FMASK GENMASK(10, 10) -#define DPS_TX_CMDQS_FMASK GENMASK(11, 11) -#define RSRC_MNGR_FMASK GENMASK(12, 12) -#define CTX_HANDLER_FMASK GENMASK(13, 13) -#define ACK_MNGR_FMASK GENMASK(14, 14) -#define D_DCPH_FMASK GENMASK(15, 15) -#define H_DCPH_FMASK GENMASK(16, 16) -#define DCMP_FMASK GENMASK(17, 17) -#define NTF_TX_CMDQS_FMASK GENMASK(18, 18) -#define TX_0_FMASK GENMASK(19, 19) -#define TX_1_FMASK GENMASK(20, 20) -#define FNR_FMASK GENMASK(21, 21) -#define QSB2AXI_CMDQ_L_FMASK GENMASK(22, 22) -#define AGGR_WRAPPER_FMASK GENMASK(23, 23) -#define RAM_SLAVEWAY_FMASK GENMASK(24, 24) -#define QMB_FMASK GENMASK(25, 25) -#define WEIGHT_ARB_FMASK GENMASK(26, 26) -#define GSI_IF_FMASK GENMASK(27, 27) -#define GLOBAL_FMASK GENMASK(28, 28) -#define GLOBAL_2X_CLK_FMASK GENMASK(29, 29) - -#define IPA_REG_ROUTE_OFFSET 0x00000048 -#define ROUTE_DIS_FMASK GENMASK(0, 0) -#define ROUTE_DEF_PIPE_FMASK GENMASK(5, 1) -#define ROUTE_DEF_HDR_TABLE_FMASK GENMASK(6, 6) -#define ROUTE_DEF_HDR_OFST_FMASK GENMASK(16, 7) -#define ROUTE_FRAG_DEF_PIPE_FMASK GENMASK(21, 17) -#define ROUTE_DEF_RETAIN_HDR_FMASK GENMASK(24, 24) - -#define IPA_REG_SHARED_MEM_SIZE_OFFSET 0x00000054 -#define SHARED_MEM_SIZE_FMASK GENMASK(15, 0) -#define SHARED_MEM_BADDR_FMASK GENMASK(31, 16) - -#define IPA_REG_QSB_MAX_WRITES_OFFSET 0x00000074 -#define GEN_QMB_0_MAX_WRITES_FMASK GENMASK(3, 0) -#define GEN_QMB_1_MAX_WRITES_FMASK GENMASK(7, 4) - -#define IPA_REG_QSB_MAX_READS_OFFSET 0x00000078 -#define GEN_QMB_0_MAX_READS_FMASK GENMASK(3, 0) -#define GEN_QMB_1_MAX_READS_FMASK GENMASK(7, 4) -/* The next two fields are present for IPA v4.0 and above */ -#define GEN_QMB_0_MAX_READS_BEATS_FMASK GENMASK(23, 16) -#define GEN_QMB_1_MAX_READS_BEATS_FMASK GENMASK(31, 24) - -static inline u32 ipa_reg_state_aggr_active_offset(enum ipa_version version) -{ - if (version == IPA_VERSION_3_5_1) - return 0x0000010c; - - return 0x000000b4; -} -/* ipa->available defines the valid bits in the STATE_AGGR_ACTIVE register */ - -/* The next register is present for IPA v4.2 and above */ -#define IPA_REG_FILT_ROUT_HASH_EN_OFFSET 0x00000148 -#define IPV6_ROUTER_HASH_EN GENMASK(0, 0) -#define IPV6_FILTER_HASH_EN GENMASK(4, 4) -#define IPV4_ROUTER_HASH_EN GENMASK(8, 8) -#define IPV4_FILTER_HASH_EN GENMASK(12, 12) - -static inline u32 ipa_reg_filt_rout_hash_flush_offset(enum ipa_version version) -{ - if (version == IPA_VERSION_3_5_1) - return 0x0000090; - - return 0x000014c; -} - -#define IPV6_ROUTER_HASH_FLUSH GENMASK(0, 0) -#define IPV6_FILTER_HASH_FLUSH GENMASK(4, 4) -#define IPV4_ROUTER_HASH_FLUSH GENMASK(8, 8) -#define IPV4_FILTER_HASH_FLUSH GENMASK(12, 12) - -#define IPA_REG_BCR_OFFSET 0x000001d0 -#define BCR_CMDQ_L_LACK_ONE_ENTRY BIT(0) -#define BCR_TX_NOT_USING_BRESP BIT(1) -#define BCR_SUSPEND_L2_IRQ BIT(3) -#define BCR_HOLB_DROP_L2_IRQ BIT(4) -#define BCR_DUAL_TX BIT(5) - -/* Backward compatibility register value to use for each version */ -static inline u32 ipa_reg_bcr_val(enum ipa_version version) -{ - if (version == IPA_VERSION_3_5_1) - return BCR_CMDQ_L_LACK_ONE_ENTRY | BCR_TX_NOT_USING_BRESP | - BCR_SUSPEND_L2_IRQ | BCR_HOLB_DROP_L2_IRQ | BCR_DUAL_TX; - - if (version == IPA_VERSION_4_0 || version == IPA_VERSION_4_1) - return BCR_CMDQ_L_LACK_ONE_ENTRY | BCR_SUSPEND_L2_IRQ | - BCR_HOLB_DROP_L2_IRQ | BCR_DUAL_TX; - - return 0x00000000; -} - - -#define IPA_REG_LOCAL_PKT_PROC_CNTXT_BASE_OFFSET 0x000001e8 - -#define IPA_REG_AGGR_FORCE_CLOSE_OFFSET 0x000001ec -/* ipa->available defines the valid bits in the AGGR_FORCE_CLOSE register */ - -#define IPA_REG_COUNTER_CFG_OFFSET 0x000001f0 -#define AGGR_GRANULARITY GENMASK(8, 4) -/* Compute the value to use in the AGGR_GRANULARITY field representing - * the given number of microseconds (up to 1 millisecond). - * x = (32 * usec) / 1000 - 1 - */ -static inline u32 ipa_aggr_granularity_val(u32 microseconds) -{ - /* assert(microseconds >= 16); (?) */ - /* assert(microseconds <= 1015); */ - - return DIV_ROUND_CLOSEST(32 * microseconds, 1000) - 1; -} - -#define IPA_REG_TX_CFG_OFFSET 0x000001fc -/* The first three fields are present for IPA v3.5.1 only */ -#define TX0_PREFETCH_DISABLE GENMASK(0, 0) -#define TX1_PREFETCH_DISABLE GENMASK(1, 1) -#define PREFETCH_ALMOST_EMPTY_SIZE GENMASK(4, 2) -/* The next fields are present for IPA v4.0 and above */ -#define PREFETCH_ALMOST_EMPTY_SIZE_TX0 GENMASK(5, 2) -#define DMAW_SCND_OUTSD_PRED_THRESHOLD GENMASK(9, 6) -#define DMAW_SCND_OUTSD_PRED_EN GENMASK(10, 10) -#define DMAW_MAX_BEATS_256_DIS GENMASK(11, 11) -#define PA_MASK_EN GENMASK(12, 12) -#define PREFETCH_ALMOST_EMPTY_SIZE_TX1 GENMASK(16, 13) -/* The last two fields are present for IPA v4.2 and above */ -#define SSPND_PA_NO_START_STATE GENMASK(18, 18) -#define SSPND_PA_NO_BQ_STATE GENMASK(19, 19) - -#define IPA_REG_FLAVOR_0_OFFSET 0x00000210 -#define BAM_MAX_PIPES_FMASK GENMASK(4, 0) -#define BAM_MAX_CONS_PIPES_FMASK GENMASK(12, 8) -#define BAM_MAX_PROD_PIPES_FMASK GENMASK(20, 16) -#define BAM_PROD_LOWEST_FMASK GENMASK(27, 24) - -static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) -{ - if (version == IPA_VERSION_4_2) - return 0x00000240; - - return 0x00000220; -} - -#define ENTER_IDLE_DEBOUNCE_THRESH_FMASK GENMASK(15, 0) -#define CONST_NON_IDLE_ENABLE_FMASK GENMASK(16, 16) - -#define IPA_REG_SRC_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ - (0x00000400 + 0x0020 * (rt)) -#define IPA_REG_SRC_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ - (0x00000404 + 0x0020 * (rt)) -#define IPA_REG_SRC_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ - (0x00000408 + 0x0020 * (rt)) -#define IPA_REG_DST_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ - (0x00000500 + 0x0020 * (rt)) -#define IPA_REG_DST_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ - (0x00000504 + 0x0020 * (rt)) -#define IPA_REG_DST_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ - (0x00000508 + 0x0020 * (rt)) -#define X_MIN_LIM_FMASK GENMASK(5, 0) -#define X_MAX_LIM_FMASK GENMASK(13, 8) -#define Y_MIN_LIM_FMASK GENMASK(21, 16) -#define Y_MAX_LIM_FMASK GENMASK(29, 24) - -#define IPA_REG_ENDP_INIT_CTRL_N_OFFSET(ep) \ - (0x00000800 + 0x0070 * (ep)) -#define ENDP_SUSPEND_FMASK GENMASK(0, 0) -#define ENDP_DELAY_FMASK GENMASK(1, 1) - -#define IPA_REG_ENDP_INIT_CFG_N_OFFSET(ep) \ - (0x00000808 + 0x0070 * (ep)) -#define FRAG_OFFLOAD_EN_FMASK GENMASK(0, 0) -#define CS_OFFLOAD_EN_FMASK GENMASK(2, 1) -#define CS_METADATA_HDR_OFFSET_FMASK GENMASK(6, 3) -#define CS_GEN_QMB_MASTER_SEL_FMASK GENMASK(8, 8) - -#define IPA_REG_ENDP_INIT_HDR_N_OFFSET(ep) \ - (0x00000810 + 0x0070 * (ep)) -#define HDR_LEN_FMASK GENMASK(5, 0) -#define HDR_OFST_METADATA_VALID_FMASK GENMASK(6, 6) -#define HDR_OFST_METADATA_FMASK GENMASK(12, 7) -#define HDR_ADDITIONAL_CONST_LEN_FMASK GENMASK(18, 13) -#define HDR_OFST_PKT_SIZE_VALID_FMASK GENMASK(19, 19) -#define HDR_OFST_PKT_SIZE_FMASK GENMASK(25, 20) -#define HDR_A5_MUX_FMASK GENMASK(26, 26) -#define HDR_LEN_INC_DEAGG_HDR_FMASK GENMASK(27, 27) -#define HDR_METADATA_REG_VALID_FMASK GENMASK(28, 28) - -#define IPA_REG_ENDP_INIT_HDR_EXT_N_OFFSET(ep) \ - (0x00000814 + 0x0070 * (ep)) -#define HDR_ENDIANNESS_FMASK GENMASK(0, 0) -#define HDR_TOTAL_LEN_OR_PAD_VALID_FMASK GENMASK(1, 1) -#define HDR_TOTAL_LEN_OR_PAD_FMASK GENMASK(2, 2) -#define HDR_PAYLOAD_LEN_INC_PADDING_FMASK GENMASK(3, 3) -#define HDR_TOTAL_LEN_OR_PAD_OFFSET_FMASK GENMASK(9, 4) -#define HDR_PAD_TO_ALIGNMENT_FMASK GENMASK(13, 10) - -#define IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(ep) \ - (0x00000818 + 0x0070 * (ep)) - -#define IPA_REG_ENDP_INIT_MODE_N_OFFSET(ep) \ - (0x00000820 + 0x0070 * (ep)) -#define MODE_FMASK GENMASK(2, 0) -#define DEST_PIPE_INDEX_FMASK GENMASK(8, 4) -#define BYTE_THRESHOLD_FMASK GENMASK(27, 12) -#define PIPE_REPLICATION_EN_FMASK GENMASK(28, 28) -#define PAD_EN_FMASK GENMASK(29, 29) -#define HDR_FTCH_DISABLE_FMASK GENMASK(30, 30) - -#define IPA_REG_ENDP_INIT_AGGR_N_OFFSET(ep) \ - (0x00000824 + 0x0070 * (ep)) -#define AGGR_EN_FMASK GENMASK(1, 0) -#define AGGR_TYPE_FMASK GENMASK(4, 2) -#define AGGR_BYTE_LIMIT_FMASK GENMASK(9, 5) -#define AGGR_TIME_LIMIT_FMASK GENMASK(14, 10) -#define AGGR_PKT_LIMIT_FMASK GENMASK(20, 15) -#define AGGR_SW_EOF_ACTIVE_FMASK GENMASK(21, 21) -#define AGGR_FORCE_CLOSE_FMASK GENMASK(22, 22) -#define AGGR_HARD_BYTE_LIMIT_ENABLE_FMASK GENMASK(24, 24) - -#define IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(ep) \ - (0x0000082c + 0x0070 * (ep)) -#define HOL_BLOCK_EN_FMASK GENMASK(0, 0) - -/* The next register is valid only for RX (IPA producer) endpoints */ -#define IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(ep) \ - (0x00000830 + 0x0070 * (ep)) -/* The next fields are present for IPA v4.2 only */ -#define BASE_VALUE_FMASK GENMASK(4, 0) -#define SCALE_FMASK GENMASK(12, 8) - -#define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(ep) \ - (0x00000834 + 0x0070 * (ep)) -#define DEAGGR_HDR_LEN_FMASK GENMASK(5, 0) -#define PACKET_OFFSET_VALID_FMASK GENMASK(7, 7) -#define PACKET_OFFSET_LOCATION_FMASK GENMASK(13, 8) -#define MAX_PACKET_LEN_FMASK GENMASK(31, 16) - -#define IPA_REG_ENDP_INIT_RSRC_GRP_N_OFFSET(ep) \ - (0x00000838 + 0x0070 * (ep)) -#define RSRC_GRP_FMASK GENMASK(1, 0) - -#define IPA_REG_ENDP_INIT_SEQ_N_OFFSET(ep) \ - (0x0000083c + 0x0070 * (ep)) -#define HPS_SEQ_TYPE_FMASK GENMASK(3, 0) -#define DPS_SEQ_TYPE_FMASK GENMASK(7, 4) -#define HPS_REP_SEQ_TYPE_FMASK GENMASK(11, 8) -#define DPS_REP_SEQ_TYPE_FMASK GENMASK(15, 12) - -#define IPA_REG_ENDP_STATUS_N_OFFSET(ep) \ - (0x00000840 + 0x0070 * (ep)) -#define STATUS_EN_FMASK GENMASK(0, 0) -#define STATUS_ENDP_FMASK GENMASK(5, 1) -#define STATUS_LOCATION_FMASK GENMASK(8, 8) -/* The next field is present for IPA v4.0 and above */ -#define STATUS_PKT_SUPPRESS_FMASK GENMASK(9, 9) - -/* "er" is either an endpoint id (for filters) or a route id (for routes) */ -#define IPA_REG_ENDP_FILTER_ROUTER_HSH_CFG_N_OFFSET(er) \ - (0x0000085c + 0x0070 * (er)) -#define FILTER_HASH_MSK_SRC_ID_FMASK GENMASK(0, 0) -#define FILTER_HASH_MSK_SRC_IP_FMASK GENMASK(1, 1) -#define FILTER_HASH_MSK_DST_IP_FMASK GENMASK(2, 2) -#define FILTER_HASH_MSK_SRC_PORT_FMASK GENMASK(3, 3) -#define FILTER_HASH_MSK_DST_PORT_FMASK GENMASK(4, 4) -#define FILTER_HASH_MSK_PROTOCOL_FMASK GENMASK(5, 5) -#define FILTER_HASH_MSK_METADATA_FMASK GENMASK(6, 6) -#define IPA_REG_ENDP_FILTER_HASH_MSK_ALL GENMASK(6, 0) - -#define ROUTER_HASH_MSK_SRC_ID_FMASK GENMASK(16, 16) -#define ROUTER_HASH_MSK_SRC_IP_FMASK GENMASK(17, 17) -#define ROUTER_HASH_MSK_DST_IP_FMASK GENMASK(18, 18) -#define ROUTER_HASH_MSK_SRC_PORT_FMASK GENMASK(19, 19) -#define ROUTER_HASH_MSK_DST_PORT_FMASK GENMASK(20, 20) -#define ROUTER_HASH_MSK_PROTOCOL_FMASK GENMASK(21, 21) -#define ROUTER_HASH_MSK_METADATA_FMASK GENMASK(22, 22) -#define IPA_REG_ENDP_ROUTER_HASH_MSK_ALL GENMASK(22, 16) - -#define IPA_REG_IRQ_STTS_OFFSET \ - IPA_REG_IRQ_STTS_EE_N_OFFSET(GSI_EE_AP) -#define IPA_REG_IRQ_STTS_EE_N_OFFSET(ee) \ - (0x00003008 + 0x1000 * (ee)) - -#define IPA_REG_IRQ_EN_OFFSET \ - IPA_REG_IRQ_EN_EE_N_OFFSET(GSI_EE_AP) -#define IPA_REG_IRQ_EN_EE_N_OFFSET(ee) \ - (0x0000300c + 0x1000 * (ee)) - -#define IPA_REG_IRQ_CLR_OFFSET \ - IPA_REG_IRQ_CLR_EE_N_OFFSET(GSI_EE_AP) -#define IPA_REG_IRQ_CLR_EE_N_OFFSET(ee) \ - (0x00003010 + 0x1000 * (ee)) - -#define IPA_REG_IRQ_UC_OFFSET \ - IPA_REG_IRQ_UC_EE_N_OFFSET(GSI_EE_AP) -#define IPA_REG_IRQ_UC_EE_N_OFFSET(ee) \ - (0x0000301c + 0x1000 * (ee)) - -#define IPA_REG_IRQ_SUSPEND_INFO_OFFSET \ - IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(GSI_EE_AP) -#define IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(ee) \ - (0x00003030 + 0x1000 * (ee)) -/* ipa->available defines the valid bits in the SUSPEND_INFO register */ - -#define IPA_REG_SUSPEND_IRQ_EN_OFFSET \ - IPA_REG_SUSPEND_IRQ_EN_EE_N_OFFSET(GSI_EE_AP) -#define IPA_REG_SUSPEND_IRQ_EN_EE_N_OFFSET(ee) \ - (0x00003034 + 0x1000 * (ee)) -/* ipa->available defines the valid bits in the SUSPEND_IRQ_EN register */ - -#define IPA_REG_SUSPEND_IRQ_CLR_OFFSET \ - IPA_REG_SUSPEND_IRQ_CLR_EE_N_OFFSET(GSI_EE_AP) -#define IPA_REG_SUSPEND_IRQ_CLR_EE_N_OFFSET(ee) \ - (0x00003038 + 0x1000 * (ee)) -/* ipa->available defines the valid bits in the SUSPEND_IRQ_CLR register */ - -/** enum ipa_cs_offload_en - checksum offload field in ENDP_INIT_CFG_N */ +/* enum ipa_reg_id - IPA register IDs */ +enum ipa_reg_id { + COMP_CFG, + CLKON_CFG, + ROUTE, + SHARED_MEM_SIZE, + QSB_MAX_WRITES, + QSB_MAX_READS, + FILT_ROUT_HASH_EN, /* IPA v4.2 */ + FILT_ROUT_HASH_FLUSH, /* Not IPA v4.2 nor IPA v5.0+ */ + FILT_ROUT_CACHE_FLUSH, /* IPA v5.0+ */ + STATE_AGGR_ACTIVE, + IPA_BCR, /* Not IPA v4.5+ */ + LOCAL_PKT_PROC_CNTXT, + AGGR_FORCE_CLOSE, + COUNTER_CFG, /* Not IPA v4.5+ */ + IPA_TX_CFG, /* IPA v3.5+ */ + FLAVOR_0, /* IPA v3.5+ */ + IDLE_INDICATION_CFG, /* IPA v3.5+ */ + QTIME_TIMESTAMP_CFG, /* IPA v4.5+ */ + TIMERS_XO_CLK_DIV_CFG, /* IPA v4.5+ */ + TIMERS_PULSE_GRAN_CFG, /* IPA v4.5+ */ + SRC_RSRC_GRP_01_RSRC_TYPE, + SRC_RSRC_GRP_23_RSRC_TYPE, + SRC_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+; IPA v4.5, IPA v5.0 */ + SRC_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+; IPA v5.0 */ + DST_RSRC_GRP_01_RSRC_TYPE, + DST_RSRC_GRP_23_RSRC_TYPE, + DST_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+; IPA v4.5, IPA v5.0 */ + DST_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+; IPA v5.0 */ + ENDP_INIT_CTRL, /* Not IPA v4.2+ for TX, not IPA v4.0+ for RX */ + ENDP_INIT_CFG, + ENDP_INIT_NAT, /* TX only */ + ENDP_INIT_HDR, + ENDP_INIT_HDR_EXT, + ENDP_INIT_HDR_METADATA_MASK, /* RX only */ + ENDP_INIT_MODE, /* TX only */ + ENDP_INIT_AGGR, + ENDP_INIT_HOL_BLOCK_EN, /* RX only */ + ENDP_INIT_HOL_BLOCK_TIMER, /* RX only */ + ENDP_INIT_DEAGGR, /* TX only */ + ENDP_INIT_RSRC_GRP, + ENDP_INIT_SEQ, /* TX only */ + ENDP_STATUS, + ENDP_FILTER_ROUTER_HSH_CFG, /* Not IPA v4.2 */ + ENDP_FILTER_CACHE_CFG, /* IPA v5.0+ */ + ENDP_ROUTER_CACHE_CFG, /* IPA v5.0+ */ + /* The IRQ registers that follow are only used for GSI_EE_AP */ + IPA_IRQ_STTS, + IPA_IRQ_EN, + IPA_IRQ_CLR, + IPA_IRQ_UC, + IRQ_SUSPEND_INFO, + IRQ_SUSPEND_EN, /* IPA v3.1+ */ + IRQ_SUSPEND_CLR, /* IPA v3.1+ */ + IPA_REG_ID_COUNT, /* Last; not an ID */ +}; + +/* COMP_CFG register */ +enum ipa_reg_comp_cfg_field_id { + COMP_CFG_ENABLE, /* Not IPA v4.0+ */ + RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS, /* IPA v4.7+ */ + GSI_SNOC_BYPASS_DIS, + GEN_QMB_0_SNOC_BYPASS_DIS, + GEN_QMB_1_SNOC_BYPASS_DIS, + IPA_DCMP_FAST_CLK_EN, /* Not IPA v4.5+ */ + IPA_QMB_SELECT_CONS_EN, /* IPA v4.0+ */ + IPA_QMB_SELECT_PROD_EN, /* IPA v4.0+ */ + GSI_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */ + GSI_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */ + GEN_QMB_0_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */ + GEN_QMB_1_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */ + GEN_QMB_0_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */ + GEN_QMB_1_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */ + GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS, /* IPA v4.0+ */ + GSI_SNOC_CNOC_LOOP_PROT_DISABLE, /* IPA v4.0+ */ + GSI_MULTI_AXI_MASTERS_DIS, /* IPA v4.0+ */ + IPA_QMB_SELECT_GLOBAL_EN, /* IPA v4.0+ */ + QMB_RAM_RD_CACHE_DISABLE, /* IPA v4.9+ */ + GENQMB_AOOOWR, /* IPA v4.9+ */ + IF_OUT_OF_BUF_STOP_RESET_MASK_EN, /* IPA v4.9+ */ + GEN_QMB_1_DYNAMIC_ASIZE, /* IPA v4.9+ */ + GEN_QMB_0_DYNAMIC_ASIZE, /* IPA v4.9+ */ + ATOMIC_FETCHER_ARB_LOCK_DIS, /* IPA v4.0+ */ + FULL_FLUSH_WAIT_RS_CLOSURE_EN, /* IPA v4.5+ */ +}; + +/* CLKON_CFG register */ +enum ipa_reg_clkon_cfg_field_id { + CLKON_RX, + CLKON_PROC, + TX_WRAPPER, + CLKON_MISC, + RAM_ARB, + FTCH_HPS, + FTCH_DPS, + CLKON_HPS, + CLKON_DPS, + RX_HPS_CMDQS, + HPS_DPS_CMDQS, + DPS_TX_CMDQS, + RSRC_MNGR, + CTX_HANDLER, + ACK_MNGR, + D_DCPH, + H_DCPH, + CLKON_DCMP, /* IPA v4.5+ */ + NTF_TX_CMDQS, /* IPA v3.5+ */ + CLKON_TX_0, /* IPA v3.5+ */ + CLKON_TX_1, /* IPA v3.5+ */ + CLKON_FNR, /* IPA v3.5.1+ */ + QSB2AXI_CMDQ_L, /* IPA v4.0+ */ + AGGR_WRAPPER, /* IPA v4.0+ */ + RAM_SLAVEWAY, /* IPA v4.0+ */ + CLKON_QMB, /* IPA v4.0+ */ + WEIGHT_ARB, /* IPA v4.0+ */ + GSI_IF, /* IPA v4.0+ */ + CLKON_GLOBAL, /* IPA v4.0+ */ + GLOBAL_2X_CLK, /* IPA v4.0+ */ + DPL_FIFO, /* IPA v4.5+ */ + DRBIP, /* IPA v4.7+ */ +}; + +/* ROUTE register */ +enum ipa_reg_route_field_id { + ROUTE_DIS, + ROUTE_DEF_PIPE, + ROUTE_DEF_HDR_TABLE, + ROUTE_DEF_HDR_OFST, + ROUTE_FRAG_DEF_PIPE, + ROUTE_DEF_RETAIN_HDR, +}; + +/* SHARED_MEM_SIZE register */ +enum ipa_reg_shared_mem_size_field_id { + MEM_SIZE, + MEM_BADDR, +}; + +/* QSB_MAX_WRITES register */ +enum ipa_reg_qsb_max_writes_field_id { + GEN_QMB_0_MAX_WRITES, + GEN_QMB_1_MAX_WRITES, +}; + +/* QSB_MAX_READS register */ +enum ipa_reg_qsb_max_reads_field_id { + GEN_QMB_0_MAX_READS, + GEN_QMB_1_MAX_READS, + GEN_QMB_0_MAX_READS_BEATS, /* IPA v4.0+ */ + GEN_QMB_1_MAX_READS_BEATS, /* IPA v4.0+ */ +}; + +/* FILT_ROUT_HASH_EN and FILT_ROUT_HASH_FLUSH registers */ +enum ipa_reg_filt_rout_hash_field_id { + IPV6_ROUTER_HASH, + IPV6_FILTER_HASH, + IPV4_ROUTER_HASH, + IPV4_FILTER_HASH, +}; + +/* FILT_ROUT_CACHE_FLUSH register */ +enum ipa_reg_filt_rout_cache_field_id { + ROUTER_CACHE, + FILTER_CACHE, +}; + +/* BCR register */ +enum ipa_bcr_compat { + BCR_CMDQ_L_LACK_ONE_ENTRY = 0x0, /* Not IPA v4.2+ */ + BCR_TX_NOT_USING_BRESP = 0x1, /* Not IPA v4.2+ */ + BCR_TX_SUSPEND_IRQ_ASSERT_ONCE = 0x2, /* Not IPA v4.0+ */ + BCR_SUSPEND_L2_IRQ = 0x3, /* Not IPA v4.2+ */ + BCR_HOLB_DROP_L2_IRQ = 0x4, /* Not IPA v4.2+ */ + BCR_DUAL_TX = 0x5, /* IPA v3.5+ */ + BCR_ENABLE_FILTER_DATA_CACHE = 0x6, /* IPA v3.5+ */ + BCR_NOTIF_PRIORITY_OVER_ZLT = 0x7, /* IPA v3.5+ */ + BCR_FILTER_PREFETCH_EN = 0x8, /* IPA v3.5+ */ + BCR_ROUTER_PREFETCH_EN = 0x9, /* IPA v3.5+ */ +}; + +/* LOCAL_PKT_PROC_CNTXT register */ +enum ipa_reg_local_pkt_proc_cntxt_field_id { + IPA_BASE_ADDR, +}; + +/* COUNTER_CFG register */ +enum ipa_reg_counter_cfg_field_id { + EOT_COAL_GRANULARITY, /* Not IPA v3.5+ */ + AGGR_GRANULARITY, +}; + +/* IPA_TX_CFG register */ +enum ipa_reg_ipa_tx_cfg_field_id { + TX0_PREFETCH_DISABLE, /* Not IPA v4.0+ */ + TX1_PREFETCH_DISABLE, /* Not IPA v4.0+ */ + PREFETCH_ALMOST_EMPTY_SIZE, /* Not IPA v4.0+ */ + PREFETCH_ALMOST_EMPTY_SIZE_TX0, /* IPA v4.0+ */ + DMAW_SCND_OUTSD_PRED_THRESHOLD, /* IPA v4.0+ */ + DMAW_SCND_OUTSD_PRED_EN, /* IPA v4.0+ */ + DMAW_MAX_BEATS_256_DIS, /* IPA v4.0+ */ + PA_MASK_EN, /* IPA v4.0+ */ + PREFETCH_ALMOST_EMPTY_SIZE_TX1, /* IPA v4.0+ */ + DUAL_TX_ENABLE, /* IPA v4.5+ */ + SSPND_PA_NO_START_STATE, /* IPA v4,2+, not IPA v4.5 */ + SSPND_PA_NO_BQ_STATE, /* IPA v4.2 only */ + HOLB_STICKY_DROP_EN, /* IPA v5.0+ */ +}; + +/* FLAVOR_0 register */ +enum ipa_reg_flavor_0_field_id { + MAX_PIPES, + MAX_CONS_PIPES, + MAX_PROD_PIPES, + PROD_LOWEST, +}; + +/* IDLE_INDICATION_CFG register */ +enum ipa_reg_idle_indication_cfg_field_id { + ENTER_IDLE_DEBOUNCE_THRESH, + CONST_NON_IDLE_ENABLE, +}; + +/* QTIME_TIMESTAMP_CFG register */ +enum ipa_reg_qtime_timestamp_cfg_field_id { + DPL_TIMESTAMP_LSB, /* Not IPA v5.5+ */ + DPL_TIMESTAMP_SEL, /* Not IPA v5.5+ */ + TAG_TIMESTAMP_LSB, + NAT_TIMESTAMP_LSB, +}; + +/* TIMERS_XO_CLK_DIV_CFG register */ +enum ipa_reg_timers_xo_clk_div_cfg_field_id { + DIV_VALUE, + DIV_ENABLE, +}; + +/* TIMERS_PULSE_GRAN_CFG register */ +enum ipa_reg_timers_pulse_gran_cfg_field_id { + PULSE_GRAN_0, + PULSE_GRAN_1, + PULSE_GRAN_2, + PULSE_GRAN_3, +}; + +/* Values for IPA_GRAN_x fields of TIMERS_PULSE_GRAN_CFG */ +enum ipa_pulse_gran { + IPA_GRAN_10_US = 0x0, + IPA_GRAN_20_US = 0x1, + IPA_GRAN_50_US = 0x2, + IPA_GRAN_100_US = 0x3, + IPA_GRAN_1_MS = 0x4, + IPA_GRAN_10_MS = 0x5, + IPA_GRAN_100_MS = 0x6, + IPA_GRAN_655350_US = 0x7, +}; + +/* {SRC,DST}_RSRC_GRP_{01,23,45,67}_RSRC_TYPE registers */ +enum ipa_reg_rsrc_grp_rsrc_type_field_id { + X_MIN_LIM, + X_MAX_LIM, + Y_MIN_LIM, + Y_MAX_LIM, +}; + +/* ENDP_INIT_CTRL register */ +enum ipa_reg_endp_init_ctrl_field_id { + ENDP_SUSPEND, /* Not IPA v4.0+ */ + ENDP_DELAY, /* Not IPA v4.2+ */ +}; + +/* ENDP_INIT_CFG register */ +enum ipa_reg_endp_init_cfg_field_id { + FRAG_OFFLOAD_EN, + CS_OFFLOAD_EN, + CS_METADATA_HDR_OFFSET, + CS_GEN_QMB_MASTER_SEL, + PIPE_REPLICATE_EN, /* IPA v5.5+ */ +}; + +/** enum ipa_cs_offload_en - ENDP_INIT_CFG register CS_OFFLOAD_EN field value */ enum ipa_cs_offload_en { - IPA_CS_OFFLOAD_NONE = 0, - IPA_CS_OFFLOAD_UL = 1, - IPA_CS_OFFLOAD_DL = 2, - IPA_CS_RSVD + IPA_CS_OFFLOAD_NONE = 0x0, + IPA_CS_OFFLOAD_UL /* TX */ = 0x1, /* Not IPA v4.5+ */ + IPA_CS_OFFLOAD_DL /* RX */ = 0x2, /* Not IPA v4.5+ */ + IPA_CS_OFFLOAD_INLINE /* TX and RX */ = 0x1, /* IPA v4.5+ */ +}; + +/* ENDP_INIT_NAT register */ +enum ipa_reg_endp_init_nat_field_id { + NAT_EN, +}; + +/** enum ipa_nat_type - ENDP_INIT_NAT register NAT_EN field value */ +enum ipa_nat_type { + IPA_NAT_TYPE_BYPASS = 0, + IPA_NAT_TYPE_SRC = 1, + IPA_NAT_TYPE_DST = 2, +}; + +/* ENDP_INIT_HDR register */ +enum ipa_reg_endp_init_hdr_field_id { + HDR_LEN, + HDR_OFST_METADATA_VALID, + HDR_OFST_METADATA, + HDR_ADDITIONAL_CONST_LEN, + HDR_OFST_PKT_SIZE_VALID, + HDR_OFST_PKT_SIZE, + HDR_A5_MUX, /* Not IPA v4.9+ */ + HDR_LEN_INC_DEAGG_HDR, + HDR_METADATA_REG_VALID, /* Not IPA v4.5+ */ + HDR_LEN_MSB, /* IPA v4.5+ */ + HDR_OFST_METADATA_MSB, /* IPA v4.5+ */ +}; + +/* ENDP_INIT_HDR_EXT register */ +enum ipa_reg_endp_init_hdr_ext_field_id { + HDR_ENDIANNESS, + HDR_TOTAL_LEN_OR_PAD_VALID, + HDR_TOTAL_LEN_OR_PAD, + HDR_PAYLOAD_LEN_INC_PADDING, + HDR_TOTAL_LEN_OR_PAD_OFFSET, + HDR_PAD_TO_ALIGNMENT, + HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB, /* IPA v4.5+ */ + HDR_OFST_PKT_SIZE_MSB, /* IPA v4.5+ */ + HDR_ADDITIONAL_CONST_LEN_MSB, /* IPA v4.5+ */ + HDR_BYTES_TO_REMOVE_VALID, /* IPA v5.0+ */ + HDR_BYTES_TO_REMOVE, /* IPA v5.0+ */ +}; + +/* ENDP_INIT_MODE register */ +enum ipa_reg_endp_init_mode_field_id { + ENDP_MODE, + DCPH_ENABLE, /* IPA v4.5+ */ + DEST_PIPE_INDEX, + BYTE_THRESHOLD, + PIPE_REPLICATION_EN, /* Not IPA v5.5+ */ + PAD_EN, + HDR_FTCH_DISABLE, /* IPA v4.5+ */ + DRBIP_ACL_ENABLE, /* IPA v4.9+ */ +}; + +/** enum ipa_mode - ENDP_INIT_MODE register MODE field value */ +enum ipa_mode { + IPA_BASIC = 0x0, + IPA_ENABLE_FRAMING_HDLC = 0x1, + IPA_ENABLE_DEFRAMING_HDLC = 0x2, + IPA_DMA = 0x3, +}; + +/* ENDP_INIT_AGGR register */ +enum ipa_reg_endp_init_aggr_field_id { + AGGR_EN, + AGGR_TYPE, + BYTE_LIMIT, + TIME_LIMIT, + PKT_LIMIT, + SW_EOF_ACTIVE, + FORCE_CLOSE, + HARD_BYTE_LIMIT_EN, + AGGR_GRAN_SEL, + AGGR_COAL_L2, /* IPA v5.5+ */ }; -/** enum ipa_aggr_en - aggregation type field in ENDP_INIT_AGGR_N */ +/** enum ipa_aggr_en - ENDP_INIT_AGGR register AGGR_EN field value */ enum ipa_aggr_en { - IPA_BYPASS_AGGR = 0, - IPA_ENABLE_AGGR = 1, - IPA_ENABLE_DEAGGR = 2, + IPA_BYPASS_AGGR /* TX and RX */ = 0x0, + IPA_ENABLE_AGGR /* RX */ = 0x1, + IPA_ENABLE_DEAGGR /* TX */ = 0x2, }; -/** enum ipa_aggr_type - aggregation type field in in_ENDP_INIT_AGGR_N */ +/** enum ipa_aggr_type - ENDP_INIT_AGGR register AGGR_TYPE field value */ enum ipa_aggr_type { - IPA_MBIM_16 = 0, - IPA_HDLC = 1, - IPA_TLP = 2, - IPA_RNDIS = 3, - IPA_GENERIC = 4, - IPA_COALESCE = 5, - IPA_QCMAP = 6, + IPA_MBIM_16 = 0x0, + IPA_HDLC = 0x1, + IPA_TLP = 0x2, + IPA_RNDIS = 0x3, + IPA_GENERIC = 0x4, + IPA_COALESCE = 0x5, + IPA_QCMAP = 0x6, }; -/** enum ipa_mode - mode field in ENDP_INIT_MODE_N */ -enum ipa_mode { - IPA_BASIC = 0, - IPA_ENABLE_FRAMING_HDLC = 1, - IPA_ENABLE_DEFRAMING_HDLC = 2, - IPA_DMA = 3, +/* ENDP_INIT_HOL_BLOCK_EN register */ +enum ipa_reg_endp_init_hol_block_en_field_id { + HOL_BLOCK_EN, +}; + +/* ENDP_INIT_HOL_BLOCK_TIMER register */ +enum ipa_reg_endp_init_hol_block_timer_field_id { + TIMER_BASE_VALUE, /* Not IPA v4.5+ */ + TIMER_SCALE, /* IPA v4.2 only */ + TIMER_LIMIT, /* IPA v4.5+ */ + TIMER_GRAN_SEL, /* IPA v4.5+ */ +}; + +/* ENDP_INIT_DEAGGR register */ +enum ipa_reg_endp_deaggr_field_id { + DEAGGR_HDR_LEN, + SYSPIPE_ERR_DETECTION, + PACKET_OFFSET_VALID, + PACKET_OFFSET_LOCATION, + IGNORE_MIN_PKT_ERR, + MAX_PACKET_LEN, +}; + +/* ENDP_INIT_RSRC_GRP register */ +enum ipa_reg_endp_init_rsrc_grp_field_id { + ENDP_RSRC_GRP, +}; + +/* ENDP_INIT_SEQ register */ +enum ipa_reg_endp_init_seq_field_id { + SEQ_TYPE, + SEQ_REP_TYPE, /* Not IPA v4.5+ */ }; /** - * enum ipa_seq_type - HPS and DPS sequencer type fields in in ENDP_INIT_SEQ_N - * @IPA_SEQ_DMA_ONLY: only DMA is performed - * @IPA_SEQ_PKT_PROCESS_NO_DEC_UCP: - * packet processing + no decipher + microcontroller (Ethernet Bridging) - * @IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP: - * second packet processing pass + no decipher + microcontroller - * @IPA_SEQ_DMA_DEC: DMA + cipher/decipher - * @IPA_SEQ_DMA_COMP_DECOMP: DMA + compression/decompression - * @IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP: - * packet processing + no decipher + no uCP + HPS REP DMA parser - * @IPA_SEQ_INVALID: invalid sequencer type + * enum ipa_seq_type - HPS and DPS sequencer type + * @IPA_SEQ_DMA: Perform DMA only + * @IPA_SEQ_1_PASS: One pass through the pipeline + * @IPA_SEQ_2_PASS_SKIP_LAST_UC: Two passes, skip the microcprocessor + * @IPA_SEQ_1_PASS_SKIP_LAST_UC: One pass, skip the microcprocessor + * @IPA_SEQ_2_PASS: Two passes through the pipeline + * @IPA_SEQ_3_PASS_SKIP_LAST_UC: Three passes, skip the microcprocessor + * @IPA_SEQ_DECIPHER: Optional deciphering step (combined) + * + * The low-order byte of the sequencer type register defines the number of + * passes a packet takes through the IPA pipeline. The last pass through can + * optionally skip the microprocessor. Deciphering is optional for all types; + * if enabled, an additional mask (two bits) is added to the type value. * - * The values defined here are broken into 4-bit nibbles that are written - * into fields of the INIT_SEQ_N endpoint registers. + * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are + * supported (or meaningful). */ enum ipa_seq_type { - IPA_SEQ_DMA_ONLY = 0x0000, - IPA_SEQ_PKT_PROCESS_NO_DEC_UCP = 0x0002, - IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP = 0x0004, - IPA_SEQ_DMA_DEC = 0x0011, - IPA_SEQ_DMA_COMP_DECOMP = 0x0020, - IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP = 0x0806, - IPA_SEQ_INVALID = 0xffff, + IPA_SEQ_DMA = 0x00, + IPA_SEQ_1_PASS = 0x02, + IPA_SEQ_2_PASS_SKIP_LAST_UC = 0x04, + IPA_SEQ_1_PASS_SKIP_LAST_UC = 0x06, + IPA_SEQ_2_PASS = 0x0a, + IPA_SEQ_3_PASS_SKIP_LAST_UC = 0x0c, + /* The next value can be ORed with the above */ + IPA_SEQ_DECIPHER = 0x11, +}; + +/** + * enum ipa_seq_rep_type - replicated packet sequencer type + * @IPA_SEQ_REP_DMA_PARSER: DMA parser for replicated packets + * + * This goes in the second byte of the endpoint sequencer type register. + * + * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are + * supported (or meaningful). + */ +enum ipa_seq_rep_type { + IPA_SEQ_REP_DMA_PARSER = 0x08, +}; + +/* ENDP_STATUS register */ +enum ipa_reg_endp_status_field_id { + STATUS_EN, + STATUS_ENDP, + STATUS_LOCATION, /* Not IPA v4.5+ */ + STATUS_PKT_SUPPRESS, /* IPA v4.0+ */ +}; + +/* ENDP_FILTER_ROUTER_HSH_CFG register */ +enum ipa_reg_endp_filter_router_hsh_cfg_field_id { + FILTER_HASH_MSK_SRC_ID, + FILTER_HASH_MSK_SRC_IP, + FILTER_HASH_MSK_DST_IP, + FILTER_HASH_MSK_SRC_PORT, + FILTER_HASH_MSK_DST_PORT, + FILTER_HASH_MSK_PROTOCOL, + FILTER_HASH_MSK_METADATA, + FILTER_HASH_MSK_ALL, /* Bitwise OR of the above 6 fields */ + + ROUTER_HASH_MSK_SRC_ID, + ROUTER_HASH_MSK_SRC_IP, + ROUTER_HASH_MSK_DST_IP, + ROUTER_HASH_MSK_SRC_PORT, + ROUTER_HASH_MSK_DST_PORT, + ROUTER_HASH_MSK_PROTOCOL, + ROUTER_HASH_MSK_METADATA, + ROUTER_HASH_MSK_ALL, /* Bitwise OR of the above 6 fields */ }; -int ipa_reg_init(struct ipa *ipa); +/* ENDP_FILTER_CACHE_CFG and ENDP_ROUTER_CACHE_CFG registers */ +enum ipa_reg_endp_cache_cfg_field_id { + CACHE_MSK_SRC_ID, + CACHE_MSK_SRC_IP, + CACHE_MSK_DST_IP, + CACHE_MSK_SRC_PORT, + CACHE_MSK_DST_PORT, + CACHE_MSK_PROTOCOL, + CACHE_MSK_METADATA, +}; + +/* IPA_IRQ_STTS, IPA_IRQ_EN, and IPA_IRQ_CLR registers */ +/** + * enum ipa_irq_id - Bit positions representing type of IPA IRQ + * @IPA_IRQ_UC_0: Microcontroller event interrupt + * @IPA_IRQ_UC_1: Microcontroller response interrupt + * @IPA_IRQ_TX_SUSPEND: Data ready interrupt + * @IPA_IRQ_COUNT: Number of IRQ ids (must be last) + * + * IRQ types not described above are not currently used. + * + * @IPA_IRQ_BAD_SNOC_ACCESS: (Not currently used) + * @IPA_IRQ_EOT_COAL: (Not currently used) + * @IPA_IRQ_UC_2: (Not currently used) + * @IPA_IRQ_UC_3: (Not currently used) + * @IPA_IRQ_UC_IN_Q_NOT_EMPTY: (Not currently used) + * @IPA_IRQ_UC_RX_CMD_Q_NOT_FULL: (Not currently used) + * @IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY: (Not currently used) + * @IPA_IRQ_RX_ERR: (Not currently used) + * @IPA_IRQ_DEAGGR_ERR: (Not currently used) + * @IPA_IRQ_TX_ERR: (Not currently used) + * @IPA_IRQ_STEP_MODE: (Not currently used) + * @IPA_IRQ_PROC_ERR: (Not currently used) + * @IPA_IRQ_TX_HOLB_DROP: (Not currently used) + * @IPA_IRQ_BAM_GSI_IDLE: (Not currently used) + * @IPA_IRQ_PIPE_YELLOW_BELOW: (Not currently used) + * @IPA_IRQ_PIPE_RED_BELOW: (Not currently used) + * @IPA_IRQ_PIPE_YELLOW_ABOVE: (Not currently used) + * @IPA_IRQ_PIPE_RED_ABOVE: (Not currently used) + * @IPA_IRQ_UCP: (Not currently used) + * @IPA_IRQ_DCMP: (Not currently used) + * @IPA_IRQ_GSI_EE: (Not currently used) + * @IPA_IRQ_GSI_IPA_IF_TLV_RCVD: (Not currently used) + * @IPA_IRQ_GSI_UC: (Not currently used) + * @IPA_IRQ_TLV_LEN_MIN_DSM: (Not currently used) + * @IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN: (Not currently used) + * @IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN: (Not currently used) + * @IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN: (Not currently used) + * @IPA_IRQ_ERROR_NON_FATAL: (Not currently used) + * @IPA_IRQ_ERROR_FATAL: (Not currently used) + */ +enum ipa_irq_id { + IPA_IRQ_BAD_SNOC_ACCESS = 0x0, /* Not IPA v5.5+ */ + IPA_IRQ_EOT_COAL = 0x1, /* Not IPA v3.5+ */ + IPA_IRQ_UC_0 = 0x2, + IPA_IRQ_UC_1 = 0x3, + IPA_IRQ_UC_2 = 0x4, + IPA_IRQ_UC_3 = 0x5, + IPA_IRQ_UC_IN_Q_NOT_EMPTY = 0x6, + IPA_IRQ_UC_RX_CMD_Q_NOT_FULL = 0x7, + IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY = 0x8, + IPA_IRQ_RX_ERR = 0x9, /* Not IPA v5.5+ */ + IPA_IRQ_DEAGGR_ERR = 0xa, /* Not IPA v5.5+ */ + IPA_IRQ_TX_ERR = 0xb, /* Not IPA v5.5+ */ + IPA_IRQ_STEP_MODE = 0xc, /* Not IPA v5.5+ */ + IPA_IRQ_PROC_ERR = 0xd, /* Not IPA v5.5+ */ + IPA_IRQ_TX_SUSPEND = 0xe, + IPA_IRQ_TX_HOLB_DROP = 0xf, + IPA_IRQ_BAM_GSI_IDLE = 0x10, + IPA_IRQ_PIPE_YELLOW_BELOW = 0x11, + IPA_IRQ_PIPE_RED_BELOW = 0x12, + IPA_IRQ_PIPE_YELLOW_ABOVE = 0x13, + IPA_IRQ_PIPE_RED_ABOVE = 0x14, + IPA_IRQ_UCP = 0x15, + IPA_IRQ_DCMP = 0x16, /* Not IPA v4.5+ */ + IPA_IRQ_GSI_EE = 0x17, + IPA_IRQ_GSI_IPA_IF_TLV_RCVD = 0x18, + IPA_IRQ_GSI_UC = 0x19, + IPA_IRQ_TLV_LEN_MIN_DSM = 0x1a, /* IPA v4.5-v5.2 */ + IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN = 0x1b, /* IPA v4.9-v5.2 */ + IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN = 0x1c, /* IPA v4.9-v5.2 */ + IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN = 0x1d, /* IPA v4.9-v5.2 */ + IPA_IRQ_ERROR_NON_FATAL = 0x1e, /* IPA v5.5+ */ + IPA_IRQ_ERROR_FATAL = 0x1f, /* IPA v5.5+ */ + IPA_IRQ_COUNT, /* Last; not an id */ +}; + +/* IPA_IRQ_UC register */ +enum ipa_reg_ipa_irq_uc_field_id { + UC_INTR, +}; + +extern const struct regs ipa_regs_v3_1; +extern const struct regs ipa_regs_v3_5_1; +extern const struct regs ipa_regs_v4_2; +extern const struct regs ipa_regs_v4_5; +extern const struct regs ipa_regs_v4_7; +extern const struct regs ipa_regs_v4_9; +extern const struct regs ipa_regs_v4_11; +extern const struct regs ipa_regs_v5_0; +extern const struct regs ipa_regs_v5_5; + +const struct reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id); + +int ipa_reg_init(struct ipa *ipa, struct platform_device *pdev); void ipa_reg_exit(struct ipa *ipa); #endif /* _IPA_REG_H_ */ |