diff options
Diffstat (limited to 'drivers/net/pcs')
| -rw-r--r-- | drivers/net/pcs/Kconfig | 6 | ||||
| -rw-r--r-- | drivers/net/pcs/Makefile | 3 | ||||
| -rw-r--r-- | drivers/net/pcs/pcs-lynx.c | 46 | ||||
| -rw-r--r-- | drivers/net/pcs/pcs-mtk-lynxi.c | 27 | ||||
| -rw-r--r-- | drivers/net/pcs/pcs-rzn1-miic.c | 47 | ||||
| -rw-r--r-- | drivers/net/pcs/pcs-xpcs-nxp.c | 24 | ||||
| -rw-r--r-- | drivers/net/pcs/pcs-xpcs-plat.c | 460 | ||||
| -rw-r--r-- | drivers/net/pcs/pcs-xpcs-wx.c | 56 | ||||
| -rw-r--r-- | drivers/net/pcs/pcs-xpcs.c | 981 | ||||
| -rw-r--r-- | drivers/net/pcs/pcs-xpcs.h | 71 |
10 files changed, 1193 insertions, 528 deletions
diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig index 87cf308fc6d8..f6aa437473de 100644 --- a/drivers/net/pcs/Kconfig +++ b/drivers/net/pcs/Kconfig @@ -6,11 +6,11 @@ menu "PCS device drivers" config PCS_XPCS - tristate + tristate "Synopsys DesignWare Ethernet XPCS" select PHYLINK help - This module provides helper functions for Synopsys DesignWare XPCS - controllers. + This module provides a driver and helper functions for Synopsys + DesignWare XPCS controllers. config PCS_LYNX tristate diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile index fb1694192ae6..4f7920618b90 100644 --- a/drivers/net/pcs/Makefile +++ b/drivers/net/pcs/Makefile @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 # Makefile for Linux PCS drivers -pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-nxp.o pcs-xpcs-wx.o +pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-plat.o \ + pcs-xpcs-nxp.o pcs-xpcs-wx.o obj-$(CONFIG_PCS_XPCS) += pcs_xpcs.o obj-$(CONFIG_PCS_LYNX) += pcs-lynx.o diff --git a/drivers/net/pcs/pcs-lynx.c b/drivers/net/pcs/pcs-lynx.c index dc3962b2aa6b..23b40e9eacbb 100644 --- a/drivers/net/pcs/pcs-lynx.c +++ b/drivers/net/pcs/pcs-lynx.c @@ -35,6 +35,27 @@ enum sgmii_speed { #define phylink_pcs_to_lynx(pl_pcs) container_of((pl_pcs), struct lynx_pcs, pcs) #define lynx_to_phylink_pcs(lynx) (&(lynx)->pcs) +static unsigned int lynx_pcs_inband_caps(struct phylink_pcs *pcs, + phy_interface_t interface) +{ + switch (interface) { + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; + + case PHY_INTERFACE_MODE_10GBASER: + case PHY_INTERFACE_MODE_2500BASEX: + return LINK_INBAND_DISABLE; + + case PHY_INTERFACE_MODE_USXGMII: + return LINK_INBAND_ENABLE; + + default: + return 0; + } +} + static void lynx_pcs_get_state_usxgmii(struct mdio_device *pcs, struct phylink_link_state *state) { @@ -61,11 +82,10 @@ static void lynx_pcs_get_state_usxgmii(struct mdio_device *pcs, static void lynx_pcs_get_state_2500basex(struct mdio_device *pcs, struct phylink_link_state *state) { - int bmsr, lpa; + int bmsr; bmsr = mdiodev_read(pcs, MII_BMSR); - lpa = mdiodev_read(pcs, MII_LPA); - if (bmsr < 0 || lpa < 0) { + if (bmsr < 0) { state->link = false; return; } @@ -80,7 +100,7 @@ static void lynx_pcs_get_state_2500basex(struct mdio_device *pcs, state->duplex = DUPLEX_FULL; } -static void lynx_pcs_get_state(struct phylink_pcs *pcs, +static void lynx_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, struct phylink_link_state *state) { struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs); @@ -89,7 +109,7 @@ static void lynx_pcs_get_state(struct phylink_pcs *pcs, case PHY_INTERFACE_MODE_1000BASEX: case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_QSGMII: - phylink_mii_c22_pcs_get_state(lynx->mdio, state); + phylink_mii_c22_pcs_get_state(lynx->mdio, neg_mode, state); break; case PHY_INTERFACE_MODE_2500BASEX: lynx_pcs_get_state_2500basex(lynx->mdio, state); @@ -307,15 +327,26 @@ static void lynx_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode, } static const struct phylink_pcs_ops lynx_pcs_phylink_ops = { + .pcs_inband_caps = lynx_pcs_inband_caps, .pcs_get_state = lynx_pcs_get_state, .pcs_config = lynx_pcs_config, .pcs_an_restart = lynx_pcs_an_restart, .pcs_link_up = lynx_pcs_link_up, }; +static const phy_interface_t lynx_interfaces[] = { + PHY_INTERFACE_MODE_SGMII, + PHY_INTERFACE_MODE_QSGMII, + PHY_INTERFACE_MODE_1000BASEX, + PHY_INTERFACE_MODE_2500BASEX, + PHY_INTERFACE_MODE_10GBASER, + PHY_INTERFACE_MODE_USXGMII, +}; + static struct phylink_pcs *lynx_pcs_create(struct mdio_device *mdio) { struct lynx_pcs *lynx; + int i; lynx = kzalloc(sizeof(*lynx), GFP_KERNEL); if (!lynx) @@ -324,9 +355,11 @@ static struct phylink_pcs *lynx_pcs_create(struct mdio_device *mdio) mdio_device_get(mdio); lynx->mdio = mdio; lynx->pcs.ops = &lynx_pcs_phylink_ops; - lynx->pcs.neg_mode = true; lynx->pcs.poll = true; + for (i = 0; i < ARRAY_SIZE(lynx_interfaces); i++) + __set_bit(lynx_interfaces[i], lynx->pcs.supported_interfaces); + return lynx_to_phylink_pcs(lynx); } @@ -398,4 +431,5 @@ void lynx_pcs_destroy(struct phylink_pcs *pcs) } EXPORT_SYMBOL(lynx_pcs_destroy); +MODULE_DESCRIPTION("NXP Lynx PCS phylink library"); MODULE_LICENSE("Dual BSD/GPL"); diff --git a/drivers/net/pcs/pcs-mtk-lynxi.c b/drivers/net/pcs/pcs-mtk-lynxi.c index 8501dd365279..149ddf51d785 100644 --- a/drivers/net/pcs/pcs-mtk-lynxi.c +++ b/drivers/net/pcs/pcs-mtk-lynxi.c @@ -88,7 +88,24 @@ static struct mtk_pcs_lynxi *pcs_to_mtk_pcs_lynxi(struct phylink_pcs *pcs) return container_of(pcs, struct mtk_pcs_lynxi, pcs); } +static unsigned int mtk_pcs_lynxi_inband_caps(struct phylink_pcs *pcs, + phy_interface_t interface) +{ + switch (interface) { + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_SGMII: + return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; + + case PHY_INTERFACE_MODE_2500BASEX: + return LINK_INBAND_DISABLE; + + default: + return 0; + } +} + static void mtk_pcs_lynxi_get_state(struct phylink_pcs *pcs, + unsigned int neg_mode, struct phylink_link_state *state) { struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs); @@ -98,7 +115,8 @@ static void mtk_pcs_lynxi_get_state(struct phylink_pcs *pcs, regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &bm); regmap_read(mpcs->regmap, SGMSYS_PCS_ADVERTISE, &adv); - phylink_mii_c22_pcs_decode_state(state, FIELD_GET(SGMII_BMSR, bm), + phylink_mii_c22_pcs_decode_state(state, neg_mode, + FIELD_GET(SGMII_BMSR, bm), FIELD_GET(SGMII_LPA, adv)); } @@ -241,6 +259,7 @@ static void mtk_pcs_lynxi_disable(struct phylink_pcs *pcs) } static const struct phylink_pcs_ops mtk_pcs_lynxi_ops = { + .pcs_inband_caps = mtk_pcs_lynxi_inband_caps, .pcs_get_state = mtk_pcs_lynxi_get_state, .pcs_config = mtk_pcs_lynxi_config, .pcs_an_restart = mtk_pcs_lynxi_restart_an, @@ -286,10 +305,13 @@ struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev, mpcs->regmap = regmap; mpcs->flags = flags; mpcs->pcs.ops = &mtk_pcs_lynxi_ops; - mpcs->pcs.neg_mode = true; mpcs->pcs.poll = true; mpcs->interface = PHY_INTERFACE_MODE_NA; + __set_bit(PHY_INTERFACE_MODE_SGMII, mpcs->pcs.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_1000BASEX, mpcs->pcs.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_2500BASEX, mpcs->pcs.supported_interfaces); + return &mpcs->pcs; } EXPORT_SYMBOL(mtk_pcs_lynxi_create); @@ -303,4 +325,5 @@ void mtk_pcs_lynxi_destroy(struct phylink_pcs *pcs) } EXPORT_SYMBOL(mtk_pcs_lynxi_destroy); +MODULE_DESCRIPTION("MediaTek SGMII library for LynxI"); MODULE_LICENSE("GPL"); diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-miic.c index d93f84fbb1fd..d79bb9b06cd2 100644 --- a/drivers/net/pcs/pcs-rzn1-miic.c +++ b/drivers/net/pcs/pcs-rzn1-miic.c @@ -183,7 +183,7 @@ static void miic_converter_enable(struct miic *miic, int port, int enable) miic_reg_rmw(miic, MIIC_CONVRST, MIIC_CONVRST_PHYIF_RST(port), val); } -static int miic_config(struct phylink_pcs *pcs, unsigned int mode, +static int miic_config(struct phylink_pcs *pcs, unsigned int neg_mode, phy_interface_t interface, const unsigned long *advertising, bool permit) { @@ -234,7 +234,7 @@ static int miic_config(struct phylink_pcs *pcs, unsigned int mode, return 0; } -static void miic_link_up(struct phylink_pcs *pcs, unsigned int mode, +static void miic_link_up(struct phylink_pcs *pcs, unsigned int neg_mode, phy_interface_t interface, int speed, int duplex) { struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); @@ -268,21 +268,37 @@ static void miic_link_up(struct phylink_pcs *pcs, unsigned int mode, (MIIC_CONVCTRL_CONV_SPEED | MIIC_CONVCTRL_FULLD), val); } -static int miic_validate(struct phylink_pcs *pcs, unsigned long *supported, - const struct phylink_link_state *state) +static int miic_pre_init(struct phylink_pcs *pcs) { - if (phy_interface_mode_is_rgmii(state->interface) || - state->interface == PHY_INTERFACE_MODE_RMII || - state->interface == PHY_INTERFACE_MODE_MII) - return 1; + struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); + struct miic *miic = miic_port->miic; + u32 val, mask; + + /* Start RX clock if required */ + if (pcs->rxc_always_on) { + /* In MII through mode, the clock signals will be driven by the + * external PHY, which might not be initialized yet. Set RMII + * as default mode to ensure that a reference clock signal is + * generated. + */ + miic_port->interface = PHY_INTERFACE_MODE_RMII; - return -EINVAL; + val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, CONV_MODE_RMII) | + FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, CONV_MODE_100MBPS); + mask = MIIC_CONVCTRL_CONV_MODE | MIIC_CONVCTRL_CONV_SPEED; + + miic_reg_rmw(miic, MIIC_CONVCTRL(miic_port->port), mask, val); + + miic_converter_enable(miic, miic_port->port, 1); + } + + return 0; } static const struct phylink_pcs_ops miic_phylink_ops = { - .pcs_validate = miic_validate, .pcs_config = miic_config, .pcs_link_up = miic_link_up, + .pcs_pre_init = miic_pre_init, }; struct phylink_pcs *miic_create(struct device *dev, struct device_node *np) @@ -334,6 +350,10 @@ struct phylink_pcs *miic_create(struct device *dev, struct device_node *np) miic_port->port = port - 1; miic_port->pcs.ops = &miic_phylink_ops; + phy_interface_set_rgmii(miic_port->pcs.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_RMII, miic_port->pcs.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_MII, miic_port->pcs.supported_interfaces); + return &miic_port->pcs; } EXPORT_SYMBOL(miic_create); @@ -443,13 +463,10 @@ static int miic_parse_dt(struct device *dev, u32 *mode_cfg) if (of_property_read_u32(np, "renesas,miic-switch-portin", &conf) == 0) dt_val[0] = conf; - for_each_child_of_node(np, conv) { + for_each_available_child_of_node(np, conv) { if (of_property_read_u32(conv, "reg", &port)) continue; - if (!of_device_is_available(conv)) - continue; - if (of_property_read_u32(conv, "renesas,miic-input", &conf) == 0) dt_val[port] = conf; } @@ -523,7 +540,7 @@ static struct platform_driver miic_driver = { .of_match_table = miic_of_mtable, }, .probe = miic_probe, - .remove_new = miic_remove, + .remove = miic_remove, }; module_platform_driver(miic_driver); diff --git a/drivers/net/pcs/pcs-xpcs-nxp.c b/drivers/net/pcs/pcs-xpcs-nxp.c index d16fc58cd48d..e8efe94cf4ec 100644 --- a/drivers/net/pcs/pcs-xpcs-nxp.c +++ b/drivers/net/pcs/pcs-xpcs-nxp.c @@ -152,26 +152,18 @@ static int nxp_sja1110_pma_config(struct dw_xpcs *xpcs, /* Enable TX and RX PLLs and circuits. * Release reset of PMA to enable data flow to/from PCS. */ - ret = xpcs_read(xpcs, MDIO_MMD_VEND2, SJA1110_POWERDOWN_ENABLE); - if (ret < 0) - return ret; - - val = ret & ~(SJA1110_TXPLL_PD | SJA1110_TXPD | SJA1110_RXCH_PD | - SJA1110_RXBIAS_PD | SJA1110_RESET_SER_EN | - SJA1110_RESET_SER | SJA1110_RESET_DES); - val |= SJA1110_RXPKDETEN | SJA1110_RCVEN; - - ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_POWERDOWN_ENABLE, val); + ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, SJA1110_POWERDOWN_ENABLE, + SJA1110_TXPLL_PD | SJA1110_TXPD | SJA1110_RXCH_PD | + SJA1110_RXBIAS_PD | SJA1110_RESET_SER_EN | + SJA1110_RESET_SER | SJA1110_RESET_DES | + SJA1110_RXPKDETEN | SJA1110_RCVEN, + SJA1110_RXPKDETEN | SJA1110_RCVEN); if (ret < 0) return ret; /* Program continuous-time linear equalizer (CTLE) settings. */ - ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_RX_CDR_CTLE, - rx_cdr_ctle); - if (ret < 0) - return ret; - - return 0; + return xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_RX_CDR_CTLE, + rx_cdr_ctle); } int nxp_sja1110_sgmii_pma_config(struct dw_xpcs *xpcs) diff --git a/drivers/net/pcs/pcs-xpcs-plat.c b/drivers/net/pcs/pcs-xpcs-plat.c new file mode 100644 index 000000000000..629315f1e57c --- /dev/null +++ b/drivers/net/pcs/pcs-xpcs-plat.c @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Synopsys DesignWare XPCS platform device driver + * + * Copyright (C) 2024 Serge Semin + */ + +#include <linux/atomic.h> +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/device.h> +#include <linux/kernel.h> +#include <linux/mdio.h> +#include <linux/module.h> +#include <linux/pcs/pcs-xpcs.h> +#include <linux/phy.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/property.h> +#include <linux/sizes.h> + +#include "pcs-xpcs.h" + +/* Page select register for the indirect MMIO CSRs access */ +#define DW_VR_CSR_VIEWPORT 0xff + +struct dw_xpcs_plat { + struct platform_device *pdev; + struct mii_bus *bus; + bool reg_indir; + int reg_width; + void __iomem *reg_base; + struct clk *cclk; +}; + +static ptrdiff_t xpcs_mmio_addr_format(int dev, int reg) +{ + return FIELD_PREP(0x1f0000, dev) | FIELD_PREP(0xffff, reg); +} + +static u16 xpcs_mmio_addr_page(ptrdiff_t csr) +{ + return FIELD_GET(0x1fff00, csr); +} + +static ptrdiff_t xpcs_mmio_addr_offset(ptrdiff_t csr) +{ + return FIELD_GET(0xff, csr); +} + +static int xpcs_mmio_read_reg_indirect(struct dw_xpcs_plat *pxpcs, + int dev, int reg) +{ + ptrdiff_t csr, ofs; + u16 page; + int ret; + + csr = xpcs_mmio_addr_format(dev, reg); + page = xpcs_mmio_addr_page(csr); + ofs = xpcs_mmio_addr_offset(csr); + + ret = pm_runtime_resume_and_get(&pxpcs->pdev->dev); + if (ret) + return ret; + + switch (pxpcs->reg_width) { + case 4: + writel(page, pxpcs->reg_base + (DW_VR_CSR_VIEWPORT << 2)); + ret = readl(pxpcs->reg_base + (ofs << 2)); + break; + default: + writew(page, pxpcs->reg_base + (DW_VR_CSR_VIEWPORT << 1)); + ret = readw(pxpcs->reg_base + (ofs << 1)); + break; + } + + pm_runtime_put(&pxpcs->pdev->dev); + + return ret; +} + +static int xpcs_mmio_write_reg_indirect(struct dw_xpcs_plat *pxpcs, + int dev, int reg, u16 val) +{ + ptrdiff_t csr, ofs; + u16 page; + int ret; + + csr = xpcs_mmio_addr_format(dev, reg); + page = xpcs_mmio_addr_page(csr); + ofs = xpcs_mmio_addr_offset(csr); + + ret = pm_runtime_resume_and_get(&pxpcs->pdev->dev); + if (ret) + return ret; + + switch (pxpcs->reg_width) { + case 4: + writel(page, pxpcs->reg_base + (DW_VR_CSR_VIEWPORT << 2)); + writel(val, pxpcs->reg_base + (ofs << 2)); + break; + default: + writew(page, pxpcs->reg_base + (DW_VR_CSR_VIEWPORT << 1)); + writew(val, pxpcs->reg_base + (ofs << 1)); + break; + } + + pm_runtime_put(&pxpcs->pdev->dev); + + return 0; +} + +static int xpcs_mmio_read_reg_direct(struct dw_xpcs_plat *pxpcs, + int dev, int reg) +{ + ptrdiff_t csr; + int ret; + + csr = xpcs_mmio_addr_format(dev, reg); + + ret = pm_runtime_resume_and_get(&pxpcs->pdev->dev); + if (ret) + return ret; + + switch (pxpcs->reg_width) { + case 4: + ret = readl(pxpcs->reg_base + (csr << 2)); + break; + default: + ret = readw(pxpcs->reg_base + (csr << 1)); + break; + } + + pm_runtime_put(&pxpcs->pdev->dev); + + return ret; +} + +static int xpcs_mmio_write_reg_direct(struct dw_xpcs_plat *pxpcs, + int dev, int reg, u16 val) +{ + ptrdiff_t csr; + int ret; + + csr = xpcs_mmio_addr_format(dev, reg); + + ret = pm_runtime_resume_and_get(&pxpcs->pdev->dev); + if (ret) + return ret; + + switch (pxpcs->reg_width) { + case 4: + writel(val, pxpcs->reg_base + (csr << 2)); + break; + default: + writew(val, pxpcs->reg_base + (csr << 1)); + break; + } + + pm_runtime_put(&pxpcs->pdev->dev); + + return 0; +} + +static int xpcs_mmio_read_c22(struct mii_bus *bus, int addr, int reg) +{ + struct dw_xpcs_plat *pxpcs = bus->priv; + + if (addr != 0) + return -ENODEV; + + if (pxpcs->reg_indir) + return xpcs_mmio_read_reg_indirect(pxpcs, MDIO_MMD_VEND2, reg); + else + return xpcs_mmio_read_reg_direct(pxpcs, MDIO_MMD_VEND2, reg); +} + +static int xpcs_mmio_write_c22(struct mii_bus *bus, int addr, int reg, u16 val) +{ + struct dw_xpcs_plat *pxpcs = bus->priv; + + if (addr != 0) + return -ENODEV; + + if (pxpcs->reg_indir) + return xpcs_mmio_write_reg_indirect(pxpcs, MDIO_MMD_VEND2, reg, val); + else + return xpcs_mmio_write_reg_direct(pxpcs, MDIO_MMD_VEND2, reg, val); +} + +static int xpcs_mmio_read_c45(struct mii_bus *bus, int addr, int dev, int reg) +{ + struct dw_xpcs_plat *pxpcs = bus->priv; + + if (addr != 0) + return -ENODEV; + + if (pxpcs->reg_indir) + return xpcs_mmio_read_reg_indirect(pxpcs, dev, reg); + else + return xpcs_mmio_read_reg_direct(pxpcs, dev, reg); +} + +static int xpcs_mmio_write_c45(struct mii_bus *bus, int addr, int dev, + int reg, u16 val) +{ + struct dw_xpcs_plat *pxpcs = bus->priv; + + if (addr != 0) + return -ENODEV; + + if (pxpcs->reg_indir) + return xpcs_mmio_write_reg_indirect(pxpcs, dev, reg, val); + else + return xpcs_mmio_write_reg_direct(pxpcs, dev, reg, val); +} + +static struct dw_xpcs_plat *xpcs_plat_create_data(struct platform_device *pdev) +{ + struct dw_xpcs_plat *pxpcs; + + pxpcs = devm_kzalloc(&pdev->dev, sizeof(*pxpcs), GFP_KERNEL); + if (!pxpcs) + return ERR_PTR(-ENOMEM); + + pxpcs->pdev = pdev; + + dev_set_drvdata(&pdev->dev, pxpcs); + + return pxpcs; +} + +static int xpcs_plat_init_res(struct dw_xpcs_plat *pxpcs) +{ + struct platform_device *pdev = pxpcs->pdev; + struct device *dev = &pdev->dev; + resource_size_t spc_size; + struct resource *res; + + if (!device_property_read_u32(dev, "reg-io-width", &pxpcs->reg_width)) { + if (pxpcs->reg_width != 2 && pxpcs->reg_width != 4) { + dev_err(dev, "Invalid reg-space data width\n"); + return -EINVAL; + } + } else { + pxpcs->reg_width = 2; + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "direct") ?: + platform_get_resource_byname(pdev, IORESOURCE_MEM, "indirect"); + if (!res) { + dev_err(dev, "No reg-space found\n"); + return -EINVAL; + } + + if (!strcmp(res->name, "indirect")) + pxpcs->reg_indir = true; + + if (pxpcs->reg_indir) + spc_size = pxpcs->reg_width * SZ_256; + else + spc_size = pxpcs->reg_width * SZ_2M; + + if (resource_size(res) < spc_size) { + dev_err(dev, "Invalid reg-space size\n"); + return -EINVAL; + } + + pxpcs->reg_base = devm_ioremap_resource(dev, res); + if (IS_ERR(pxpcs->reg_base)) { + dev_err(dev, "Failed to map reg-space\n"); + return PTR_ERR(pxpcs->reg_base); + } + + return 0; +} + +static int xpcs_plat_init_clk(struct dw_xpcs_plat *pxpcs) +{ + struct device *dev = &pxpcs->pdev->dev; + int ret; + + pxpcs->cclk = devm_clk_get(dev, "csr"); + if (IS_ERR(pxpcs->cclk)) + return dev_err_probe(dev, PTR_ERR(pxpcs->cclk), + "Failed to get CSR clock\n"); + + pm_runtime_set_active(dev); + ret = devm_pm_runtime_enable(dev); + if (ret) { + dev_err(dev, "Failed to enable runtime-PM\n"); + return ret; + } + + return 0; +} + +static int xpcs_plat_init_bus(struct dw_xpcs_plat *pxpcs) +{ + struct device *dev = &pxpcs->pdev->dev; + static atomic_t id = ATOMIC_INIT(-1); + int ret; + + pxpcs->bus = devm_mdiobus_alloc_size(dev, 0); + if (!pxpcs->bus) + return -ENOMEM; + + pxpcs->bus->name = "DW XPCS MCI/APB3"; + pxpcs->bus->read = xpcs_mmio_read_c22; + pxpcs->bus->write = xpcs_mmio_write_c22; + pxpcs->bus->read_c45 = xpcs_mmio_read_c45; + pxpcs->bus->write_c45 = xpcs_mmio_write_c45; + pxpcs->bus->phy_mask = ~0; + pxpcs->bus->parent = dev; + pxpcs->bus->priv = pxpcs; + + snprintf(pxpcs->bus->id, MII_BUS_ID_SIZE, + "dwxpcs-%x", atomic_inc_return(&id)); + + /* MDIO-bus here serves as just a back-end engine abstracting out + * the MDIO and MCI/APB3 IO interfaces utilized for the DW XPCS CSRs + * access. + */ + ret = devm_mdiobus_register(dev, pxpcs->bus); + if (ret) { + dev_err(dev, "Failed to create MDIO bus\n"); + return ret; + } + + return 0; +} + +/* Note there is no need in the next function antagonist because the MDIO-bus + * de-registration will effectively remove and destroy all the MDIO-devices + * registered on the bus. + */ +static int xpcs_plat_init_dev(struct dw_xpcs_plat *pxpcs) +{ + struct device *dev = &pxpcs->pdev->dev; + struct mdio_device *mdiodev; + int ret; + + /* There is a single memory-mapped DW XPCS device */ + mdiodev = mdio_device_create(pxpcs->bus, 0); + if (IS_ERR(mdiodev)) + return PTR_ERR(mdiodev); + + /* Associate the FW-node with the device structure so it can be looked + * up later. Make sure DD-core is aware of the OF-node being re-used. + */ + device_set_node(&mdiodev->dev, fwnode_handle_get(dev_fwnode(dev))); + mdiodev->dev.of_node_reused = true; + + /* Pass the data further so the DW XPCS driver core could use it */ + mdiodev->dev.platform_data = (void *)device_get_match_data(dev); + + ret = mdio_device_register(mdiodev); + if (ret) { + dev_err(dev, "Failed to register MDIO device\n"); + goto err_clean_data; + } + + return 0; + +err_clean_data: + mdiodev->dev.platform_data = NULL; + + fwnode_handle_put(dev_fwnode(&mdiodev->dev)); + device_set_node(&mdiodev->dev, NULL); + + mdio_device_free(mdiodev); + + return ret; +} + +static int xpcs_plat_probe(struct platform_device *pdev) +{ + struct dw_xpcs_plat *pxpcs; + int ret; + + pxpcs = xpcs_plat_create_data(pdev); + if (IS_ERR(pxpcs)) + return PTR_ERR(pxpcs); + + ret = xpcs_plat_init_res(pxpcs); + if (ret) + return ret; + + ret = xpcs_plat_init_clk(pxpcs); + if (ret) + return ret; + + ret = xpcs_plat_init_bus(pxpcs); + if (ret) + return ret; + + ret = xpcs_plat_init_dev(pxpcs); + if (ret) + return ret; + + return 0; +} + +static int __maybe_unused xpcs_plat_pm_runtime_suspend(struct device *dev) +{ + struct dw_xpcs_plat *pxpcs = dev_get_drvdata(dev); + + clk_disable_unprepare(pxpcs->cclk); + + return 0; +} + +static int __maybe_unused xpcs_plat_pm_runtime_resume(struct device *dev) +{ + struct dw_xpcs_plat *pxpcs = dev_get_drvdata(dev); + + return clk_prepare_enable(pxpcs->cclk); +} + +static const struct dev_pm_ops xpcs_plat_pm_ops = { + SET_RUNTIME_PM_OPS(xpcs_plat_pm_runtime_suspend, + xpcs_plat_pm_runtime_resume, + NULL) +}; + +DW_XPCS_INFO_DECLARE(xpcs_generic, DW_XPCS_ID_NATIVE, DW_XPCS_PMA_ID_NATIVE); +DW_XPCS_INFO_DECLARE(xpcs_pma_gen1_3g, DW_XPCS_ID_NATIVE, DW_XPCS_PMA_GEN1_3G_ID); +DW_XPCS_INFO_DECLARE(xpcs_pma_gen2_3g, DW_XPCS_ID_NATIVE, DW_XPCS_PMA_GEN2_3G_ID); +DW_XPCS_INFO_DECLARE(xpcs_pma_gen2_6g, DW_XPCS_ID_NATIVE, DW_XPCS_PMA_GEN2_6G_ID); +DW_XPCS_INFO_DECLARE(xpcs_pma_gen4_3g, DW_XPCS_ID_NATIVE, DW_XPCS_PMA_GEN4_3G_ID); +DW_XPCS_INFO_DECLARE(xpcs_pma_gen4_6g, DW_XPCS_ID_NATIVE, DW_XPCS_PMA_GEN4_6G_ID); +DW_XPCS_INFO_DECLARE(xpcs_pma_gen5_10g, DW_XPCS_ID_NATIVE, DW_XPCS_PMA_GEN5_10G_ID); +DW_XPCS_INFO_DECLARE(xpcs_pma_gen5_12g, DW_XPCS_ID_NATIVE, DW_XPCS_PMA_GEN5_12G_ID); + +static const struct of_device_id xpcs_of_ids[] = { + { .compatible = "snps,dw-xpcs", .data = &xpcs_generic }, + { .compatible = "snps,dw-xpcs-gen1-3g", .data = &xpcs_pma_gen1_3g }, + { .compatible = "snps,dw-xpcs-gen2-3g", .data = &xpcs_pma_gen2_3g }, + { .compatible = "snps,dw-xpcs-gen2-6g", .data = &xpcs_pma_gen2_6g }, + { .compatible = "snps,dw-xpcs-gen4-3g", .data = &xpcs_pma_gen4_3g }, + { .compatible = "snps,dw-xpcs-gen4-6g", .data = &xpcs_pma_gen4_6g }, + { .compatible = "snps,dw-xpcs-gen5-10g", .data = &xpcs_pma_gen5_10g }, + { .compatible = "snps,dw-xpcs-gen5-12g", .data = &xpcs_pma_gen5_12g }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, xpcs_of_ids); + +static struct platform_driver xpcs_plat_driver = { + .probe = xpcs_plat_probe, + .driver = { + .name = "dwxpcs", + .pm = &xpcs_plat_pm_ops, + .of_match_table = xpcs_of_ids, + }, +}; +module_platform_driver(xpcs_plat_driver); + +MODULE_DESCRIPTION("Synopsys DesignWare XPCS platform device driver"); +MODULE_AUTHOR("Signed-off-by: Serge Semin <fancer.lancer@gmail.com>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/net/pcs/pcs-xpcs-wx.c b/drivers/net/pcs/pcs-xpcs-wx.c index 19c75886f070..fc52f7aa5f59 100644 --- a/drivers/net/pcs/pcs-xpcs-wx.c +++ b/drivers/net/pcs/pcs-xpcs-wx.c @@ -46,25 +46,23 @@ #define TXGBE_VCO_CAL_LD0 0x72 #define TXGBE_VCO_CAL_REF0 0x76 -static int txgbe_read_pma(struct dw_xpcs *xpcs, int reg) +static int txgbe_write_pma(struct dw_xpcs *xpcs, int reg, u16 val) { - return xpcs_read(xpcs, MDIO_MMD_PMAPMD, TXGBE_PMA_MMD + reg); + return xpcs_write(xpcs, MDIO_MMD_PMAPMD, TXGBE_PMA_MMD + reg, val); } -static int txgbe_write_pma(struct dw_xpcs *xpcs, int reg, u16 val) +static int txgbe_modify_pma(struct dw_xpcs *xpcs, int reg, u16 mask, u16 set) { - return xpcs_write(xpcs, MDIO_MMD_PMAPMD, TXGBE_PMA_MMD + reg, val); + return xpcs_modify(xpcs, MDIO_MMD_PMAPMD, TXGBE_PMA_MMD + reg, mask, + set); } static void txgbe_pma_config_10gbaser(struct dw_xpcs *xpcs) { - int val; - txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL0, 0x21); txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL3, 0); - val = txgbe_read_pma(xpcs, TXGBE_TX_GENCTL1); - val = u16_replace_bits(val, 0x5, TXGBE_TX_GENCTL1_VBOOST_LVL); - txgbe_write_pma(xpcs, TXGBE_TX_GENCTL1, val); + txgbe_modify_pma(xpcs, TXGBE_TX_GENCTL1, TXGBE_TX_GENCTL1_VBOOST_LVL, + FIELD_PREP(TXGBE_TX_GENCTL1_VBOOST_LVL, 0x5)); txgbe_write_pma(xpcs, TXGBE_MISC_CTL0, TXGBE_MISC_CTL0_PLL | TXGBE_MISC_CTL0_CR_PARA_SEL | TXGBE_MISC_CTL0_RX_VREF(0xF)); txgbe_write_pma(xpcs, TXGBE_VCO_CAL_LD0, 0x549); @@ -78,38 +76,29 @@ static void txgbe_pma_config_10gbaser(struct dw_xpcs *xpcs) txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL0, TXGBE_RX_EQ_CTL0_CTLE_POLE(2) | TXGBE_RX_EQ_CTL0_CTLE_BOOST(5)); - val = txgbe_read_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL); - val &= ~TXGBE_RX_EQ_ATTN_LVL0; - txgbe_write_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, val); + txgbe_modify_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, TXGBE_RX_EQ_ATTN_LVL0, 0); txgbe_write_pma(xpcs, TXGBE_DFE_TAP_CTL0, 0xBE); - val = txgbe_read_pma(xpcs, TXGBE_AFE_DFE_ENABLE); - val &= ~(TXGBE_DFE_EN_0 | TXGBE_AFE_EN_0); - txgbe_write_pma(xpcs, TXGBE_AFE_DFE_ENABLE, val); - val = txgbe_read_pma(xpcs, TXGBE_RX_EQ_CTL4); - val &= ~TXGBE_RX_EQ_CTL4_CONT_ADAPT0; - txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL4, val); + txgbe_modify_pma(xpcs, TXGBE_AFE_DFE_ENABLE, + TXGBE_DFE_EN_0 | TXGBE_AFE_EN_0, 0); + txgbe_modify_pma(xpcs, TXGBE_RX_EQ_CTL4, TXGBE_RX_EQ_CTL4_CONT_ADAPT0, + 0); } static void txgbe_pma_config_1g(struct dw_xpcs *xpcs) { - int val; - - val = txgbe_read_pma(xpcs, TXGBE_TX_GENCTL1); - val = u16_replace_bits(val, 0x5, TXGBE_TX_GENCTL1_VBOOST_LVL); - val &= ~TXGBE_TX_GENCTL1_VBOOST_EN0; - txgbe_write_pma(xpcs, TXGBE_TX_GENCTL1, val); + txgbe_modify_pma(xpcs, TXGBE_TX_GENCTL1, + TXGBE_TX_GENCTL1_VBOOST_LVL | + TXGBE_TX_GENCTL1_VBOOST_EN0, + FIELD_PREP(TXGBE_TX_GENCTL1_VBOOST_LVL, 0x5)); txgbe_write_pma(xpcs, TXGBE_MISC_CTL0, TXGBE_MISC_CTL0_PLL | TXGBE_MISC_CTL0_CR_PARA_SEL | TXGBE_MISC_CTL0_RX_VREF(0xF)); txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL0, TXGBE_RX_EQ_CTL0_VGA1_GAIN(7) | TXGBE_RX_EQ_CTL0_VGA2_GAIN(7) | TXGBE_RX_EQ_CTL0_CTLE_BOOST(6)); - val = txgbe_read_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL); - val &= ~TXGBE_RX_EQ_ATTN_LVL0; - txgbe_write_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, val); + txgbe_modify_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, TXGBE_RX_EQ_ATTN_LVL0, 0); txgbe_write_pma(xpcs, TXGBE_DFE_TAP_CTL0, 0); - val = txgbe_read_pma(xpcs, TXGBE_RX_GEN_CTL3); - val = u16_replace_bits(val, 0x4, TXGBE_RX_GEN_CTL3_LOS_TRSHLD0); - txgbe_write_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, val); + txgbe_modify_pma(xpcs, TXGBE_RX_GEN_CTL3, TXGBE_RX_GEN_CTL3_LOS_TRSHLD0, + FIELD_PREP(TXGBE_RX_GEN_CTL3_LOS_TRSHLD0, 0x4)); txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL0, 0x20); txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL3, 0x46); @@ -172,7 +161,7 @@ static bool txgbe_xpcs_mode_quirk(struct dw_xpcs *xpcs) int txgbe_xpcs_switch_mode(struct dw_xpcs *xpcs, phy_interface_t interface) { - int val, ret; + int ret; switch (interface) { case PHY_INTERFACE_MODE_10GBASER: @@ -194,9 +183,8 @@ int txgbe_xpcs_switch_mode(struct dw_xpcs *xpcs, phy_interface_t interface) if (interface == PHY_INTERFACE_MODE_10GBASER) { xpcs_write(xpcs, MDIO_MMD_PCS, MDIO_CTRL2, MDIO_PCS_CTRL2_10GBR); - val = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_CTRL1); - val |= MDIO_CTRL1_SPEED10G; - xpcs_write(xpcs, MDIO_MMD_PMAPMD, MDIO_CTRL1, val); + xpcs_modify(xpcs, MDIO_MMD_PMAPMD, MDIO_CTRL1, + MDIO_CTRL1_SPEED10G, MDIO_CTRL1_SPEED10G); txgbe_pma_config_10gbaser(xpcs); } else { xpcs_write(xpcs, MDIO_MMD_PCS, MDIO_CTRL2, MDIO_PCS_CTRL2_10GBX); diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c index 31f0beba638a..3d1bd5aac093 100644 --- a/drivers/net/pcs/pcs-xpcs.c +++ b/drivers/net/pcs/pcs-xpcs.c @@ -6,11 +6,14 @@ * Author: Jose Abreu <Jose.Abreu@synopsys.com> */ +#include <linux/clk.h> #include <linux/delay.h> #include <linux/pcs/pcs-xpcs.h> #include <linux/mdio.h> +#include <linux/phy.h> #include <linux/phylink.h> -#include <linux/workqueue.h> +#include <linux/property.h> + #include "pcs-xpcs.h" #define phylink_pcs_to_xpcs(pl_pcs) \ @@ -104,81 +107,42 @@ static const int xpcs_2500basex_features[] = { __ETHTOOL_LINK_MODE_MASK_NBITS, }; -static const phy_interface_t xpcs_usxgmii_interfaces[] = { - PHY_INTERFACE_MODE_USXGMII, -}; - -static const phy_interface_t xpcs_10gkr_interfaces[] = { - PHY_INTERFACE_MODE_10GKR, -}; - -static const phy_interface_t xpcs_xlgmii_interfaces[] = { - PHY_INTERFACE_MODE_XLGMII, -}; - -static const phy_interface_t xpcs_10gbaser_interfaces[] = { - PHY_INTERFACE_MODE_10GBASER, -}; - -static const phy_interface_t xpcs_sgmii_interfaces[] = { - PHY_INTERFACE_MODE_SGMII, -}; - -static const phy_interface_t xpcs_1000basex_interfaces[] = { - PHY_INTERFACE_MODE_1000BASEX, -}; - -static const phy_interface_t xpcs_2500basex_interfaces[] = { - PHY_INTERFACE_MODE_2500BASEX, - PHY_INTERFACE_MODE_MAX, -}; - -enum { - DW_XPCS_USXGMII, - DW_XPCS_10GKR, - DW_XPCS_XLGMII, - DW_XPCS_10GBASER, - DW_XPCS_SGMII, - DW_XPCS_1000BASEX, - DW_XPCS_2500BASEX, - DW_XPCS_INTERFACE_MAX, -}; - -struct xpcs_compat { +struct dw_xpcs_compat { + phy_interface_t interface; const int *supported; - const phy_interface_t *interface; - int num_interfaces; int an_mode; int (*pma_config)(struct dw_xpcs *xpcs); }; -struct xpcs_id { +struct dw_xpcs_desc { u32 id; u32 mask; - const struct xpcs_compat *compat; + const struct dw_xpcs_compat *compat; }; -static const struct xpcs_compat *xpcs_find_compat(const struct xpcs_id *id, - phy_interface_t interface) +static const struct dw_xpcs_compat * +xpcs_find_compat(struct dw_xpcs *xpcs, phy_interface_t interface) { - int i, j; - - for (i = 0; i < DW_XPCS_INTERFACE_MAX; i++) { - const struct xpcs_compat *compat = &id->compat[i]; + const struct dw_xpcs_compat *compat; - for (j = 0; j < compat->num_interfaces; j++) - if (compat->interface[j] == interface) - return compat; - } + for (compat = xpcs->desc->compat; compat->supported; compat++) + if (compat->interface == interface) + return compat; return NULL; } +struct phylink_pcs *xpcs_to_phylink_pcs(struct dw_xpcs *xpcs) +{ + return &xpcs->pcs; +} +EXPORT_SYMBOL_GPL(xpcs_to_phylink_pcs); + int xpcs_get_an_mode(struct dw_xpcs *xpcs, phy_interface_t interface) { - const struct xpcs_compat *compat; + const struct dw_xpcs_compat *compat; - compat = xpcs_find_compat(xpcs->id, interface); + compat = xpcs_find_compat(xpcs, interface); if (!compat) return -ENODEV; @@ -186,7 +150,7 @@ int xpcs_get_an_mode(struct dw_xpcs *xpcs, phy_interface_t interface) } EXPORT_SYMBOL_GPL(xpcs_get_an_mode); -static bool __xpcs_linkmode_supported(const struct xpcs_compat *compat, +static bool __xpcs_linkmode_supported(const struct dw_xpcs_compat *compat, enum ethtool_link_mode_bit_indices linkmode) { int i; @@ -211,6 +175,11 @@ int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val) return mdiodev_c45_write(xpcs->mdiodev, dev, reg, val); } +int xpcs_modify(struct dw_xpcs *xpcs, int dev, u32 reg, u16 mask, u16 set) +{ + return mdiodev_c45_modify(xpcs->mdiodev, dev, reg, mask, set); +} + static int xpcs_modify_changed(struct dw_xpcs *xpcs, int dev, u32 reg, u16 mask, u16 set) { @@ -228,6 +197,12 @@ static int xpcs_write_vendor(struct dw_xpcs *xpcs, int dev, int reg, return xpcs_write(xpcs, dev, DW_VENDOR | reg, val); } +static int xpcs_modify_vendor(struct dw_xpcs *xpcs, int dev, int reg, u16 mask, + u16 set) +{ + return xpcs_modify(xpcs, dev, DW_VENDOR | reg, mask, set); +} + int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg) { return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg); @@ -238,47 +213,26 @@ int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val) return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val); } -static int xpcs_dev_flag(struct dw_xpcs *xpcs) +static int xpcs_modify_vpcs(struct dw_xpcs *xpcs, int reg, u16 mask, u16 val) { - int ret, oui; - - ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID1); - if (ret < 0) - return ret; - - oui = ret; - - ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID2); - if (ret < 0) - return ret; - - ret = (ret >> 10) & 0x3F; - oui |= ret << 16; - - if (oui == DW_OUI_WX) - xpcs->dev_flag = DW_DEV_TXGBE; - - return 0; + return xpcs_modify_vendor(xpcs, MDIO_MMD_PCS, reg, mask, val); } static int xpcs_poll_reset(struct dw_xpcs *xpcs, int dev) { - /* Poll until the reset bit clears (50ms per retry == 0.6 sec) */ - unsigned int retries = 12; - int ret; + int ret, val; - do { - msleep(50); - ret = xpcs_read(xpcs, dev, MDIO_CTRL1); - if (ret < 0) - return ret; - } while (ret & MDIO_CTRL1_RESET && --retries); + ret = read_poll_timeout(xpcs_read, val, + val < 0 || !(val & BMCR_RESET), + 50000, 600000, true, xpcs, dev, MII_BMCR); + if (val < 0) + ret = val; - return (ret & MDIO_CTRL1_RESET) ? -ETIMEDOUT : 0; + return ret; } static int xpcs_soft_reset(struct dw_xpcs *xpcs, - const struct xpcs_compat *compat) + const struct dw_xpcs_compat *compat) { int ret, dev; @@ -293,10 +247,10 @@ static int xpcs_soft_reset(struct dw_xpcs *xpcs, dev = MDIO_MMD_VEND2; break; default: - return -1; + return -EINVAL; } - ret = xpcs_write(xpcs, dev, MDIO_CTRL1, MDIO_CTRL1_RESET); + ret = xpcs_write(xpcs, dev, MII_BMCR, BMCR_RESET); if (ret < 0) return ret; @@ -357,7 +311,7 @@ static int xpcs_read_fault_c73(struct dw_xpcs *xpcs, return 0; } -static void xpcs_config_usxgmii(struct dw_xpcs *xpcs, int speed) +static void xpcs_link_up_usxgmii(struct dw_xpcs *xpcs, int speed) { int ret, speed_sel; @@ -385,41 +339,29 @@ static void xpcs_config_usxgmii(struct dw_xpcs *xpcs, int speed) return; } - ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1); + ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_EN, DW_USXGMII_EN); if (ret < 0) goto out; - ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_EN); - if (ret < 0) - goto out; - - ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1); - if (ret < 0) - goto out; - - ret &= ~DW_USXGMII_SS_MASK; - ret |= speed_sel | DW_USXGMII_FULL; - - ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret); + ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, DW_USXGMII_SS_MASK, + speed_sel | DW_USXGMII_FULL); if (ret < 0) goto out; - ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1); - if (ret < 0) - goto out; - - ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_RST); + ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_RST, + DW_USXGMII_RST); if (ret < 0) goto out; return; out: - pr_err("%s: XPCS access returned %pe\n", __func__, ERR_PTR(ret)); + dev_err(&xpcs->mdiodev->dev, "%s: XPCS access returned %pe\n", + __func__, ERR_PTR(ret)); } static int _xpcs_config_aneg_c73(struct dw_xpcs *xpcs, - const struct xpcs_compat *compat) + const struct dw_xpcs_compat *compat) { int ret, adv; @@ -464,7 +406,7 @@ static int _xpcs_config_aneg_c73(struct dw_xpcs *xpcs, } static int xpcs_config_aneg_c73(struct dw_xpcs *xpcs, - const struct xpcs_compat *compat) + const struct dw_xpcs_compat *compat) { int ret; @@ -472,18 +414,14 @@ static int xpcs_config_aneg_c73(struct dw_xpcs *xpcs, if (ret < 0) return ret; - ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_CTRL1); - if (ret < 0) - return ret; - - ret |= MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART; - - return xpcs_write(xpcs, MDIO_MMD_AN, MDIO_CTRL1, ret); + return xpcs_modify(xpcs, MDIO_MMD_AN, MDIO_CTRL1, + MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART, + MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); } static int xpcs_aneg_done_c73(struct dw_xpcs *xpcs, struct phylink_link_state *state, - const struct xpcs_compat *compat, u16 an_stat1) + const struct dw_xpcs_compat *compat, u16 an_stat1) { int ret; @@ -608,85 +546,112 @@ static int xpcs_validate(struct phylink_pcs *pcs, unsigned long *supported, const struct phylink_link_state *state) { __ETHTOOL_DECLARE_LINK_MODE_MASK(xpcs_supported) = { 0, }; - const struct xpcs_compat *compat; + const struct dw_xpcs_compat *compat; struct dw_xpcs *xpcs; int i; xpcs = phylink_pcs_to_xpcs(pcs); - compat = xpcs_find_compat(xpcs->id, state->interface); + compat = xpcs_find_compat(xpcs, state->interface); + if (!compat) + return -EINVAL; /* Populate the supported link modes for this PHY interface type. * FIXME: what about the port modes and autoneg bit? This masks * all those away. */ - if (compat) - for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) - set_bit(compat->supported[i], xpcs_supported); + for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) + set_bit(compat->supported[i], xpcs_supported); linkmode_and(supported, supported, xpcs_supported); return 0; } -void xpcs_get_interfaces(struct dw_xpcs *xpcs, unsigned long *interfaces) +static unsigned int xpcs_inband_caps(struct phylink_pcs *pcs, + phy_interface_t interface) { - int i, j; + struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); + const struct dw_xpcs_compat *compat; - for (i = 0; i < DW_XPCS_INTERFACE_MAX; i++) { - const struct xpcs_compat *compat = &xpcs->id->compat[i]; + compat = xpcs_find_compat(xpcs, interface); + if (!compat) + return 0; + + switch (compat->an_mode) { + case DW_AN_C73: + return LINK_INBAND_ENABLE; + + case DW_AN_C37_SGMII: + case DW_AN_C37_1000BASEX: + return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; + + case DW_10GBASER: + case DW_2500BASEX: + return LINK_INBAND_DISABLE; - for (j = 0; j < compat->num_interfaces; j++) - if (compat->interface[j] < PHY_INTERFACE_MODE_MAX) - __set_bit(compat->interface[j], interfaces); + default: + return 0; } } -EXPORT_SYMBOL_GPL(xpcs_get_interfaces); -int xpcs_config_eee(struct dw_xpcs *xpcs, int mult_fact_100ns, int enable) +static void xpcs_get_interfaces(struct dw_xpcs *xpcs, unsigned long *interfaces) { - int ret; + const struct dw_xpcs_compat *compat; - ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0); - if (ret < 0) - return ret; + for (compat = xpcs->desc->compat; compat->supported; compat++) + __set_bit(compat->interface, interfaces); +} - if (enable) { - /* Enable EEE */ - ret = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | - DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | - DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | - mult_fact_100ns << DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT; - } else { - ret &= ~(DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | - DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | - DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | - DW_VR_MII_EEE_MULT_FACT_100NS); +static int xpcs_switch_interface_mode(struct dw_xpcs *xpcs, + phy_interface_t interface) +{ + int ret = 0; + + if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { + ret = txgbe_xpcs_switch_mode(xpcs, interface); + } else if (xpcs->interface != interface) { + if (interface == PHY_INTERFACE_MODE_SGMII) + xpcs->need_reset = true; + xpcs->interface = interface; } - ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, ret); - if (ret < 0) - return ret; + return ret; +} - ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1); - if (ret < 0) - return ret; +static void xpcs_pre_config(struct phylink_pcs *pcs, phy_interface_t interface) +{ + struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); + const struct dw_xpcs_compat *compat; + int ret; - if (enable) - ret |= DW_VR_MII_EEE_TRN_LPI; - else - ret &= ~DW_VR_MII_EEE_TRN_LPI; + ret = xpcs_switch_interface_mode(xpcs, interface); + if (ret) + dev_err(&xpcs->mdiodev->dev, "switch interface failed: %pe\n", + ERR_PTR(ret)); + + if (!xpcs->need_reset) + return; - return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, ret); + compat = xpcs_find_compat(xpcs, interface); + if (!compat) { + dev_err(&xpcs->mdiodev->dev, "unsupported interface %s\n", + phy_modes(interface)); + return; + } + + ret = xpcs_soft_reset(xpcs, compat); + if (ret) + dev_err(&xpcs->mdiodev->dev, "soft reset failed: %pe\n", + ERR_PTR(ret)); + + xpcs->need_reset = false; } -EXPORT_SYMBOL_GPL(xpcs_config_eee); static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, unsigned int neg_mode) { int ret, mdio_ctrl, tx_conf; - - if (xpcs->dev_flag == DW_DEV_TXGBE) - xpcs_write_vpcs(xpcs, DW_VR_XS_PCS_DIG_CTRL1, DW_CL37_BP | DW_EN_VSMMD1); + u16 mask, val; /* For AN for C37 SGMII mode, the settings are :- * 1) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 0b (Disable SGMII AN in case @@ -698,63 +663,62 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, * speed/duplex mode change by HW after SGMII AN complete) * 5) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 1b (Enable SGMII AN) * + * Note that VR_MII_MMD_CTRL is MII_BMCR. + * * Note: Since it is MAC side SGMII, there is no need to set * SR_MII_AN_ADV. MAC side SGMII receives AN Tx Config from * PHY about the link state change after C28 AN is completed * between PHY and Link Partner. There is also no need to * trigger AN restart for MAC-side SGMII. */ - mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL); + mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR); if (mdio_ctrl < 0) return mdio_ctrl; - if (mdio_ctrl & AN_CL37_EN) { - ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, - mdio_ctrl & ~AN_CL37_EN); + if (mdio_ctrl & BMCR_ANENABLE) { + ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, + mdio_ctrl & ~BMCR_ANENABLE); if (ret < 0) return ret; } - ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL); - if (ret < 0) - return ret; + mask = DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK; + val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, + DW_VR_MII_PCS_MODE_C37_SGMII); - ret &= ~(DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK); - ret |= (DW_VR_MII_PCS_MODE_C37_SGMII << - DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT & - DW_VR_MII_PCS_MODE_MASK); - if (xpcs->dev_flag == DW_DEV_TXGBE) { - ret |= DW_VR_MII_AN_CTRL_8BIT; + if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { + mask |= DW_VR_MII_AN_CTRL_8BIT; + val |= DW_VR_MII_AN_CTRL_8BIT; /* Hardware requires it to be PHY side SGMII */ tx_conf = DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII; } else { tx_conf = DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII; } - ret |= tx_conf << DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT & - DW_VR_MII_TX_CONFIG_MASK; - ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret); - if (ret < 0) - return ret; - ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1); + val |= FIELD_PREP(DW_VR_MII_TX_CONFIG_MASK, tx_conf); + + ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, mask, val); if (ret < 0) return ret; + val = 0; + mask = DW_VR_MII_DIG_CTRL1_2G5_EN | DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; + if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) - ret |= DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; - else - ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; + val = DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; - if (xpcs->dev_flag == DW_DEV_TXGBE) - ret |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL; + if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { + mask |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL; + val |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL; + } - ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret); + ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, mask, val); if (ret < 0) return ret; if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) - ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, - mdio_ctrl | AN_CL37_EN); + ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, + mdio_ctrl | BMCR_ANENABLE); return ret; } @@ -766,34 +730,36 @@ static int xpcs_config_aneg_c37_1000basex(struct dw_xpcs *xpcs, phy_interface_t interface = PHY_INTERFACE_MODE_1000BASEX; int ret, mdio_ctrl, adv; bool changed = 0; - - if (xpcs->dev_flag == DW_DEV_TXGBE) - xpcs_write_vpcs(xpcs, DW_VR_XS_PCS_DIG_CTRL1, DW_CL37_BP | DW_EN_VSMMD1); + u16 mask, val; /* According to Chap 7.12, to set 1000BASE-X C37 AN, AN must * be disabled first:- * 1) VR_MII_MMD_CTRL Bit(12)[AN_ENABLE] = 0b * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 00b (1000BASE-X C37) + * + * Note that VR_MII_MMD_CTRL is MII_BMCR. */ - mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL); + mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR); if (mdio_ctrl < 0) return mdio_ctrl; - if (mdio_ctrl & AN_CL37_EN) { - ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, - mdio_ctrl & ~AN_CL37_EN); + if (mdio_ctrl & BMCR_ANENABLE) { + ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, + mdio_ctrl & ~BMCR_ANENABLE); if (ret < 0) return ret; } - ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL); - if (ret < 0) - return ret; + mask = DW_VR_MII_PCS_MODE_MASK; + val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, + DW_VR_MII_PCS_MODE_C37_1000BASEX); - ret &= ~DW_VR_MII_PCS_MODE_MASK; - if (!xpcs->pcs.poll) - ret |= DW_VR_MII_AN_INTR_EN; - ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret); + if (!xpcs->pcs.poll) { + mask |= DW_VR_MII_AN_INTR_EN; + val |= DW_VR_MII_AN_INTR_EN; + } + + ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, mask, val); if (ret < 0) return ret; @@ -817,8 +783,8 @@ static int xpcs_config_aneg_c37_1000basex(struct dw_xpcs *xpcs, return ret; if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { - ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, - mdio_ctrl | AN_CL37_EN); + ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, + mdio_ctrl | BMCR_ANENABLE); if (ret < 0) return ret; } @@ -830,38 +796,37 @@ static int xpcs_config_2500basex(struct dw_xpcs *xpcs) { int ret; - ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1); - if (ret < 0) - return ret; - ret |= DW_VR_MII_DIG_CTRL1_2G5_EN; - ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; - ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret); + ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, + DW_VR_MII_DIG_CTRL1_2G5_EN | + DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW, + DW_VR_MII_DIG_CTRL1_2G5_EN); if (ret < 0) return ret; - ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL); - if (ret < 0) - return ret; - ret &= ~AN_CL37_EN; - ret |= SGMII_SPEED_SS6; - ret &= ~SGMII_SPEED_SS13; - return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, ret); + return xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, + BMCR_ANENABLE | BMCR_SPEED1000 | BMCR_SPEED100, + BMCR_SPEED1000); } -int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface, - const unsigned long *advertising, unsigned int neg_mode) +static int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface, + const unsigned long *advertising, + unsigned int neg_mode) { - const struct xpcs_compat *compat; + const struct dw_xpcs_compat *compat; int ret; - compat = xpcs_find_compat(xpcs->id, interface); + compat = xpcs_find_compat(xpcs, interface); if (!compat) return -ENODEV; - if (xpcs->dev_flag == DW_DEV_TXGBE) { - ret = txgbe_xpcs_switch_mode(xpcs, interface); - if (ret) - return ret; + if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { + /* Wangxun devices need backplane CL37 AN enabled for + * SGMII and 1000base-X + */ + if (interface == PHY_INTERFACE_MODE_SGMII || + interface == PHY_INTERFACE_MODE_1000BASEX) + xpcs_write_vpcs(xpcs, DW_VR_XS_PCS_DIG_CTRL1, + DW_CL37_BP | DW_EN_VSMMD1); } switch (compat->an_mode) { @@ -891,7 +856,7 @@ int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface, return ret; break; default: - return -1; + return -EINVAL; } if (compat->pma_config) { @@ -902,7 +867,6 @@ int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface, return 0; } -EXPORT_SYMBOL_GPL(xpcs_do_config); static int xpcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, phy_interface_t interface, @@ -916,7 +880,7 @@ static int xpcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, static int xpcs_get_state_c73(struct dw_xpcs *xpcs, struct phylink_link_state *state, - const struct xpcs_compat *compat) + const struct dw_xpcs_compat *compat) { bool an_enabled; int pcs_stat1; @@ -1010,8 +974,7 @@ static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs, state->link = true; - speed_value = (ret & DW_VR_MII_AN_STS_C37_ANSGM_SP) >> - DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT; + speed_value = FIELD_GET(DW_VR_MII_AN_STS_C37_ANSGM_SP, ret); if (speed_value == DW_VR_MII_C37_ANSGM_SP_1000) state->speed = SPEED_1000; else if (speed_value == DW_VR_MII_C37_ANSGM_SP_100) @@ -1028,14 +991,14 @@ static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs, state->link = true; - speed = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1); + speed = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR); if (speed < 0) return speed; - speed &= SGMII_SPEED_SS13 | SGMII_SPEED_SS6; - if (speed == SGMII_SPEED_SS6) + speed &= BMCR_SPEED100 | BMCR_SPEED1000; + if (speed == BMCR_SPEED1000) state->speed = SPEED_1000; - else if (speed == SGMII_SPEED_SS13) + else if (speed == BMCR_SPEED100) state->speed = SPEED_100; else if (speed == 0) state->speed = SPEED_10; @@ -1044,9 +1007,9 @@ static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs, if (duplex < 0) return duplex; - if (duplex & DW_FULL_DUPLEX) + if (duplex & ADVERTISE_1000XFULL) state->duplex = DUPLEX_FULL; - else if (duplex & DW_HALF_DUPLEX) + else if (duplex & ADVERTISE_1000XHALF) state->duplex = DUPLEX_HALF; xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0); @@ -1056,6 +1019,7 @@ static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs, } static int xpcs_get_state_c37_1000basex(struct dw_xpcs *xpcs, + unsigned int neg_mode, struct phylink_link_state *state) { int lpa, bmsr; @@ -1084,7 +1048,7 @@ static int xpcs_get_state_c37_1000basex(struct dw_xpcs *xpcs, } } - phylink_mii_c22_pcs_decode_state(state, bmsr, lpa); + phylink_mii_c22_pcs_decode_state(state, neg_mode, bmsr, lpa); } return 0; @@ -1095,13 +1059,13 @@ static int xpcs_get_state_2500basex(struct dw_xpcs *xpcs, { int ret; - ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_STS); + ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR); if (ret < 0) { state->link = 0; return ret; } - state->link = !!(ret & DW_VR_MII_MMD_STS_LINK_STS); + state->link = !!(ret & BMSR_LSTATUS); if (!state->link) return 0; @@ -1112,14 +1076,14 @@ static int xpcs_get_state_2500basex(struct dw_xpcs *xpcs, return 0; } -static void xpcs_get_state(struct phylink_pcs *pcs, +static void xpcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, struct phylink_link_state *state) { struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); - const struct xpcs_compat *compat; + const struct dw_xpcs_compat *compat; int ret; - compat = xpcs_find_compat(xpcs->id, state->interface); + compat = xpcs_find_compat(xpcs, state->interface); if (!compat) return; @@ -1129,311 +1093,434 @@ static void xpcs_get_state(struct phylink_pcs *pcs, break; case DW_AN_C73: ret = xpcs_get_state_c73(xpcs, state, compat); - if (ret) { - pr_err("xpcs_get_state_c73 returned %pe\n", - ERR_PTR(ret)); - return; - } + if (ret) + dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", + "xpcs_get_state_c73", ERR_PTR(ret)); break; case DW_AN_C37_SGMII: ret = xpcs_get_state_c37_sgmii(xpcs, state); - if (ret) { - pr_err("xpcs_get_state_c37_sgmii returned %pe\n", - ERR_PTR(ret)); - } + if (ret) + dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", + "xpcs_get_state_c37_sgmii", ERR_PTR(ret)); break; case DW_AN_C37_1000BASEX: - ret = xpcs_get_state_c37_1000basex(xpcs, state); - if (ret) { - pr_err("xpcs_get_state_c37_1000basex returned %pe\n", - ERR_PTR(ret)); - } + ret = xpcs_get_state_c37_1000basex(xpcs, neg_mode, state); + if (ret) + dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", + "xpcs_get_state_c37_1000basex", ERR_PTR(ret)); break; case DW_2500BASEX: ret = xpcs_get_state_2500basex(xpcs, state); - if (ret) { - pr_err("xpcs_get_state_2500basex returned %pe\n", - ERR_PTR(ret)); - } + if (ret) + dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", + "xpcs_get_state_2500basex", ERR_PTR(ret)); break; default: return; } } -static void xpcs_link_up_sgmii(struct dw_xpcs *xpcs, unsigned int neg_mode, - int speed, int duplex) +static void xpcs_link_up_sgmii_1000basex(struct dw_xpcs *xpcs, + unsigned int neg_mode, + phy_interface_t interface, + int speed, int duplex) { - int val, ret; + int ret; if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) return; - val = mii_bmcr_encode_fixed(speed, duplex); - ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val); + if (interface == PHY_INTERFACE_MODE_1000BASEX) { + if (speed != SPEED_1000) { + dev_err(&xpcs->mdiodev->dev, + "%s: speed %dMbps not supported\n", + __func__, speed); + return; + } + + if (duplex != DUPLEX_FULL) + dev_err(&xpcs->mdiodev->dev, + "%s: half duplex not supported\n", + __func__); + } + + ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, + mii_bmcr_encode_fixed(speed, duplex)); if (ret) - pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret)); + dev_err(&xpcs->mdiodev->dev, "%s: xpcs_write returned %pe\n", + __func__, ERR_PTR(ret)); } -static void xpcs_link_up_1000basex(struct dw_xpcs *xpcs, unsigned int neg_mode, - int speed, int duplex) +static void xpcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode, + phy_interface_t interface, int speed, int duplex) { - int val, ret; + struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); - if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) - return; + switch (interface) { + case PHY_INTERFACE_MODE_USXGMII: + xpcs_link_up_usxgmii(xpcs, speed); + break; - switch (speed) { - case SPEED_1000: - val = BMCR_SPEED1000; + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + xpcs_link_up_sgmii_1000basex(xpcs, neg_mode, interface, speed, + duplex); break; - case SPEED_100: - case SPEED_10: + default: - pr_err("%s: speed = %d\n", __func__, speed); - return; + break; } +} + +static void xpcs_an_restart(struct phylink_pcs *pcs) +{ + struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); + + xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, BMCR_ANRESTART, + BMCR_ANRESTART); +} + +static int xpcs_config_eee(struct dw_xpcs *xpcs, bool enable) +{ + u16 mask, val; + int ret; - if (duplex == DUPLEX_FULL) - val |= BMCR_FULLDPLX; + mask = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | + DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | + DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | + DW_VR_MII_EEE_MULT_FACT_100NS; + + if (enable) + val = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | + DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | + DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | + FIELD_PREP(DW_VR_MII_EEE_MULT_FACT_100NS, + xpcs->eee_mult_fact); else - pr_err("%s: half duplex not supported\n", __func__); + val = 0; - ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val); - if (ret) - pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret)); + ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, mask, + val); + if (ret < 0) + return ret; + + return xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, + DW_VR_MII_EEE_TRN_LPI, + enable ? DW_VR_MII_EEE_TRN_LPI : 0); } -void xpcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode, - phy_interface_t interface, int speed, int duplex) +static void xpcs_disable_eee(struct phylink_pcs *pcs) { struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); - if (interface == PHY_INTERFACE_MODE_USXGMII) - return xpcs_config_usxgmii(xpcs, speed); - if (interface == PHY_INTERFACE_MODE_SGMII) - return xpcs_link_up_sgmii(xpcs, neg_mode, speed, duplex); - if (interface == PHY_INTERFACE_MODE_1000BASEX) - return xpcs_link_up_1000basex(xpcs, neg_mode, speed, duplex); + xpcs_config_eee(xpcs, false); } -EXPORT_SYMBOL_GPL(xpcs_link_up); -static void xpcs_an_restart(struct phylink_pcs *pcs) +static void xpcs_enable_eee(struct phylink_pcs *pcs) { struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); - int ret; - ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1); - if (ret >= 0) { - ret |= BMCR_ANRESTART; - xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret); - } + xpcs_config_eee(xpcs, true); } -static u32 xpcs_get_id(struct dw_xpcs *xpcs) +/** + * xpcs_config_eee_mult_fact() - set the EEE clock multiplying factor + * @xpcs: pointer to a &struct dw_xpcs instance + * @mult_fact: the multiplying factor + * + * Configure the EEE clock multiplying factor. This value should be such that + * clk_eee_time_period * (mult_fact + 1) is within the range 80 to 120ns. + */ +void xpcs_config_eee_mult_fact(struct dw_xpcs *xpcs, u8 mult_fact) +{ + xpcs->eee_mult_fact = mult_fact; +} +EXPORT_SYMBOL_GPL(xpcs_config_eee_mult_fact); + +static int xpcs_read_ids(struct dw_xpcs *xpcs) { int ret; u32 id; - /* First, search C73 PCS using PCS MMD */ + /* First, search C73 PCS using PCS MMD 3. Return ENODEV if communication + * failed indicating that device couldn't be reached. + */ ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID1); if (ret < 0) - return 0xffffffff; + return -ENODEV; id = ret << 16; ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID2); if (ret < 0) - return 0xffffffff; + return ret; - /* If Device IDs are not all zeros or all ones, - * we found C73 AN-type device + id |= ret; + + /* If Device IDs are not all zeros or ones, then 10GBase-X/R or C73 + * KR/KX4 PCS found. Otherwise fallback to detecting 1000Base-X or C37 + * PCS in MII MMD 31. */ - if ((id | ret) && (id | ret) != 0xffffffff) - return id | ret; + if (!id || id == 0xffffffff) { + ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID1); + if (ret < 0) + return ret; + + id = ret << 16; + + ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID2); + if (ret < 0) + return ret; - /* Next, search C37 PCS using Vendor-Specific MII MMD */ - ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID1); + id |= ret; + } + + /* Set the PCS ID if it hasn't been pre-initialized */ + if (xpcs->info.pcs == DW_XPCS_ID_NATIVE) + xpcs->info.pcs = id; + + /* Find out PMA/PMD ID from MMD 1 device ID registers */ + ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID1); if (ret < 0) - return 0xffffffff; + return ret; - id = ret << 16; + id = ret; - ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID2); + ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID2); if (ret < 0) - return 0xffffffff; + return ret; + + /* Note the inverted dword order and masked out Model/Revision numbers + * with respect to what is done with the PCS ID... + */ + ret = (ret >> 10) & 0x3F; + id |= ret << 16; - /* If Device IDs are not all zeros, we found C37 AN-type device */ - if (id | ret) - return id | ret; + /* Set the PMA ID if it hasn't been pre-initialized */ + if (xpcs->info.pma == DW_XPCS_PMA_ID_NATIVE) + xpcs->info.pma = id; - return 0xffffffff; + return 0; } -static const struct xpcs_compat synopsys_xpcs_compat[DW_XPCS_INTERFACE_MAX] = { - [DW_XPCS_USXGMII] = { +static const struct dw_xpcs_compat synopsys_xpcs_compat[] = { + { + .interface = PHY_INTERFACE_MODE_USXGMII, .supported = xpcs_usxgmii_features, - .interface = xpcs_usxgmii_interfaces, - .num_interfaces = ARRAY_SIZE(xpcs_usxgmii_interfaces), .an_mode = DW_AN_C73, - }, - [DW_XPCS_10GKR] = { + }, { + .interface = PHY_INTERFACE_MODE_10GKR, .supported = xpcs_10gkr_features, - .interface = xpcs_10gkr_interfaces, - .num_interfaces = ARRAY_SIZE(xpcs_10gkr_interfaces), .an_mode = DW_AN_C73, - }, - [DW_XPCS_XLGMII] = { + }, { + .interface = PHY_INTERFACE_MODE_XLGMII, .supported = xpcs_xlgmii_features, - .interface = xpcs_xlgmii_interfaces, - .num_interfaces = ARRAY_SIZE(xpcs_xlgmii_interfaces), .an_mode = DW_AN_C73, - }, - [DW_XPCS_10GBASER] = { + }, { + .interface = PHY_INTERFACE_MODE_10GBASER, .supported = xpcs_10gbaser_features, - .interface = xpcs_10gbaser_interfaces, - .num_interfaces = ARRAY_SIZE(xpcs_10gbaser_interfaces), .an_mode = DW_10GBASER, - }, - [DW_XPCS_SGMII] = { + }, { + .interface = PHY_INTERFACE_MODE_SGMII, .supported = xpcs_sgmii_features, - .interface = xpcs_sgmii_interfaces, - .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces), .an_mode = DW_AN_C37_SGMII, - }, - [DW_XPCS_1000BASEX] = { + }, { + .interface = PHY_INTERFACE_MODE_1000BASEX, .supported = xpcs_1000basex_features, - .interface = xpcs_1000basex_interfaces, - .num_interfaces = ARRAY_SIZE(xpcs_1000basex_interfaces), .an_mode = DW_AN_C37_1000BASEX, - }, - [DW_XPCS_2500BASEX] = { + }, { + .interface = PHY_INTERFACE_MODE_2500BASEX, .supported = xpcs_2500basex_features, - .interface = xpcs_2500basex_interfaces, - .num_interfaces = ARRAY_SIZE(xpcs_2500basex_interfaces), .an_mode = DW_2500BASEX, - }, + }, { + } }; -static const struct xpcs_compat nxp_sja1105_xpcs_compat[DW_XPCS_INTERFACE_MAX] = { - [DW_XPCS_SGMII] = { +static const struct dw_xpcs_compat nxp_sja1105_xpcs_compat[] = { + { + .interface = PHY_INTERFACE_MODE_SGMII, .supported = xpcs_sgmii_features, - .interface = xpcs_sgmii_interfaces, - .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces), .an_mode = DW_AN_C37_SGMII, .pma_config = nxp_sja1105_sgmii_pma_config, - }, + }, { + } }; -static const struct xpcs_compat nxp_sja1110_xpcs_compat[DW_XPCS_INTERFACE_MAX] = { - [DW_XPCS_SGMII] = { +static const struct dw_xpcs_compat nxp_sja1110_xpcs_compat[] = { + { + .interface = PHY_INTERFACE_MODE_SGMII, .supported = xpcs_sgmii_features, - .interface = xpcs_sgmii_interfaces, - .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces), .an_mode = DW_AN_C37_SGMII, .pma_config = nxp_sja1110_sgmii_pma_config, - }, - [DW_XPCS_2500BASEX] = { + }, { + .interface = PHY_INTERFACE_MODE_2500BASEX, .supported = xpcs_2500basex_features, - .interface = xpcs_2500basex_interfaces, - .num_interfaces = ARRAY_SIZE(xpcs_2500basex_interfaces), .an_mode = DW_2500BASEX, .pma_config = nxp_sja1110_2500basex_pma_config, - }, + }, { + } }; -static const struct xpcs_id xpcs_id_list[] = { +static const struct dw_xpcs_desc xpcs_desc_list[] = { { - .id = SYNOPSYS_XPCS_ID, - .mask = SYNOPSYS_XPCS_MASK, + .id = DW_XPCS_ID, + .mask = DW_XPCS_ID_MASK, .compat = synopsys_xpcs_compat, }, { .id = NXP_SJA1105_XPCS_ID, - .mask = SYNOPSYS_XPCS_MASK, + .mask = DW_XPCS_ID_MASK, .compat = nxp_sja1105_xpcs_compat, }, { .id = NXP_SJA1110_XPCS_ID, - .mask = SYNOPSYS_XPCS_MASK, + .mask = DW_XPCS_ID_MASK, .compat = nxp_sja1110_xpcs_compat, }, }; static const struct phylink_pcs_ops xpcs_phylink_ops = { .pcs_validate = xpcs_validate, + .pcs_inband_caps = xpcs_inband_caps, + .pcs_pre_config = xpcs_pre_config, .pcs_config = xpcs_config, .pcs_get_state = xpcs_get_state, .pcs_an_restart = xpcs_an_restart, .pcs_link_up = xpcs_link_up, + .pcs_disable_eee = xpcs_disable_eee, + .pcs_enable_eee = xpcs_enable_eee, }; -static struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev, - phy_interface_t interface) +static int xpcs_identify(struct dw_xpcs *xpcs) { - struct dw_xpcs *xpcs; - u32 xpcs_id; int i, ret; + ret = xpcs_read_ids(xpcs); + if (ret < 0) + return ret; + + for (i = 0; i < ARRAY_SIZE(xpcs_desc_list); i++) { + const struct dw_xpcs_desc *entry = &xpcs_desc_list[i]; + + if ((xpcs->info.pcs & entry->mask) == entry->id) { + xpcs->desc = entry; + return 0; + } + } + + return -ENODEV; +} + +static struct dw_xpcs *xpcs_create_data(struct mdio_device *mdiodev) +{ + struct dw_xpcs *xpcs; + xpcs = kzalloc(sizeof(*xpcs), GFP_KERNEL); if (!xpcs) return ERR_PTR(-ENOMEM); mdio_device_get(mdiodev); xpcs->mdiodev = mdiodev; + xpcs->pcs.ops = &xpcs_phylink_ops; + xpcs->pcs.poll = true; - xpcs_id = xpcs_get_id(xpcs); - - for (i = 0; i < ARRAY_SIZE(xpcs_id_list); i++) { - const struct xpcs_id *entry = &xpcs_id_list[i]; - const struct xpcs_compat *compat; + return xpcs; +} - if ((xpcs_id & entry->mask) != entry->id) - continue; +static void xpcs_free_data(struct dw_xpcs *xpcs) +{ + mdio_device_put(xpcs->mdiodev); + kfree(xpcs); +} - xpcs->id = entry; +static int xpcs_init_clks(struct dw_xpcs *xpcs) +{ + static const char *ids[DW_XPCS_NUM_CLKS] = { + [DW_XPCS_CORE_CLK] = "core", + [DW_XPCS_PAD_CLK] = "pad", + }; + struct device *dev = &xpcs->mdiodev->dev; + int ret, i; - compat = xpcs_find_compat(entry, interface); - if (!compat) { - ret = -ENODEV; - goto out; - } + for (i = 0; i < DW_XPCS_NUM_CLKS; ++i) + xpcs->clks[i].id = ids[i]; - ret = xpcs_dev_flag(xpcs); - if (ret) - goto out; + ret = clk_bulk_get_optional(dev, DW_XPCS_NUM_CLKS, xpcs->clks); + if (ret) + return dev_err_probe(dev, ret, "Failed to get clocks\n"); - xpcs->pcs.ops = &xpcs_phylink_ops; - xpcs->pcs.neg_mode = true; + ret = clk_bulk_prepare_enable(DW_XPCS_NUM_CLKS, xpcs->clks); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable clocks\n"); - if (xpcs->dev_flag != DW_DEV_TXGBE) { - xpcs->pcs.poll = true; + return 0; +} - ret = xpcs_soft_reset(xpcs, compat); - if (ret) - goto out; - } +static void xpcs_clear_clks(struct dw_xpcs *xpcs) +{ + clk_bulk_disable_unprepare(DW_XPCS_NUM_CLKS, xpcs->clks); - return xpcs; - } + clk_bulk_put(DW_XPCS_NUM_CLKS, xpcs->clks); +} - ret = -ENODEV; +static int xpcs_init_id(struct dw_xpcs *xpcs) +{ + const struct dw_xpcs_info *info; -out: - mdio_device_put(mdiodev); - kfree(xpcs); + info = dev_get_platdata(&xpcs->mdiodev->dev); + if (!info) { + xpcs->info.pcs = DW_XPCS_ID_NATIVE; + xpcs->info.pma = DW_XPCS_PMA_ID_NATIVE; + } else { + xpcs->info = *info; + } - return ERR_PTR(ret); + return xpcs_identify(xpcs); } -void xpcs_destroy(struct dw_xpcs *xpcs) +static struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev) { - if (xpcs) - mdio_device_put(xpcs->mdiodev); - kfree(xpcs); + struct dw_xpcs *xpcs; + int ret; + + xpcs = xpcs_create_data(mdiodev); + if (IS_ERR(xpcs)) + return xpcs; + + ret = xpcs_init_clks(xpcs); + if (ret) + goto out_free_data; + + ret = xpcs_init_id(xpcs); + if (ret) + goto out_clear_clks; + + xpcs_get_interfaces(xpcs, xpcs->pcs.supported_interfaces); + + if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) + xpcs->pcs.poll = false; + else + xpcs->need_reset = true; + + return xpcs; + +out_clear_clks: + xpcs_clear_clks(xpcs); + +out_free_data: + xpcs_free_data(xpcs); + + return ERR_PTR(ret); } -EXPORT_SYMBOL_GPL(xpcs_destroy); -struct dw_xpcs *xpcs_create_mdiodev(struct mii_bus *bus, int addr, - phy_interface_t interface) +/** + * xpcs_create_mdiodev() - create a DW xPCS instance with the MDIO @addr + * @bus: pointer to the MDIO-bus descriptor for the device to be looked at + * @addr: device MDIO-bus ID + * + * Return: a pointer to the DW XPCS handle if successful, otherwise -ENODEV if + * the PCS device couldn't be found on the bus and other negative errno related + * to the data allocation and MDIO-bus communications. + */ +struct dw_xpcs *xpcs_create_mdiodev(struct mii_bus *bus, int addr) { struct mdio_device *mdiodev; struct dw_xpcs *xpcs; @@ -1442,7 +1529,7 @@ struct dw_xpcs *xpcs_create_mdiodev(struct mii_bus *bus, int addr, if (IS_ERR(mdiodev)) return ERR_CAST(mdiodev); - xpcs = xpcs_create(mdiodev, interface); + xpcs = xpcs_create(mdiodev); /* xpcs_create() has taken a refcount on the mdiodev if it was * successful. If xpcs_create() fails, this will free the mdio @@ -1456,4 +1543,70 @@ struct dw_xpcs *xpcs_create_mdiodev(struct mii_bus *bus, int addr, } EXPORT_SYMBOL_GPL(xpcs_create_mdiodev); +struct phylink_pcs *xpcs_create_pcs_mdiodev(struct mii_bus *bus, int addr) +{ + struct dw_xpcs *xpcs; + + xpcs = xpcs_create_mdiodev(bus, addr); + if (IS_ERR(xpcs)) + return ERR_CAST(xpcs); + + return &xpcs->pcs; +} +EXPORT_SYMBOL_GPL(xpcs_create_pcs_mdiodev); + +/** + * xpcs_create_fwnode() - Create a DW xPCS instance from @fwnode + * @fwnode: fwnode handle poining to the DW XPCS device + * + * Return: a pointer to the DW XPCS handle if successful, otherwise -ENODEV if + * the fwnode device is unavailable or the PCS device couldn't be found on the + * bus, -EPROBE_DEFER if the respective MDIO-device instance couldn't be found, + * other negative errno related to the data allocations and MDIO-bus + * communications. + */ +struct dw_xpcs *xpcs_create_fwnode(struct fwnode_handle *fwnode) +{ + struct mdio_device *mdiodev; + struct dw_xpcs *xpcs; + + if (!fwnode_device_is_available(fwnode)) + return ERR_PTR(-ENODEV); + + mdiodev = fwnode_mdio_find_device(fwnode); + if (!mdiodev) + return ERR_PTR(-EPROBE_DEFER); + + xpcs = xpcs_create(mdiodev); + + /* xpcs_create() has taken a refcount on the mdiodev if it was + * successful. If xpcs_create() fails, this will free the mdio + * device here. In any case, we don't need to hold our reference + * anymore, and putting it here will allow mdio_device_put() in + * xpcs_destroy() to automatically free the mdio device. + */ + mdio_device_put(mdiodev); + + return xpcs; +} +EXPORT_SYMBOL_GPL(xpcs_create_fwnode); + +void xpcs_destroy(struct dw_xpcs *xpcs) +{ + if (!xpcs) + return; + + xpcs_clear_clks(xpcs); + + xpcs_free_data(xpcs); +} +EXPORT_SYMBOL_GPL(xpcs_destroy); + +void xpcs_destroy_pcs(struct phylink_pcs *pcs) +{ + xpcs_destroy(phylink_pcs_to_xpcs(pcs)); +} +EXPORT_SYMBOL_GPL(xpcs_destroy_pcs); + +MODULE_DESCRIPTION("Synopsys DesignWare XPCS library"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/net/pcs/pcs-xpcs.h b/drivers/net/pcs/pcs-xpcs.h index 96c36b32ca99..929fa238445e 100644 --- a/drivers/net/pcs/pcs-xpcs.h +++ b/drivers/net/pcs/pcs-xpcs.h @@ -6,8 +6,8 @@ * Author: Jose Abreu <Jose.Abreu@synopsys.com> */ -#define SYNOPSYS_XPCS_ID 0x7996ced0 -#define SYNOPSYS_XPCS_MASK 0xffffffff +#include <linux/bits.h> +#include <linux/pcs/pcs-xpcs.h> /* Vendor regs access */ #define DW_VENDOR BIT(15) @@ -54,74 +54,71 @@ /* Clause 37 Defines */ /* VR MII MMD registers offsets */ -#define DW_VR_MII_MMD_CTRL 0x0000 -#define DW_VR_MII_MMD_STS 0x0001 -#define DW_VR_MII_MMD_STS_LINK_STS BIT(2) #define DW_VR_MII_DIG_CTRL1 0x8000 -#define DW_VR_MII_AN_CTRL 0x8001 -#define DW_VR_MII_AN_INTR_STS 0x8002 -/* Enable 2.5G Mode */ -#define DW_VR_MII_DIG_CTRL1_2G5_EN BIT(2) -/* EEE Mode Control Register */ -#define DW_VR_MII_EEE_MCTRL0 0x8006 -#define DW_VR_MII_EEE_MCTRL1 0x800b -#define DW_VR_MII_DIG_CTRL2 0x80e1 - -/* VR_MII_DIG_CTRL1 */ #define DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW BIT(9) +#define DW_VR_MII_DIG_CTRL1_2G5_EN BIT(2) #define DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL BIT(0) -/* VR_MII_DIG_CTRL2 */ -#define DW_VR_MII_DIG_CTRL2_TX_POL_INV BIT(4) -#define DW_VR_MII_DIG_CTRL2_RX_POL_INV BIT(0) - -/* VR_MII_AN_CTRL */ +#define DW_VR_MII_AN_CTRL 0x8001 #define DW_VR_MII_AN_CTRL_8BIT BIT(8) -#define DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT 3 #define DW_VR_MII_TX_CONFIG_MASK BIT(3) #define DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII 0x1 #define DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII 0x0 -#define DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT 1 #define DW_VR_MII_PCS_MODE_MASK GENMASK(2, 1) #define DW_VR_MII_PCS_MODE_C37_1000BASEX 0x0 #define DW_VR_MII_PCS_MODE_C37_SGMII 0x2 #define DW_VR_MII_AN_INTR_EN BIT(0) -/* VR_MII_AN_INTR_STS */ +#define DW_VR_MII_AN_INTR_STS 0x8002 #define DW_VR_MII_AN_STS_C37_ANCMPLT_INTR BIT(0) #define DW_VR_MII_AN_STS_C37_ANSGM_FD BIT(1) -#define DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT 2 #define DW_VR_MII_AN_STS_C37_ANSGM_SP GENMASK(3, 2) #define DW_VR_MII_C37_ANSGM_SP_10 0x0 #define DW_VR_MII_C37_ANSGM_SP_100 0x1 #define DW_VR_MII_C37_ANSGM_SP_1000 0x2 #define DW_VR_MII_C37_ANSGM_SP_LNKSTS BIT(4) -/* SR MII MMD Control defines */ -#define AN_CL37_EN BIT(12) /* Enable Clause 37 auto-nego */ -#define SGMII_SPEED_SS13 BIT(13) /* SGMII speed along with SS6 */ -#define SGMII_SPEED_SS6 BIT(6) /* SGMII speed along with SS13 */ - -/* SR MII MMD AN Advertisement defines */ -#define DW_HALF_DUPLEX BIT(6) -#define DW_FULL_DUPLEX BIT(5) - -/* VR MII EEE Control 0 defines */ +#define DW_VR_MII_EEE_MCTRL0 0x8006 #define DW_VR_MII_EEE_LTX_EN BIT(0) /* LPI Tx Enable */ #define DW_VR_MII_EEE_LRX_EN BIT(1) /* LPI Rx Enable */ #define DW_VR_MII_EEE_TX_QUIET_EN BIT(2) /* Tx Quiet Enable */ #define DW_VR_MII_EEE_RX_QUIET_EN BIT(3) /* Rx Quiet Enable */ #define DW_VR_MII_EEE_TX_EN_CTRL BIT(4) /* Tx Control Enable */ #define DW_VR_MII_EEE_RX_EN_CTRL BIT(7) /* Rx Control Enable */ - -#define DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT 8 #define DW_VR_MII_EEE_MULT_FACT_100NS GENMASK(11, 8) -/* VR MII EEE Control 1 defines */ +#define DW_VR_MII_EEE_MCTRL1 0x800b #define DW_VR_MII_EEE_TRN_LPI BIT(0) /* Transparent Mode Enable */ +#define DW_VR_MII_DIG_CTRL2 0x80e1 +#define DW_VR_MII_DIG_CTRL2_TX_POL_INV BIT(4) +#define DW_VR_MII_DIG_CTRL2_RX_POL_INV BIT(0) + +#define DW_XPCS_INFO_DECLARE(_name, _pcs, _pma) \ + static const struct dw_xpcs_info _name = { .pcs = _pcs, .pma = _pma } + +struct dw_xpcs_desc; + +enum dw_xpcs_clock { + DW_XPCS_CORE_CLK, + DW_XPCS_PAD_CLK, + DW_XPCS_NUM_CLKS, +}; + +struct dw_xpcs { + struct dw_xpcs_info info; + const struct dw_xpcs_desc *desc; + struct mdio_device *mdiodev; + struct clk_bulk_data clks[DW_XPCS_NUM_CLKS]; + struct phylink_pcs pcs; + phy_interface_t interface; + bool need_reset; + u8 eee_mult_fact; +}; + int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg); int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val); +int xpcs_modify(struct dw_xpcs *xpcs, int dev, u32 reg, u16 mask, u16 set); int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg); int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val); int nxp_sja1105_sgmii_pma_config(struct dw_xpcs *xpcs); |