diff options
Diffstat (limited to 'drivers/net/wireless/realtek/rtw89/mac_be.c')
| -rw-r--r-- | drivers/net/wireless/realtek/rtw89/mac_be.c | 446 |
1 files changed, 411 insertions, 35 deletions
diff --git a/drivers/net/wireless/realtek/rtw89/mac_be.c b/drivers/net/wireless/realtek/rtw89/mac_be.c index be30c9346293..8c9d326dc907 100644 --- a/drivers/net/wireless/realtek/rtw89/mac_be.c +++ b/drivers/net/wireless/realtek/rtw89/mac_be.c @@ -29,6 +29,7 @@ static const u32 rtw89_mac_mem_base_addrs_be[RTW89_MAC_MEM_NUM] = { [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR_BE, [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR_BE, [RTW89_MAC_MEM_WD_PAGE] = WD_PAGE_BASE_ADDR_BE, + [RTW89_MAC_MEM_MLD_TBL] = MLD_TBL_BASE_ADDR_BE, }; static const struct rtw89_port_reg rtw89_port_base_be = { @@ -52,6 +53,9 @@ static const struct rtw89_port_reg rtw89_port_base_be = { .mbssid = R_BE_MBSSID_CTRL, .mbssid_drop = R_BE_MBSSID_DROP_0, .tsf_sync = R_BE_PORT_0_TSF_SYNC, + .ptcl_dbg = R_BE_PTCL_DBG, + .ptcl_dbg_info = R_BE_PTCL_DBG_INFO, + .bcn_drop_all = R_BE_BCN_DROP_ALL0, .hiq_win = {R_BE_P0MB_HGQ_WINDOW_CFG_0, R_BE_PORT_HGQ_WINDOW_CFG, R_BE_PORT_HGQ_WINDOW_CFG + 1, R_BE_PORT_HGQ_WINDOW_CFG + 2, R_BE_PORT_HGQ_WINDOW_CFG + 3}, @@ -705,8 +709,8 @@ static int sec_eng_init_be(struct rtw89_dev *rtwdev) val32 |= B_BE_CLK_EN_CGCMP | B_BE_CLK_EN_WAPI | B_BE_CLK_EN_WEP_TKIP | B_BE_SEC_TX_ENC | B_BE_SEC_RX_DEC | B_BE_MC_DEC | B_BE_BC_DEC | - B_BE_BMC_MGNT_DEC | B_BE_UC_MGNT_DEC; - val32 &= ~B_BE_SEC_PRE_ENQUE_TX; + B_BE_BMC_MGNT_DEC | B_BE_UC_MGNT_DEC | + B_BE_SEC_PRE_ENQUE_TX; rtw89_write32(rtwdev, R_BE_SEC_ENG_CTRL, val32); rtw89_write32_set(rtwdev, R_BE_SEC_MPDU_PROC, B_BE_APPEND_ICV | B_BE_APPEND_MIC); @@ -770,7 +774,7 @@ static int dmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) return ret; } - ret = rtw89_mac_preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); + ret = rtw89_mac_preload_init(rtwdev, mac_idx, rtwdev->mac.qta_mode); if (ret) { rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); return ret; @@ -988,6 +992,9 @@ static int spatial_reuse_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_SR_CTRL, mac_idx); rtw89_write8_clr(rtwdev, reg, B_BE_SR_EN | B_BE_SR_CTRL_PLCP_EN); + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BSSID_SRC_CTRL, mac_idx); + rtw89_write8_set(rtwdev, reg, B_BE_PLCP_SRC_EN); + return 0; } @@ -995,7 +1002,8 @@ static int tmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) { u32 reg; - rtw89_write32_clr(rtwdev, R_BE_TB_PPDU_CTRL, B_BE_QOSNULL_UPD_MUEDCA_EN); + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TB_PPDU_CTRL, mac_idx); + rtw89_write32_clr(rtwdev, reg, B_BE_QOSNULL_UPD_MUEDCA_EN); reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMTX_TCR_BE_4, mac_idx); rtw89_write32_mask(rtwdev, reg, B_BE_EHT_HE_PPDU_4XLTF_ZLD_USTIMER_MASK, 0x12); @@ -1449,6 +1457,71 @@ static int set_cpuio_be(struct rtw89_dev *rtwdev, return 0; } +static int dle_upd_qta_aval_page_be(struct rtw89_dev *rtwdev, + enum rtw89_mac_dle_ctrl_type type, + enum rtw89_mac_dle_ple_quota_id quota_id) +{ + u32 val; + + if (type == DLE_CTRL_TYPE_WDE) { + rtw89_write32_mask(rtwdev, R_BE_WDE_BUFMGN_CTL, + B_BE_WDE_AVAL_UPD_QTAID_MASK, quota_id); + rtw89_write32_set(rtwdev, R_BE_WDE_BUFMGN_CTL, B_BE_WDE_AVAL_UPD_REQ); + + return read_poll_timeout(rtw89_read32, val, + !(val & B_BE_WDE_AVAL_UPD_REQ), + 1, 2000, false, rtwdev, R_BE_WDE_BUFMGN_CTL); + } else if (type == DLE_CTRL_TYPE_PLE) { + rtw89_write32_mask(rtwdev, R_BE_PLE_BUFMGN_CTL, + B_BE_PLE_AVAL_UPD_QTAID_MASK, quota_id); + rtw89_write32_set(rtwdev, R_BE_PLE_BUFMGN_CTL, B_BE_PLE_AVAL_UPD_REQ); + + return read_poll_timeout(rtw89_read32, val, + !(val & B_BE_PLE_AVAL_UPD_REQ), + 1, 2000, false, rtwdev, R_BE_PLE_BUFMGN_CTL); + } + + rtw89_warn(rtwdev, "%s wrong type %d\n", __func__, type); + return -EINVAL; +} + +static int dle_quota_change_be(struct rtw89_dev *rtwdev, bool band1_en) +{ + int ret; + + if (band1_en) { + ret = dle_upd_qta_aval_page_be(rtwdev, DLE_CTRL_TYPE_PLE, + PLE_QTAID_B0_TXPL); + if (ret) { + rtw89_err(rtwdev, "update PLE B0 TX avail page fail %d\n", ret); + return ret; + } + + ret = dle_upd_qta_aval_page_be(rtwdev, DLE_CTRL_TYPE_PLE, + PLE_QTAID_CMAC0_RX); + if (ret) { + rtw89_err(rtwdev, "update PLE CMAC0 RX avail page fail %d\n", ret); + return ret; + } + } else { + ret = dle_upd_qta_aval_page_be(rtwdev, DLE_CTRL_TYPE_PLE, + PLE_QTAID_B1_TXPL); + if (ret) { + rtw89_err(rtwdev, "update PLE B1 TX avail page fail %d\n", ret); + return ret; + } + + ret = dle_upd_qta_aval_page_be(rtwdev, DLE_CTRL_TYPE_PLE, + PLE_QTAID_CMAC1_RX); + if (ret) { + rtw89_err(rtwdev, "update PLE CMAC1 RX avail page fail %d\n", ret); + return ret; + } + } + + return 0; +} + static int preload_init_be(struct rtw89_dev *rtwdev, u8 mac_idx, enum rtw89_qta_mode mode) { @@ -1480,6 +1553,13 @@ static int preload_init_be(struct rtw89_dev *rtwdev, u8 mac_idx, static int dbcc_bb_ctrl_be(struct rtw89_dev *rtwdev, bool bb1_en) { + u32 set = B_BE_FEN_BB1PLAT_RSTB | B_BE_FEN_BB1_IP_RSTN; + + if (bb1_en) + rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE, set); + else + rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE, set); + return 0; } @@ -1538,7 +1618,7 @@ static int band1_enable_be(struct rtw89_dev *rtwdev) return ret; } - ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode); + ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true); if (ret) { rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); return ret; @@ -1593,7 +1673,7 @@ static int band1_disable_be(struct rtw89_dev *rtwdev) return ret; } - ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode); + ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, false); if (ret) { rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); return ret; @@ -1616,7 +1696,7 @@ static int dbcc_enable_be(struct rtw89_dev *rtwdev, bool enable) if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) { ret = rtw89_fw_h2c_notify_dbcc(rtwdev, true); if (ret) { - rtw89_err(rtwdev, "%s:[ERR]notfify dbcc1 fail %d\n", + rtw89_err(rtwdev, "%s:[ERR] notify dbcc1 fail %d\n", __func__, ret); return ret; } @@ -1625,7 +1705,7 @@ static int dbcc_enable_be(struct rtw89_dev *rtwdev, bool enable) if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) { ret = rtw89_fw_h2c_notify_dbcc(rtwdev, false); if (ret) { - rtw89_err(rtwdev, "%s:[ERR]notfify dbcc1 fail %d\n", + rtw89_err(rtwdev, "%s:[ERR] notify dbcc1 fail %d\n", __func__, ret); return ret; } @@ -1672,6 +1752,7 @@ static int set_host_rpr_be(struct rtw89_dev *rtwdev) static int trx_init_be(struct rtw89_dev *rtwdev) { + enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; int ret; @@ -1715,6 +1796,233 @@ static int trx_init_be(struct rtw89_dev *rtwdev) return ret; } + if (chip_id == RTL8922A) + rtw89_write32_clr(rtwdev, R_BE_RSP_CHK_SIG, + B_BE_RSP_STATIC_RTS_CHK_SERV_BW_EN); + + return 0; +} + +int rtw89_mac_cfg_gnt_v2(struct rtw89_dev *rtwdev, + const struct rtw89_mac_ax_coex_gnt *gnt_cfg) +{ + u32 val = 0; + + if (gnt_cfg->band[0].gnt_bt) + val |= B_BE_GNT_BT_BB0_VAL | B_BE_GNT_BT_RX_BB0_VAL | + B_BE_GNT_BT_TX_BB0_VAL; + + if (gnt_cfg->band[0].gnt_bt_sw_en) + val |= B_BE_GNT_BT_BB0_SWCTRL | B_BE_GNT_BT_RX_BB0_SWCTRL | + B_BE_GNT_BT_TX_BB0_SWCTRL; + + if (gnt_cfg->band[0].gnt_wl) + val |= B_BE_GNT_WL_BB0_VAL | B_BE_GNT_WL_RX_VAL | + B_BE_GNT_WL_TX_VAL | B_BE_GNT_WL_BB_PWR_VAL; + + if (gnt_cfg->band[0].gnt_wl_sw_en) + val |= B_BE_GNT_WL_BB0_SWCTRL | B_BE_GNT_WL_RX_SWCTRL | + B_BE_GNT_WL_TX_SWCTRL | B_BE_GNT_WL_BB_PWR_SWCTRL; + + if (gnt_cfg->band[1].gnt_bt) + val |= B_BE_GNT_BT_BB1_VAL | B_BE_GNT_BT_RX_BB1_VAL | + B_BE_GNT_BT_TX_BB1_VAL; + + if (gnt_cfg->band[1].gnt_bt_sw_en) + val |= B_BE_GNT_BT_BB1_SWCTRL | B_BE_GNT_BT_RX_BB1_SWCTRL | + B_BE_GNT_BT_TX_BB1_SWCTRL; + + if (gnt_cfg->band[1].gnt_wl) + val |= B_BE_GNT_WL_BB1_VAL | B_BE_GNT_WL_RX_VAL | + B_BE_GNT_WL_TX_VAL | B_BE_GNT_WL_BB_PWR_VAL; + + if (gnt_cfg->band[1].gnt_wl_sw_en) + val |= B_BE_GNT_WL_BB1_SWCTRL | B_BE_GNT_WL_RX_SWCTRL | + B_BE_GNT_WL_TX_SWCTRL | B_BE_GNT_WL_BB_PWR_SWCTRL; + + if (gnt_cfg->bt[0].wlan_act_en) + val |= B_BE_WL_ACT_SWCTRL; + if (gnt_cfg->bt[0].wlan_act) + val |= B_BE_WL_ACT_VAL; + if (gnt_cfg->bt[1].wlan_act_en) + val |= B_BE_WL_ACT2_SWCTRL; + if (gnt_cfg->bt[1].wlan_act) + val |= B_BE_WL_ACT2_VAL; + + rtw89_write32(rtwdev, R_BE_GNT_SW_CTRL, val); + + return 0; +} +EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v2); + +int rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev *rtwdev, bool wl) +{ + struct rtw89_btc *btc = &rtwdev->btc; + struct rtw89_btc_dm *dm = &btc->dm; + struct rtw89_mac_ax_gnt *g = dm->gnt.band; + struct rtw89_mac_ax_wl_act *gbt = dm->gnt.bt; + int i; + + if (wl) + return 0; + + for (i = 0; i < RTW89_PHY_NUM; i++) { + g[i].gnt_bt_sw_en = 1; + g[i].gnt_bt = 1; + g[i].gnt_wl_sw_en = 1; + g[i].gnt_wl = 0; + gbt[i].wlan_act = 1; + gbt[i].wlan_act_en = 0; + } + + return rtw89_mac_cfg_gnt_v2(rtwdev, &dm->gnt); +} +EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v2); + +static +int rtw89_mac_cfg_plt_be(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) +{ + u32 reg; + u16 val; + int ret; + + ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); + if (ret) + return ret; + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BT_PLT, plt->band); + val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_BE_TX_PLT_GNT_LTE_RX : 0) | + (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_BE_TX_PLT_GNT_BT_TX : 0) | + (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_BE_TX_PLT_GNT_BT_RX : 0) | + (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_BE_TX_PLT_GNT_WL : 0) | + (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_BE_RX_PLT_GNT_LTE_RX : 0) | + (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_BE_RX_PLT_GNT_BT_TX : 0) | + (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_BE_RX_PLT_GNT_BT_RX : 0) | + (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_BE_RX_PLT_GNT_WL : 0) | + B_BE_PLT_EN; + rtw89_write16(rtwdev, reg, val); + + return 0; +} + +static u16 rtw89_mac_get_plt_cnt_be(struct rtw89_dev *rtwdev, u8 band) +{ + u32 reg; + u16 cnt; + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BT_PLT, band); + cnt = rtw89_read32_mask(rtwdev, reg, B_BE_BT_PLT_PKT_CNT_MASK); + rtw89_write16_set(rtwdev, reg, B_BE_BT_PLT_RST); + + return cnt; +} + +static int rtw89_set_hw_sch_tx_en_v2(struct rtw89_dev *rtwdev, u8 mac_idx, + u32 tx_en, u32 tx_en_mask) +{ + u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CTN_DRV_TXEN, mac_idx); + u32 val; + int ret; + + ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); + if (ret) + return ret; + + val = rtw89_read32(rtwdev, reg); + val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); + rtw89_write32(rtwdev, reg, val); + + return 0; +} + +int rtw89_mac_stop_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, + u32 *tx_en, enum rtw89_sch_tx_sel sel) +{ + int ret; + + *tx_en = rtw89_read32(rtwdev, + rtw89_mac_reg_by_idx(rtwdev, R_BE_CTN_DRV_TXEN, mac_idx)); + + switch (sel) { + case RTW89_SCH_TX_SEL_ALL: + ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx, 0, + B_BE_CTN_TXEN_ALL_MASK); + if (ret) + return ret; + break; + case RTW89_SCH_TX_SEL_HIQ: + ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx, + 0, B_BE_CTN_TXEN_HGQ); + if (ret) + return ret; + break; + case RTW89_SCH_TX_SEL_MG0: + ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx, + 0, B_BE_CTN_TXEN_MGQ); + if (ret) + return ret; + break; + case RTW89_SCH_TX_SEL_MACID: + ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx, 0, + B_BE_CTN_TXEN_ALL_MASK); + if (ret) + return ret; + break; + default: + return 0; + } + + return 0; +} +EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v2); + +int rtw89_mac_resume_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) +{ + int ret; + + ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx, tx_en, + B_BE_CTN_TXEN_ALL_MASK); + if (ret) + return ret; + + return 0; +} +EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v2); + +void rtw89_mac_cfg_phy_rpt_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) +{ + u32 reg, val; + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RCR, mac_idx); + val = enable ? MAC_AX_PHY_RPT_SIZE_8 : MAC_AX_PHY_RPT_SIZE_0; + rtw89_write32_mask(rtwdev, reg, B_BE_PHY_RPT_SZ_MASK, val); + rtw89_write32_mask(rtwdev, reg, B_BE_HDR_CNV_SZ_MASK, MAC_AX_HDR_CNV_SIZE_0); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_DRV_INFO_OPTION, mac_idx); + rtw89_write32_mask(rtwdev, reg, B_BE_DRV_INFO_PHYRPT_EN, enable); +} +EXPORT_SYMBOL(rtw89_mac_cfg_phy_rpt_be); + +static +int rtw89_mac_cfg_ppdu_status_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) +{ + u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PPDU_STAT, mac_idx); + int ret; + + ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); + if (ret) + return ret; + + if (!enable) { + rtw89_write32_clr(rtwdev, reg, B_BE_PPDU_STAT_RPT_EN); + return 0; + } + + rtw89_write32_mask(rtwdev, R_BE_HW_PPDU_STATUS, B_BE_FWD_PPDU_STAT_MASK, 3); + rtw89_write32(rtwdev, reg, B_BE_PPDU_STAT_RPT_EN | B_BE_PPDU_MAC_INFO | + B_BE_APP_RX_CNT_RPT | B_BE_APP_PLCP_HDR_RPT | + B_BE_PPDU_STAT_RPT_CRC32 | B_BE_PPDU_STAT_RPT_DMA); + return 0; } @@ -1722,8 +2030,7 @@ static bool rtw89_mac_get_txpwr_cr_be(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u32 reg_base, u32 *cr) { - const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; - enum rtw89_qta_mode mode = dle_mem->mode; + enum rtw89_qta_mode mode = rtwdev->mac.qta_mode; int ret; ret = rtw89_mac_check_mac_en(rtwdev, (enum rtw89_mac_idx)phy_idx, @@ -1799,13 +2106,13 @@ static int rtw89_mac_init_bfee_be(struct rtw89_dev *rtwdev, u8 mac_idx) } static int rtw89_mac_set_csi_para_reg_be(struct rtw89_dev *rtwdev, - struct ieee80211_vif *vif, - struct ieee80211_sta *sta) + struct rtw89_vif_link *rtwvif_link, + struct rtw89_sta_link *rtwsta_link) { - struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; - u8 mac_idx = rtwvif->mac_idx; - u8 port_sel = rtwvif->port; + struct ieee80211_link_sta *link_sta; + u8 mac_idx = rtwvif_link->mac_idx; + u8 port_sel = rtwvif_link->port; u8 sound_dim = 3, t; u8 *phy_cap; u32 reg; @@ -1816,7 +2123,10 @@ static int rtw89_mac_set_csi_para_reg_be(struct rtw89_dev *rtwdev, if (ret) return ret; - phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; + rcu_read_lock(); + + link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); + phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info; if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { @@ -1827,11 +2137,11 @@ static int rtw89_mac_set_csi_para_reg_be(struct rtw89_dev *rtwdev, sound_dim = min(sound_dim, t); } - if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || - (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { - ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); - stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); - t = u32_get_bits(sta->deflink.vht_cap.cap, + if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || + (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { + ldpc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); + stbc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); + t = u32_get_bits(link_sta->vht_cap.cap, IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK); sound_dim = min(sound_dim, t); } @@ -1839,6 +2149,8 @@ static int rtw89_mac_set_csi_para_reg_be(struct rtw89_dev *rtwdev, nc = min(nc, sound_dim); nr = min(nr, sound_dim); + rcu_read_unlock(); + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); rtw89_write32_set(rtwdev, reg, B_BE_BFMEE_BFPARAM_SEL); @@ -1863,12 +2175,12 @@ static int rtw89_mac_set_csi_para_reg_be(struct rtw89_dev *rtwdev, } static int rtw89_mac_csi_rrsc_be(struct rtw89_dev *rtwdev, - struct ieee80211_vif *vif, - struct ieee80211_sta *sta) + struct rtw89_vif_link *rtwvif_link, + struct rtw89_sta_link *rtwsta_link) { - struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); - u8 mac_idx = rtwvif->mac_idx; + struct ieee80211_link_sta *link_sta; + u8 mac_idx = rtwvif_link->mac_idx; int ret; u32 reg; @@ -1876,22 +2188,28 @@ static int rtw89_mac_csi_rrsc_be(struct rtw89_dev *rtwdev, if (ret) return ret; - if (sta->deflink.he_cap.has_he) { + rcu_read_lock(); + + link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); + + if (link_sta->he_cap.has_he) { rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); } - if (sta->deflink.vht_cap.vht_supported) { + if (link_sta->vht_cap.vht_supported) { rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); } - if (sta->deflink.ht_cap.ht_supported) { + if (link_sta->ht_cap.ht_supported) { rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); } + rcu_read_unlock(); + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); rtw89_write32_set(rtwdev, reg, B_BE_BFMEE_BFPARAM_SEL); rtw89_write32_clr(rtwdev, reg, B_BE_BFMEE_CSI_FORCE_RETE_EN); @@ -1903,17 +2221,25 @@ static int rtw89_mac_csi_rrsc_be(struct rtw89_dev *rtwdev, } static void rtw89_mac_bf_assoc_be(struct rtw89_dev *rtwdev, - struct ieee80211_vif *vif, - struct ieee80211_sta *sta) + struct rtw89_vif_link *rtwvif_link, + struct rtw89_sta_link *rtwsta_link) { - struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; + struct ieee80211_link_sta *link_sta; + bool has_beamformer_cap; + + rcu_read_lock(); + + link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); + has_beamformer_cap = rtw89_sta_has_beamformer_cap(link_sta); + + rcu_read_unlock(); - if (rtw89_sta_has_beamformer_cap(sta)) { + if (has_beamformer_cap) { rtw89_debug(rtwdev, RTW89_DBG_BF, "initialize bfee for new association\n"); - rtw89_mac_init_bfee_be(rtwdev, rtwvif->mac_idx); - rtw89_mac_set_csi_para_reg_be(rtwdev, vif, sta); - rtw89_mac_csi_rrsc_be(rtwdev, vif, sta); + rtw89_mac_init_bfee_be(rtwdev, rtwvif_link->mac_idx); + rtw89_mac_set_csi_para_reg_be(rtwdev, rtwvif_link, rtwsta_link); + rtw89_mac_csi_rrsc_be(rtwdev, rtwvif_link, rtwsta_link); } } @@ -2020,6 +2346,32 @@ static void rtw89_mac_dump_qta_lost_be(struct rtw89_dev *rtwdev) dump_err_status_dispatcher_be(rtwdev); } +static int rtw89_wow_config_mac_be(struct rtw89_dev *rtwdev, bool enable_wow) +{ + if (enable_wow) { + rtw89_write32_set(rtwdev, R_BE_RX_STOP, B_BE_HOST_RX_STOP); + rtw89_write32_clr(rtwdev, R_BE_RX_FLTR_OPT, B_BE_SNIFFER_MODE); + rtw89_mac_cpu_io_rx(rtwdev, enable_wow); + rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); + rtw89_write32(rtwdev, R_BE_FWD_ERR, 0); + rtw89_write32(rtwdev, R_BE_FWD_ACTN0, 0); + rtw89_write32(rtwdev, R_BE_FWD_ACTN1, 0); + rtw89_write32(rtwdev, R_BE_FWD_ACTN2, 0); + rtw89_write32(rtwdev, R_BE_FWD_TF0, 0); + rtw89_write32(rtwdev, R_BE_FWD_TF1, 0); + rtw89_write32(rtwdev, R_BE_FWD_ERR, 0); + rtw89_write32(rtwdev, R_BE_HW_PPDU_STATUS, 0); + rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY); + } else { + rtw89_mac_cpu_io_rx(rtwdev, enable_wow); + rtw89_write32_clr(rtwdev, R_BE_RX_STOP, B_BE_HOST_RX_STOP); + rtw89_write32_set(rtwdev, R_BE_RX_FLTR_OPT, R_BE_RX_FLTR_OPT); + rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); + } + + return 0; +} + static void rtw89_mac_dump_cmac_err_status_be(struct rtw89_dev *rtwdev, u8 band) { @@ -2218,6 +2570,7 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_be = { .rx_fltr = R_BE_RX_FLTR_OPT, .port_base = &rtw89_port_base_be, .agg_len_ht = R_BE_AGG_LEN_HT_0, + .ps_status = R_BE_WMTX_POWER_BE_BIT_CTL, .muedca_ctrl = { .addr = R_BE_MUEDCA_EN, @@ -2228,6 +2581,13 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_be = { .mask = B_BE_BFMEE_HT_NDPA_EN | B_BE_BFMEE_VHT_NDPA_EN | B_BE_BFMEE_HE_NDPA_EN | B_BE_BFMEE_EHT_NDPA_EN, }, + .narrow_bw_ru_dis = { + .addr = R_BE_RXTRIG_TEST_USER_2, + .mask = B_BE_RXTRIG_RU26_DIS, + }, + .wow_ctrl = {.addr = R_BE_WOW_CTRL, .mask = B_BE_WOW_WOWEN,}, + .agg_limit = {.addr = R_BE_AMPDU_AGG_LIMIT, .mask = B_BE_AMPDU_MAX_TIME_MASK,}, + .txcnt_limit = {.addr = R_BE_TXCNT, .mask = B_BE_L_TXCNT_LMT_MASK,}, .check_mac_en = rtw89_mac_check_mac_en_be, .sys_init = sys_init_be, @@ -2239,6 +2599,8 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_be = { .bf_assoc = rtw89_mac_bf_assoc_be, .typ_fltr_opt = rtw89_mac_typ_fltr_opt_be, + .cfg_ppdu_status = rtw89_mac_cfg_ppdu_status_be, + .cfg_phy_rpt = rtw89_mac_cfg_phy_rpt_be, .dle_mix_cfg = dle_mix_cfg_be, .chk_dle_rdy = chk_dle_rdy_be, @@ -2250,14 +2612,20 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_be = { .wde_quota_cfg = wde_quota_cfg_be, .ple_quota_cfg = ple_quota_cfg_be, .set_cpuio = set_cpuio_be, + .dle_quota_change = dle_quota_change_be, .disable_cpu = rtw89_mac_disable_cpu_be, .fwdl_enable_wcpu = rtw89_mac_fwdl_enable_wcpu_be, .fwdl_get_status = fwdl_get_status_be, .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_be, + .fwdl_secure_idmem_share_mode = NULL, .parse_efuse_map = rtw89_parse_efuse_map_be, .parse_phycap_map = rtw89_parse_phycap_map_be, .cnv_efuse_state = rtw89_cnv_efuse_state_be, + .efuse_read_fw_secure = rtw89_efuse_read_fw_secure_be, + + .cfg_plt = rtw89_mac_cfg_plt_be, + .get_plt_cnt = rtw89_mac_get_plt_cnt_be, .get_txpwr_cr = rtw89_mac_get_txpwr_cr_be, @@ -2268,5 +2636,13 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_be = { .dump_err_status = rtw89_mac_dump_err_status_be, .is_txq_empty = mac_is_txq_empty_be, + + .prep_chan_list = rtw89_hw_scan_prep_chan_list_be, + .free_chan_list = rtw89_hw_scan_free_chan_list_be, + .add_chan_list = rtw89_hw_scan_add_chan_list_be, + .add_chan_list_pno = rtw89_pno_scan_add_chan_list_be, + .scan_offload = rtw89_fw_h2c_scan_offload_be, + + .wow_config_mac = rtw89_wow_config_mac_be, }; EXPORT_SYMBOL(rtw89_mac_gen_be); |