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path: root/drivers/pci/dwc/pcie-designware-ep.c
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Diffstat (limited to 'drivers/pci/dwc/pcie-designware-ep.c')
-rw-r--r--drivers/pci/dwc/pcie-designware-ep.c342
1 files changed, 0 insertions, 342 deletions
diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c
deleted file mode 100644
index 398406393f37..000000000000
--- a/drivers/pci/dwc/pcie-designware-ep.c
+++ /dev/null
@@ -1,342 +0,0 @@
-/**
- * Synopsys Designware PCIe Endpoint controller driver
- *
- * Copyright (C) 2017 Texas Instruments
- * Author: Kishon Vijay Abraham I <kishon@ti.com>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 of
- * the License as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <linux/of.h>
-
-#include "pcie-designware.h"
-#include <linux/pci-epc.h>
-#include <linux/pci-epf.h>
-
-void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
-{
- struct pci_epc *epc = ep->epc;
-
- pci_epc_linkup(epc);
-}
-
-static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
-{
- u32 reg;
-
- reg = PCI_BASE_ADDRESS_0 + (4 * bar);
- dw_pcie_writel_dbi2(pci, reg, 0x0);
- dw_pcie_writel_dbi(pci, reg, 0x0);
-}
-
-static int dw_pcie_ep_write_header(struct pci_epc *epc,
- struct pci_epf_header *hdr)
-{
- struct dw_pcie_ep *ep = epc_get_drvdata(epc);
- struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-
- dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, hdr->vendorid);
- dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, hdr->deviceid);
- dw_pcie_writeb_dbi(pci, PCI_REVISION_ID, hdr->revid);
- dw_pcie_writeb_dbi(pci, PCI_CLASS_PROG, hdr->progif_code);
- dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE,
- hdr->subclass_code | hdr->baseclass_code << 8);
- dw_pcie_writeb_dbi(pci, PCI_CACHE_LINE_SIZE,
- hdr->cache_line_size);
- dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_VENDOR_ID,
- hdr->subsys_vendor_id);
- dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_ID, hdr->subsys_id);
- dw_pcie_writeb_dbi(pci, PCI_INTERRUPT_PIN,
- hdr->interrupt_pin);
-
- return 0;
-}
-
-static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
- dma_addr_t cpu_addr,
- enum dw_pcie_as_type as_type)
-{
- int ret;
- u32 free_win;
- struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-
- free_win = find_first_zero_bit(&ep->ib_window_map,
- sizeof(ep->ib_window_map));
- if (free_win >= ep->num_ib_windows) {
- dev_err(pci->dev, "no free inbound window\n");
- return -EINVAL;
- }
-
- ret = dw_pcie_prog_inbound_atu(pci, free_win, bar, cpu_addr,
- as_type);
- if (ret < 0) {
- dev_err(pci->dev, "Failed to program IB window\n");
- return ret;
- }
-
- ep->bar_to_atu[bar] = free_win;
- set_bit(free_win, &ep->ib_window_map);
-
- return 0;
-}
-
-static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t phys_addr,
- u64 pci_addr, size_t size)
-{
- u32 free_win;
- struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-
- free_win = find_first_zero_bit(&ep->ob_window_map,
- sizeof(ep->ob_window_map));
- if (free_win >= ep->num_ob_windows) {
- dev_err(pci->dev, "no free outbound window\n");
- return -EINVAL;
- }
-
- dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
- phys_addr, pci_addr, size);
-
- set_bit(free_win, &ep->ob_window_map);
- ep->outbound_addr[free_win] = phys_addr;
-
- return 0;
-}
-
-static void dw_pcie_ep_clear_bar(struct pci_epc *epc, enum pci_barno bar)
-{
- struct dw_pcie_ep *ep = epc_get_drvdata(epc);
- struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
- u32 atu_index = ep->bar_to_atu[bar];
-
- dw_pcie_ep_reset_bar(pci, bar);
-
- dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);
- clear_bit(atu_index, &ep->ib_window_map);
-}
-
-static int dw_pcie_ep_set_bar(struct pci_epc *epc, enum pci_barno bar,
- dma_addr_t bar_phys, size_t size, int flags)
-{
- int ret;
- struct dw_pcie_ep *ep = epc_get_drvdata(epc);
- struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
- enum dw_pcie_as_type as_type;
- u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
-
- if (!(flags & PCI_BASE_ADDRESS_SPACE))
- as_type = DW_PCIE_AS_MEM;
- else
- as_type = DW_PCIE_AS_IO;
-
- ret = dw_pcie_ep_inbound_atu(ep, bar, bar_phys, as_type);
- if (ret)
- return ret;
-
- dw_pcie_writel_dbi2(pci, reg, size - 1);
- dw_pcie_writel_dbi(pci, reg, flags);
-
- return 0;
-}
-
-static int dw_pcie_find_index(struct dw_pcie_ep *ep, phys_addr_t addr,
- u32 *atu_index)
-{
- u32 index;
-
- for (index = 0; index < ep->num_ob_windows; index++) {
- if (ep->outbound_addr[index] != addr)
- continue;
- *atu_index = index;
- return 0;
- }
-
- return -EINVAL;
-}
-
-static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, phys_addr_t addr)
-{
- int ret;
- u32 atu_index;
- struct dw_pcie_ep *ep = epc_get_drvdata(epc);
- struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-
- ret = dw_pcie_find_index(ep, addr, &atu_index);
- if (ret < 0)
- return;
-
- dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND);
- clear_bit(atu_index, &ep->ob_window_map);
-}
-
-static int dw_pcie_ep_map_addr(struct pci_epc *epc, phys_addr_t addr,
- u64 pci_addr, size_t size)
-{
- int ret;
- struct dw_pcie_ep *ep = epc_get_drvdata(epc);
- struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-
- ret = dw_pcie_ep_outbound_atu(ep, addr, pci_addr, size);
- if (ret) {
- dev_err(pci->dev, "failed to enable address\n");
- return ret;
- }
-
- return 0;
-}
-
-static int dw_pcie_ep_get_msi(struct pci_epc *epc)
-{
- int val;
- u32 lower_addr;
- u32 upper_addr;
- struct dw_pcie_ep *ep = epc_get_drvdata(epc);
- struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-
- val = dw_pcie_readb_dbi(pci, MSI_MESSAGE_CONTROL);
- val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
-
- lower_addr = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_L32);
- upper_addr = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_U32);
-
- if (!(lower_addr || upper_addr))
- return -EINVAL;
-
- return val;
-}
-
-static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int)
-{
- int val;
- struct dw_pcie_ep *ep = epc_get_drvdata(epc);
- struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-
- val = (encode_int << MSI_CAP_MMC_SHIFT);
- dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);
-
- return 0;
-}
-
-static int dw_pcie_ep_raise_irq(struct pci_epc *epc,
- enum pci_epc_irq_type type, u8 interrupt_num)
-{
- struct dw_pcie_ep *ep = epc_get_drvdata(epc);
-
- if (!ep->ops->raise_irq)
- return -EINVAL;
-
- return ep->ops->raise_irq(ep, type, interrupt_num);
-}
-
-static void dw_pcie_ep_stop(struct pci_epc *epc)
-{
- struct dw_pcie_ep *ep = epc_get_drvdata(epc);
- struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-
- if (!pci->ops->stop_link)
- return;
-
- pci->ops->stop_link(pci);
-}
-
-static int dw_pcie_ep_start(struct pci_epc *epc)
-{
- struct dw_pcie_ep *ep = epc_get_drvdata(epc);
- struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-
- if (!pci->ops->start_link)
- return -EINVAL;
-
- return pci->ops->start_link(pci);
-}
-
-static const struct pci_epc_ops epc_ops = {
- .write_header = dw_pcie_ep_write_header,
- .set_bar = dw_pcie_ep_set_bar,
- .clear_bar = dw_pcie_ep_clear_bar,
- .map_addr = dw_pcie_ep_map_addr,
- .unmap_addr = dw_pcie_ep_unmap_addr,
- .set_msi = dw_pcie_ep_set_msi,
- .get_msi = dw_pcie_ep_get_msi,
- .raise_irq = dw_pcie_ep_raise_irq,
- .start = dw_pcie_ep_start,
- .stop = dw_pcie_ep_stop,
-};
-
-void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
-{
- struct pci_epc *epc = ep->epc;
-
- pci_epc_mem_exit(epc);
-}
-
-int dw_pcie_ep_init(struct dw_pcie_ep *ep)
-{
- int ret;
- void *addr;
- enum pci_barno bar;
- struct pci_epc *epc;
- struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
- struct device *dev = pci->dev;
- struct device_node *np = dev->of_node;
-
- if (!pci->dbi_base || !pci->dbi_base2) {
- dev_err(dev, "dbi_base/deb_base2 is not populated\n");
- return -EINVAL;
- }
-
- ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows);
- if (ret < 0) {
- dev_err(dev, "unable to read *num-ib-windows* property\n");
- return ret;
- }
-
- ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows);
- if (ret < 0) {
- dev_err(dev, "unable to read *num-ob-windows* property\n");
- return ret;
- }
-
- addr = devm_kzalloc(dev, sizeof(phys_addr_t) * ep->num_ob_windows,
- GFP_KERNEL);
- if (!addr)
- return -ENOMEM;
- ep->outbound_addr = addr;
-
- for (bar = BAR_0; bar <= BAR_5; bar++)
- dw_pcie_ep_reset_bar(pci, bar);
-
- if (ep->ops->ep_init)
- ep->ops->ep_init(ep);
-
- epc = devm_pci_epc_create(dev, &epc_ops);
- if (IS_ERR(epc)) {
- dev_err(dev, "failed to create epc device\n");
- return PTR_ERR(epc);
- }
-
- ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
- if (ret < 0)
- epc->max_functions = 1;
-
- ret = pci_epc_mem_init(epc, ep->phys_base, ep->addr_size);
- if (ret < 0) {
- dev_err(dev, "Failed to initialize address space\n");
- return ret;
- }
-
- ep->epc = epc;
- epc_set_drvdata(epc, ep);
- dw_pcie_setup(pci);
-
- return 0;
-}
generated by cgit (git 2.34.1) at 2025-12-25 22:18:11 +0000