diff options
Diffstat (limited to 'drivers/phy/phy-xgene.c')
| -rw-r--r-- | drivers/phy/phy-xgene.c | 28 |
1 files changed, 8 insertions, 20 deletions
diff --git a/drivers/phy/phy-xgene.c b/drivers/phy/phy-xgene.c index ae266e0c8368..5007dc7a357c 100644 --- a/drivers/phy/phy-xgene.c +++ b/drivers/phy/phy-xgene.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * AppliedMicro X-Gene Multi-purpose PHY driver * @@ -6,19 +7,6 @@ * Tuan Phan <tphan@apm.com> * Suman Tripathi <stripathi@apm.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - * * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes. * The first PLL clock macro is used for internal reference clock. The second * PLL clock macro is used to generate the clock for the PHY. This driver @@ -51,6 +39,7 @@ * Currently, this driver only supports Gen3 SATA mode with external clock. */ #include <linux/module.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/io.h> #include <linux/delay.h> @@ -973,7 +962,8 @@ static void xgene_phy_sata_cfg_lanes(struct xgene_phy_ctx *ctx) serdes_wr(ctx, lane, RXTX_REG1, val); /* Latch VTT value based on the termination to ground and - enable TX FIFO */ + * enable TX FIFO + */ serdes_rd(ctx, lane, RXTX_REG2, &val); val = RXTX_REG2_VTT_ENA_SET(val, 0x1); val = RXTX_REG2_VTT_SEL_SET(val, 0x1); @@ -1354,7 +1344,7 @@ static int xgene_phy_hw_initialize(struct xgene_phy_ctx *ctx, static void xgene_phy_force_lat_summer_cal(struct xgene_phy_ctx *ctx, int lane) { int i; - struct { + static const struct { u32 reg; u32 val; } serdes_reg[] = { @@ -1621,13 +1611,13 @@ static const struct phy_ops xgene_phy_ops = { }; static struct phy *xgene_phy_xlate(struct device *dev, - struct of_phandle_args *args) + const struct of_phandle_args *args) { struct xgene_phy_ctx *ctx = dev_get_drvdata(dev); if (args->args_count <= 0) return ERR_PTR(-EINVAL); - if (args->args[0] < MODE_SATA || args->args[0] >= MODE_MAX) + if (args->args[0] >= MODE_MAX) return ERR_PTR(-EINVAL); ctx->mode = args->args[0]; @@ -1656,7 +1646,6 @@ static int xgene_phy_probe(struct platform_device *pdev) { struct phy_provider *phy_provider; struct xgene_phy_ctx *ctx; - struct resource *res; u32 default_spd[] = DEFAULT_SATA_SPD_SEL; u32 default_txboost_gain[] = DEFAULT_SATA_TXBOOST_GAIN; u32 default_txeye_direction[] = DEFAULT_SATA_TXEYEDIRECTION; @@ -1673,8 +1662,7 @@ static int xgene_phy_probe(struct platform_device *pdev) ctx->dev = &pdev->dev; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - ctx->sds_base = devm_ioremap_resource(&pdev->dev, res); + ctx->sds_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(ctx->sds_base)) return PTR_ERR(ctx->sds_base); |