diff options
Diffstat (limited to 'drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h')
| -rw-r--r-- | drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h index 3d9713d348fe..951de964dc12 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h @@ -7,13 +7,20 @@ #define QCOM_PHY_QMP_PCS_PCIE_V5_20_H_ /* Only for QMP V5_20 PHY - PCIe PCS registers */ +#define QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2 0x00c #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084 #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0 #define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST 0x0e0 +#define QPHY_PCIE_V5_20_PCS_G3_RXEQEVAL_TIME 0x0f0 +#define QPHY_PCIE_V5_20_PCS_G4_RXEQEVAL_TIME 0x0f4 +#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184 +#define QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2 0x024 +#define QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2 0x028 + #endif |