diff options
Diffstat (limited to 'drivers/phy/qualcomm/phy-qcom-qmp.h')
| -rw-r--r-- | drivers/phy/qualcomm/phy-qcom-qmp.h | 54 |
1 files changed, 27 insertions, 27 deletions
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 6cb660455088..64af9720b3f9 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -208,33 +208,33 @@ #define QSERDES_RX_RX_INTERFACE_MODE 0x12c /* Only for QMP V2 PHY - PCS registers */ -#define QPHY_POWER_DOWN_CONTROL 0x04 -#define QPHY_TXDEEMPH_M6DB_V0 0x24 -#define QPHY_TXDEEMPH_M3P5DB_V0 0x28 -#define QPHY_TX_LARGE_AMP_DRV_LVL 0x34 -#define QPHY_TX_LARGE_AMP_POST_EMP_LVL 0x38 -#define QPHY_TX_SMALL_AMP_DRV_LVL 0x3c -#define QPHY_TX_SMALL_AMP_POST_EMP_LVL 0x40 -#define QPHY_ENDPOINT_REFCLK_DRIVE 0x54 -#define QPHY_RX_IDLE_DTCT_CNTRL 0x58 -#define QPHY_POWER_STATE_CONFIG1 0x60 -#define QPHY_POWER_STATE_CONFIG2 0x64 -#define QPHY_POWER_STATE_CONFIG4 0x6c -#define QPHY_LOCK_DETECT_CONFIG1 0x80 -#define QPHY_LOCK_DETECT_CONFIG2 0x84 -#define QPHY_LOCK_DETECT_CONFIG3 0x88 -#define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0 -#define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4 -#define QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP 0xcc -#define QPHY_RX_SYM_RESYNC_CTRL 0x13c -#define QPHY_RX_MIN_HIBERN8_TIME 0x140 -#define QPHY_RX_SIGDET_CTRL2 0x148 -#define QPHY_RX_PWM_GEAR_BAND 0x154 -#define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8 -#define QPHY_OSC_DTCT_ACTIONS 0x1ac -#define QPHY_RX_SIGDET_LVL 0x1d8 -#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc -#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 +#define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x04 +#define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x24 +#define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x28 +#define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x34 +#define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x38 +#define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x3c +#define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x40 +#define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x54 +#define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x58 +#define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x60 +#define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x64 +#define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x6c +#define QPHY_V2_PCS_LOCK_DETECT_CONFIG1 0x80 +#define QPHY_V2_PCS_LOCK_DETECT_CONFIG2 0x84 +#define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x88 +#define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0 +#define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4 +#define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0xcc +#define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c +#define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140 +#define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148 +#define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154 +#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8 +#define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac +#define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8 +#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc +#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 /* Only for QMP V3 & V4 PHY - DP COM registers */ #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 |