diff options
Diffstat (limited to 'drivers/pinctrl/intel/pinctrl-intel.h')
| -rw-r--r-- | drivers/pinctrl/intel/pinctrl-intel.h | 137 |
1 files changed, 90 insertions, 47 deletions
diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index cc78c483518f..c1520797f895 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -10,49 +10,45 @@ #ifndef PINCTRL_INTEL_H #define PINCTRL_INTEL_H +#include <linux/array_size.h> +#include <linux/bits.h> +#include <linux/compiler_types.h> #include <linux/gpio/driver.h> #include <linux/irq.h> #include <linux/pm.h> +#include <linux/pinctrl/pinctrl.h> #include <linux/spinlock_types.h> -struct pinctrl_pin_desc; struct platform_device; struct device; /** * struct intel_pingroup - Description about group of pins - * @name: Name of the groups - * @pins: All pins in this group - * @npins: Number of pins in this groups - * @mode: Native mode in which the group is muxed out @pins. Used if @modes - * is %NULL. + * @grp: Generic data of the pin group (name and pins) + * @mode: Native mode in which the group is muxed out @pins. Used if @modes is %NULL. * @modes: If not %NULL this will hold mode for each pin in @pins */ struct intel_pingroup { - const char *name; - const unsigned int *pins; - size_t npins; + struct pingroup grp; unsigned short mode; const unsigned int *modes; }; /** * struct intel_function - Description about a function - * @name: Name of the function - * @groups: An array of groups for this function - * @ngroups: Number of groups in @groups + * @func: Generic data of the pin function (name and groups of pins) */ struct intel_function { - const char *name; - const char * const *groups; - size_t ngroups; + struct pinfunction func; }; +#define INTEL_PINCTRL_MAX_GPP_SIZE 32 + /** * struct intel_padgroup - Hardware pad group information * @reg_num: GPI_IS register number * @base: Starting pin of this group - * @size: Size of this group (maximum is 32). + * @size: Size of this group (maximum is %INTEL_PINCTRL_MAX_GPP_SIZE). * @gpio_base: Starting GPIO base of this group * @padown_num: PAD_OWN register number (assigned by the core driver) * @@ -80,6 +76,15 @@ enum { INTEL_GPIO_BASE_MATCH = 0, }; +/* Initialise struct intel_padgroup */ +#define INTEL_GPP(r, s, e, g) \ + { \ + .reg_num = (r), \ + .base = (s), \ + .size = ((e) - (s) + 1), \ + .gpio_base = (g), \ + } + /** * struct intel_community - Intel pin community description * @barno: MMIO BAR number where registers for this community reside @@ -98,19 +103,22 @@ enum { * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK, * HOSTSW_OWN, GPI_IS, GPI_IE. Used when @gpps is %NULL. * @gpp_num_padown_regs: Number of pad registers each pad group consumes at - * minimum. Use %0 if the number of registers can be - * determined by the size of the group. + * minimum. Used when @gpps is %NULL. * @gpps: Pad groups if the controller has variable size pad groups * @ngpps: Number of pad groups in this community * @pad_map: Optional non-linear mapping of the pads + * @nirqs: Optional total number of IRQs this community can generate + * @acpi_space_id: Optional address space ID for ACPI OpRegion handler * @regs: Community specific common registers (reserved for core driver) * @pad_regs: Community specific pad registers (reserved for core driver) * - * In some of Intel GPIO host controllers this driver supports each pad group + * In older Intel GPIO host controllers, this driver supports, each pad group * is of equal size (except the last one). In that case the driver can just - * fill in @gpp_size field and let the core driver to handle the rest. If - * the controller has pad groups of variable size the client driver can - * pass custom @gpps and @ngpps instead. + * fill in @gpp_size and @gpp_num_padown_regs fields and let the core driver + * to handle the rest. + * + * In newer Intel GPIO host controllers each pad group is of variable size, + * so the client driver can pass custom @gpps and @ngpps instead. */ struct intel_community { unsigned int barno; @@ -127,6 +135,8 @@ struct intel_community { const struct intel_padgroup *gpps; size_t ngpps; const unsigned int *pad_map; + unsigned short nirqs; + unsigned short acpi_space_id; /* Reserved for the core driver */ void __iomem *regs; @@ -136,6 +146,32 @@ struct intel_community { /* Additional features supported by the hardware */ #define PINCTRL_FEATURE_DEBOUNCE BIT(0) #define PINCTRL_FEATURE_1K_PD BIT(1) +#define PINCTRL_FEATURE_GPIO_HW_INFO BIT(2) +#define PINCTRL_FEATURE_PWM BIT(3) +#define PINCTRL_FEATURE_BLINK BIT(4) +#define PINCTRL_FEATURE_EXP BIT(5) + +#define __INTEL_COMMUNITY(b, s, e, g, n, gs, gn, soc) \ + { \ + .barno = (b), \ + .padown_offset = soc ## _PAD_OWN, \ + .padcfglock_offset = soc ## _PADCFGLOCK, \ + .hostown_offset = soc ## _HOSTSW_OWN, \ + .is_offset = soc ## _GPI_IS, \ + .ie_offset = soc ## _GPI_IE, \ + .gpp_size = (gs), \ + .gpp_num_padown_regs = (gn), \ + .pin_base = (s), \ + .npins = ((e) - (s) + 1), \ + .gpps = (g), \ + .ngpps = (n), \ + } + +#define INTEL_COMMUNITY_GPPS(b, s, e, g, soc) \ + __INTEL_COMMUNITY(b, s, e, g, ARRAY_SIZE(g), 0, 0, soc) + +#define INTEL_COMMUNITY_SIZE(b, s, e, gs, gn, soc) \ + __INTEL_COMMUNITY(b, s, e, NULL, 0, gs, gn, soc) /** * PIN_GROUP - Declare a pin group @@ -145,22 +181,20 @@ struct intel_community { * a single integer or an array of integers in which case mode is per * pin. */ -#define PIN_GROUP(n, p, m) \ - { \ - .name = (n), \ - .pins = (p), \ - .npins = ARRAY_SIZE((p)), \ - .mode = __builtin_choose_expr( \ - __builtin_constant_p((m)), (m), 0), \ - .modes = __builtin_choose_expr( \ - __builtin_constant_p((m)), NULL, (m)), \ +#define PIN_GROUP(n, p, m) \ + { \ + .grp = PINCTRL_PINGROUP((n), (p), ARRAY_SIZE((p))), \ + .mode = __builtin_choose_expr(__builtin_constant_p((m)), (m), 0), \ + .modes = __builtin_choose_expr(__builtin_constant_p((m)), NULL, (m)), \ } -#define FUNCTION(n, g) \ - { \ - .name = (n), \ - .groups = (g), \ - .ngroups = ARRAY_SIZE((g)), \ +#define PIN_GROUP_GPIO(n, p, m) \ + PIN_GROUP(n, p, m), \ + PIN_GROUP(n "_gpio", p, 0) + +#define FUNCTION(n, g) \ + { \ + .func = PINCTRL_PINFUNCTION((n), (g), ARRAY_SIZE(g)), \ } /** @@ -190,6 +224,8 @@ struct intel_pinctrl_soc_data { size_t ncommunities; }; +const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev); + struct intel_pad_context; struct intel_community_context; @@ -210,7 +246,6 @@ struct intel_pinctrl_context { * @pctldesc: Pin controller description * @pctldev: Pointer to the pin controller device * @chip: GPIO chip in this pin controller - * @irqchip: IRQ chip in this pin controller * @soc: SoC/PCH specific pin configuration data * @communities: All communities in this pin controller * @ncommunities: Number of communities in this pin controller @@ -223,7 +258,6 @@ struct intel_pinctrl { struct pinctrl_desc pctldesc; struct pinctrl_dev *pctldev; struct gpio_chip chip; - struct irq_chip irqchip; const struct intel_pinctrl_soc_data *soc; struct intel_community *communities; size_t ncommunities; @@ -231,18 +265,27 @@ struct intel_pinctrl { int irq; }; +int intel_pinctrl_probe(struct platform_device *pdev, + const struct intel_pinctrl_soc_data *soc_data); + int intel_pinctrl_probe_by_hid(struct platform_device *pdev); int intel_pinctrl_probe_by_uid(struct platform_device *pdev); -#ifdef CONFIG_PM_SLEEP -int intel_pinctrl_suspend_noirq(struct device *dev); -int intel_pinctrl_resume_noirq(struct device *dev); -#endif +extern const struct dev_pm_ops intel_pinctrl_pm_ops; + +const struct intel_community *intel_get_community(const struct intel_pinctrl *pctrl, + unsigned int pin); + +int intel_gpio_add_pin_ranges(struct gpio_chip *gc); + +int intel_get_groups_count(struct pinctrl_dev *pctldev); +const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group); +int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, + const unsigned int **pins, unsigned int *npins); -#define INTEL_PINCTRL_PM_OPS(_name) \ -const struct dev_pm_ops _name = { \ - SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend_noirq, \ - intel_pinctrl_resume_noirq) \ -} +int intel_get_functions_count(struct pinctrl_dev *pctldev); +const char *intel_get_function_name(struct pinctrl_dev *pctldev, unsigned int function); +int intel_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function, + const char * const **groups, unsigned int * const ngroups); #endif /* PINCTRL_INTEL_H */ |