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path: root/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
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Diffstat (limited to 'drivers/pinctrl/mediatek/pinctrl-mtk-common.h')
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-common.h41
1 files changed, 31 insertions, 10 deletions
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
index 98f27cdc609a..11afa12a96cb 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
@@ -193,6 +193,12 @@ struct mtk_eint_offsets {
*
* @grp_desc: The driving group info.
* @pin_drv_grp: The driving group for all pins.
+ * @spec_ies: Special pin setting for input enable
+ * @n_spec_ies: Number of entries in spec_ies
+ * @spec_pupd: Special pull up/down setting
+ * @n_spec_pupd: Number of entries in spec_pupd
+ * @spec_smt: Special pin setting for schmitt
+ * @n_spec_smt: Number of entries in spec_smt
* @spec_pull_set: Each SoC may have special pins for pull up/down setting,
* these pins' pull setting are very different, they have separate pull
* up/down bit, R0 and R1 resistor bit, so they need special pull setting.
@@ -210,7 +216,10 @@ struct mtk_eint_offsets {
* @spec_dir_set: In very few SoCs, direction control registers are not
* arranged continuously, they may be cut to parts. So they need special
* dir setting.
-
+ * @mt8365_set_clr_mode: In mt8365, some pins won't set correcty because they
+ * need to use the main R/W register to read/update/write the modes instead of
+ * the SET/CLR register.
+ *
* @dir_offset: The direction register offset.
* @pullen_offset: The pull-up/pull-down enable register offset.
* @pinmux_offset: The pinmux register offset.
@@ -231,13 +240,24 @@ struct mtk_pinctrl_devdata {
unsigned int n_grp_cls;
const struct mtk_pin_drv_grp *pin_drv_grp;
unsigned int n_pin_drv_grps;
- int (*spec_pull_set)(struct regmap *reg, unsigned int pin,
- unsigned char align, bool isup, unsigned int arg);
- int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin,
- unsigned char align, int value, enum pin_config_param arg);
+ const struct mtk_pin_ies_smt_set *spec_ies;
+ unsigned int n_spec_ies;
+ const struct mtk_pin_spec_pupd_set_samereg *spec_pupd;
+ unsigned int n_spec_pupd;
+ const struct mtk_pin_ies_smt_set *spec_smt;
+ unsigned int n_spec_smt;
+ int (*spec_pull_set)(struct regmap *regmap,
+ const struct mtk_pinctrl_devdata *devdata,
+ unsigned int pin, bool isup, unsigned int r1r0);
+ int (*spec_ies_smt_set)(struct regmap *reg,
+ const struct mtk_pinctrl_devdata *devdata,
+ unsigned int pin, int value, enum pin_config_param arg);
void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin,
unsigned int mode);
void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin);
+ int (*mt8365_set_clr_mode)(struct regmap *regmap,
+ unsigned int bit, unsigned int reg_pullen, unsigned int reg_pullsel,
+ bool enable, bool isup);
unsigned int dir_offset;
unsigned int ies_offset;
unsigned int smt_offset;
@@ -277,14 +297,15 @@ int mtk_pctrl_init(struct platform_device *pdev,
const struct mtk_pinctrl_devdata *data,
struct regmap *regmap);
+int mtk_pctrl_common_probe(struct platform_device *pdev);
+
int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
- const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
- unsigned int info_num, unsigned int pin,
- unsigned char align, bool isup, unsigned int r1r0);
+ const struct mtk_pinctrl_devdata *devdata,
+ unsigned int pin, bool isup, unsigned int r1r0);
int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
- const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
- unsigned int pin, unsigned char align, int value);
+ const struct mtk_pinctrl_devdata *devdata,
+ unsigned int pin, int value, enum pin_config_param arg);
extern const struct dev_pm_ops mtk_eint_pm_ops;