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path: root/drivers/pinctrl/qcom/pinctrl-msm.h
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Diffstat (limited to 'drivers/pinctrl/qcom/pinctrl-msm.h')
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm.h61
1 files changed, 42 insertions, 19 deletions
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
index dd0d949f7a9e..4625fa5320a9 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.h
+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
@@ -5,25 +5,43 @@
#ifndef __PINCTRL_MSM_H__
#define __PINCTRL_MSM_H__
+#include <linux/pm.h>
+#include <linux/types.h>
+
+#include <linux/pinctrl/pinctrl.h>
+
+struct platform_device;
+
struct pinctrl_pin_desc;
-/**
- * struct msm_function - a pinmux function
- * @name: Name of the pinmux function.
- * @groups: List of pingroups for this function.
- * @ngroups: Number of entries in @groups.
- */
-struct msm_function {
- const char *name;
- const char * const *groups;
- unsigned ngroups;
-};
+#define APQ_PIN_FUNCTION(fname) \
+ [APQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname, \
+ fname##_groups, \
+ ARRAY_SIZE(fname##_groups))
+
+#define IPQ_PIN_FUNCTION(fname) \
+ [IPQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname, \
+ fname##_groups, \
+ ARRAY_SIZE(fname##_groups))
+
+#define MSM_PIN_FUNCTION(fname) \
+ [msm_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \
+ fname##_groups, \
+ ARRAY_SIZE(fname##_groups))
+
+#define MSM_GPIO_PIN_FUNCTION(fname) \
+ [msm_mux_##fname] = PINCTRL_GPIO_PINFUNCTION(#fname, \
+ fname##_groups, \
+ ARRAY_SIZE(fname##_groups))
+
+#define QCA_PIN_FUNCTION(fname) \
+ [qca_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \
+ fname##_groups, \
+ ARRAY_SIZE(fname##_groups))
/**
* struct msm_pingroup - Qualcomm pingroup definition
- * @name: Name of the pingroup.
- * @pins: A list of pins assigned to this pingroup.
- * @npins: Number of entries in @pins.
+ * @grp: Generic data of the pin group (name and pins)
* @funcs: A list of pinmux functions that can be selected for
* this group. The index of the selected function is used
* for programming the function selector.
@@ -45,7 +63,11 @@ struct msm_function {
* @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group.
* @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt
* status.
+ * @intr_wakeup_present_bit: Offset in @intr_target_reg specifying the GPIO can generate
+ * wakeup events.
+ * @intr_wakeup_enable_bit: Offset in @intr_target_reg to enable wakeup events for the GPIO.
* @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing.
+ * @intr_target_width: Number of bits used for specifying interrupt routing target.
* @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from
* this gpio should get routed to the KPSS processor.
* @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit.
@@ -56,9 +78,7 @@ struct msm_function {
* otherwise 1.
*/
struct msm_pingroup {
- const char *name;
- const unsigned *pins;
- unsigned npins;
+ struct pingroup grp;
unsigned *funcs;
unsigned nfuncs;
@@ -75,6 +95,7 @@ struct msm_pingroup {
unsigned pull_bit:5;
unsigned drv_bit:5;
+ unsigned i2c_pull_bit:5;
unsigned od_bit:5;
unsigned egpio_enable:5;
@@ -87,7 +108,10 @@ struct msm_pingroup {
unsigned intr_status_bit:5;
unsigned intr_ack_high:1;
+ unsigned intr_wakeup_present_bit:5;
+ unsigned intr_wakeup_enable_bit:5;
unsigned intr_target_bit:5;
+ unsigned intr_target_width:5;
unsigned intr_target_kpss_val:5;
unsigned intr_raw_status_bit:5;
unsigned intr_polarity_bit:5;
@@ -132,7 +156,7 @@ struct msm_gpio_wakeirq_map {
struct msm_pinctrl_soc_data {
const struct pinctrl_pin_desc *pins;
unsigned npins;
- const struct msm_function *functions;
+ const struct pinfunction *functions;
unsigned nfunctions;
const struct msm_pingroup *groups;
unsigned ngroups;
@@ -152,6 +176,5 @@ extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;
int msm_pinctrl_probe(struct platform_device *pdev,
const struct msm_pinctrl_soc_data *soc_data);
-int msm_pinctrl_remove(struct platform_device *pdev);
#endif