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path: root/drivers/pinctrl/stm32/pinctrl-stm32.c
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Diffstat (limited to 'drivers/pinctrl/stm32/pinctrl-stm32.c')
-rw-r--r--drivers/pinctrl/stm32/pinctrl-stm32.c905
1 files changed, 690 insertions, 215 deletions
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index 9ed764731570..6a99708a5a23 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -6,7 +6,9 @@
*
* Heavily based on Mediatek's pinctrl driver
*/
+#include <linux/bitfield.h>
#include <linux/clk.h>
+#include <linux/export.h>
#include <linux/gpio/driver.h>
#include <linux/hwspinlock.h>
#include <linux/io.h>
@@ -15,24 +17,29 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/of_device.h>
#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/seq_file.h>
+#include <linux/slab.h>
+#include <linux/string_choices.h>
+
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
-#include <linux/platform_device.h>
-#include <linux/regmap.h>
-#include <linux/reset.h>
-#include <linux/slab.h>
#include "../core.h"
#include "../pinconf.h"
#include "../pinctrl-utils.h"
#include "pinctrl-stm32.h"
+#define STM32_GPIO_CID1 1
+
#define STM32_GPIO_MODER 0x00
#define STM32_GPIO_TYPER 0x04
#define STM32_GPIO_SPEEDR 0x08
@@ -43,24 +50,40 @@
#define STM32_GPIO_LCKR 0x1c
#define STM32_GPIO_AFRL 0x20
#define STM32_GPIO_AFRH 0x24
-
-/* custom bitfield to backup pin status */
-#define STM32_GPIO_BKP_MODE_SHIFT 0
-#define STM32_GPIO_BKP_MODE_MASK GENMASK(1, 0)
-#define STM32_GPIO_BKP_ALT_SHIFT 2
-#define STM32_GPIO_BKP_ALT_MASK GENMASK(5, 2)
-#define STM32_GPIO_BKP_SPEED_SHIFT 6
-#define STM32_GPIO_BKP_SPEED_MASK GENMASK(7, 6)
-#define STM32_GPIO_BKP_PUPD_SHIFT 8
-#define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8)
-#define STM32_GPIO_BKP_TYPE 10
-#define STM32_GPIO_BKP_VAL 11
+#define STM32_GPIO_SECCFGR 0x30
+#define STM32_GPIO_DELAYRL 0x40
+#define STM32_GPIO_ADVCFGRL 0x48
+#define STM32_GPIO_CIDCFGR(x) (0x50 + (0x8 * (x)))
+#define STM32_GPIO_SEMCR(x) (0x54 + (0x8 * (x)))
+
+/* Unitary delay for STM32_GPIO_DELAYRL */
+#define STM32_GPIO_DELAYRL_PS 250
+
+#define STM32_GPIO_ADVCFGR_DLYPATH_MASK BIT(0)
+#define STM32_GPIO_ADVCFGR_DE_MASK BIT(1)
+#define STM32_GPIO_ADVCFGR_INVCLK_MASK BIT(2)
+#define STM32_GPIO_ADVCFGR_RET_MASK BIT(3)
+#define STM32_GPIO_ADVCFGR_IO_SYNC_MASK \
+ (STM32_GPIO_ADVCFGR_DE_MASK \
+ | STM32_GPIO_ADVCFGR_INVCLK_MASK \
+ | STM32_GPIO_ADVCFGR_RET_MASK)
+
+#define STM32_GPIO_CIDCFGR_CFEN BIT(0)
+#define STM32_GPIO_CIDCFGR_SEMEN BIT(1)
+#define STM32_GPIO_CIDCFGR_SCID_MASK GENMASK(5, 4)
+#define STM32_GPIO_CIDCFGR_SEMWL_CID1 BIT(16 + STM32_GPIO_CID1)
+
+#define STM32_GPIO_SEMCR_SEM_MUTEX BIT(0)
+#define STM32_GPIO_SEMCR_SEMCID_MASK GENMASK(5, 4)
#define STM32_GPIO_PINS_PER_BANK 16
#define STM32_GPIO_IRQ_LINE 16
#define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
+/* Vendor specific pin configuration */
+#define STM32_GPIO_PIN_CONFIG_IO_SYNC (PIN_CONFIG_END + 1)
+
#define gpio_range_to_bank(chip) \
container_of(chip, struct stm32_gpio_bank, range)
@@ -73,6 +96,33 @@ static const char * const stm32_gpio_functions[] = {
"af8", "af9", "af10",
"af11", "af12", "af13",
"af14", "af15", "analog",
+ "reserved",
+};
+
+static const char * const stm32_gpio_io_sync[] = {
+ "pass-through",
+ "clock inverted",
+ "data on rising edge",
+ "data on falling edge",
+ "data on both edges",
+};
+
+static u8 io_sync_2_advcfgr[] = {
+ /* data or clock GPIO pass-through */
+ [0] = 0,
+ /* clock GPIO inverted */
+ [1] = STM32_GPIO_ADVCFGR_INVCLK_MASK,
+ /* data GPIO re-sampled on clock rising edge */
+ [2] = STM32_GPIO_ADVCFGR_RET_MASK,
+ /* data GPIO re-sampled on clock falling edge */
+ [3] = STM32_GPIO_ADVCFGR_RET_MASK | STM32_GPIO_ADVCFGR_INVCLK_MASK,
+ /* data GPIO re-sampled on both clock edges */
+ [4] = STM32_GPIO_ADVCFGR_RET_MASK | STM32_GPIO_ADVCFGR_DE_MASK,
+};
+
+static const struct pinconf_generic_params stm32_gpio_bindings[] = {
+ {"st,io-sync", STM32_GPIO_PIN_CONFIG_IO_SYNC, 0,
+ stm32_gpio_io_sync, ARRAY_SIZE(stm32_gpio_io_sync)},
};
struct stm32_pinctrl_group {
@@ -81,9 +131,19 @@ struct stm32_pinctrl_group {
unsigned pin;
};
+struct stm32_pin_backup {
+ unsigned int alt:4;
+ unsigned int mode:2;
+ unsigned int bias:2;
+ unsigned int speed:2;
+ unsigned int drive:1;
+ unsigned int value:1;
+ unsigned int advcfg:4;
+ unsigned int skew_delay:4;
+};
+
struct stm32_gpio_bank {
void __iomem *base;
- struct clk *clk;
struct reset_control *rstc;
spinlock_t lock;
struct gpio_chip gpio_chip;
@@ -92,8 +152,11 @@ struct stm32_gpio_bank {
struct irq_domain *domain;
u32 bank_nr;
u32 bank_ioport_nr;
- u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
+ struct stm32_pin_backup pin_backup[STM32_GPIO_PINS_PER_BANK];
u8 irq_type[STM32_GPIO_PINS_PER_BANK];
+ bool secure_control;
+ bool io_sync_control;
+ bool rif_control;
};
struct stm32_pinctrl {
@@ -104,6 +167,7 @@ struct stm32_pinctrl {
unsigned ngroups;
const char **grp_names;
struct stm32_gpio_bank *banks;
+ struct clk_bulk_data *clks;
unsigned nbanks;
const struct stm32_pinctrl_match_data *match_data;
struct irq_domain *domain;
@@ -117,6 +181,8 @@ struct stm32_pinctrl {
spinlock_t irqmux_lock;
};
+static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, u32 *alt);
+
static inline int stm32_gpio_pin(int gpio)
{
return gpio % STM32_GPIO_PINS_PER_BANK;
@@ -153,55 +219,134 @@ static inline u32 stm32_gpio_get_alt(u32 function)
static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,
u32 offset, u32 value)
{
- bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);
- bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;
+ bank->pin_backup[offset].value = value;
}
static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,
u32 mode, u32 alt)
{
- bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |
- STM32_GPIO_BKP_ALT_MASK);
- bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;
- bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;
+ bank->pin_backup[offset].mode = mode;
+ bank->pin_backup[offset].alt = alt;
}
static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,
u32 drive)
{
- bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);
- bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;
+ bank->pin_backup[offset].drive = drive;
}
static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,
u32 speed)
{
- bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;
- bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;
+ bank->pin_backup[offset].speed = speed;
}
static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
u32 bias)
{
- bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;
- bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;
+ bank->pin_backup[offset].bias = bias;
+}
+
+static void stm32_gpio_backup_advcfg(struct stm32_gpio_bank *bank, u32 offset, u32 mask, u32 value)
+{
+ u32 val;
+
+ val = bank->pin_backup[offset].advcfg;
+ val &= ~mask;
+ val |= value & mask;
+ bank->pin_backup[offset].advcfg = val;
+}
+
+static void stm32_gpio_backup_skew_delay(struct stm32_gpio_bank *bank, u32 offset, u32 delay)
+{
+ bank->pin_backup[offset].skew_delay = delay;
+}
+
+/* RIF functions */
+
+static bool stm32_gpio_rif_valid(struct stm32_gpio_bank *bank, unsigned int gpio_nr)
+{
+ u32 cid;
+
+ cid = readl_relaxed(bank->base + STM32_GPIO_CIDCFGR(gpio_nr));
+
+ if (!(cid & STM32_GPIO_CIDCFGR_CFEN))
+ return true;
+
+ if (!(cid & STM32_GPIO_CIDCFGR_SEMEN)) {
+ if (FIELD_GET(STM32_GPIO_CIDCFGR_SCID_MASK, cid) == STM32_GPIO_CID1)
+ return true;
+
+ return false;
+ }
+
+ if (cid & STM32_GPIO_CIDCFGR_SEMWL_CID1)
+ return true;
+
+ return false;
+}
+
+static bool stm32_gpio_rif_acquire_semaphore(struct stm32_gpio_bank *bank, unsigned int gpio_nr)
+{
+ u32 cid, sem;
+
+ cid = readl_relaxed(bank->base + STM32_GPIO_CIDCFGR(gpio_nr));
+
+ if (!(cid & STM32_GPIO_CIDCFGR_CFEN))
+ return true;
+
+ if (!(cid & STM32_GPIO_CIDCFGR_SEMEN)) {
+ if (FIELD_GET(STM32_GPIO_CIDCFGR_SCID_MASK, cid) == STM32_GPIO_CID1)
+ return true;
+
+ return false;
+ }
+
+ if (!(cid & STM32_GPIO_CIDCFGR_SEMWL_CID1))
+ return false;
+
+ sem = readl_relaxed(bank->base + STM32_GPIO_SEMCR(gpio_nr));
+ if (sem & STM32_GPIO_SEMCR_SEM_MUTEX) {
+ if (FIELD_GET(STM32_GPIO_SEMCR_SEMCID_MASK, sem) == STM32_GPIO_CID1)
+ return true;
+
+ return false;
+ }
+
+ writel_relaxed(STM32_GPIO_SEMCR_SEM_MUTEX, bank->base + STM32_GPIO_SEMCR(gpio_nr));
+
+ sem = readl_relaxed(bank->base + STM32_GPIO_SEMCR(gpio_nr));
+ if (sem & STM32_GPIO_SEMCR_SEM_MUTEX &&
+ FIELD_GET(STM32_GPIO_SEMCR_SEMCID_MASK, sem) == STM32_GPIO_CID1)
+ return true;
+
+ return false;
+}
+
+static void stm32_gpio_rif_release_semaphore(struct stm32_gpio_bank *bank, unsigned int gpio_nr)
+{
+ u32 cid;
+
+ cid = readl_relaxed(bank->base + STM32_GPIO_CIDCFGR(gpio_nr));
+
+ if (!(cid & STM32_GPIO_CIDCFGR_CFEN))
+ return;
+
+ if (cid & STM32_GPIO_CIDCFGR_SEMEN)
+ writel_relaxed(0, bank->base + STM32_GPIO_SEMCR(gpio_nr));
}
/* GPIO functions */
static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
- unsigned offset, int value)
+ unsigned int offset, u32 value)
{
stm32_gpio_backup_value(bank, offset, value);
if (!value)
offset += STM32_GPIO_PINS_PER_BANK;
- clk_enable(bank->clk);
-
writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
-
- clk_disable(bank->clk);
}
static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
@@ -217,38 +362,39 @@ static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
return -EINVAL;
}
- return pinctrl_gpio_request(chip->base + offset);
-}
+ if (bank->rif_control && !stm32_gpio_rif_acquire_semaphore(bank, offset)) {
+ dev_err(pctl->dev, "pin %d not available.\n", offset);
+ return -EACCES;
+ }
-static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
-{
- pinctrl_gpio_free(chip->base + offset);
+ return pinctrl_gpio_request(chip, offset);
}
-static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
+static void stm32_gpio_free(struct gpio_chip *chip, unsigned int offset)
{
struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
- int ret;
- clk_enable(bank->clk);
+ pinctrl_gpio_free(chip, offset);
- ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
+ if (bank->rif_control)
+ stm32_gpio_rif_release_semaphore(bank, offset);
+}
- clk_disable(bank->clk);
+static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
- return ret;
+ return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
}
-static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+static int stm32_gpio_set(struct gpio_chip *chip, unsigned int offset,
+ int value)
{
struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
__stm32_gpio_set(bank, offset, value);
-}
-static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
- return pinctrl_gpio_direction_input(chip->base + offset);
+ return 0;
}
static int stm32_gpio_direction_output(struct gpio_chip *chip,
@@ -257,9 +403,8 @@ static int stm32_gpio_direction_output(struct gpio_chip *chip,
struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
__stm32_gpio_set(bank, offset, value);
- pinctrl_gpio_direction_output(chip->base + offset);
- return 0;
+ return pinctrl_gpio_direction_output(chip, offset);
}
@@ -294,16 +439,57 @@ static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
return ret;
}
+static int stm32_gpio_init_valid_mask(struct gpio_chip *chip,
+ unsigned long *valid_mask,
+ unsigned int ngpios)
+{
+ struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
+ unsigned int i;
+ u32 sec;
+
+ /* All gpio are valid per default */
+ bitmap_fill(valid_mask, ngpios);
+
+ if (bank->secure_control) {
+ /* Tag secured pins as invalid */
+ sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR);
+
+ for (i = 0; i < ngpios; i++) {
+ if (sec & BIT(i)) {
+ clear_bit(i, valid_mask);
+ dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i);
+ }
+ }
+ }
+
+ if (bank->rif_control) {
+ for (i = 0; i < ngpios; i++) {
+ if (!test_bit(i, valid_mask))
+ continue;
+
+ if (stm32_gpio_rif_valid(bank, i))
+ continue;
+
+ dev_dbg(pctl->dev, "RIF semaphore ownership conflict, GPIO %u", i);
+ clear_bit(i, valid_mask);
+ }
+ }
+
+ return 0;
+}
+
static const struct gpio_chip stm32_gpio_template = {
.request = stm32_gpio_request,
.free = stm32_gpio_free,
.get = stm32_gpio_get,
.set = stm32_gpio_set,
- .direction_input = stm32_gpio_direction_input,
+ .direction_input = pinctrl_gpio_direction_input,
.direction_output = stm32_gpio_direction_output,
.to_irq = stm32_gpio_to_irq,
.get_direction = stm32_gpio_get_direction,
.set_config = gpiochip_generic_config,
+ .init_valid_mask = stm32_gpio_init_valid_mask,
};
static void stm32_gpio_irq_trigger(struct irq_data *d)
@@ -311,6 +497,10 @@ static void stm32_gpio_irq_trigger(struct irq_data *d)
struct stm32_gpio_bank *bank = d->domain->host_data;
int level;
+ /* Do not access the GPIO if this is not LEVEL triggered IRQ. */
+ if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK))
+ return;
+
/* If level interrupt type then retrig */
level = stm32_gpio_get(&bank->gpio_chip, d->hwirq);
if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
@@ -356,7 +546,7 @@ static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
int ret;
- ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
+ ret = pinctrl_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
if (ret)
return ret;
@@ -393,6 +583,7 @@ static struct irq_chip stm32_gpio_irq_chip = {
.irq_set_wake = irq_chip_set_wake_parent,
.irq_request_resources = stm32_gpio_irq_request_resources,
.irq_release_resources = stm32_gpio_irq_release_resources,
+ .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL,
};
static int stm32_gpio_domain_translate(struct irq_domain *d,
@@ -514,7 +705,7 @@ stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
u32 pin_num, u32 fnum)
{
- int i;
+ int i, k;
for (i = 0; i < pctl->npins; i++) {
const struct stm32_desc_pin *pin = pctl->pins + i;
@@ -523,7 +714,10 @@ static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
if (pin->pin.number != pin_num)
continue;
- while (func && func->name) {
+ if (fnum == STM32_PIN_RSVD)
+ return true;
+
+ for (k = 0; k < STM32_CONFIG_NUM; k++) {
if (func->num == fnum)
return true;
func++;
@@ -656,7 +850,6 @@ static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np_config,
struct pinctrl_map **map, unsigned *num_maps)
{
- struct device_node *np;
unsigned reserved_maps;
int ret;
@@ -664,12 +857,11 @@ static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
*num_maps = 0;
reserved_maps = 0;
- for_each_child_of_node(np_config, np) {
+ for_each_child_of_node_scoped(np_config, np) {
ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
&reserved_maps, num_maps);
if (ret < 0) {
pinctrl_utils_free_map(pctldev, *map, *num_maps);
- of_node_put(np);
return ret;
}
}
@@ -750,7 +942,6 @@ static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
unsigned long flags;
int err = 0;
- clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
if (pctl->hwlock) {
@@ -779,21 +970,15 @@ static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
unlock:
spin_unlock_irqrestore(&bank->lock, flags);
- clk_disable(bank->clk);
return err;
}
-void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
- u32 *alt)
+static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, u32 *alt)
{
u32 val;
int alt_shift = (pin % 8) * 4;
int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
- unsigned long flags;
-
- clk_enable(bank->clk);
- spin_lock_irqsave(&bank->lock, flags);
val = readl_relaxed(bank->base + alt_offset);
val &= GENMASK(alt_shift + 3, alt_shift);
@@ -802,9 +987,6 @@ void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
val = readl_relaxed(bank->base + STM32_GPIO_MODER);
val &= GENMASK(pin * 2 + 1, pin * 2);
*mode = val >> (pin * 2);
-
- spin_unlock_irqrestore(&bank->lock, flags);
- clk_disable(bank->clk);
}
static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
@@ -829,6 +1011,11 @@ static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
return -EINVAL;
}
+ if (function == STM32_PIN_RSVD) {
+ dev_dbg(pctl->dev, "Reserved pins, skipping HW update.\n");
+ return 0;
+ }
+
bank = gpiochip_get_data(range->gc);
pin = stm32_gpio_pin(g->pin);
@@ -848,12 +1035,43 @@ static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
return stm32_pmx_set_mode(bank, pin, !input, 0);
}
+static int stm32_pmx_request(struct pinctrl_dev *pctldev, unsigned int gpio)
+{
+ struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ unsigned int offset = stm32_gpio_pin(gpio);
+ struct pinctrl_gpio_range *range;
+ struct stm32_gpio_bank *bank;
+
+ range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, gpio);
+ if (!range) {
+ dev_err(pctl->dev, "No gpio range defined.\n");
+ return -EINVAL;
+ }
+
+ if (!gpiochip_line_is_valid(range->gc, offset)) {
+ dev_warn(pctl->dev, "Can't access gpio %d\n", gpio);
+ return -EACCES;
+ }
+
+ bank = gpiochip_get_data(range->gc);
+ if (!bank)
+ return -ENODEV;
+
+ if (bank->rif_control && !stm32_gpio_rif_acquire_semaphore(bank, offset)) {
+ dev_err(pctl->dev, "pin %d not available.\n", offset);
+ return -EACCES;
+ }
+
+ return 0;
+}
+
static const struct pinmux_ops stm32_pmx_ops = {
.get_functions_count = stm32_pmx_get_funcs_cnt,
.get_function_name = stm32_pmx_get_func_name,
.get_function_groups = stm32_pmx_get_func_groups,
.set_mux = stm32_pmx_set_mux,
.gpio_set_direction = stm32_pmx_gpio_set_direction,
+ .request = stm32_pmx_request,
.strict = true,
};
@@ -867,7 +1085,6 @@ static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
u32 val;
int err = 0;
- clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
if (pctl->hwlock) {
@@ -891,7 +1108,6 @@ static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
unlock:
spin_unlock_irqrestore(&bank->lock, flags);
- clk_disable(bank->clk);
return err;
}
@@ -899,18 +1115,11 @@ unlock:
static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
unsigned int offset)
{
- unsigned long flags;
u32 val;
- clk_enable(bank->clk);
- spin_lock_irqsave(&bank->lock, flags);
-
val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
val &= BIT(offset);
- spin_unlock_irqrestore(&bank->lock, flags);
- clk_disable(bank->clk);
-
return (val >> offset);
}
@@ -922,7 +1131,6 @@ static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
u32 val;
int err = 0;
- clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
if (pctl->hwlock) {
@@ -946,7 +1154,6 @@ static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
unlock:
spin_unlock_irqrestore(&bank->lock, flags);
- clk_disable(bank->clk);
return err;
}
@@ -954,18 +1161,11 @@ unlock:
static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
unsigned int offset)
{
- unsigned long flags;
u32 val;
- clk_enable(bank->clk);
- spin_lock_irqsave(&bank->lock, flags);
-
val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
val &= GENMASK(offset * 2 + 1, offset * 2);
- spin_unlock_irqrestore(&bank->lock, flags);
- clk_disable(bank->clk);
-
return (val >> (offset * 2));
}
@@ -977,7 +1177,6 @@ static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
u32 val;
int err = 0;
- clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
if (pctl->hwlock) {
@@ -1001,7 +1200,6 @@ static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
unlock:
spin_unlock_irqrestore(&bank->lock, flags);
- clk_disable(bank->clk);
return err;
}
@@ -1009,30 +1207,168 @@ unlock:
static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
unsigned int offset)
{
- unsigned long flags;
u32 val;
- clk_enable(bank->clk);
- spin_lock_irqsave(&bank->lock, flags);
-
val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
val &= GENMASK(offset * 2 + 1, offset * 2);
+ return (val >> (offset * 2));
+}
+
+static void
+stm32_pconf_set_advcfgr_nolock(struct stm32_gpio_bank *bank, int offset, u32 mask, u32 value)
+{
+ int advcfgr_offset = STM32_GPIO_ADVCFGRL + (offset / 8) * 4;
+ int advcfgr_shift = (offset % 8) * 4;
+ u32 val;
+
+ val = readl_relaxed(bank->base + advcfgr_offset);
+ val &= ~(mask << advcfgr_shift);
+ val |= (value & mask) << advcfgr_shift;
+ writel_relaxed(val, bank->base + advcfgr_offset);
+
+ stm32_gpio_backup_advcfg(bank, offset, mask, value);
+}
+
+static int stm32_pconf_set_advcfgr(struct stm32_gpio_bank *bank, int offset, u32 mask, u32 value)
+{
+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
+ unsigned long flags;
+ int err = 0;
+
+ if (!bank->io_sync_control)
+ return -ENOTSUPP;
+
+ spin_lock_irqsave(&bank->lock, flags);
+
+ if (pctl->hwlock) {
+ err = hwspin_lock_timeout_in_atomic(pctl->hwlock, HWSPNLCK_TIMEOUT);
+ if (err) {
+ dev_err(pctl->dev, "Can't get hwspinlock\n");
+ goto unlock;
+ }
+ }
+
+ stm32_pconf_set_advcfgr_nolock(bank, offset, mask, value);
+
+ if (pctl->hwlock)
+ hwspin_unlock_in_atomic(pctl->hwlock);
+
+unlock:
spin_unlock_irqrestore(&bank->lock, flags);
- clk_disable(bank->clk);
- return (val >> (offset * 2));
+ return err;
}
-static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
- unsigned int offset, bool dir)
+static u32 stm32_pconf_get_advcfgr(struct stm32_gpio_bank *bank, int offset, u32 mask)
+{
+ int advcfgr_offset = STM32_GPIO_ADVCFGRL + (offset / 8) * 4;
+ int advcfgr_shift = (offset % 8) * 4;
+ u32 val;
+
+ if (!bank->io_sync_control)
+ return 0;
+
+ val = readl_relaxed(bank->base + advcfgr_offset);
+ val >>= advcfgr_shift;
+
+ return val & mask;
+}
+
+static int stm32_pconf_set_io_sync(struct stm32_gpio_bank *bank, int offset, u32 io_sync)
{
+ if (io_sync >= ARRAY_SIZE(io_sync_2_advcfgr))
+ return -EINVAL;
+
+ return stm32_pconf_set_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_IO_SYNC_MASK,
+ io_sync_2_advcfgr[io_sync]);
+}
+
+static const char *stm32_pconf_get_io_sync_str(struct stm32_gpio_bank *bank, int offset)
+{
+ u32 io_sync = stm32_pconf_get_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_IO_SYNC_MASK);
+
+ if (io_sync & STM32_GPIO_ADVCFGR_RET_MASK) {
+ if (io_sync & STM32_GPIO_ADVCFGR_DE_MASK)
+ return "data GPIO re-sampled on both clock edges";
+
+ if (io_sync & STM32_GPIO_ADVCFGR_INVCLK_MASK)
+ return "data GPIO re-sampled on clock falling edge";
+
+ return "data GPIO re-sampled on clock rising edge";
+ }
+
+ if (io_sync & STM32_GPIO_ADVCFGR_INVCLK_MASK)
+ return "clock GPIO inverted";
+
+ return NULL;
+}
+
+static int
+stm32_pconf_set_skew_delay(struct stm32_gpio_bank *bank, int offset, u32 delay, bool is_dir_input)
+{
+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
+ int delay_offset = STM32_GPIO_DELAYRL + (offset / 8) * 4;
+ int delay_shift = (offset % 8) * 4;
unsigned long flags;
+ int err = 0;
u32 val;
- clk_enable(bank->clk);
+ if (!bank->io_sync_control)
+ return -ENOTSUPP;
+
spin_lock_irqsave(&bank->lock, flags);
+ if (pctl->hwlock) {
+ err = hwspin_lock_timeout_in_atomic(pctl->hwlock, HWSPNLCK_TIMEOUT);
+ if (err) {
+ dev_err(pctl->dev, "Can't get hwspinlock\n");
+ goto unlock;
+ }
+ }
+
+ val = readl_relaxed(bank->base + delay_offset);
+ val &= ~GENMASK(delay_shift + 3, delay_shift);
+ val |= (delay << delay_shift);
+ writel_relaxed(val, bank->base + delay_offset);
+
+ stm32_gpio_backup_skew_delay(bank, offset, delay);
+
+ stm32_pconf_set_advcfgr_nolock(bank, offset, STM32_GPIO_ADVCFGR_DLYPATH_MASK,
+ is_dir_input ? STM32_GPIO_ADVCFGR_DLYPATH_MASK : 0);
+
+ if (pctl->hwlock)
+ hwspin_unlock_in_atomic(pctl->hwlock);
+
+unlock:
+ spin_unlock_irqrestore(&bank->lock, flags);
+
+ return err;
+}
+
+static u32 stm32_pconf_get_skew_delay_val(struct stm32_gpio_bank *bank, int offset)
+{
+ int delay_offset = STM32_GPIO_DELAYRL + (offset / 8) * 4;
+ int delay_shift = (offset % 8) * 4;
+ u32 val;
+
+ val = readl_relaxed(bank->base + delay_offset);
+ val &= GENMASK(delay_shift + 3, delay_shift);
+
+ return val >> delay_shift;
+}
+
+static const char *stm32_pconf_get_skew_dir_str(struct stm32_gpio_bank *bank, int offset)
+{
+ return stm32_pconf_get_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_DLYPATH_MASK) ?
+ "input" : "output";
+}
+
+static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
+ unsigned int offset, bool dir)
+{
+ bool val;
+
if (dir)
val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
BIT(offset));
@@ -1040,17 +1376,15 @@ static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
BIT(offset));
- spin_unlock_irqrestore(&bank->lock, flags);
- clk_disable(bank->clk);
-
return val;
}
static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
- unsigned int pin, enum pin_config_param param,
- enum pin_config_param arg)
+ unsigned int pin, unsigned long config)
{
struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ unsigned int param = pinconf_to_config_param(config);
+ u32 arg = pinconf_to_config_argument(config);
struct pinctrl_gpio_range *range;
struct stm32_gpio_bank *bank;
int offset, ret = 0;
@@ -1064,6 +1398,16 @@ static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
bank = gpiochip_get_data(range->gc);
offset = stm32_gpio_pin(pin);
+ if (!gpiochip_line_is_valid(range->gc, offset)) {
+ dev_warn(pctl->dev, "Can't access gpio %d\n", pin);
+ return -EACCES;
+ }
+
+ if (bank->rif_control && !stm32_gpio_rif_acquire_semaphore(bank, offset)) {
+ dev_err(pctl->dev, "pin %d not available.\n", offset);
+ return -EACCES;
+ }
+
switch (param) {
case PIN_CONFIG_DRIVE_PUSH_PULL:
ret = stm32_pconf_set_driving(bank, offset, 0);
@@ -1083,10 +1427,21 @@ static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
case PIN_CONFIG_BIAS_PULL_DOWN:
ret = stm32_pconf_set_bias(bank, offset, 2);
break;
- case PIN_CONFIG_OUTPUT:
+ case PIN_CONFIG_LEVEL:
__stm32_gpio_set(bank, offset, arg);
ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
break;
+ case PIN_CONFIG_SKEW_DELAY_INPUT_PS:
+ arg /= STM32_GPIO_DELAYRL_PS;
+ ret = stm32_pconf_set_skew_delay(bank, offset, arg, true);
+ break;
+ case PIN_CONFIG_SKEW_DELAY_OUTPUT_PS:
+ arg /= STM32_GPIO_DELAYRL_PS;
+ ret = stm32_pconf_set_skew_delay(bank, offset, arg, false);
+ break;
+ case STM32_GPIO_PIN_CONFIG_IO_SYNC:
+ ret = stm32_pconf_set_io_sync(bank, offset, arg);
+ break;
default:
ret = -ENOTSUPP;
}
@@ -1114,9 +1469,7 @@ static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
for (i = 0; i < num_configs; i++) {
mutex_lock(&pctldev->mutex);
- ret = stm32_pconf_parse_conf(pctldev, g->pin,
- pinconf_to_config_param(configs[i]),
- pinconf_to_config_argument(configs[i]));
+ ret = stm32_pconf_parse_conf(pctldev, g->pin, configs[i]);
mutex_unlock(&pctldev->mutex);
if (ret < 0)
return ret;
@@ -1133,9 +1486,7 @@ static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
int i, ret;
for (i = 0; i < num_configs; i++) {
- ret = stm32_pconf_parse_conf(pctldev, pin,
- pinconf_to_config_param(configs[i]),
- pinconf_to_config_argument(configs[i]));
+ ret = stm32_pconf_parse_conf(pctldev, pin, configs[i]);
if (ret < 0)
return ret;
}
@@ -1143,10 +1494,27 @@ static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
return 0;
}
+static struct stm32_desc_pin *
+stm32_pconf_get_pin_desc_by_pin_number(struct stm32_pinctrl *pctl,
+ unsigned int pin_number)
+{
+ struct stm32_desc_pin *pins = pctl->pins;
+ int i;
+
+ for (i = 0; i < pctl->npins; i++) {
+ if (pins->pin.number == pin_number)
+ return pins;
+ pins++;
+ }
+ return NULL;
+}
+
static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s,
unsigned int pin)
{
+ struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct stm32_desc_pin *pin_desc;
struct pinctrl_gpio_range *range;
struct stm32_gpio_bank *bank;
int offset;
@@ -1166,6 +1534,11 @@ static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
bank = gpiochip_get_data(range->gc);
offset = stm32_gpio_pin(pin);
+ if (!gpiochip_line_is_valid(range->gc, offset)) {
+ seq_puts(s, "NO ACCESS");
+ return;
+ }
+
stm32_pmx_get_mode(bank, offset, &mode, &alt);
bias = stm32_pconf_get_bias(bank, offset);
@@ -1176,7 +1549,7 @@ static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
case 0:
val = stm32_pconf_get(bank, offset, true);
seq_printf(s, "- %s - %s",
- val ? "high" : "low",
+ str_high_low(val),
biasing[bias]);
break;
@@ -1186,7 +1559,7 @@ static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
speed = stm32_pconf_get_speed(bank, offset);
val = stm32_pconf_get(bank, offset, false);
seq_printf(s, "- %s - %s - %s - %s %s",
- val ? "high" : "low",
+ str_high_low(val),
drive ? "open drain" : "push pull",
biasing[bias],
speeds[speed], "speed");
@@ -1196,7 +1569,12 @@ static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
case 2:
drive = stm32_pconf_get_driving(bank, offset);
speed = stm32_pconf_get_speed(bank, offset);
- seq_printf(s, "%d - %s - %s - %s %s", alt,
+ pin_desc = stm32_pconf_get_pin_desc_by_pin_number(pctl, pin);
+ if (!pin_desc)
+ return;
+
+ seq_printf(s, "%d (%s) - %s - %s - %s %s", alt,
+ pin_desc->functions[alt + 1].name,
drive ? "open drain" : "push pull",
biasing[bias],
speeds[speed], "speed");
@@ -1206,6 +1584,22 @@ static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
case 3:
break;
}
+
+ if (bank->io_sync_control) {
+ const char *io_sync_str, *skew_dir_str;
+ u32 skew_delay;
+
+ io_sync_str = stm32_pconf_get_io_sync_str(bank, offset);
+ skew_dir_str = stm32_pconf_get_skew_dir_str(bank, offset);
+ skew_delay = stm32_pconf_get_skew_delay_val(bank, offset);
+
+ if (io_sync_str)
+ seq_printf(s, " - IO-sync: %s", io_sync_str);
+
+ if (skew_delay)
+ seq_printf(s, " - Skew-delay: %u (%u ps) %s", skew_delay,
+ skew_delay * STM32_GPIO_DELAYRL_PS, skew_dir_str);
+ }
}
static const struct pinconf_ops stm32_pconf_ops = {
@@ -1215,45 +1609,64 @@ static const struct pinconf_ops stm32_pconf_ops = {
.pin_config_dbg_show = stm32_pconf_dbg_show,
};
-static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
- struct device_node *np)
+static struct stm32_desc_pin *stm32_pctrl_get_desc_pin_from_gpio(struct stm32_pinctrl *pctl,
+ struct stm32_gpio_bank *bank,
+ unsigned int offset)
+{
+ unsigned int stm32_pin_nb = bank->bank_nr * STM32_GPIO_PINS_PER_BANK + offset;
+ struct stm32_desc_pin *pin_desc;
+ int i;
+
+ /* With few exceptions (e.g. bank 'Z'), pin number matches with pin index in array */
+ if (stm32_pin_nb < pctl->npins) {
+ pin_desc = pctl->pins + stm32_pin_nb;
+ if (pin_desc->pin.number == stm32_pin_nb)
+ return pin_desc;
+ }
+
+ /* Otherwise, loop all array to find the pin with the right number */
+ for (i = 0; i < pctl->npins; i++) {
+ pin_desc = pctl->pins + i;
+ if (pin_desc->pin.number == stm32_pin_nb)
+ return pin_desc;
+ }
+ return NULL;
+}
+
+static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode_handle *fwnode)
{
struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
int bank_ioport_nr;
struct pinctrl_gpio_range *range = &bank->range;
- struct of_phandle_args args;
+ struct fwnode_reference_args args;
struct device *dev = pctl->dev;
struct resource res;
int npins = STM32_GPIO_PINS_PER_BANK;
int bank_nr, err, i = 0;
+ struct stm32_desc_pin *stm32_pin;
+ char **names;
if (!IS_ERR(bank->rstc))
reset_control_deassert(bank->rstc);
- if (of_address_to_resource(np, 0, &res))
+ if (of_address_to_resource(to_of_node(fwnode), 0, &res))
return -ENODEV;
bank->base = devm_ioremap_resource(dev, &res);
if (IS_ERR(bank->base))
return PTR_ERR(bank->base);
- err = clk_prepare(bank->clk);
- if (err) {
- dev_err(dev, "failed to prepare clk (%d)\n", err);
- return err;
- }
-
bank->gpio_chip = stm32_gpio_template;
- of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label);
+ fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label);
- if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, i, &args)) {
+ if (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, i, &args)) {
bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
bank->gpio_chip.base = args.args[1];
/* get the last defined gpio line (offset + nb of pins) */
npins = args.args[0] + args.args[2];
- while (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, ++i, &args))
+ while (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, ++i, &args))
npins = max(npins, (int)(args.args[0] + args.args[2]));
} else {
bank_nr = pctl->nbanks;
@@ -1268,27 +1681,49 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
&pctl->banks[bank_nr].range);
}
- if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr))
+ if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr))
bank_ioport_nr = bank_nr;
- bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
+ bank->gpio_chip.base = -1;
bank->gpio_chip.ngpio = npins;
- bank->gpio_chip.of_node = np;
+ bank->gpio_chip.fwnode = fwnode;
bank->gpio_chip.parent = dev;
bank->bank_nr = bank_nr;
bank->bank_ioport_nr = bank_ioport_nr;
+ bank->secure_control = pctl->match_data->secure_control;
+ bank->io_sync_control = pctl->match_data->io_sync_control;
+ bank->rif_control = pctl->match_data->rif_control;
spin_lock_init(&bank->lock);
- /* create irq hierarchical domain */
- bank->fwnode = of_node_to_fwnode(np);
+ if (pctl->domain) {
+ /* create irq hierarchical domain */
+ bank->fwnode = fwnode;
- bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,
- STM32_GPIO_IRQ_LINE, bank->fwnode,
- &stm32_gpio_domain_ops, bank);
+ bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE,
+ bank->fwnode, &stm32_gpio_domain_ops,
+ bank);
- if (!bank->domain)
- return -ENODEV;
+ if (!bank->domain)
+ return -ENODEV;
+ }
+
+ names = devm_kcalloc(dev, npins, sizeof(char *), GFP_KERNEL);
+ if (!names)
+ return -ENOMEM;
+
+ for (i = 0; i < npins; i++) {
+ stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i);
+ if (stm32_pin && stm32_pin->pin.name) {
+ names[i] = devm_kasprintf(dev, GFP_KERNEL, "%s", stm32_pin->pin.name);
+ if (!names[i])
+ return -ENOMEM;
+ } else {
+ names[i] = NULL;
+ }
+ }
+
+ bank->gpio_chip.names = (const char * const *)names;
err = gpiochip_add_data(&bank->gpio_chip, bank);
if (err) {
@@ -1300,12 +1735,13 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
return 0;
}
-static struct irq_domain *stm32_pctrl_get_irq_domain(struct device_node *np)
+static struct irq_domain *stm32_pctrl_get_irq_domain(struct platform_device *pdev)
{
+ struct device_node *np = pdev->dev.of_node;
struct device_node *parent;
struct irq_domain *domain;
- if (!of_find_property(np, "interrupt-parent", NULL))
+ if (!of_property_present(np, "interrupt-parent"))
return NULL;
parent = of_irq_find_parent(np);
@@ -1313,6 +1749,7 @@ static struct irq_domain *stm32_pctrl_get_irq_domain(struct device_node *np)
return ERR_PTR(-ENXIO);
domain = irq_find_host(parent);
+ of_node_put(parent);
if (!domain)
/* domain not registered yet */
return ERR_PTR(-EPROBE_DEFER);
@@ -1405,7 +1842,8 @@ static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
if (pctl->pkg && !(pctl->pkg & p->pkg))
continue;
pins->pin = p->pin;
- pins->functions = p->functions;
+ memcpy((struct stm32_desc_pin *)pins->functions, p->functions,
+ STM32_CONFIG_NUM * sizeof(struct stm32_desc_function));
pins++;
nb_pins_available++;
}
@@ -1417,26 +1855,18 @@ static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
int stm32_pctl_probe(struct platform_device *pdev)
{
- struct device_node *np = pdev->dev.of_node;
- struct device_node *child;
- const struct of_device_id *match;
+ const struct stm32_pinctrl_match_data *match_data;
+ struct fwnode_handle *child;
struct device *dev = &pdev->dev;
struct stm32_pinctrl *pctl;
struct pinctrl_pin_desc *pins;
- int i, ret, hwlock_id, banks = 0;
+ int i, ret, hwlock_id;
+ unsigned int banks;
- if (!np)
+ match_data = device_get_match_data(dev);
+ if (!match_data)
return -EINVAL;
- match = of_match_device(dev->driver->of_match_table, dev);
- if (!match || !match->data)
- return -EINVAL;
-
- if (!of_find_property(np, "pins-are-numbered", NULL)) {
- dev_err(dev, "only support pins-are-numbered format\n");
- return -EINVAL;
- }
-
pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
if (!pctl)
return -ENOMEM;
@@ -1444,9 +1874,11 @@ int stm32_pctl_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, pctl);
/* check for IRQ controller (may require deferred probe) */
- pctl->domain = stm32_pctrl_get_irq_domain(np);
+ pctl->domain = stm32_pctrl_get_irq_domain(pdev);
if (IS_ERR(pctl->domain))
return PTR_ERR(pctl->domain);
+ if (!pctl->domain)
+ dev_warn(dev, "pinctrl without interrupt support\n");
/* hwspinlock is optional */
hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
@@ -1454,16 +1886,16 @@ int stm32_pctl_probe(struct platform_device *pdev)
if (hwlock_id == -EPROBE_DEFER)
return hwlock_id;
} else {
- pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
+ pctl->hwlock = devm_hwspin_lock_request_specific(dev, hwlock_id);
}
spin_lock_init(&pctl->irqmux_lock);
pctl->dev = dev;
- pctl->match_data = match->data;
+ pctl->match_data = match_data;
/* get optional package information */
- if (!of_property_read_u32(np, "st,package", &pctl->pkg))
+ if (!device_property_read_u32(dev, "st,package", &pctl->pkg))
dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
@@ -1503,6 +1935,8 @@ int stm32_pctl_probe(struct platform_device *pdev)
pctl->pctl_desc.confops = &stm32_pconf_ops;
pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
pctl->pctl_desc.pmxops = &stm32_pmx_ops;
+ pctl->pctl_desc.num_custom_params = ARRAY_SIZE(stm32_gpio_bindings);
+ pctl->pctl_desc.custom_params = stm32_gpio_bindings;
pctl->dev = &pdev->dev;
pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
@@ -1513,10 +1947,7 @@ int stm32_pctl_probe(struct platform_device *pdev)
return PTR_ERR(pctl->pctl_dev);
}
- for_each_available_child_of_node(np, child)
- if (of_property_read_bool(child, "gpio-controller"))
- banks++;
-
+ banks = gpiochip_node_count(dev);
if (!banks) {
dev_err(dev, "at least one GPIO bank is required\n");
return -EINVAL;
@@ -1526,53 +1957,68 @@ int stm32_pctl_probe(struct platform_device *pdev)
if (!pctl->banks)
return -ENOMEM;
+ pctl->clks = devm_kcalloc(dev, banks, sizeof(*pctl->clks),
+ GFP_KERNEL);
+ if (!pctl->clks)
+ return -ENOMEM;
+
i = 0;
- for_each_available_child_of_node(np, child) {
+ for_each_gpiochip_node(dev, child) {
struct stm32_gpio_bank *bank = &pctl->banks[i];
+ struct device_node *np = to_of_node(child);
- if (of_property_read_bool(child, "gpio-controller")) {
- bank->rstc = of_reset_control_get_exclusive(child,
- NULL);
- if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) {
- of_node_put(child);
- return -EPROBE_DEFER;
- }
+ bank->rstc = of_reset_control_get_exclusive(np, NULL);
+ if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) {
+ fwnode_handle_put(child);
+ return -EPROBE_DEFER;
+ }
- bank->clk = of_clk_get_by_name(child, NULL);
- if (IS_ERR(bank->clk)) {
- if (PTR_ERR(bank->clk) != -EPROBE_DEFER)
- dev_err(dev,
- "failed to get clk (%ld)\n",
- PTR_ERR(bank->clk));
- of_node_put(child);
- return PTR_ERR(bank->clk);
- }
- i++;
+ pctl->clks[i].clk = of_clk_get_by_name(np, NULL);
+ if (IS_ERR(pctl->clks[i].clk)) {
+ fwnode_handle_put(child);
+ return dev_err_probe(dev, PTR_ERR(pctl->clks[i].clk),
+ "failed to get clk\n");
}
+ pctl->clks[i].id = "pctl";
+ i++;
}
- for_each_available_child_of_node(np, child) {
- if (of_property_read_bool(child, "gpio-controller")) {
- ret = stm32_gpiolib_register_bank(pctl, child);
- if (ret) {
- of_node_put(child);
- return ret;
- }
+ ret = clk_bulk_prepare_enable(banks, pctl->clks);
+ if (ret) {
+ dev_err(dev, "failed to prepare_enable clk (%d)\n", ret);
+ return ret;
+ }
- pctl->nbanks++;
+ for_each_gpiochip_node(dev, child) {
+ ret = stm32_gpiolib_register_bank(pctl, child);
+ if (ret) {
+ fwnode_handle_put(child);
+ goto err_register;
}
+
+ pctl->nbanks++;
}
dev_info(dev, "Pinctrl STM32 initialized\n");
return 0;
+err_register:
+ for (i = 0; i < pctl->nbanks; i++) {
+ struct stm32_gpio_bank *bank = &pctl->banks[i];
+
+ gpiochip_remove(&bank->gpio_chip);
+ }
+
+ clk_bulk_disable_unprepare(banks, pctl->clks);
+ return ret;
}
+EXPORT_SYMBOL(stm32_pctl_probe);
static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
struct stm32_pinctrl *pctl, u32 pin)
{
const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);
- u32 val, alt, mode, offset = stm32_gpio_pin(pin);
+ u32 mode, offset = stm32_gpio_pin(pin);
struct pinctrl_gpio_range *range;
struct stm32_gpio_bank *bank;
bool pin_is_irq;
@@ -1582,60 +2028,89 @@ static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
if (!range)
return 0;
- pin_is_irq = gpiochip_line_is_irq(range->gc, offset);
+ bank = gpiochip_get_data(range->gc);
- if (!desc || (!pin_is_irq && !desc->gpio_owner))
+ if (!gpiochip_line_is_valid(range->gc, offset))
return 0;
- bank = gpiochip_get_data(range->gc);
+ if (bank->rif_control && !stm32_gpio_rif_acquire_semaphore(bank, offset)) {
+ dev_err(pctl->dev, "pin %d not available.\n", offset);
+ return -EACCES;
+ }
- alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;
- alt >>= STM32_GPIO_BKP_ALT_SHIFT;
- mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;
- mode >>= STM32_GPIO_BKP_MODE_SHIFT;
+ pin_is_irq = gpiochip_line_is_irq(range->gc, offset);
- ret = stm32_pmx_set_mode(bank, offset, mode, alt);
+ if (!desc || (!pin_is_irq && !desc->gpio_owner))
+ return 0;
+
+ mode = bank->pin_backup[offset].mode;
+ ret = stm32_pmx_set_mode(bank, offset, mode, bank->pin_backup[offset].alt);
if (ret)
return ret;
- if (mode == 1) {
- val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);
- val = val >> STM32_GPIO_BKP_VAL;
- __stm32_gpio_set(bank, offset, val);
- }
+ if (mode == 1)
+ __stm32_gpio_set(bank, offset, bank->pin_backup[offset].value);
- val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);
- val >>= STM32_GPIO_BKP_TYPE;
- ret = stm32_pconf_set_driving(bank, offset, val);
+ ret = stm32_pconf_set_driving(bank, offset, bank->pin_backup[offset].drive);
if (ret)
return ret;
- val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;
- val >>= STM32_GPIO_BKP_SPEED_SHIFT;
- ret = stm32_pconf_set_speed(bank, offset, val);
+ ret = stm32_pconf_set_speed(bank, offset, bank->pin_backup[offset].speed);
if (ret)
return ret;
- val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;
- val >>= STM32_GPIO_BKP_PUPD_SHIFT;
- ret = stm32_pconf_set_bias(bank, offset, val);
+ ret = stm32_pconf_set_bias(bank, offset, bank->pin_backup[offset].bias);
if (ret)
return ret;
+ if (bank->io_sync_control) {
+ bool is_input = bank->pin_backup[offset].advcfg & STM32_GPIO_ADVCFGR_DLYPATH_MASK;
+
+ ret = stm32_pconf_set_skew_delay(bank, offset,
+ bank->pin_backup[offset].skew_delay,
+ is_input);
+ if (ret)
+ return ret;
+
+ ret = stm32_pconf_set_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_IO_SYNC_MASK,
+ bank->pin_backup[offset].advcfg);
+ if (ret)
+ return ret;
+ }
+
if (pin_is_irq)
regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
return 0;
}
+int __maybe_unused stm32_pinctrl_suspend(struct device *dev)
+{
+ struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
+
+ clk_bulk_disable(pctl->nbanks, pctl->clks);
+
+ return 0;
+}
+EXPORT_SYMBOL(stm32_pinctrl_suspend);
+
int __maybe_unused stm32_pinctrl_resume(struct device *dev)
{
struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
struct stm32_pinctrl_group *g = pctl->groups;
- int i;
+ int i, ret;
+
+ ret = clk_bulk_enable(pctl->nbanks, pctl->clks);
+ if (ret)
+ return ret;
for (i = 0; i < pctl->ngroups; i++, g++)
stm32_pinctrl_restore_gpio_regs(pctl, g->pin);
return 0;
}
+EXPORT_SYMBOL(stm32_pinctrl_resume);
+
+MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@foss.st.com>");
+MODULE_DESCRIPTION("STM32 core pinctrl driver");
+MODULE_LICENSE("GPL");
generated by cgit (git 2.34.1) at 2025-12-25 19:43:31 +0000