diff options
Diffstat (limited to 'drivers/scsi/3w-9xxx.h')
| -rw-r--r-- | drivers/scsi/3w-9xxx.h | 287 |
1 files changed, 148 insertions, 139 deletions
diff --git a/drivers/scsi/3w-9xxx.h b/drivers/scsi/3w-9xxx.h index 040f7214e5b7..0b23b0422e88 100644 --- a/drivers/scsi/3w-9xxx.h +++ b/drivers/scsi/3w-9xxx.h @@ -1,8 +1,8 @@ /* 3w-9xxx.h -- 3ware 9000 Storage Controller device driver for Linux. - Written By: Adam Radford <linuxraid@lsi.com> - Modifications By: Tom Couch <linuxraid@lsi.com> + Written By: Adam Radford <aradford@gmail.com> + Modifications By: Tom Couch Copyright (C) 2004-2009 Applied Micro Circuits Corporation. Copyright (C) 2010 LSI Corporation. @@ -41,10 +41,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA Bugs/Comments/Suggestions should be mailed to: - linuxraid@lsi.com - - For more information, goto: - http://www.lsi.com + aradford@gmail.com */ #ifndef _3W_9XXX_H @@ -52,8 +49,8 @@ /* AEN string type */ typedef struct TAG_twa_message_type { - unsigned int code; - char* text; + unsigned int code; + char *text; } twa_message_type; /* AEN strings */ @@ -266,9 +263,9 @@ static twa_message_type twa_error_table[] = { #define TW_CONTROL_ENABLE_INTERRUPTS 0x00000080 #define TW_CONTROL_DISABLE_INTERRUPTS 0x00000040 #define TW_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020 -#define TW_CONTROL_CLEAR_PARITY_ERROR 0x00800000 -#define TW_CONTROL_CLEAR_QUEUE_ERROR 0x00400000 -#define TW_CONTROL_CLEAR_PCI_ABORT 0x00100000 +#define TW_CONTROL_CLEAR_PARITY_ERROR 0x00800000 +#define TW_CONTROL_CLEAR_QUEUE_ERROR 0x00400000 +#define TW_CONTROL_CLEAR_PCI_ABORT 0x00100000 /* Status register bit definitions */ #define TW_STATUS_MAJOR_VERSION_MASK 0xF0000000 @@ -287,25 +284,25 @@ static twa_message_type twa_error_table[] = { #define TW_STATUS_COMMAND_QUEUE_EMPTY 0x00001000 #define TW_STATUS_EXPECTED_BITS 0x00002000 #define TW_STATUS_UNEXPECTED_BITS 0x00F00000 -#define TW_STATUS_VALID_INTERRUPT 0x00DF0000 +#define TW_STATUS_VALID_INTERRUPT 0x00DF0000 /* PCI related defines */ #define TW_PCI_CLEAR_PARITY_ERRORS 0xc100 #define TW_PCI_CLEAR_PCI_ABORT 0x2000 /* Command packet opcodes used by the driver */ -#define TW_OP_INIT_CONNECTION 0x1 -#define TW_OP_GET_PARAM 0x12 -#define TW_OP_SET_PARAM 0x13 -#define TW_OP_EXECUTE_SCSI 0x10 +#define TW_OP_INIT_CONNECTION 0x1 +#define TW_OP_GET_PARAM 0x12 +#define TW_OP_SET_PARAM 0x13 +#define TW_OP_EXECUTE_SCSI 0x10 #define TW_OP_DOWNLOAD_FIRMWARE 0x16 -#define TW_OP_RESET 0x1C +#define TW_OP_RESET 0x1C /* Asynchronous Event Notification (AEN) codes used by the driver */ -#define TW_AEN_QUEUE_EMPTY 0x0000 -#define TW_AEN_SOFT_RESET 0x0001 +#define TW_AEN_QUEUE_EMPTY 0x0000 +#define TW_AEN_SOFT_RESET 0x0001 #define TW_AEN_SYNC_TIME_WITH_HOST 0x031 -#define TW_AEN_SEVERITY_ERROR 0x1 +#define TW_AEN_SEVERITY_ERROR 0x1 #define TW_AEN_SEVERITY_DEBUG 0x4 #define TW_AEN_NOT_RETRIEVED 0x1 #define TW_AEN_RETRIEVED 0x2 @@ -324,16 +321,11 @@ static twa_message_type twa_error_table[] = { #define TW_CURRENT_DRIVER_BUILD 0 #define TW_CURRENT_DRIVER_BRANCH 0 -/* Phase defines */ -#define TW_PHASE_INITIAL 0 -#define TW_PHASE_SINGLE 1 -#define TW_PHASE_SGLIST 2 - /* Misc defines */ #define TW_9550SX_DRAIN_COMPLETED 0xFFFF -#define TW_SECTOR_SIZE 512 -#define TW_ALIGNMENT_9000 4 /* 4 bytes */ -#define TW_ALIGNMENT_9000_SGL 0x3 +#define TW_SECTOR_SIZE 512 +#define TW_ALIGNMENT_9000 4 /* 4 bytes */ +#define TW_ALIGNMENT_9000_SGL 0x3 #define TW_MAX_UNITS 16 #define TW_MAX_UNITS_9650SE 32 #define TW_INIT_MESSAGE_CREDITS 0x100 @@ -346,7 +338,7 @@ static twa_message_type twa_error_table[] = { #define TW_BASE_FW_SRL 24 #define TW_BASE_FW_BRANCH 0 #define TW_BASE_FW_BUILD 1 -#define TW_FW_SRL_LUNS_SUPPORTED 28 +#define TW_FW_SRL_LUNS_SUPPORTED 28 #define TW_Q_LENGTH 256 #define TW_Q_START 0 #define TW_MAX_SLOT 32 @@ -354,19 +346,19 @@ static twa_message_type twa_error_table[] = { #define TW_MAX_CMDS_PER_LUN 254 #define TW_MAX_RESPONSE_DRAIN 256 #define TW_MAX_AEN_DRAIN 255 -#define TW_IN_RESET 2 +#define TW_IN_RESET 2 #define TW_USING_MSI 3 #define TW_IN_ATTENTION_LOOP 4 -#define TW_MAX_SECTORS 256 -#define TW_AEN_WAIT_TIME 1000 -#define TW_IOCTL_WAIT_TIME (1 * HZ) /* 1 second */ -#define TW_MAX_CDB_LEN 16 -#define TW_ISR_DONT_COMPLETE 2 -#define TW_ISR_DONT_RESULT 3 -#define TW_IOCTL_CHRDEV_TIMEOUT 60 /* 60 seconds */ -#define TW_IOCTL_CHRDEV_FREE -1 -#define TW_COMMAND_OFFSET 128 /* 128 bytes */ -#define TW_VERSION_TABLE 0x0402 +#define TW_MAX_SECTORS 256 +#define TW_AEN_WAIT_TIME 1000 +#define TW_IOCTL_WAIT_TIME (1 * HZ) /* 1 second */ +#define TW_MAX_CDB_LEN 16 +#define TW_ISR_DONT_COMPLETE 2 +#define TW_ISR_DONT_RESULT 3 +#define TW_IOCTL_CHRDEV_TIMEOUT 60 /* 60 seconds */ +#define TW_IOCTL_CHRDEV_FREE -1 +#define TW_COMMAND_OFFSET 128 /* 128 bytes */ +#define TW_VERSION_TABLE 0x0402 #define TW_TIMEKEEP_TABLE 0x040A #define TW_INFORMATION_TABLE 0x0403 #define TW_PARAM_FWVER 3 @@ -375,22 +367,22 @@ static twa_message_type twa_error_table[] = { #define TW_PARAM_BIOSVER_LENGTH 16 #define TW_PARAM_PORTCOUNT 3 #define TW_PARAM_PORTCOUNT_LENGTH 1 -#define TW_MIN_SGL_LENGTH 0x200 /* 512 bytes */ -#define TW_MAX_SENSE_LENGTH 256 -#define TW_EVENT_SOURCE_AEN 0x1000 -#define TW_EVENT_SOURCE_COMMAND 0x1001 -#define TW_EVENT_SOURCE_PCHIP 0x1002 -#define TW_EVENT_SOURCE_DRIVER 0x1003 +#define TW_MIN_SGL_LENGTH 0x200 /* 512 bytes */ +#define TW_MAX_SENSE_LENGTH 256 +#define TW_EVENT_SOURCE_AEN 0x1000 +#define TW_EVENT_SOURCE_COMMAND 0x1001 +#define TW_EVENT_SOURCE_PCHIP 0x1002 +#define TW_EVENT_SOURCE_DRIVER 0x1003 #define TW_IOCTL_GET_COMPATIBILITY_INFO 0x101 -#define TW_IOCTL_GET_LAST_EVENT 0x102 -#define TW_IOCTL_GET_FIRST_EVENT 0x103 -#define TW_IOCTL_GET_NEXT_EVENT 0x104 -#define TW_IOCTL_GET_PREVIOUS_EVENT 0x105 -#define TW_IOCTL_GET_LOCK 0x106 -#define TW_IOCTL_RELEASE_LOCK 0x107 -#define TW_IOCTL_FIRMWARE_PASS_THROUGH 0x108 +#define TW_IOCTL_GET_LAST_EVENT 0x102 +#define TW_IOCTL_GET_FIRST_EVENT 0x103 +#define TW_IOCTL_GET_NEXT_EVENT 0x104 +#define TW_IOCTL_GET_PREVIOUS_EVENT 0x105 +#define TW_IOCTL_GET_LOCK 0x106 +#define TW_IOCTL_RELEASE_LOCK 0x107 +#define TW_IOCTL_FIRMWARE_PASS_THROUGH 0x108 #define TW_IOCTL_ERROR_STATUS_NOT_LOCKED 0x1001 // Not locked -#define TW_IOCTL_ERROR_STATUS_LOCKED 0x1002 // Already locked +#define TW_IOCTL_ERROR_STATUS_LOCKED 0x1002 // Already locked #define TW_IOCTL_ERROR_STATUS_NO_MORE_EVENTS 0x1003 // No more events #define TW_IOCTL_ERROR_STATUS_AEN_CLOBBER 0x1004 // AEN clobber occurred #define TW_IOCTL_ERROR_OS_EFAULT -EFAULT // Bad address @@ -405,12 +397,12 @@ static twa_message_type twa_error_table[] = { #define TW_SENSE_DATA_LENGTH 18 #define TW_STATUS_CHECK_CONDITION 2 #define TW_ERROR_LOGICAL_UNIT_NOT_SUPPORTED 0x10a -#define TW_ERROR_UNIT_OFFLINE 0x128 +#define TW_ERROR_UNIT_OFFLINE 0x128 #define TW_MESSAGE_SOURCE_CONTROLLER_ERROR 3 #define TW_MESSAGE_SOURCE_CONTROLLER_EVENT 4 -#define TW_MESSAGE_SOURCE_LINUX_DRIVER 6 +#define TW_MESSAGE_SOURCE_LINUX_DRIVER 6 #define TW_DRIVER TW_MESSAGE_SOURCE_LINUX_DRIVER -#define TW_MESSAGE_SOURCE_LINUX_OS 9 +#define TW_MESSAGE_SOURCE_LINUX_OS 9 #define TW_OS TW_MESSAGE_SOURCE_LINUX_OS #ifndef PCI_DEVICE_ID_3WARE_9000 #define PCI_DEVICE_ID_3WARE_9000 0x1002 @@ -442,24 +434,38 @@ static twa_message_type twa_error_table[] = { #define TW_RESID_OUT(x) ((x >> 4) & 0xff) /* request_id: 12, lun: 4 */ -#define TW_REQ_LUN_IN(lun, request_id) (((lun << 12) & 0xf000) | (request_id & 0xfff)) -#define TW_LUN_OUT(lun) ((lun >> 12) & 0xf) +#define TW_REQ_LUN_IN(lun, request_id) \ + cpu_to_le16(((lun << 12) & 0xf000) | (request_id & 0xfff)) +#define TW_LUN_OUT(lun) ((le16_to_cpu(lun) >> 12) & 0xf) /* Macros */ #define TW_CONTROL_REG_ADDR(x) (x->base_addr) #define TW_STATUS_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + 0x4) -#define TW_COMMAND_QUEUE_REG_ADDR(x) (sizeof(dma_addr_t) > 4 ? ((unsigned char __iomem *)x->base_addr + 0x20) : ((unsigned char __iomem *)x->base_addr + 0x8)) -#define TW_COMMAND_QUEUE_REG_ADDR_LARGE(x) ((unsigned char __iomem *)x->base_addr + 0x20) -#define TW_RESPONSE_QUEUE_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + 0xC) -#define TW_RESPONSE_QUEUE_REG_ADDR_LARGE(x) ((unsigned char __iomem *)x->base_addr + 0x30) -#define TW_CLEAR_ALL_INTERRUPTS(x) (writel(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x))) -#define TW_CLEAR_ATTENTION_INTERRUPT(x) (writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x))) -#define TW_CLEAR_HOST_INTERRUPT(x) (writel(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x))) -#define TW_DISABLE_INTERRUPTS(x) (writel(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x))) -#define TW_ENABLE_AND_CLEAR_INTERRUPTS(x) (writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | TW_CONTROL_UNMASK_RESPONSE_INTERRUPT | TW_CONTROL_ENABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x))) -#define TW_MASK_COMMAND_INTERRUPT(x) (writel(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x))) -#define TW_UNMASK_COMMAND_INTERRUPT(x) (writel(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x))) -#define TW_SOFT_RESET(x) (writel(TW_CONTROL_ISSUE_SOFT_RESET | \ +#define TW_COMMAND_QUEUE_REG_ADDR(x) \ + (sizeof(dma_addr_t) > 4 ? ((unsigned char __iomem *)x->base_addr + 0x20) : ((unsigned char __iomem *)x->base_addr + 0x8)) +#define TW_COMMAND_QUEUE_REG_ADDR_LARGE(x) \ + ((unsigned char __iomem *)x->base_addr + 0x20) +#define TW_RESPONSE_QUEUE_REG_ADDR(x) \ + ((unsigned char __iomem *)x->base_addr + 0xC) +#define TW_RESPONSE_QUEUE_REG_ADDR_LARGE(x) \ + ((unsigned char __iomem *)x->base_addr + 0x30) +#define TW_CLEAR_ALL_INTERRUPTS(x) \ + (writel(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x))) +#define TW_CLEAR_ATTENTION_INTERRUPT(x) \ + (writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x))) +#define TW_CLEAR_HOST_INTERRUPT(x) \ + (writel(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x))) +#define TW_DISABLE_INTERRUPTS(x) \ + (writel(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x))) +#define TW_ENABLE_AND_CLEAR_INTERRUPTS(x) \ + (writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | \ + TW_CONTROL_UNMASK_RESPONSE_INTERRUPT | \ + TW_CONTROL_ENABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x))) +#define TW_MASK_COMMAND_INTERRUPT(x) \ + (writel(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x))) +#define TW_UNMASK_COMMAND_INTERRUPT(x) \ + (writel(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x))) +#define TW_SOFT_RESET(x) (writel(TW_CONTROL_ISSUE_SOFT_RESET | \ TW_CONTROL_CLEAR_HOST_INTERRUPT | \ TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | \ TW_CONTROL_MASK_COMMAND_INTERRUPT | \ @@ -477,70 +483,75 @@ printk(KERN_WARNING "3w-9xxx: ERROR: (0x%02X:0x%04X): %s.\n",a,b,c); \ #define TW_APACHE_MAX_SGL_LENGTH (sizeof(dma_addr_t) > 4 ? 72 : 109) #define TW_ESCALADE_MAX_SGL_LENGTH (sizeof(dma_addr_t) > 4 ? 41 : 62) #define TW_PADDING_LENGTH (sizeof(dma_addr_t) > 4 ? 8 : 0) -#define TW_CPU_TO_SGL(x) (sizeof(dma_addr_t) > 4 ? cpu_to_le64(x) : cpu_to_le32(x)) -#pragma pack(1) +#if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) +typedef __le64 twa_addr_t; +#define TW_CPU_TO_SGL(x) cpu_to_le64(x) +#else +typedef __le32 twa_addr_t; +#define TW_CPU_TO_SGL(x) cpu_to_le32(x) +#endif /* Scatter Gather List Entry */ typedef struct TAG_TW_SG_Entry { - dma_addr_t address; - u32 length; -} TW_SG_Entry; + twa_addr_t address; + __le32 length; +} __packed TW_SG_Entry; /* Command Packet */ typedef struct TW_Command { - unsigned char opcode__sgloffset; - unsigned char size; - unsigned char request_id; - unsigned char unit__hostid; + u8 opcode__sgloffset; + u8 size; + u8 request_id; + u8 unit__hostid; /* Second DWORD */ - unsigned char status; - unsigned char flags; + u8 status; + u8 flags; union { - unsigned short block_count; - unsigned short parameter_count; + __le16 block_count; + __le16 parameter_count; } byte6_offset; union { struct { - u32 lba; - TW_SG_Entry sgl[TW_ESCALADE_MAX_SGL_LENGTH]; - dma_addr_t padding; + __le32 lba; + TW_SG_Entry sgl[TW_ESCALADE_MAX_SGL_LENGTH]; + twa_addr_t padding; } io; struct { - TW_SG_Entry sgl[TW_ESCALADE_MAX_SGL_LENGTH]; - u32 padding; - dma_addr_t padding2; + TW_SG_Entry sgl[TW_ESCALADE_MAX_SGL_LENGTH]; + __le32 padding; + twa_addr_t padding2; } param; } byte8_offset; } TW_Command; /* Command Packet for 9000+ controllers */ typedef struct TAG_TW_Command_Apache { - unsigned char opcode__reserved; - unsigned char unit; - unsigned short request_id__lunl; - unsigned char status; - unsigned char sgl_offset; - unsigned short sgl_entries__lunh; - unsigned char cdb[16]; - TW_SG_Entry sg_list[TW_APACHE_MAX_SGL_LENGTH]; - unsigned char padding[TW_PADDING_LENGTH]; + u8 opcode__reserved; + u8 unit; + __le16 request_id__lunl; + u8 status; + u8 sgl_offset; + __le16 sgl_entries__lunh; + u8 cdb[16]; + TW_SG_Entry sg_list[TW_APACHE_MAX_SGL_LENGTH]; + u8 padding[TW_PADDING_LENGTH]; } TW_Command_Apache; /* New command packet header */ typedef struct TAG_TW_Command_Apache_Header { unsigned char sense_data[TW_SENSE_DATA_LENGTH]; struct { - char reserved[4]; - unsigned short error; - unsigned char padding; - unsigned char severity__reserved; + u8 reserved[4]; + __le16 error; + u8 padding; + u8 severity__reserved; } status_block; unsigned char err_specific_desc[98]; struct { - unsigned char size_header; - unsigned short reserved; - unsigned char size_sense; + u8 size_header; + u8 reserved[2]; + u8 size_sense; } header_desc; } TW_Command_Apache_Header; @@ -555,19 +566,19 @@ typedef struct TAG_TW_Command_Full { /* Initconnection structure */ typedef struct TAG_TW_Initconnect { - unsigned char opcode__reserved; - unsigned char size; - unsigned char request_id; - unsigned char res2; - unsigned char status; - unsigned char flags; - unsigned short message_credits; - u32 features; - unsigned short fw_srl; - unsigned short fw_arch_id; - unsigned short fw_branch; - unsigned short fw_build; - u32 result; + u8 opcode__reserved; + u8 size; + u8 request_id; + u8 res2; + u8 status; + u8 flags; + __le16 message_credits; + __le32 features; + __le16 fw_srl; + __le16 fw_arch_id; + __le16 fw_branch; + __le16 fw_build; + __le32 result; } TW_Initconnect; /* Event info structure */ @@ -594,9 +605,9 @@ typedef struct TAG_TW_Ioctl_Driver_Command { typedef struct TAG_TW_Ioctl_Apache { TW_Ioctl_Driver_Command driver_command; - char padding[488]; + char padding[488]; TW_Command_Full firmware_command; - char data_buffer[1]; + char data_buffer[]; } TW_Ioctl_Buf_Apache; /* Lock structure for ioctl get/release lock */ @@ -608,11 +619,11 @@ typedef struct TAG_TW_Lock { /* GetParam descriptor */ typedef struct { - unsigned short table_id; - unsigned short parameter_id; - unsigned short parameter_size_bytes; - unsigned short actual_parameter_size_bytes; - unsigned char data[1]; + __le16 table_id; + __le16 parameter_id; + __le16 parameter_size_bytes; + __le16 actual_parameter_size_bytes; + u8 data[]; } TW_Param_Apache, *PTW_Param_Apache; /* Response queue */ @@ -639,13 +650,11 @@ typedef struct TAG_TW_Compatibility_Info unsigned short fw_on_ctlr_build; } TW_Compatibility_Info; -#pragma pack() - typedef struct TAG_TW_Device_Extension { - u32 __iomem *base_addr; - unsigned long *generic_buffer_virt[TW_Q_LENGTH]; - dma_addr_t generic_buffer_phys[TW_Q_LENGTH]; - TW_Command_Full *command_packet_virt[TW_Q_LENGTH]; + u32 __iomem *base_addr; + unsigned long *generic_buffer_virt[TW_Q_LENGTH]; + dma_addr_t generic_buffer_phys[TW_Q_LENGTH]; + TW_Command_Full *command_packet_virt[TW_Q_LENGTH]; dma_addr_t command_packet_phys[TW_Q_LENGTH]; struct pci_dev *tw_pci_dev; struct scsi_cmnd *srb[TW_Q_LENGTH]; @@ -655,10 +664,10 @@ typedef struct TAG_TW_Device_Extension { unsigned char pending_queue[TW_Q_LENGTH]; unsigned char pending_head; unsigned char pending_tail; - int state[TW_Q_LENGTH]; + int state[TW_Q_LENGTH]; unsigned int posted_request_count; unsigned int max_posted_request_count; - unsigned int pending_request_count; + unsigned int pending_request_count; unsigned int max_pending_request_count; unsigned int max_sgl_entries; unsigned int sgl_entries; @@ -669,12 +678,12 @@ typedef struct TAG_TW_Device_Extension { struct Scsi_Host *host; long flags; int reset_print; - TW_Event *event_queue[TW_Q_LENGTH]; - unsigned char error_index; + TW_Event *event_queue[TW_Q_LENGTH]; + unsigned char error_index; unsigned char event_queue_wrapped; - unsigned int error_sequence_id; - int ioctl_sem_lock; - u32 ioctl_msec; + unsigned int error_sequence_id; + int ioctl_sem_lock; + ktime_t ioctl_time; int chrdev_request_id; wait_queue_head_t ioctl_wqueue; struct mutex ioctl_lock; |