diff options
Diffstat (limited to 'drivers/scsi/qla2xxx/qla_mr.h')
| -rw-r--r-- | drivers/scsi/qla2xxx/qla_mr.h | 54 |
1 files changed, 28 insertions, 26 deletions
diff --git a/drivers/scsi/qla2xxx/qla_mr.h b/drivers/scsi/qla2xxx/qla_mr.h index aeaa1b40b1fc..3a2bd953a976 100644 --- a/drivers/scsi/qla2xxx/qla_mr.h +++ b/drivers/scsi/qla2xxx/qla_mr.h @@ -1,12 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * QLogic Fibre Channel HBA Driver * Copyright (c) 2003-2014 QLogic Corporation - * - * See LICENSE.qla2xxx for copyright and licensing details. */ #ifndef __QLA_MR_H #define __QLA_MR_H +#include "qla_dsd.h" + /* * The PCI VendorID and DeviceID for our board. */ @@ -46,8 +47,7 @@ struct cmd_type_7_fx00 { uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */ __le32 byte_count; /* Total byte count. */ - uint32_t dseg_0_address[2]; /* Data segment 0 address. */ - uint32_t dseg_0_len; /* Data segment 0 length. */ + struct dsd64 dsd; }; #define STATUS_TYPE_FX00 0x01 /* Status entry. */ @@ -95,7 +95,7 @@ struct tsk_mgmt_entry_fx00 { uint8_t sys_define; uint8_t entry_status; /* Entry Status. */ - __le32 handle; /* System handle. */ + uint32_t handle; /* System handle. */ uint32_t reserved_0; @@ -120,13 +120,13 @@ struct abort_iocb_entry_fx00 { uint8_t sys_define; /* System defined. */ uint8_t entry_status; /* Entry Status. */ - __le32 handle; /* System handle. */ + uint32_t handle; /* System handle. */ __le32 reserved_0; __le16 tgt_id_sts; /* Completion status. */ __le16 options; - __le32 abort_handle; /* System handle. */ + uint32_t abort_handle; /* System handle. */ __le32 reserved_2; __le16 req_que_no; @@ -165,7 +165,7 @@ struct fxdisc_entry_fx00 { uint8_t sys_define; /* System Defined. */ uint8_t entry_status; /* Entry Status. */ - __le32 handle; /* System handle. */ + uint32_t handle; /* System handle. */ __le32 reserved_0; /* System handle. */ __le16 func_num; @@ -176,10 +176,12 @@ struct fxdisc_entry_fx00 { uint8_t flags; uint8_t reserved_1; - __le32 dseg_rq_address[2]; /* Data segment 0 address. */ - __le32 dseg_rq_len; /* Data segment 0 length. */ - __le32 dseg_rsp_address[2]; /* Data segment 1 address. */ - __le32 dseg_rsp_len; /* Data segment 1 length. */ + /* + * Use array size 1 below to prevent that Coverity complains about + * the append_dsd64() calls for the two arrays below. + */ + struct dsd64 dseg_rq[1]; + struct dsd64 dseg_rsp[1]; __le32 dataword; __le32 adapid; @@ -280,8 +282,8 @@ struct register_host_info { #define QLAFX00_TGT_NODE_LIST_SIZE (sizeof(uint32_t) * 32) struct config_info_data { - uint8_t model_num[16]; - uint8_t model_description[80]; + uint8_t model_num[16] __nonstring; + uint8_t model_description[80] __nonstring; uint8_t reserved0[160]; uint8_t symbolic_name[64]; uint8_t serial_num[32]; @@ -360,47 +362,47 @@ struct config_info_data { #define CONTINUE_A64_TYPE_FX00 0x03 /* Continuation entry. */ #define QLAFX00_SET_HST_INTR(ha, value) \ - WRT_REG_DWORD((ha)->cregbase + QLAFX00_HST_TO_HBA_REG, \ + wrt_reg_dword((ha)->cregbase + QLAFX00_HST_TO_HBA_REG, \ value) #define QLAFX00_CLR_HST_INTR(ha, value) \ - WRT_REG_DWORD((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \ + wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \ ~value) #define QLAFX00_RD_INTR_REG(ha) \ - RD_REG_DWORD((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG) + rd_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG) #define QLAFX00_CLR_INTR_REG(ha, value) \ - WRT_REG_DWORD((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \ + wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \ ~value) #define QLAFX00_SET_HBA_SOC_REG(ha, off, val)\ - WRT_REG_DWORD((ha)->cregbase + off, val) + wrt_reg_dword((ha)->cregbase + off, val) #define QLAFX00_GET_HBA_SOC_REG(ha, off)\ - RD_REG_DWORD((ha)->cregbase + off) + rd_reg_dword((ha)->cregbase + off) #define QLAFX00_HBA_RST_REG(ha, val)\ - WRT_REG_DWORD((ha)->cregbase + QLAFX00_HST_RST_REG, val) + wrt_reg_dword((ha)->cregbase + QLAFX00_HST_RST_REG, val) #define QLAFX00_RD_ICNTRL_REG(ha) \ - RD_REG_DWORD((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG) + rd_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG) #define QLAFX00_ENABLE_ICNTRL_REG(ha) \ - WRT_REG_DWORD((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \ + wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \ (QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) | \ QLAFX00_ICR_ENB_MASK)) #define QLAFX00_DISABLE_ICNTRL_REG(ha) \ - WRT_REG_DWORD((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \ + wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \ (QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) & \ QLAFX00_ICR_DIS_MASK)) #define QLAFX00_RD_REG(ha, off) \ - RD_REG_DWORD((ha)->cregbase + off) + rd_reg_dword((ha)->cregbase + off) #define QLAFX00_WR_REG(ha, off, val) \ - WRT_REG_DWORD((ha)->cregbase + off, val) + wrt_reg_dword((ha)->cregbase + off, val) struct qla_mt_iocb_rqst_fx00 { __le32 reserved_0; |