diff options
Diffstat (limited to 'drivers/spi/spi-pxa2xx.c')
| -rw-r--r-- | drivers/spi/spi-pxa2xx.c | 997 |
1 files changed, 257 insertions, 740 deletions
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index 6721910e5f2a..ec7117a94d5f 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -1,48 +1,42 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs - * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2013, 2021 Intel Corporation */ -#include <linux/acpi.h> +#include <linux/atomic.h> #include <linux/bitops.h> +#include <linux/bug.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/device.h> +#include <linux/dmaengine.h> #include <linux/err.h> -#include <linux/errno.h> #include <linux/gpio/consumer.h> -#include <linux/gpio.h> -#include <linux/init.h> #include <linux/interrupt.h> +#include <linux/io.h> #include <linux/ioport.h> -#include <linux/kernel.h> +#include <linux/math64.h> +#include <linux/minmax.h> #include <linux/module.h> -#include <linux/mod_devicetable.h> -#include <linux/of.h> -#include <linux/pci.h> -#include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/property.h> #include <linux/slab.h> -#include <linux/spi/pxa2xx_spi.h> +#include <linux/types.h> + #include <linux/spi/spi.h> +#include "internals.h" #include "spi-pxa2xx.h" -MODULE_AUTHOR("Stephen Street"); -MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:pxa2xx-spi"); - #define TIMOUT_DFLT 1000 /* - * for testing SSCR1 changes that require SSP restart, basically - * everything except the service and interrupt enables, the pxa270 developer + * For testing SSCR1 changes that require SSP restart, basically + * everything except the service and interrupt enables, the PXA270 developer * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this - * list, but the PXA255 dev man says all bits without really meaning the - * service and interrupt enables + * list, but the PXA255 developer manual says all bits without really meaning + * the service and interrupt enables. */ #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ @@ -64,6 +58,14 @@ MODULE_ALIAS("platform:pxa2xx-spi"); | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \ | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) +struct chip_data { + u32 cr1; + u32 dds_rate; + u32 threshold; + u16 lpss_rx_threshold; + u16 lpss_tx_threshold; +}; + #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) #define LPSS_CS_CONTROL_SW_MODE BIT(0) #define LPSS_CS_CONTROL_CS_HIGH BIT(1) @@ -71,8 +73,9 @@ MODULE_ALIAS("platform:pxa2xx-spi"); #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT) #define LPSS_PRIV_CLOCK_GATE 0x38 -#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3 -#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3 +#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3 +#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3 +#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_OFF 0x0 struct lpss_config { /* LPSS offset from drv_data->ioaddr */ @@ -89,7 +92,6 @@ struct lpss_config { /* Chip select control */ unsigned cs_sel_shift; unsigned cs_sel_mask; - unsigned cs_num; /* Quirks */ unsigned cs_clk_stays_gated : 1; }; @@ -127,7 +129,6 @@ static const struct lpss_config lpss_platforms[] = { .tx_threshold_hi = 224, .cs_sel_shift = 2, .cs_sel_mask = 1 << 2, - .cs_num = 2, }, { /* LPSS_SPT_SSP */ .offset = 0x200, @@ -198,6 +199,17 @@ static bool is_mmp2_ssp(const struct driver_data *drv_data) return drv_data->ssp_type == MMP2_SSP; } +static bool is_mrfld_ssp(const struct driver_data *drv_data) +{ + return drv_data->ssp_type == MRFLD_SSP; +} + +static void pxa2xx_spi_update(const struct driver_data *drv_data, u32 reg, u32 mask, u32 value) +{ + if ((pxa2xx_spi_read(drv_data, reg) & mask) != value) + pxa2xx_spi_write(drv_data, reg, value & mask); +} + static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data) { switch (drv_data->ssp_type) { @@ -239,7 +251,7 @@ static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data) break; } - return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask; + return read_SSSR_bits(drv_data, mask) == mask; } static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data, @@ -284,13 +296,11 @@ static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data, case QUARK_X1000_SSP: return clk_div | QUARK_X1000_SSCR0_Motorola - | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits) - | SSCR0_SSE; + | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits); default: return clk_div | SSCR0_Motorola | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) - | SSCR0_SSE | (bits > 16 ? SSCR0_EDSS : 0); } } @@ -312,6 +322,20 @@ static void __lpss_ssp_write_priv(struct driver_data *drv_data, writel(value, drv_data->lpss_base + offset); } +static bool __lpss_ssp_update_priv(struct driver_data *drv_data, unsigned int offset, + u32 mask, u32 value) +{ + u32 new, curr; + + curr = __lpss_ssp_read_priv(drv_data, offset); + new = (curr & ~mask) | (value & mask); + if (new == curr) + return false; + + __lpss_ssp_write_priv(drv_data, offset, new); + return true; +} + /* * lpss_ssp_setup - perform LPSS SSP specific setup * @drv_data: pointer to the driver private data @@ -325,24 +349,19 @@ static void lpss_ssp_setup(struct driver_data *drv_data) u32 value; config = lpss_get_config(drv_data); - drv_data->lpss_base = drv_data->ioaddr + config->offset; + drv_data->lpss_base = drv_data->ssp->mmio_base + config->offset; /* Enable software chip select control */ - value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); - value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH); - value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH; - __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); + value = LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH; + __lpss_ssp_update_priv(drv_data, config->reg_cs_ctrl, value, value); /* Enable multiblock DMA transfers */ if (drv_data->controller_info->enable_dma) { - __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1); + __lpss_ssp_update_priv(drv_data, config->reg_ssp, BIT(0), BIT(0)); if (config->reg_general >= 0) { - value = __lpss_ssp_read_priv(drv_data, - config->reg_general); - value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE; - __lpss_ssp_write_priv(drv_data, - config->reg_general, value); + value = LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE; + __lpss_ssp_update_priv(drv_data, config->reg_general, value, value); } } } @@ -352,30 +371,19 @@ static void lpss_ssp_select_cs(struct spi_device *spi, { struct driver_data *drv_data = spi_controller_get_devdata(spi->controller); - u32 value, cs; + u32 cs; - if (!config->cs_sel_mask) + cs = spi_get_chipselect(spi, 0) << config->cs_sel_shift; + if (!__lpss_ssp_update_priv(drv_data, config->reg_cs_ctrl, config->cs_sel_mask, cs)) return; - value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); - - cs = spi->chip_select; - cs <<= config->cs_sel_shift; - if (cs != (value & config->cs_sel_mask)) { - /* - * When switching another chip select output active the - * output must be selected first and wait 2 ssp_clk cycles - * before changing state to active. Otherwise a short - * glitch will occur on the previous chip select since - * output select is latched but state control is not. - */ - value &= ~config->cs_sel_mask; - value |= cs; - __lpss_ssp_write_priv(drv_data, - config->reg_cs_ctrl, value); - ndelay(1000000000 / - (drv_data->controller->max_speed_hz / 2)); - } + /* + * When switching another chip select output active the output must be + * selected first and wait 2 ssp_clk cycles before changing state to + * active. Otherwise a short glitch will occur on the previous chip + * select since output select is latched but state control is not. + */ + ndelay(1000000000 / (drv_data->controller->max_speed_hz / 2)); } static void lpss_ssp_cs_control(struct spi_device *spi, bool enable) @@ -383,55 +391,37 @@ static void lpss_ssp_cs_control(struct spi_device *spi, bool enable) struct driver_data *drv_data = spi_controller_get_devdata(spi->controller); const struct lpss_config *config; - u32 value; + u32 mask; config = lpss_get_config(drv_data); if (enable) lpss_ssp_select_cs(spi, config); - value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); - if (enable) - value &= ~LPSS_CS_CONTROL_CS_HIGH; - else - value |= LPSS_CS_CONTROL_CS_HIGH; - __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); + mask = LPSS_CS_CONTROL_CS_HIGH; + __lpss_ssp_update_priv(drv_data, config->reg_cs_ctrl, mask, enable ? 0 : mask); if (config->cs_clk_stays_gated) { - u32 clkgate; - /* * Changing CS alone when dynamic clock gating is on won't * actually flip CS at that time. This ruins SPI transfers * that specify delays, or have no data. Toggle the clock mode * to force on briefly to poke the CS pin to move. */ - clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE); - value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) | - LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON; - - __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value); - __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate); + mask = LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK; + if (__lpss_ssp_update_priv(drv_data, LPSS_PRIV_CLOCK_GATE, mask, + LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON)) + __lpss_ssp_update_priv(drv_data, LPSS_PRIV_CLOCK_GATE, mask, + LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_OFF); } } static void cs_assert(struct spi_device *spi) { - struct chip_data *chip = spi_get_ctldata(spi); struct driver_data *drv_data = spi_controller_get_devdata(spi->controller); if (drv_data->ssp_type == CE4100_SSP) { - pxa2xx_spi_write(drv_data, SSSR, chip->frm); - return; - } - - if (chip->cs_control) { - chip->cs_control(PXA2XX_CS_ASSERT); - return; - } - - if (chip->gpiod_cs) { - gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted); + pxa2xx_spi_write(drv_data, SSSR, spi_get_chipselect(spi, 0)); return; } @@ -441,7 +431,6 @@ static void cs_assert(struct spi_device *spi) static void cs_deassert(struct spi_device *spi) { - struct chip_data *chip = spi_get_ctldata(spi); struct driver_data *drv_data = spi_controller_get_devdata(spi->controller); unsigned long timeout; @@ -455,16 +444,6 @@ static void cs_deassert(struct spi_device *spi) !time_after(jiffies, timeout)) cpu_relax(); - if (chip->cs_control) { - chip->cs_control(PXA2XX_CS_DEASSERT); - return; - } - - if (chip->gpiod_cs) { - gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted); - return; - } - if (is_lpss_ssp(drv_data)) lpss_ssp_cs_control(spi, false); } @@ -482,7 +461,7 @@ int pxa2xx_spi_flush(struct driver_data *drv_data) unsigned long limit = loops_per_jiffy << 1; do { - while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) + while (read_SSSR_bits(drv_data, SSSR_RNE)) pxa2xx_spi_read(drv_data, SSDR); } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); write_SSSR_CS(drv_data, SSSR_ROR); @@ -496,8 +475,7 @@ static void pxa2xx_spi_off(struct driver_data *drv_data) if (is_mmp2_ssp(drv_data)) return; - pxa2xx_spi_write(drv_data, SSCR0, - pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); + pxa_ssp_disable(drv_data->ssp); } static int null_writer(struct driver_data *drv_data) @@ -518,8 +496,7 @@ static int null_reader(struct driver_data *drv_data) { u8 n_bytes = drv_data->n_bytes; - while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) - && (drv_data->rx < drv_data->rx_end)) { + while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { pxa2xx_spi_read(drv_data, SSDR); drv_data->rx += n_bytes; } @@ -541,8 +518,7 @@ static int u8_writer(struct driver_data *drv_data) static int u8_reader(struct driver_data *drv_data) { - while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) - && (drv_data->rx < drv_data->rx_end)) { + while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); ++drv_data->rx; } @@ -564,8 +540,7 @@ static int u16_writer(struct driver_data *drv_data) static int u16_reader(struct driver_data *drv_data) { - while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) - && (drv_data->rx < drv_data->rx_end)) { + while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); drv_data->rx += 2; } @@ -587,8 +562,7 @@ static int u32_writer(struct driver_data *drv_data) static int u32_reader(struct driver_data *drv_data) { - while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) - && (drv_data->rx < drv_data->rx_end)) { + while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); drv_data->rx += 4; } @@ -598,67 +572,76 @@ static int u32_reader(struct driver_data *drv_data) static void reset_sccr1(struct driver_data *drv_data) { - struct chip_data *chip = - spi_get_ctldata(drv_data->controller->cur_msg->spi); - u32 sccr1_reg; + u32 mask = drv_data->int_cr1 | drv_data->dma_cr1, threshold; + struct chip_data *chip; + + if (drv_data->controller->cur_msg) { + chip = spi_get_ctldata(drv_data->controller->cur_msg->spi); + threshold = chip->threshold; + } else { + threshold = 0; + } - sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1; switch (drv_data->ssp_type) { case QUARK_X1000_SSP: - sccr1_reg &= ~QUARK_X1000_SSCR1_RFT; + mask |= QUARK_X1000_SSCR1_RFT; break; case CE4100_SSP: - sccr1_reg &= ~CE4100_SSCR1_RFT; + mask |= CE4100_SSCR1_RFT; break; default: - sccr1_reg &= ~SSCR1_RFT; + mask |= SSCR1_RFT; break; } - sccr1_reg |= chip->threshold; - pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); + + pxa2xx_spi_update(drv_data, SSCR1, mask, threshold); } -static void int_error_stop(struct driver_data *drv_data, const char* msg) +static void int_stop_and_reset(struct driver_data *drv_data) { - /* Stop and reset SSP */ + /* Clear and disable interrupts */ write_SSSR_CS(drv_data, drv_data->clear_sr); reset_sccr1(drv_data); - if (!pxa25x_ssp_comp(drv_data)) - pxa2xx_spi_write(drv_data, SSTO, 0); + if (pxa25x_ssp_comp(drv_data)) + return; + + pxa2xx_spi_write(drv_data, SSTO, 0); +} + +static void int_error_stop(struct driver_data *drv_data, const char *msg, int err) +{ + int_stop_and_reset(drv_data); pxa2xx_spi_flush(drv_data); pxa2xx_spi_off(drv_data); - dev_err(&drv_data->pdev->dev, "%s\n", msg); + dev_err(drv_data->ssp->dev, "%s\n", msg); - drv_data->controller->cur_msg->status = -EIO; + drv_data->controller->cur_msg->status = err; spi_finalize_current_transfer(drv_data->controller); } static void int_transfer_complete(struct driver_data *drv_data) { - /* Clear and disable interrupts */ - write_SSSR_CS(drv_data, drv_data->clear_sr); - reset_sccr1(drv_data); - if (!pxa25x_ssp_comp(drv_data)) - pxa2xx_spi_write(drv_data, SSTO, 0); + int_stop_and_reset(drv_data); spi_finalize_current_transfer(drv_data->controller); } static irqreturn_t interrupt_transfer(struct driver_data *drv_data) { - u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ? - drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; + u32 irq_status; - u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask; + irq_status = read_SSSR_bits(drv_data, drv_data->mask_sr); + if (!(pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE)) + irq_status &= ~SSSR_TFS; if (irq_status & SSSR_ROR) { - int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); + int_error_stop(drv_data, "interrupt_transfer: FIFO overrun", -EIO); return IRQ_HANDLED; } if (irq_status & SSSR_TUR) { - int_error_stop(drv_data, "interrupt_transfer: fifo underrun"); + int_error_stop(drv_data, "interrupt_transfer: FIFO underrun", -EIO); return IRQ_HANDLED; } @@ -670,7 +653,7 @@ static irqreturn_t interrupt_transfer(struct driver_data *drv_data) } } - /* Drain rx fifo, Fill tx fifo and prevent overruns */ + /* Drain Rx FIFO, Fill Tx FIFO and prevent overruns */ do { if (drv_data->read(drv_data)) { int_transfer_complete(drv_data); @@ -691,8 +674,8 @@ static irqreturn_t interrupt_transfer(struct driver_data *drv_data) sccr1_reg &= ~SSCR1_TIE; /* - * PXA25x_SSP has no timeout, set up rx threshould for the - * remaining RX bytes. + * PXA25x_SSP has no timeout, set up Rx threshold for + * the remaining Rx bytes. */ if (pxa25x_ssp_comp(drv_data)) { u32 rx_thre; @@ -724,15 +707,10 @@ static irqreturn_t interrupt_transfer(struct driver_data *drv_data) static void handle_bad_msg(struct driver_data *drv_data) { + int_stop_and_reset(drv_data); pxa2xx_spi_off(drv_data); - pxa2xx_spi_write(drv_data, SSCR1, - pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1); - if (!pxa25x_ssp_comp(drv_data)) - pxa2xx_spi_write(drv_data, SSTO, 0); - write_SSSR_CS(drv_data, drv_data->clear_sr); - dev_err(&drv_data->pdev->dev, - "bad message state in interrupt handler\n"); + dev_err(drv_data->ssp->dev, "bad message state in interrupt handler\n"); } static irqreturn_t ssp_int(int irq, void *dev_id) @@ -748,7 +726,7 @@ static irqreturn_t ssp_int(int irq, void *dev_id) * the IRQ was not for us (we shouldn't be RPM suspended when the * interrupt is enabled). */ - if (pm_runtime_suspended(&drv_data->pdev->dev)) + if (pm_runtime_suspended(drv_data->ssp->dev)) return IRQ_NONE; /* @@ -916,7 +894,7 @@ static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) /* * Calculate the divisor for the SCR (Serial Clock Rate), avoiding - * that the SSP transmission rate can be greater than the device rate + * that the SSP transmission rate can be greater than the device rate. */ if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff; @@ -946,11 +924,11 @@ static bool pxa2xx_spi_can_dma(struct spi_controller *controller, struct spi_device *spi, struct spi_transfer *xfer) { - struct chip_data *chip = spi_get_ctldata(spi); + struct driver_data *drv_data = spi_controller_get_devdata(controller); - return chip->enable_dma && + return drv_data->controller_info->enable_dma && xfer->len <= MAX_DMA_LEN && - xfer->len >= chip->dma_burst_size; + xfer->len >= drv_data->controller_info->dma_burst_size; } static int pxa2xx_spi_transfer_one(struct spi_controller *controller, @@ -958,11 +936,9 @@ static int pxa2xx_spi_transfer_one(struct spi_controller *controller, struct spi_transfer *transfer) { struct driver_data *drv_data = spi_controller_get_devdata(controller); - struct spi_message *message = controller->cur_msg; struct chip_data *chip = spi_get_ctldata(spi); - u32 dma_thresh = chip->dma_threshold; - u32 dma_burst = chip->dma_burst_size; u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data); + u32 dma_thresh; u32 clk_div; u8 bits; u32 speed; @@ -972,21 +948,11 @@ static int pxa2xx_spi_transfer_one(struct spi_controller *controller, int dma_mapped; /* Check if we can DMA this transfer */ - if (transfer->len > MAX_DMA_LEN && chip->enable_dma) { - - /* reject already-mapped transfers; PIO won't always work */ - if (message->is_dma_mapped - || transfer->rx_dma || transfer->tx_dma) { - dev_err(&spi->dev, - "Mapped transfer length of %u is greater than %d\n", - transfer->len, MAX_DMA_LEN); - return -EINVAL; - } - - /* warn ... we force this to PIO mode */ + if (transfer->len > MAX_DMA_LEN && drv_data->controller_info->enable_dma) { + /* Warn ... we force this to PIO mode */ dev_warn_ratelimited(&spi->dev, - "DMA disabled for transfer length %ld greater than %d\n", - (long)transfer->len, MAX_DMA_LEN); + "DMA disabled for transfer length %u greater than %d\n", + transfer->len, MAX_DMA_LEN); } /* Setup the transfer state based on the type of transfer */ @@ -994,13 +960,10 @@ static int pxa2xx_spi_transfer_one(struct spi_controller *controller, dev_err(&spi->dev, "Flush failed\n"); return -EIO; } - drv_data->n_bytes = chip->n_bytes; drv_data->tx = (void *)transfer->tx_buf; drv_data->tx_end = drv_data->tx + transfer->len; drv_data->rx = transfer->rx_buf; drv_data->rx_end = drv_data->rx + transfer->len; - drv_data->write = drv_data->tx ? chip->write : null_writer; - drv_data->read = drv_data->rx ? chip->read : null_reader; /* Change speed and bit per word on a per transfer */ bits = transfer->bits_per_word; @@ -1010,41 +973,21 @@ static int pxa2xx_spi_transfer_one(struct spi_controller *controller, if (bits <= 8) { drv_data->n_bytes = 1; - drv_data->read = drv_data->read != null_reader ? - u8_reader : null_reader; - drv_data->write = drv_data->write != null_writer ? - u8_writer : null_writer; + drv_data->read = drv_data->rx ? u8_reader : null_reader; + drv_data->write = drv_data->tx ? u8_writer : null_writer; } else if (bits <= 16) { drv_data->n_bytes = 2; - drv_data->read = drv_data->read != null_reader ? - u16_reader : null_reader; - drv_data->write = drv_data->write != null_writer ? - u16_writer : null_writer; + drv_data->read = drv_data->rx ? u16_reader : null_reader; + drv_data->write = drv_data->tx ? u16_writer : null_writer; } else if (bits <= 32) { drv_data->n_bytes = 4; - drv_data->read = drv_data->read != null_reader ? - u32_reader : null_reader; - drv_data->write = drv_data->write != null_writer ? - u32_writer : null_writer; - } - /* - * if bits/word is changed in dma mode, then must check the - * thresholds and burst also - */ - if (chip->enable_dma) { - if (pxa2xx_spi_set_dma_burst_and_threshold(chip, - spi, - bits, &dma_burst, - &dma_thresh)) - dev_warn_ratelimited(&spi->dev, - "DMA burst size reduced to match bits_per_word\n"); + drv_data->read = drv_data->rx ? u32_reader : null_reader; + drv_data->write = drv_data->tx ? u32_writer : null_writer; } - dma_mapped = controller->can_dma && - controller->can_dma(controller, spi, transfer) && - controller->cur_msg_mapped; + dma_thresh = SSCR1_RxTresh(RX_THRESH_DFLT) | SSCR1_TxTresh(TX_THRESH_DFLT); + dma_mapped = spi_xfer_is_dma_mapped(controller, spi, transfer); if (dma_mapped) { - /* Ensure we have the correct interrupt handler */ drv_data->transfer_handler = pxa2xx_spi_dma_transfer; @@ -1080,54 +1023,52 @@ static int pxa2xx_spi_transfer_one(struct spi_controller *controller, dma_mapped ? "DMA" : "PIO"); if (is_lpss_ssp(drv_data)) { - if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff) - != chip->lpss_rx_threshold) - pxa2xx_spi_write(drv_data, SSIRF, - chip->lpss_rx_threshold); - if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff) - != chip->lpss_tx_threshold) - pxa2xx_spi_write(drv_data, SSITF, - chip->lpss_tx_threshold); + pxa2xx_spi_update(drv_data, SSIRF, GENMASK(7, 0), chip->lpss_rx_threshold); + pxa2xx_spi_update(drv_data, SSITF, GENMASK(15, 0), chip->lpss_tx_threshold); } - if (is_quark_x1000_ssp(drv_data) && - (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate)) - pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate); - - /* see if we need to reload the config registers */ - if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0) - || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask) - != (cr1 & change_mask)) { - /* stop the SSP, and update the other bits */ - if (!is_mmp2_ssp(drv_data)) - pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE); - if (!pxa25x_ssp_comp(drv_data)) - pxa2xx_spi_write(drv_data, SSTO, chip->timeout); - /* first set CR1 without interrupt and service enables */ - pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask); - /* restart the SSP */ - pxa2xx_spi_write(drv_data, SSCR0, cr0); + if (is_mrfld_ssp(drv_data)) { + u32 mask = SFIFOTT_RFT | SFIFOTT_TFT; + u32 thresh = 0; - } else { - if (!pxa25x_ssp_comp(drv_data)) - pxa2xx_spi_write(drv_data, SSTO, chip->timeout); + thresh |= SFIFOTT_RxThresh(chip->lpss_rx_threshold); + thresh |= SFIFOTT_TxThresh(chip->lpss_tx_threshold); + + pxa2xx_spi_update(drv_data, SFIFOTT, mask, thresh); } + if (is_quark_x1000_ssp(drv_data)) + pxa2xx_spi_update(drv_data, DDS_RATE, GENMASK(23, 0), chip->dds_rate); + + /* Stop the SSP */ + if (!is_mmp2_ssp(drv_data)) + pxa_ssp_disable(drv_data->ssp); + + if (!pxa25x_ssp_comp(drv_data)) + pxa2xx_spi_write(drv_data, SSTO, TIMOUT_DFLT); + + /* First set CR1 without interrupt and service enables */ + pxa2xx_spi_update(drv_data, SSCR1, change_mask, cr1); + + /* See if we need to reload the configuration registers */ + pxa2xx_spi_update(drv_data, SSCR0, GENMASK(31, 0), cr0); + + /* Restart the SSP */ + pxa_ssp_enable(drv_data->ssp); + if (is_mmp2_ssp(drv_data)) { - u8 tx_level = (pxa2xx_spi_read(drv_data, SSSR) - & SSSR_TFL_MASK) >> 8; + u8 tx_level = read_SSSR_bits(drv_data, SSSR_TFL_MASK) >> 8; if (tx_level) { - /* On MMP2, flipping SSE doesn't to empty TXFIFO. */ - dev_warn(&spi->dev, "%d bytes of garbage in TXFIFO!\n", - tx_level); + /* On MMP2, flipping SSE doesn't to empty Tx FIFO. */ + dev_warn(&spi->dev, "%u bytes of garbage in Tx FIFO!\n", tx_level); if (tx_level > transfer->len) tx_level = transfer->len; drv_data->tx += tx_level; } } - if (spi_controller_is_slave(controller)) { + if (spi_controller_is_target(controller)) { while (drv_data->write(drv_data)) ; if (drv_data->gpiod_ready) { @@ -1139,29 +1080,18 @@ static int pxa2xx_spi_transfer_one(struct spi_controller *controller, /* * Release the data by enabling service requests and interrupts, - * without changing any mode bits + * without changing any mode bits. */ pxa2xx_spi_write(drv_data, SSCR1, cr1); return 1; } -static int pxa2xx_spi_slave_abort(struct spi_controller *controller) +static int pxa2xx_spi_target_abort(struct spi_controller *controller) { struct driver_data *drv_data = spi_controller_get_devdata(controller); - /* Stop and reset SSP */ - write_SSSR_CS(drv_data, drv_data->clear_sr); - reset_sccr1(drv_data); - if (!pxa25x_ssp_comp(drv_data)) - pxa2xx_spi_write(drv_data, SSTO, 0); - pxa2xx_spi_flush(drv_data); - pxa2xx_spi_off(drv_data); - - dev_dbg(&drv_data->pdev->dev, "transfer aborted\n"); - - drv_data->controller->cur_msg->status = -EINTR; - spi_finalize_current_transfer(drv_data->controller); + int_error_stop(drv_data, "transfer aborted", -EINTR); return 0; } @@ -1171,15 +1101,10 @@ static void pxa2xx_spi_handle_err(struct spi_controller *controller, { struct driver_data *drv_data = spi_controller_get_devdata(controller); + int_stop_and_reset(drv_data); + /* Disable the SSP */ pxa2xx_spi_off(drv_data); - /* Clear and disable interrupts and service requests */ - write_SSSR_CS(drv_data, drv_data->clear_sr); - pxa2xx_spi_write(drv_data, SSCR1, - pxa2xx_spi_read(drv_data, SSCR1) - & ~(drv_data->int_cr1 | drv_data->dma_cr1)); - if (!pxa25x_ssp_comp(drv_data)) - pxa2xx_spi_write(drv_data, SSTO, 0); /* * Stop the DMA if running. Note DMA callback handler may have unset @@ -1202,66 +1127,8 @@ static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller) return 0; } -static int setup_cs(struct spi_device *spi, struct chip_data *chip, - struct pxa2xx_spi_chip *chip_info) -{ - struct driver_data *drv_data = - spi_controller_get_devdata(spi->controller); - struct gpio_desc *gpiod; - int err = 0; - - if (chip == NULL) - return 0; - - if (drv_data->cs_gpiods) { - gpiod = drv_data->cs_gpiods[spi->chip_select]; - if (gpiod) { - chip->gpiod_cs = gpiod; - chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; - gpiod_set_value(gpiod, chip->gpio_cs_inverted); - } - - return 0; - } - - if (chip_info == NULL) - return 0; - - /* NOTE: setup() can be called multiple times, possibly with - * different chip_info, release previously requested GPIO - */ - if (chip->gpiod_cs) { - gpiod_put(chip->gpiod_cs); - chip->gpiod_cs = NULL; - } - - /* If (*cs_control) is provided, ignore GPIO chip select */ - if (chip_info->cs_control) { - chip->cs_control = chip_info->cs_control; - return 0; - } - - if (gpio_is_valid(chip_info->gpio_cs)) { - err = gpio_request(chip_info->gpio_cs, "SPI_CS"); - if (err) { - dev_err(&spi->dev, "failed to request chip select GPIO%d\n", - chip_info->gpio_cs); - return err; - } - - gpiod = gpio_to_desc(chip_info->gpio_cs); - chip->gpiod_cs = gpiod; - chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; - - err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted); - } - - return err; -} - static int setup(struct spi_device *spi) { - struct pxa2xx_spi_chip *chip_info; struct chip_data *chip; const struct lpss_config *config; struct driver_data *drv_data = @@ -1274,6 +1141,11 @@ static int setup(struct spi_device *spi) tx_hi_thres = 0; rx_thres = RX_THRESH_QUARK_X1000_DFLT; break; + case MRFLD_SSP: + tx_thres = TX_THRESH_MRFLD_DFLT; + tx_hi_thres = 0; + rx_thres = RX_THRESH_MRFLD_DFLT; + break; case CE4100_SSP: tx_thres = TX_THRESH_CE4100_DFLT; tx_hi_thres = 0; @@ -1292,7 +1164,7 @@ static int setup(struct spi_device *spi) break; default: tx_hi_thres = 0; - if (spi_controller_is_slave(drv_data->controller)) { + if (spi_controller_is_target(drv_data->controller)) { tx_thres = 1; rx_thres = 2; } else { @@ -1302,72 +1174,38 @@ static int setup(struct spi_device *spi) break; } - /* Only alloc on first setup */ + if (drv_data->ssp_type == CE4100_SSP) { + if (spi_get_chipselect(spi, 0) > 4) { + dev_err(&spi->dev, "failed setup: cs number must not be > 4.\n"); + return -EINVAL; + } + } + + /* Only allocate on the first setup */ chip = spi_get_ctldata(spi); if (!chip) { chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); if (!chip) return -ENOMEM; - - if (drv_data->ssp_type == CE4100_SSP) { - if (spi->chip_select > 4) { - dev_err(&spi->dev, - "failed setup: cs number must not be > 4.\n"); - kfree(chip); - return -EINVAL; - } - - chip->frm = spi->chip_select; - } - chip->enable_dma = drv_data->controller_info->enable_dma; - chip->timeout = TIMOUT_DFLT; } - /* protocol drivers may change the chip settings, so... - * if chip_info exists, use it */ - chip_info = spi->controller_data; - - /* chip_info isn't always needed */ chip->cr1 = 0; - if (chip_info) { - if (chip_info->timeout) - chip->timeout = chip_info->timeout; - if (chip_info->tx_threshold) - tx_thres = chip_info->tx_threshold; - if (chip_info->tx_hi_threshold) - tx_hi_thres = chip_info->tx_hi_threshold; - if (chip_info->rx_threshold) - rx_thres = chip_info->rx_threshold; - chip->dma_threshold = 0; - if (chip_info->enable_loopback) - chip->cr1 = SSCR1_LBM; - } - if (spi_controller_is_slave(drv_data->controller)) { + if (spi_controller_is_target(drv_data->controller)) { chip->cr1 |= SSCR1_SCFR; chip->cr1 |= SSCR1_SCLKDIR; chip->cr1 |= SSCR1_SFRMDIR; chip->cr1 |= SSCR1_SPH; } - chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); - chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) - | SSITF_TxHiThresh(tx_hi_thres); - - /* set dma burst and threshold outside of chip_info path so that if - * chip_info goes away after setting chip->enable_dma, the - * burst and threshold can still respond to changes in bits_per_word */ - if (chip->enable_dma) { - /* set up legal burst and threshold for dma */ - if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, - spi->bits_per_word, - &chip->dma_burst_size, - &chip->dma_threshold)) { - dev_warn(&spi->dev, - "in setup: DMA burst size reduced to match bits_per_word\n"); - } - dev_dbg(&spi->dev, - "in setup: DMA burst size set to %u\n", - chip->dma_burst_size); + if (is_lpss_ssp(drv_data)) { + chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); + chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | + SSITF_TxHiThresh(tx_hi_thres); + } + + if (is_mrfld_ssp(drv_data)) { + chip->lpss_rx_threshold = rx_thres; + chip->lpss_tx_threshold = tx_thres; } switch (drv_data->ssp_type) { @@ -1388,260 +1226,42 @@ static int setup(struct spi_device *spi) } chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); - chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) - | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); + chip->cr1 |= ((spi->mode & SPI_CPHA) ? SSCR1_SPH : 0) | + ((spi->mode & SPI_CPOL) ? SSCR1_SPO : 0); if (spi->mode & SPI_LOOP) chip->cr1 |= SSCR1_LBM; - if (spi->bits_per_word <= 8) { - chip->n_bytes = 1; - chip->read = u8_reader; - chip->write = u8_writer; - } else if (spi->bits_per_word <= 16) { - chip->n_bytes = 2; - chip->read = u16_reader; - chip->write = u16_writer; - } else if (spi->bits_per_word <= 32) { - chip->n_bytes = 4; - chip->read = u32_reader; - chip->write = u32_writer; - } - spi_set_ctldata(spi, chip); - if (drv_data->ssp_type == CE4100_SSP) - return 0; - - return setup_cs(spi, chip, chip_info); + return 0; } static void cleanup(struct spi_device *spi) { struct chip_data *chip = spi_get_ctldata(spi); - struct driver_data *drv_data = - spi_controller_get_devdata(spi->controller); - - if (!chip) - return; - - if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods && - chip->gpiod_cs) - gpiod_put(chip->gpiod_cs); kfree(chip); } -static const struct acpi_device_id pxa2xx_spi_acpi_match[] = { - { "INT33C0", LPSS_LPT_SSP }, - { "INT33C1", LPSS_LPT_SSP }, - { "INT3430", LPSS_LPT_SSP }, - { "INT3431", LPSS_LPT_SSP }, - { "80860F0E", LPSS_BYT_SSP }, - { "8086228E", LPSS_BSW_SSP }, - { }, -}; -MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); - -/* - * PCI IDs of compound devices that integrate both host controller and private - * integrated DMA engine. Please note these are not used in module - * autoloading and probing in this module but matching the LPSS SSP type. - */ -static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = { - /* SPT-LP */ - { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP }, - { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP }, - /* SPT-H */ - { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP }, - { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP }, - /* KBL-H */ - { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP }, - { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP }, - /* CML-V */ - { PCI_VDEVICE(INTEL, 0xa3a9), LPSS_SPT_SSP }, - { PCI_VDEVICE(INTEL, 0xa3aa), LPSS_SPT_SSP }, - /* BXT A-Step */ - { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP }, - { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP }, - { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP }, - /* BXT B-Step */ - { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP }, - { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP }, - { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP }, - /* GLK */ - { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP }, - { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP }, - { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP }, - /* ICL-LP */ - { PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP }, - { PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP }, - { PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP }, - /* EHL */ - { PCI_VDEVICE(INTEL, 0x4b2a), LPSS_BXT_SSP }, - { PCI_VDEVICE(INTEL, 0x4b2b), LPSS_BXT_SSP }, - { PCI_VDEVICE(INTEL, 0x4b37), LPSS_BXT_SSP }, - /* JSL */ - { PCI_VDEVICE(INTEL, 0x4daa), LPSS_CNL_SSP }, - { PCI_VDEVICE(INTEL, 0x4dab), LPSS_CNL_SSP }, - { PCI_VDEVICE(INTEL, 0x4dfb), LPSS_CNL_SSP }, - /* APL */ - { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP }, - { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP }, - { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP }, - /* CNL-LP */ - { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP }, - { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP }, - { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP }, - /* CNL-H */ - { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP }, - { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP }, - { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP }, - /* CML-LP */ - { PCI_VDEVICE(INTEL, 0x02aa), LPSS_CNL_SSP }, - { PCI_VDEVICE(INTEL, 0x02ab), LPSS_CNL_SSP }, - { PCI_VDEVICE(INTEL, 0x02fb), LPSS_CNL_SSP }, - /* CML-H */ - { PCI_VDEVICE(INTEL, 0x06aa), LPSS_CNL_SSP }, - { PCI_VDEVICE(INTEL, 0x06ab), LPSS_CNL_SSP }, - { PCI_VDEVICE(INTEL, 0x06fb), LPSS_CNL_SSP }, - /* TGL-LP */ - { PCI_VDEVICE(INTEL, 0xa0aa), LPSS_CNL_SSP }, - { PCI_VDEVICE(INTEL, 0xa0ab), LPSS_CNL_SSP }, - { PCI_VDEVICE(INTEL, 0xa0de), LPSS_CNL_SSP }, - { PCI_VDEVICE(INTEL, 0xa0df), LPSS_CNL_SSP }, - { PCI_VDEVICE(INTEL, 0xa0fb), LPSS_CNL_SSP }, - { PCI_VDEVICE(INTEL, 0xa0fd), LPSS_CNL_SSP }, - { PCI_VDEVICE(INTEL, 0xa0fe), LPSS_CNL_SSP }, - { }, -}; - -static const struct of_device_id pxa2xx_spi_of_match[] = { - { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP }, - {}, -}; -MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match); - -#ifdef CONFIG_ACPI - -static int pxa2xx_spi_get_port_id(struct device *dev) -{ - struct acpi_device *adev; - unsigned int devid; - int port_id = -1; - - adev = ACPI_COMPANION(dev); - if (adev && adev->pnp.unique_id && - !kstrtouint(adev->pnp.unique_id, 0, &devid)) - port_id = devid; - return port_id; -} - -#else /* !CONFIG_ACPI */ - -static int pxa2xx_spi_get_port_id(struct device *dev) -{ - return -1; -} - -#endif /* CONFIG_ACPI */ - - -#ifdef CONFIG_PCI - -static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param) -{ - return param == chan->device->dev; -} - -#endif /* CONFIG_PCI */ - -static struct pxa2xx_spi_controller * -pxa2xx_spi_init_pdata(struct platform_device *pdev) -{ - struct pxa2xx_spi_controller *pdata; - struct ssp_device *ssp; - struct resource *res; - struct device *parent = pdev->dev.parent; - struct pci_dev *pcidev = dev_is_pci(parent) ? to_pci_dev(parent) : NULL; - const struct pci_device_id *pcidev_id = NULL; - enum pxa_ssp_type type; - const void *match; - - if (pcidev) - pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, pcidev); - - match = device_get_match_data(&pdev->dev); - if (match) - type = (enum pxa_ssp_type)match; - else if (pcidev_id) - type = (enum pxa_ssp_type)pcidev_id->driver_data; - else - return ERR_PTR(-EINVAL); - - pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); - if (!pdata) - return ERR_PTR(-ENOMEM); - - ssp = &pdata->ssp; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(ssp->mmio_base)) - return ERR_CAST(ssp->mmio_base); - - ssp->phys_base = res->start; - -#ifdef CONFIG_PCI - if (pcidev_id) { - pdata->tx_param = parent; - pdata->rx_param = parent; - pdata->dma_filter = pxa2xx_spi_idma_filter; - } -#endif - - ssp->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(ssp->clk)) - return ERR_CAST(ssp->clk); - - ssp->irq = platform_get_irq(pdev, 0); - if (ssp->irq < 0) - return ERR_PTR(ssp->irq); - - ssp->type = type; - ssp->dev = &pdev->dev; - ssp->port_id = pxa2xx_spi_get_port_id(&pdev->dev); - - pdata->is_slave = device_property_read_bool(&pdev->dev, "spi-slave"); - pdata->num_chipselect = 1; - pdata->enable_dma = true; - pdata->dma_burst_size = 1; - - return pdata; -} - static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller, unsigned int cs) { struct driver_data *drv_data = spi_controller_get_devdata(controller); - if (has_acpi_companion(&drv_data->pdev->dev)) { - switch (drv_data->ssp_type) { - /* - * For Atoms the ACPI DeviceSelection used by the Windows - * driver starts from 1 instead of 0 so translate it here - * to match what Linux expects. - */ - case LPSS_BYT_SSP: - case LPSS_BSW_SSP: - return cs - 1; + switch (drv_data->ssp_type) { + /* + * For some of Intel Atoms the ACPI DeviceSelection used by the Windows + * driver starts from 1 instead of 0 so translate it here to match what + * Linux expects. + */ + case LPSS_BYT_SSP: + case LPSS_BSW_SSP: + return cs - 1; - default: - break; - } + default: + return cs; } - - return cs; } static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi) @@ -1649,53 +1269,30 @@ static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi) return MAX_DMA_LEN; } -static int pxa2xx_spi_probe(struct platform_device *pdev) +int pxa2xx_spi_probe(struct device *dev, struct ssp_device *ssp, + struct pxa2xx_spi_controller *platform_info) { - struct device *dev = &pdev->dev; - struct pxa2xx_spi_controller *platform_info; struct spi_controller *controller; struct driver_data *drv_data; - struct ssp_device *ssp; const struct lpss_config *config; - int status, count; + int status; u32 tmp; - platform_info = dev_get_platdata(dev); - if (!platform_info) { - platform_info = pxa2xx_spi_init_pdata(pdev); - if (IS_ERR(platform_info)) { - dev_err(&pdev->dev, "missing platform data\n"); - return PTR_ERR(platform_info); - } - } - - ssp = pxa_ssp_request(pdev->id, pdev->name); - if (!ssp) - ssp = &platform_info->ssp; - - if (!ssp->mmio_base) { - dev_err(&pdev->dev, "failed to get ssp\n"); - return -ENODEV; - } - - if (platform_info->is_slave) - controller = spi_alloc_slave(dev, sizeof(struct driver_data)); + if (platform_info->is_target) + controller = devm_spi_alloc_target(dev, sizeof(*drv_data)); else - controller = spi_alloc_master(dev, sizeof(struct driver_data)); - - if (!controller) { - dev_err(&pdev->dev, "cannot alloc spi_controller\n"); - pxa_ssp_free(ssp); + controller = devm_spi_alloc_host(dev, sizeof(*drv_data)); + if (!controller) return -ENOMEM; - } + drv_data = spi_controller_get_devdata(controller); drv_data->controller = controller; drv_data->controller_info = platform_info; - drv_data->pdev = pdev; drv_data->ssp = ssp; - controller->dev.of_node = pdev->dev.of_node; - /* the spi->mode bits understood by this driver: */ + device_set_node(&controller->dev, dev_fwnode(dev)); + + /* The spi->mode bits understood by this driver: */ controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; controller->bus_num = ssp->port_id; @@ -1704,7 +1301,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev) controller->setup = setup; controller->set_cs = pxa2xx_spi_set_cs; controller->transfer_one = pxa2xx_spi_transfer_one; - controller->slave_abort = pxa2xx_spi_slave_abort; + controller->target_abort = pxa2xx_spi_target_abort; controller->handle_err = pxa2xx_spi_handle_err; controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs; @@ -1713,8 +1310,6 @@ static int pxa2xx_spi_probe(struct platform_device *pdev) drv_data->ssp_type = ssp->type; - drv_data->ioaddr = ssp->mmio_base; - drv_data->ssdr_physical = ssp->phys_base + SSDR; if (pxa25x_ssp_comp(drv_data)) { switch (drv_data->ssp_type) { case QUARK_X1000_SSP: @@ -1740,10 +1335,8 @@ static int pxa2xx_spi_probe(struct platform_device *pdev) status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), drv_data); - if (status < 0) { - dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); - goto out_error_controller_alloc; - } + if (status < 0) + return dev_err_probe(dev, status, "cannot get IRQ %d\n", ssp->irq); /* Setup DMA if requested */ if (platform_info->enable_dma) { @@ -1756,6 +1349,8 @@ static int pxa2xx_spi_probe(struct platform_device *pdev) controller->max_dma_len = MAX_DMA_LEN; controller->max_transfer_size = pxa2xx_spi_max_dma_transfer_size; + + dev_dbg(dev, "DMA burst size set to %u\n", platform_info->dma_burst_size); } } @@ -1776,15 +1371,16 @@ static int pxa2xx_spi_probe(struct platform_device *pdev) controller->min_speed_hz = DIV_ROUND_UP(controller->max_speed_hz, 512); + pxa_ssp_disable(ssp); + /* Load default SSP configuration */ - pxa2xx_spi_write(drv_data, SSCR0, 0); switch (drv_data->ssp_type) { case QUARK_X1000_SSP: tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT); pxa2xx_spi_write(drv_data, SSCR1, tmp); - /* using the Motorola SPI protocol and use 8 bit frame */ + /* Using the Motorola SPI protocol and use 8 bit frame */ tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8); pxa2xx_spi_write(drv_data, SSCR0, tmp); break; @@ -1797,7 +1393,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev) break; default: - if (spi_controller_is_slave(controller)) { + if (spi_controller_is_target(controller)) { tmp = SSCR1_SCFR | SSCR1_SCLKDIR | SSCR1_SFRMDIR | @@ -1810,7 +1406,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev) } pxa2xx_spi_write(drv_data, SSCR1, tmp); tmp = SSCR0_Motorola | SSCR0_DataSize(8); - if (!spi_controller_is_slave(controller)) + if (!spi_controller_is_target(controller)) tmp |= SSCR0_SCR(2); pxa2xx_spi_write(drv_data, SSCR0, tmp); break; @@ -1831,45 +1427,12 @@ static int pxa2xx_spi_probe(struct platform_device *pdev) tmp &= LPSS_CAPS_CS_EN_MASK; tmp >>= LPSS_CAPS_CS_EN_SHIFT; platform_info->num_chipselect = ffz(tmp); - } else if (config->cs_num) { - platform_info->num_chipselect = config->cs_num; } } controller->num_chipselect = platform_info->num_chipselect; + controller->use_gpio_descriptors = true; - count = gpiod_count(&pdev->dev, "cs"); - if (count > 0) { - int i; - - controller->num_chipselect = max_t(int, count, - controller->num_chipselect); - - drv_data->cs_gpiods = devm_kcalloc(&pdev->dev, - controller->num_chipselect, sizeof(struct gpio_desc *), - GFP_KERNEL); - if (!drv_data->cs_gpiods) { - status = -ENOMEM; - goto out_error_clock_enabled; - } - - for (i = 0; i < controller->num_chipselect; i++) { - struct gpio_desc *gpiod; - - gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS); - if (IS_ERR(gpiod)) { - /* Means use native chip select */ - if (PTR_ERR(gpiod) == -ENOENT) - continue; - - status = PTR_ERR(gpiod); - goto out_error_clock_enabled; - } else { - drv_data->cs_gpiods[i] = gpiod; - } - } - } - - if (platform_info->is_slave) { + if (platform_info->is_target) { drv_data->gpiod_ready = devm_gpiod_get_optional(dev, "ready", GPIOD_OUT_LOW); if (IS_ERR(drv_data->gpiod_ready)) { @@ -1878,24 +1441,16 @@ static int pxa2xx_spi_probe(struct platform_device *pdev) } } - pm_runtime_set_autosuspend_delay(&pdev->dev, 50); - pm_runtime_use_autosuspend(&pdev->dev); - pm_runtime_set_active(&pdev->dev); - pm_runtime_enable(&pdev->dev); - /* Register with the SPI framework */ - platform_set_drvdata(pdev, drv_data); + dev_set_drvdata(dev, drv_data); status = spi_register_controller(controller); - if (status != 0) { - dev_err(&pdev->dev, "problem registering spi controller\n"); - goto out_error_pm_runtime_enabled; + if (status) { + dev_err_probe(dev, status, "problem registering SPI controller\n"); + goto out_error_clock_enabled; } return status; -out_error_pm_runtime_enabled: - pm_runtime_disable(&pdev->dev); - out_error_clock_enabled: clk_disable_unprepare(ssp->clk); @@ -1903,42 +1458,30 @@ out_error_dma_irq_alloc: pxa2xx_spi_dma_release(drv_data); free_irq(ssp->irq, drv_data); -out_error_controller_alloc: - spi_controller_put(controller); - pxa_ssp_free(ssp); return status; } +EXPORT_SYMBOL_NS_GPL(pxa2xx_spi_probe, "SPI_PXA2xx"); -static int pxa2xx_spi_remove(struct platform_device *pdev) +void pxa2xx_spi_remove(struct device *dev) { - struct driver_data *drv_data = platform_get_drvdata(pdev); + struct driver_data *drv_data = dev_get_drvdata(dev); struct ssp_device *ssp = drv_data->ssp; - pm_runtime_get_sync(&pdev->dev); - spi_unregister_controller(drv_data->controller); /* Disable the SSP at the peripheral and SOC level */ - pxa2xx_spi_write(drv_data, SSCR0, 0); + pxa_ssp_disable(ssp); clk_disable_unprepare(ssp->clk); /* Release DMA */ if (drv_data->controller_info->enable_dma) pxa2xx_spi_dma_release(drv_data); - pm_runtime_put_noidle(&pdev->dev); - pm_runtime_disable(&pdev->dev); - /* Release IRQ */ free_irq(ssp->irq, drv_data); - - /* Release SSP */ - pxa_ssp_free(ssp); - - return 0; } +EXPORT_SYMBOL_NS_GPL(pxa2xx_spi_remove, "SPI_PXA2xx"); -#ifdef CONFIG_PM_SLEEP static int pxa2xx_spi_suspend(struct device *dev) { struct driver_data *drv_data = dev_get_drvdata(dev); @@ -1946,9 +1489,10 @@ static int pxa2xx_spi_suspend(struct device *dev) int status; status = spi_controller_suspend(drv_data->controller); - if (status != 0) + if (status) return status; - pxa2xx_spi_write(drv_data, SSCR0, 0); + + pxa_ssp_disable(ssp); if (!pm_runtime_suspended(dev)) clk_disable_unprepare(ssp->clk); @@ -1972,9 +1516,7 @@ static int pxa2xx_spi_resume(struct device *dev) /* Start the queue running */ return spi_controller_resume(drv_data->controller); } -#endif -#ifdef CONFIG_PM static int pxa2xx_spi_runtime_suspend(struct device *dev) { struct driver_data *drv_data = dev_get_drvdata(dev); @@ -1986,40 +1528,15 @@ static int pxa2xx_spi_runtime_suspend(struct device *dev) static int pxa2xx_spi_runtime_resume(struct device *dev) { struct driver_data *drv_data = dev_get_drvdata(dev); - int status; - status = clk_prepare_enable(drv_data->ssp->clk); - return status; + return clk_prepare_enable(drv_data->ssp->clk); } -#endif -static const struct dev_pm_ops pxa2xx_spi_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) - SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, - pxa2xx_spi_runtime_resume, NULL) +EXPORT_NS_GPL_DEV_PM_OPS(pxa2xx_spi_pm_ops, SPI_PXA2xx) = { + SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) + RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, pxa2xx_spi_runtime_resume, NULL) }; -static struct platform_driver driver = { - .driver = { - .name = "pxa2xx-spi", - .pm = &pxa2xx_spi_pm_ops, - .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), - .of_match_table = of_match_ptr(pxa2xx_spi_of_match), - }, - .probe = pxa2xx_spi_probe, - .remove = pxa2xx_spi_remove, -}; - -static int __init pxa2xx_spi_init(void) -{ - return platform_driver_register(&driver); -} -subsys_initcall(pxa2xx_spi_init); - -static void __exit pxa2xx_spi_exit(void) -{ - platform_driver_unregister(&driver); -} -module_exit(pxa2xx_spi_exit); - -MODULE_SOFTDEP("pre: dw_dmac"); +MODULE_AUTHOR("Stephen Street"); +MODULE_DESCRIPTION("PXA2xx SSP SPI Controller core driver"); +MODULE_LICENSE("GPL"); |