diff options
Diffstat (limited to 'include/acpi/actbl2.h')
| -rw-r--r-- | include/acpi/actbl2.h | 1171 |
1 files changed, 962 insertions, 209 deletions
diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index b2973dbe37ee..f726bce3eb84 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ /****************************************************************************** * - * Name: actbl2.h - ACPI Table Definitions (tables not in ACPI spec) + * Name: actbl2.h - ACPI Table Definitions * - * Copyright (C) 2000 - 2022, Intel Corp. + * Copyright (C) 2000 - 2025, Intel Corp. * *****************************************************************************/ @@ -29,13 +29,16 @@ #define ACPI_SIG_BDAT "BDAT" /* BIOS Data ACPI Table */ #define ACPI_SIG_CCEL "CCEL" /* CC Event Log Table */ #define ACPI_SIG_CDAT "CDAT" /* Coherent Device Attribute Table */ +#define ACPI_SIG_ERDT "ERDT" /* Enhanced Resource Director Technology */ #define ACPI_SIG_IORT "IORT" /* IO Remapping Table */ #define ACPI_SIG_IVRS "IVRS" /* I/O Virtualization Reporting Structure */ #define ACPI_SIG_LPIT "LPIT" /* Low Power Idle Table */ #define ACPI_SIG_MADT "APIC" /* Multiple APIC Description Table */ #define ACPI_SIG_MCFG "MCFG" /* PCI Memory Mapped Configuration table */ #define ACPI_SIG_MCHI "MCHI" /* Management Controller Host Interface table */ +#define ACPI_SIG_MPAM "MPAM" /* Memory System Resource Partitioning and Monitoring Table */ #define ACPI_SIG_MPST "MPST" /* Memory Power State Table */ +#define ACPI_SIG_MRRM "MRRM" /* Memory Range and Region Mapping table */ #define ACPI_SIG_MSDM "MSDM" /* Microsoft Data Management Table */ #define ACPI_SIG_NFIT "NFIT" /* NVDIMM Firmware Interface Table */ #define ACPI_SIG_NHLT "NHLT" /* Non HD Audio Link Table */ @@ -46,11 +49,15 @@ #define ACPI_SIG_PPTT "PPTT" /* Processor Properties Topology Table */ #define ACPI_SIG_PRMT "PRMT" /* Platform Runtime Mechanism Table */ #define ACPI_SIG_RASF "RASF" /* RAS Feature table */ +#define ACPI_SIG_RAS2 "RAS2" /* RAS2 Feature table */ #define ACPI_SIG_RGRT "RGRT" /* Regulatory Graphics Resource Table */ +#define ACPI_SIG_RHCT "RHCT" /* RISC-V Hart Capabilities Table */ +#define ACPI_SIG_RIMT "RIMT" /* RISC-V IO Mapping Table */ #define ACPI_SIG_SBST "SBST" /* Smart Battery Specification Table */ #define ACPI_SIG_SDEI "SDEI" /* Software Delegated Exception Interface Table */ #define ACPI_SIG_SDEV "SDEV" /* Secure Devices table */ #define ACPI_SIG_SVKL "SVKL" /* Storage Volume Key Location Table */ +#define ACPI_SIG_SWFT "SWFT" /* SoundWire File Table */ #define ACPI_SIG_TDEL "TDEL" /* TD Event Log Table */ /* @@ -75,14 +82,13 @@ * * AEST - Arm Error Source Table * - * Conforms to: ACPI for the Armv8 RAS Extensions 1.1 Platform Design Document - * September 2020. + * Conforms to: ACPI for the Armv8 RAS Extensions 1.1(Sep 2020) and + * 2.0(May 2023) Platform Design Document. * ******************************************************************************/ struct acpi_table_aest { struct acpi_table_header header; - void *node_array[]; }; /* Common Subtable header - one per Node Structure (Subtable) */ @@ -107,7 +113,9 @@ struct acpi_aest_hdr { #define ACPI_AEST_SMMU_ERROR_NODE 2 #define ACPI_AEST_VENDOR_ERROR_NODE 3 #define ACPI_AEST_GIC_ERROR_NODE 4 -#define ACPI_AEST_NODE_TYPE_RESERVED 5 /* 5 and above are reserved */ +#define ACPI_AEST_PCIE_ERROR_NODE 5 +#define ACPI_AEST_PROXY_ERROR_NODE 6 +#define ACPI_AEST_NODE_TYPE_RESERVED 7 /* 7 and above are reserved */ /* * AEST subtables (Error nodes) @@ -186,6 +194,12 @@ typedef struct acpi_aest_vendor { } acpi_aest_vendor; +struct acpi_aest_vendor_v2 { + char acpi_hid[8]; + u32 acpi_uid; + u8 vendor_specific_data[16]; +}; + /* 4: Gic Error */ typedef struct acpi_aest_gic { @@ -202,6 +216,18 @@ typedef struct acpi_aest_gic { #define ACPI_AEST_GIC_ITS 3 #define ACPI_AEST_GIC_RESERVED 4 /* 4 and above are reserved */ +/* 5: PCIe Error */ + +struct acpi_aest_pcie { + u32 iort_node_reference; +}; + +/* 6: Proxy Error */ + +struct acpi_aest_proxy { + u64 node_address; +}; + /* Node Interface Structure */ typedef struct acpi_aest_node_interface { @@ -217,11 +243,57 @@ typedef struct acpi_aest_node_interface { } acpi_aest_node_interface; +/* Node Interface Structure V2 */ + +struct acpi_aest_node_interface_header { + u8 type; + u8 group_format; + u8 reserved[2]; + u32 flags; + u64 address; + u32 error_record_index; + u32 error_record_count; +}; + +#define ACPI_AEST_NODE_GROUP_FORMAT_4K 0 +#define ACPI_AEST_NODE_GROUP_FORMAT_16K 1 +#define ACPI_AEST_NODE_GROUP_FORMAT_64K 2 + +struct acpi_aest_node_interface_common { + u32 error_node_device; + u32 processor_affinity; + u64 error_group_register_base; + u64 fault_inject_register_base; + u64 interrupt_config_register_base; +}; + +struct acpi_aest_node_interface_4k { + u64 error_record_implemented; + u64 error_status_reporting; + u64 addressing_mode; + struct acpi_aest_node_interface_common common; +}; + +struct acpi_aest_node_interface_16k { + u64 error_record_implemented[4]; + u64 error_status_reporting[4]; + u64 addressing_mode[4]; + struct acpi_aest_node_interface_common common; +}; + +struct acpi_aest_node_interface_64k { + u64 error_record_implemented[14]; + u64 error_status_reporting[14]; + u64 addressing_mode[14]; + struct acpi_aest_node_interface_common common; +}; + /* Values for Type field above */ -#define ACPI_AEST_NODE_SYSTEM_REGISTER 0 -#define ACPI_AEST_NODE_MEMORY_MAPPED 1 -#define ACPI_AEST_XFACE_RESERVED 2 /* 2 and above are reserved */ +#define ACPI_AEST_NODE_SYSTEM_REGISTER 0 +#define ACPI_AEST_NODE_MEMORY_MAPPED 1 +#define ACPI_AEST_NODE_SINGLE_RECORD_MEMORY_MAPPED 2 +#define ACPI_AEST_XFACE_RESERVED 3 /* 2 and above are reserved */ /* Node Interrupt Structure */ @@ -235,6 +307,16 @@ typedef struct acpi_aest_node_interrupt { } acpi_aest_node_interrupt; +/* Node Interrupt Structure V2 */ + +struct acpi_aest_node_interrupt_v2 { + u8 type; + u8 reserved[2]; + u8 flags; + u32 gsiv; + u8 reserved1[4]; +}; + /* Values for Type field above */ #define ACPI_AEST_NODE_FAULT_HANDLING 0 @@ -372,10 +454,199 @@ struct acpi_table_ccel { /******************************************************************************* * + * ERDT - Enhanced Resource Director Technology (ERDT) table + * + * Conforms to "Intel Resource Director Technology Architecture Specification" + * Version 1.1, January 2025 + * + ******************************************************************************/ + +struct acpi_table_erdt { + struct acpi_table_header header; /* Common ACPI table header */ + u32 max_clos; /* Maximum classes of service */ + u8 reserved[24]; + u8 erdt_substructures[]; +}; + +/* Values for subtable type in struct acpi_subtbl_hdr_16 */ + +enum acpi_erdt_type { + ACPI_ERDT_TYPE_RMDD = 0, + ACPI_ERDT_TYPE_CACD = 1, + ACPI_ERDT_TYPE_DACD = 2, + ACPI_ERDT_TYPE_CMRC = 3, + ACPI_ERDT_TYPE_MMRC = 4, + ACPI_ERDT_TYPE_MARC = 5, + ACPI_ERDT_TYPE_CARC = 6, + ACPI_ERDT_TYPE_CMRD = 7, + ACPI_ERDT_TYPE_IBRD = 8, + ACPI_ERDT_TYPE_IBAD = 9, + ACPI_ERDT_TYPE_CARD = 10, + ACPI_ERDT_TYPE_RESERVED = 11 /* 11 and above are reserved */ +}; + +/* + * ERDT Subtables, correspond to Type in struct acpi_subtbl_hdr_16 + */ + +/* 0: RMDD - Resource Management Domain Description */ + +struct acpi_erdt_rmdd { + struct acpi_subtbl_hdr_16 header; + u16 flags; + u16 IO_l3_slices; /* Number of slices in IO cache */ + u8 IO_l3_sets; /* Number of sets in IO cache */ + u8 IO_l3_ways; /* Number of ways in IO cache */ + u64 reserved; + u16 domain_id; /* Unique domain ID */ + u32 max_rmid; /* Maximun RMID supported */ + u64 creg_base; /* Control Register Base Address */ + u16 creg_size; /* Control Register Size (4K pages) */ + u8 rmdd_structs[]; +}; + +/* 1: CACD - CPU Agent Collection Description */ + +struct acpi_erdt_cacd { + struct acpi_subtbl_hdr_16 header; + u16 reserved; + u16 domain_id; /* Unique domain ID */ + u32 X2APICIDS[]; +}; + +/* 2: DACD - Device Agent Collection Description */ + +struct acpi_erdt_dacd { + struct acpi_subtbl_hdr_16 header; + u16 reserved; + u16 domain_id; /* Unique domain ID */ + u8 dev_paths[]; +}; + +struct acpi_erdt_dacd_dev_paths { + struct acpi_subtable_header header; + u16 segment; + u8 reserved; + u8 start_bus; + u8 path[]; +}; + +/* 3: CMRC - Cache Monitoring Registers for CPU Agents */ + +struct acpi_erdt_cmrc { + struct acpi_subtbl_hdr_16 header; + u32 reserved1; + u32 flags; + u8 index_fn; + u8 reserved2[11]; + u64 cmt_reg_base; + u32 cmt_reg_size; + u16 clump_size; + u16 clump_stride; + u64 up_scale; +}; + +/* 4: MMRC - Memory-bandwidth Monitoring Registers for CPU Agents */ + +struct acpi_erdt_mmrc { + struct acpi_subtbl_hdr_16 header; + u32 reserved1; + u32 flags; + u8 index_fn; + u8 reserved2[11]; + u64 reg_base; + u32 reg_size; + u8 counter_width; + u64 up_scale; + u8 reserved3[7]; + u32 corr_factor_list_len; + u32 corr_factor_list[]; +}; + +/* 5: MARC - Memory-bandwidth Allocation Registers for CPU Agents */ + +struct acpi_erdt_marc { + struct acpi_subtbl_hdr_16 header; + u16 reserved1; + u16 flags; + u8 index_fn; + u8 reserved2[7]; + u64 reg_base_opt; + u64 reg_base_min; + u64 reg_base_max; + u32 mba_reg_size; + u32 mba_ctrl_range; +}; + +/* 6: CARC - Cache Allocation Registers for CPU Agents */ + +struct acpi_erdt_carc { + struct acpi_subtbl_hdr_16 header; +}; + +/* 7: CMRD - Cache Monitoring Registers for Device Agents */ + +struct acpi_erdt_cmrd { + struct acpi_subtbl_hdr_16 header; + u32 reserved1; + u32 flags; + u8 index_fn; + u8 reserved2[11]; + u64 reg_base; + u32 reg_size; + u16 cmt_reg_off; + u16 cmt_clump_size; + u64 up_scale; +}; + +/* 8: IBRD - Cache Monitoring Registers for Device Agents */ + +struct acpi_erdt_ibrd { + struct acpi_subtbl_hdr_16 header; + u32 reserved1; + u32 flags; + u8 index_fn; + u8 reserved2[11]; + u64 reg_base; + u32 reg_size; + u16 total_bw_offset; + u16 Iomiss_bw_offset; + u16 total_bw_clump; + u16 Iomiss_bw_clump; + u8 reserved3[7]; + u8 counter_width; + u64 up_scale; + u32 corr_factor_list_len; + u32 corr_factor_list[]; +}; + +/* 9: IBAD - IO bandwidth Allocation Registers for device agents */ + +struct acpi_erdt_ibad { + struct acpi_subtbl_hdr_16 header; +}; + +/* 10: CARD - IO bandwidth Allocation Registers for Device Agents */ + +struct acpi_erdt_card { + struct acpi_subtbl_hdr_16 header; + u32 reserved1; + u32 flags; + u32 contention_mask; + u8 index_fn; + u8 reserved2[7]; + u64 reg_base; + u32 reg_size; + u16 cat_reg_offset; + u16 cat_reg_block_size; +}; + +/******************************************************************************* + * * IORT - IO Remapping Table * * Conforms to "IO Remapping Table System Software on ARM Platforms", - * Document number: ARM DEN 0049E.e, Sep 2022 + * Document number: ARM DEN 0049E.f, Apr 2024 * ******************************************************************************/ @@ -396,7 +667,7 @@ struct acpi_iort_node { u32 identifier; u32 mapping_count; u32 mapping_offset; - char node_data[1]; + char node_data[]; }; /* Values for subtable Type above */ @@ -446,20 +717,21 @@ struct acpi_iort_memory_access { #define ACPI_IORT_MF_COHERENCY (1) #define ACPI_IORT_MF_ATTRIBUTES (1<<1) +#define ACPI_IORT_MF_CANWBS (1<<2) /* * IORT node specific subtables */ struct acpi_iort_its_group { u32 its_count; - u32 identifiers[1]; /* GIC ITS identifier array */ + u32 identifiers[]; /* GIC ITS identifier array */ }; struct acpi_iort_named_component { u32 node_flags; u64 memory_properties; /* Memory access properties */ u8 memory_address_limit; /* Memory address size limit */ - char device_name[1]; /* Path of namespace object */ + char device_name[]; /* Path of namespace object */ }; /* Masks for Flags field above */ @@ -473,7 +745,7 @@ struct acpi_iort_root_complex { u32 pci_segment_number; u8 memory_address_limit; /* Memory address size limit */ u16 pasid_capabilities; /* PASID Capabilities */ - u8 reserved[1]; /* Reserved, must be zero */ + u8 reserved[]; /* Reserved, must be zero */ }; /* Masks for ats_attribute field above */ @@ -495,7 +767,7 @@ struct acpi_iort_smmu { u32 context_interrupt_offset; u32 pmu_interrupt_count; u32 pmu_interrupt_offset; - u64 interrupts[1]; /* Interrupt array */ + u64 interrupts[]; /* Interrupt array */ }; /* Values for Model field above */ @@ -891,7 +1163,11 @@ enum acpi_madt_type { ACPI_MADT_TYPE_MSI_PIC = 21, ACPI_MADT_TYPE_BIO_PIC = 22, ACPI_MADT_TYPE_LPC_PIC = 23, - ACPI_MADT_TYPE_RESERVED = 24, /* 24 to 0x7F are reserved */ + ACPI_MADT_TYPE_RINTC = 24, + ACPI_MADT_TYPE_IMSIC = 25, + ACPI_MADT_TYPE_APLIC = 26, + ACPI_MADT_TYPE_PLIC = 27, + ACPI_MADT_TYPE_RESERVED = 28, /* 28 to 0x7F are reserved */ ACPI_MADT_TYPE_OEM_RESERVED = 0x80 /* 0x80 to 0xFF are reserved for OEM use */ }; @@ -973,7 +1249,7 @@ struct acpi_madt_local_sapic { u8 reserved[3]; /* Reserved, must be zero */ u32 lapic_flags; u32 uid; /* Numeric UID - ACPI 3.0 */ - char uid_string[1]; /* String UID - ACPI 3.0 */ + char uid_string[]; /* String UID - ACPI 3.0 */ }; /* 8: Platform Interrupt Source */ @@ -1013,7 +1289,7 @@ struct acpi_madt_local_x2apic_nmi { u8 reserved[3]; /* reserved - must be zero */ }; -/* 11: Generic interrupt - GICC (ACPI 5.0 + ACPI 6.0 + ACPI 6.3 changes) */ +/* 11: Generic interrupt - GICC (ACPI 5.0 + ACPI 6.0 + ACPI 6.3 + ACPI 6.5 changes) */ struct acpi_madt_generic_interrupt { struct acpi_subtable_header header; @@ -1033,6 +1309,7 @@ struct acpi_madt_generic_interrupt { u8 efficiency_class; u8 reserved2[1]; u16 spe_interrupt; /* ACPI 6.3 */ + u16 trbe_interrupt; /* ACPI 6.5 */ }; /* Masks for Flags field above */ @@ -1040,6 +1317,8 @@ struct acpi_madt_generic_interrupt { /* ACPI_MADT_ENABLED (1) Processor is usable if set */ #define ACPI_MADT_PERFORMANCE_IRQ_MODE (1<<1) /* 01: Performance Interrupt Mode */ #define ACPI_MADT_VGIC_IRQ_MODE (1<<2) /* 02: VGIC Maintenance Interrupt mode */ +#define ACPI_MADT_GICC_ONLINE_CAPABLE (1<<3) /* 03: Processor is online capable */ +#define ACPI_MADT_GICC_NON_COHERENT (1<<4) /* 04: GIC redistributor is not coherent */ /* 12: Generic Distributor (ACPI 5.0 + ACPI 6.0 changes) */ @@ -1084,30 +1363,48 @@ struct acpi_madt_generic_msi_frame { struct acpi_madt_generic_redistributor { struct acpi_subtable_header header; - u16 reserved; /* reserved - must be zero */ + u8 flags; + u8 reserved; /* reserved - must be zero */ u64 base_address; u32 length; }; +#define ACPI_MADT_GICR_NON_COHERENT (1) + /* 15: Generic Translator (ACPI 6.0) */ struct acpi_madt_generic_translator { struct acpi_subtable_header header; - u16 reserved; /* reserved - must be zero */ + u8 flags; + u8 reserved; /* reserved - must be zero */ u32 translation_id; u64 base_address; u32 reserved2; }; +#define ACPI_MADT_ITS_NON_COHERENT (1) + /* 16: Multiprocessor wakeup (ACPI 6.4) */ struct acpi_madt_multiproc_wakeup { struct acpi_subtable_header header; - u16 mailbox_version; + u16 version; u32 reserved; /* reserved - must be zero */ - u64 base_address; + u64 mailbox_address; + u64 reset_vector; +}; + +/* Values for Version field above */ + +enum acpi_madt_multiproc_wakeup_version { + ACPI_MADT_MP_WAKEUP_VERSION_NONE = 0, + ACPI_MADT_MP_WAKEUP_VERSION_V1 = 1, + ACPI_MADT_MP_WAKEUP_VERSION_RESERVED = 2, /* 2 and greater are reserved */ }; +#define ACPI_MADT_MP_WAKEUP_SIZE_V0 16 +#define ACPI_MADT_MP_WAKEUP_SIZE_V1 24 + #define ACPI_MULTIPROC_WAKEUP_MB_OS_SIZE 2032 #define ACPI_MULTIPROC_WAKEUP_MB_FIRMWARE_SIZE 2048 @@ -1120,7 +1417,8 @@ struct acpi_madt_multiproc_wakeup_mailbox { u8 reserved_firmware[ACPI_MULTIPROC_WAKEUP_MB_FIRMWARE_SIZE]; /* reserved for firmware use */ }; -#define ACPI_MP_WAKE_COMMAND_WAKEUP 1 +#define ACPI_MP_WAKE_COMMAND_WAKEUP 1 +#define ACPI_MP_WAKE_COMMAND_TEST 2 /* 17: CPU Core Interrupt Controller (ACPI 6.5) */ @@ -1250,10 +1548,73 @@ enum acpi_madt_lpc_pic_version { ACPI_MADT_LPC_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */ }; +/* 24: RISC-V INTC */ +struct acpi_madt_rintc { + struct acpi_subtable_header header; + u8 version; + u8 reserved; + u32 flags; + u64 hart_id; + u32 uid; /* ACPI processor UID */ + u32 ext_intc_id; /* External INTC Id */ + u64 imsic_addr; /* IMSIC base address */ + u32 imsic_size; /* IMSIC size */ +}; + +/* Values for RISC-V INTC Version field above */ + +enum acpi_madt_rintc_version { + ACPI_MADT_RINTC_VERSION_NONE = 0, + ACPI_MADT_RINTC_VERSION_V1 = 1, + ACPI_MADT_RINTC_VERSION_RESERVED = 2 /* 2 and greater are reserved */ +}; + +/* 25: RISC-V IMSIC */ +struct acpi_madt_imsic { + struct acpi_subtable_header header; + u8 version; + u8 reserved; + u32 flags; + u16 num_ids; + u16 num_guest_ids; + u8 guest_index_bits; + u8 hart_index_bits; + u8 group_index_bits; + u8 group_index_shift; +}; + +/* 26: RISC-V APLIC */ +struct acpi_madt_aplic { + struct acpi_subtable_header header; + u8 version; + u8 id; + u32 flags; + u8 hw_id[8]; + u16 num_idcs; + u16 num_sources; + u32 gsi_base; + u64 base_addr; + u32 size; +}; + +/* 27: RISC-V PLIC */ +struct acpi_madt_plic { + struct acpi_subtable_header header; + u8 version; + u8 id; + u8 hw_id[8]; + u16 num_irqs; + u16 max_prio; + u32 flags; + u32 size; + u64 base_addr; + u32 gsi_base; +}; + /* 80: OEM data */ struct acpi_madt_oem_data { - u8 oem_data[0]; + ACPI_FLEX_ARRAY(u8, oem_data); }; /* @@ -1334,6 +1695,121 @@ struct acpi_table_mchi { /******************************************************************************* * + * MPAM - Memory System Resource Partitioning and Monitoring + * + * Conforms to "ACPI for Memory System Resource Partitioning and Monitoring 2.0" + * Document number: ARM DEN 0065, December, 2022. + * + ******************************************************************************/ + +/* MPAM RIS locator types. Table 11, Location types */ +enum acpi_mpam_locator_type { + ACPI_MPAM_LOCATION_TYPE_PROCESSOR_CACHE = 0, + ACPI_MPAM_LOCATION_TYPE_MEMORY = 1, + ACPI_MPAM_LOCATION_TYPE_SMMU = 2, + ACPI_MPAM_LOCATION_TYPE_MEMORY_CACHE = 3, + ACPI_MPAM_LOCATION_TYPE_ACPI_DEVICE = 4, + ACPI_MPAM_LOCATION_TYPE_INTERCONNECT = 5, + ACPI_MPAM_LOCATION_TYPE_UNKNOWN = 0xFF +}; + +/* MPAM Functional dependency descriptor. Table 10 */ +struct acpi_mpam_func_deps { + u32 producer; + u32 reserved; +}; + +/* MPAM Processor cache locator descriptor. Table 13 */ +struct acpi_mpam_resource_cache_locator { + u64 cache_reference; + u32 reserved; +}; + +/* MPAM Memory locator descriptor. Table 14 */ +struct acpi_mpam_resource_memory_locator { + u64 proximity_domain; + u32 reserved; +}; + +/* MPAM SMMU locator descriptor. Table 15 */ +struct acpi_mpam_resource_smmu_locator { + u64 smmu_interface; + u32 reserved; +}; + +/* MPAM Memory-side cache locator descriptor. Table 16 */ +struct acpi_mpam_resource_memcache_locator { + u8 reserved[7]; + u8 level; + u32 reference; +}; + +/* MPAM ACPI device locator descriptor. Table 17 */ +struct acpi_mpam_resource_acpi_locator { + u64 acpi_hw_id; + u32 acpi_unique_id; +}; + +/* MPAM Interconnect locator descriptor. Table 18 */ +struct acpi_mpam_resource_interconnect_locator { + u64 inter_connect_desc_tbl_off; + u32 reserved; +}; + +/* MPAM Locator structure. Table 12 */ +struct acpi_mpam_resource_generic_locator { + u64 descriptor1; + u32 descriptor2; +}; + +union acpi_mpam_resource_locator { + struct acpi_mpam_resource_cache_locator cache_locator; + struct acpi_mpam_resource_memory_locator memory_locator; + struct acpi_mpam_resource_smmu_locator smmu_locator; + struct acpi_mpam_resource_memcache_locator mem_cache_locator; + struct acpi_mpam_resource_acpi_locator acpi_locator; + struct acpi_mpam_resource_interconnect_locator interconnect_ifc_locator; + struct acpi_mpam_resource_generic_locator generic_locator; +}; + +/* Memory System Component Resource Node Structure Table 9 */ +struct acpi_mpam_resource_node { + u32 identifier; + u8 ris_index; + u16 reserved1; + u8 locator_type; + union acpi_mpam_resource_locator locator; + u32 num_functional_deps; +}; + +/* Memory System Component (MSC) Node Structure. Table 4 */ +struct acpi_mpam_msc_node { + u16 length; + u8 interface_type; + u8 reserved; + u32 identifier; + u64 base_address; + u32 mmio_size; + u32 overflow_interrupt; + u32 overflow_interrupt_flags; + u32 reserved1; + u32 overflow_interrupt_affinity; + u32 error_interrupt; + u32 error_interrupt_flags; + u32 reserved2; + u32 error_interrupt_affinity; + u32 max_nrdy_usec; + u64 hardware_id_linked_device; + u32 instance_id_linked_device; + u32 num_resource_nodes; +}; + +struct acpi_table_mpam { + struct acpi_table_header header; /* Common ACPI table header */ +}; + +/******************************************************************************* + * * MPST - Memory Power State Table (ACPI 5.0) * Version 1 * @@ -1455,6 +1931,47 @@ struct acpi_msct_proximity { /******************************************************************************* * + * MRRM - Memory Range and Region Mapping (MRRM) table + * Conforms to "Intel Resource Director Technology Architecture Specification" + * Version 1.1, January 2025 + * + ******************************************************************************/ + +struct acpi_table_mrrm { + struct acpi_table_header header; /* Common ACPI table header */ + u8 max_mem_region; /* Max Memory Regions supported */ + u8 flags; /* Region assignment type */ + u8 reserved[26]; + u8 memory_range_entry[]; +}; + +/* Flags */ +#define ACPI_MRRM_FLAGS_REGION_ASSIGNMENT_OS (1<<0) + +/******************************************************************************* + * + * Memory Range entry - Memory Range entry in MRRM table + * + ******************************************************************************/ + +struct acpi_mrrm_mem_range_entry { + struct acpi_subtbl_hdr_16 header; + u32 reserved0; /* Reserved */ + u64 addr_base; /* Base addr of the mem range */ + u64 addr_len; /* Length of the mem range */ + u16 region_id_flags; /* Valid local or remote Region-ID */ + u8 local_region_id; /* Platform-assigned static local Region-ID */ + u8 remote_region_id; /* Platform-assigned static remote Region-ID */ + u32 reserved1; /* Reserved */ + /* Region-ID Programming Registers[] */ +}; + +/* Values for region_id_flags above */ +#define ACPI_MRRM_VALID_REGION_ID_FLAGS_LOCAL (1<<0) +#define ACPI_MRRM_VALID_REGION_ID_FLAGS_REMOTE (1<<1) + +/******************************************************************************* + * * MSDM - Microsoft Data Management table * * Conforms to "Microsoft Software Licensing Tables (SLIC and MSDM)", @@ -1564,7 +2081,7 @@ struct acpi_nfit_interleave { u16 reserved; /* Reserved, must be zero */ u32 line_count; u32 line_size; - u32 line_offset[1]; /* Variable length */ + u32 line_offset[]; /* Variable length */ }; /* 3: SMBIOS Management Information Structure */ @@ -1572,7 +2089,7 @@ struct acpi_nfit_interleave { struct acpi_nfit_smbios { struct acpi_nfit_header header; u32 reserved; /* Reserved, must be zero */ - u8 data[1]; /* Variable length */ + u8 data[]; /* Variable length */ }; /* 4: NVDIMM Control Region Structure */ @@ -1629,7 +2146,7 @@ struct acpi_nfit_flush_address { u32 device_handle; u16 hint_count; u8 reserved[6]; /* Reserved, must be zero */ - u64 hint_address[1]; /* Variable length */ + u64 hint_address[]; /* Variable length */ }; /* 7: Platform Capabilities Structure */ @@ -1697,22 +2214,22 @@ struct nfit_device_handle { /******************************************************************************* * - * NHLT - Non HD Audio Link Table - * - * Conforms to: Intel Smart Sound Technology NHLT Specification - * Version 0.8.1, January 2020. + * NHLT - Non HDAudio Link Table + * Version 1 * ******************************************************************************/ -/* Main table */ - struct acpi_table_nhlt { struct acpi_table_header header; /* Common ACPI table header */ - u8 endpoint_count; + u8 endpoints_count; + /* + * struct acpi_nhlt_endpoint endpoints[]; + * struct acpi_nhlt_config oed_config; + */ }; struct acpi_nhlt_endpoint { - u32 descriptor_length; + u32 length; u8 link_type; u8 instance_id; u16 vendor_id; @@ -1722,84 +2239,135 @@ struct acpi_nhlt_endpoint { u8 device_type; u8 direction; u8 virtual_bus_id; + /* + * struct acpi_nhlt_config device_config; + * struct acpi_nhlt_formats_config formats_config; + * struct acpi_nhlt_devices_info devices_info; + */ }; -/* Types for link_type field above */ - -#define ACPI_NHLT_RESERVED_HD_AUDIO 0 -#define ACPI_NHLT_RESERVED_DSP 1 -#define ACPI_NHLT_PDM 2 -#define ACPI_NHLT_SSP 3 -#define ACPI_NHLT_RESERVED_SLIMBUS 4 -#define ACPI_NHLT_RESERVED_SOUNDWIRE 5 -#define ACPI_NHLT_TYPE_RESERVED 6 /* 6 and above are reserved */ - -/* All other values above are reserved */ +/* + * Values for link_type field above + * + * Only types PDM and SSP are used + */ +#define ACPI_NHLT_LINKTYPE_HDA 0 +#define ACPI_NHLT_LINKTYPE_DSP 1 +#define ACPI_NHLT_LINKTYPE_PDM 2 +#define ACPI_NHLT_LINKTYPE_SSP 3 +#define ACPI_NHLT_LINKTYPE_SLIMBUS 4 +#define ACPI_NHLT_LINKTYPE_SDW 5 +#define ACPI_NHLT_LINKTYPE_UAOL 6 /* Values for device_id field above */ -#define ACPI_NHLT_PDM_DMIC 0xAE20 -#define ACPI_NHLT_BT_SIDEBAND 0xAE30 -#define ACPI_NHLT_I2S_TDM_CODECS 0xAE23 +#define ACPI_NHLT_DEVICEID_DMIC 0xAE20 +#define ACPI_NHLT_DEVICEID_BT 0xAE30 +#define ACPI_NHLT_DEVICEID_I2S 0xAE34 /* Values for device_type field above */ -/* SSP Link */ - -#define ACPI_NHLT_LINK_BT_SIDEBAND 0 -#define ACPI_NHLT_LINK_FM 1 -#define ACPI_NHLT_LINK_MODEM 2 -/* 3 is reserved */ -#define ACPI_NHLT_LINK_SSP_ANALOG_CODEC 4 - -/* PDM Link */ - -#define ACPI_NHLT_PDM_ON_CAVS_1P8 0 -#define ACPI_NHLT_PDM_ON_CAVS_1P5 1 +/* + * Device types unique to endpoint of link_type=PDM + * + * Type PDM used for all SKL+ platforms + */ +#define ACPI_NHLT_DEVICETYPE_PDM 0 +#define ACPI_NHLT_DEVICETYPE_PDM_SKL 1 +/* Device types unique to endpoint of link_type=SSP */ +#define ACPI_NHLT_DEVICETYPE_BT 0 +#define ACPI_NHLT_DEVICETYPE_FM 1 +#define ACPI_NHLT_DEVICETYPE_MODEM 2 +#define ACPI_NHLT_DEVICETYPE_CODEC 4 /* Values for Direction field above */ -#define ACPI_NHLT_DIR_RENDER 0 -#define ACPI_NHLT_DIR_CAPTURE 1 -#define ACPI_NHLT_DIR_RENDER_LOOPBACK 2 -#define ACPI_NHLT_DIR_RENDER_FEEDBACK 3 -#define ACPI_NHLT_DIR_RESERVED 4 /* 4 and above are reserved */ +#define ACPI_NHLT_DIR_RENDER 0 +#define ACPI_NHLT_DIR_CAPTURE 1 -struct acpi_nhlt_device_specific_config { +struct acpi_nhlt_config { u32 capabilities_size; + u8 capabilities[]; +}; + +struct acpi_nhlt_gendevice_config { u8 virtual_slot; u8 config_type; }; -struct acpi_nhlt_device_specific_config_a { - u32 capabilities_size; +/* Values for config_type field above */ + +#define ACPI_NHLT_CONFIGTYPE_GENERIC 0 +#define ACPI_NHLT_CONFIGTYPE_MICARRAY 1 + +struct acpi_nhlt_micdevice_config { u8 virtual_slot; u8 config_type; u8 array_type; }; -/* Values for Config Type above */ +/* Values for array_type field above */ -#define ACPI_NHLT_CONFIG_TYPE_GENERIC 0x00 -#define ACPI_NHLT_CONFIG_TYPE_MIC_ARRAY 0x01 -#define ACPI_NHLT_CONFIG_TYPE_RENDER_FEEDBACK 0x03 -#define ACPI_NHLT_CONFIG_TYPE_RESERVED 0x04 /* 4 and above are reserved */ +#define ACPI_NHLT_ARRAYTYPE_LINEAR2_SMALL 0xA +#define ACPI_NHLT_ARRAYTYPE_LINEAR2_BIG 0xB +#define ACPI_NHLT_ARRAYTYPE_LINEAR4_GEO1 0xC +#define ACPI_NHLT_ARRAYTYPE_PLANAR4_LSHAPED 0xD +#define ACPI_NHLT_ARRAYTYPE_LINEAR4_GEO2 0xE +#define ACPI_NHLT_ARRAYTYPE_VENDOR 0xF -struct acpi_nhlt_device_specific_config_b { - u32 capabilities_size; +struct acpi_nhlt_vendor_mic_config { + u8 type; + u8 panel; + u16 speaker_position_distance; /* mm */ + u16 horizontal_offset; /* mm */ + u16 vertical_offset; /* mm */ + u8 frequency_low_band; /* 5*Hz */ + u8 frequency_high_band; /* 500*Hz */ + u16 direction_angle; /* -180 - +180 */ + u16 elevation_angle; /* -180 - +180 */ + u16 work_vertical_angle_begin; /* -180 - +180 with 2 deg step */ + u16 work_vertical_angle_end; /* -180 - +180 with 2 deg step */ + u16 work_horizontal_angle_begin; /* -180 - +180 with 2 deg step */ + u16 work_horizontal_angle_end; /* -180 - +180 with 2 deg step */ }; -struct acpi_nhlt_device_specific_config_c { - u32 capabilities_size; +/* Values for Type field above */ + +#define ACPI_NHLT_MICTYPE_OMNIDIRECTIONAL 0 +#define ACPI_NHLT_MICTYPE_SUBCARDIOID 1 +#define ACPI_NHLT_MICTYPE_CARDIOID 2 +#define ACPI_NHLT_MICTYPE_SUPERCARDIOID 3 +#define ACPI_NHLT_MICTYPE_HYPERCARDIOID 4 +#define ACPI_NHLT_MICTYPE_8SHAPED 5 +#define ACPI_NHLT_MICTYPE_RESERVED 6 +#define ACPI_NHLT_MICTYPE_VENDORDEFINED 7 + +/* Values for Panel field above */ + +#define ACPI_NHLT_MICLOCATION_TOP 0 +#define ACPI_NHLT_MICLOCATION_BOTTOM 1 +#define ACPI_NHLT_MICLOCATION_LEFT 2 +#define ACPI_NHLT_MICLOCATION_RIGHT 3 +#define ACPI_NHLT_MICLOCATION_FRONT 4 +#define ACPI_NHLT_MICLOCATION_REAR 5 + +struct acpi_nhlt_vendor_micdevice_config { u8 virtual_slot; + u8 config_type; + u8 array_type; + u8 mics_count; + struct acpi_nhlt_vendor_mic_config mics[]; }; -struct acpi_nhlt_render_device_specific_config { - u32 capabilities_size; +union acpi_nhlt_device_config { u8 virtual_slot; + struct acpi_nhlt_gendevice_config gen; + struct acpi_nhlt_micdevice_config mic; + struct acpi_nhlt_vendor_micdevice_config vendor_mic; }; -struct acpi_nhlt_wave_extensible { +/* Inherited from Microsoft's WAVEFORMATEXTENSIBLE. */ +struct acpi_nhlt_wave_formatext { u16 format_tag; u16 channel_count; u32 samples_per_sec; @@ -1809,144 +2377,28 @@ struct acpi_nhlt_wave_extensible { u16 extra_format_size; u16 valid_bits_per_sample; u32 channel_mask; - u8 sub_format_guid[16]; -}; - -/* Values for channel_mask above */ - -#define ACPI_NHLT_SPKR_FRONT_LEFT 0x1 -#define ACPI_NHLT_SPKR_FRONT_RIGHT 0x2 -#define ACPI_NHLT_SPKR_FRONT_CENTER 0x4 -#define ACPI_NHLT_SPKR_LOW_FREQ 0x8 -#define ACPI_NHLT_SPKR_BACK_LEFT 0x10 -#define ACPI_NHLT_SPKR_BACK_RIGHT 0x20 -#define ACPI_NHLT_SPKR_FRONT_LEFT_OF_CENTER 0x40 -#define ACPI_NHLT_SPKR_FRONT_RIGHT_OF_CENTER 0x80 -#define ACPI_NHLT_SPKR_BACK_CENTER 0x100 -#define ACPI_NHLT_SPKR_SIDE_LEFT 0x200 -#define ACPI_NHLT_SPKR_SIDE_RIGHT 0x400 -#define ACPI_NHLT_SPKR_TOP_CENTER 0x800 -#define ACPI_NHLT_SPKR_TOP_FRONT_LEFT 0x1000 -#define ACPI_NHLT_SPKR_TOP_FRONT_CENTER 0x2000 -#define ACPI_NHLT_SPKR_TOP_FRONT_RIGHT 0x4000 -#define ACPI_NHLT_SPKR_TOP_BACK_LEFT 0x8000 -#define ACPI_NHLT_SPKR_TOP_BACK_CENTER 0x10000 -#define ACPI_NHLT_SPKR_TOP_BACK_RIGHT 0x20000 + u8 subformat[16]; +}; struct acpi_nhlt_format_config { - struct acpi_nhlt_wave_extensible format; - u32 capability_size; - u8 capabilities[]; + struct acpi_nhlt_wave_formatext format; + struct acpi_nhlt_config config; }; struct acpi_nhlt_formats_config { u8 formats_count; + struct acpi_nhlt_format_config formats[]; }; -struct acpi_nhlt_device_specific_hdr { - u8 virtual_slot; - u8 config_type; -}; - -/* Types for config_type above */ - -#define ACPI_NHLT_GENERIC 0 -#define ACPI_NHLT_MIC 1 -#define ACPI_NHLT_RENDER 3 - -struct acpi_nhlt_mic_device_specific_config { - struct acpi_nhlt_device_specific_hdr device_config; - u8 array_type_ext; -}; - -/* Values for array_type_ext above */ - -#define ACPI_NHLT_ARRAY_TYPE_RESERVED 0x09 /* 9 and below are reserved */ -#define ACPI_NHLT_SMALL_LINEAR_2ELEMENT 0x0A -#define ACPI_NHLT_BIG_LINEAR_2ELEMENT 0x0B -#define ACPI_NHLT_FIRST_GEOMETRY_LINEAR_4ELEMENT 0x0C -#define ACPI_NHLT_PLANAR_LSHAPED_4ELEMENT 0x0D -#define ACPI_NHLT_SECOND_GEOMETRY_LINEAR_4ELEMENT 0x0E -#define ACPI_NHLT_VENDOR_DEFINED 0x0F -#define ACPI_NHLT_ARRAY_TYPE_MASK 0x0F -#define ACPI_NHLT_ARRAY_TYPE_EXT_MASK 0x10 - -#define ACPI_NHLT_NO_EXTENSION 0x0 -#define ACPI_NHLT_MIC_SNR_SENSITIVITY_EXT (1<<4) - -struct acpi_nhlt_vendor_mic_count { - u8 microphone_count; -}; - -struct acpi_nhlt_vendor_mic_config { - u8 type; - u8 panel; - u16 speaker_position_distance; /* mm */ - u16 horizontal_offset; /* mm */ - u16 vertical_offset; /* mm */ - u8 frequency_low_band; /* 5*Hz */ - u8 frequency_high_band; /* 500*Hz */ - u16 direction_angle; /* -180 - + 180 */ - u16 elevation_angle; /* -180 - + 180 */ - u16 work_vertical_angle_begin; /* -180 - + 180 with 2 deg step */ - u16 work_vertical_angle_end; /* -180 - + 180 with 2 deg step */ - u16 work_horizontal_angle_begin; /* -180 - + 180 with 2 deg step */ - u16 work_horizontal_angle_end; /* -180 - + 180 with 2 deg step */ -}; - -/* Values for Type field above */ - -#define ACPI_NHLT_MIC_OMNIDIRECTIONAL 0 -#define ACPI_NHLT_MIC_SUBCARDIOID 1 -#define ACPI_NHLT_MIC_CARDIOID 2 -#define ACPI_NHLT_MIC_SUPER_CARDIOID 3 -#define ACPI_NHLT_MIC_HYPER_CARDIOID 4 -#define ACPI_NHLT_MIC_8_SHAPED 5 -#define ACPI_NHLT_MIC_RESERVED6 6 /* 6 is reserved */ -#define ACPI_NHLT_MIC_VENDOR_DEFINED 7 -#define ACPI_NHLT_MIC_RESERVED 8 /* 8 and above are reserved */ - -/* Values for Panel field above */ - -#define ACPI_NHLT_MIC_POSITION_TOP 0 -#define ACPI_NHLT_MIC_POSITION_BOTTOM 1 -#define ACPI_NHLT_MIC_POSITION_LEFT 2 -#define ACPI_NHLT_MIC_POSITION_RIGHT 3 -#define ACPI_NHLT_MIC_POSITION_FRONT 4 -#define ACPI_NHLT_MIC_POSITION_BACK 5 -#define ACPI_NHLT_MIC_POSITION_RESERVED 6 /* 6 and above are reserved */ - -struct acpi_nhlt_vendor_mic_device_specific_config { - struct acpi_nhlt_mic_device_specific_config mic_array_device_config; - u8 number_of_microphones; - struct acpi_nhlt_vendor_mic_config mic_config[]; /* Indexed by number_of_microphones */ -}; - -/* Microphone SNR and Sensitivity extension */ - -struct acpi_nhlt_mic_snr_sensitivity_extension { - u32 SNR; - u32 sensitivity; -}; - -/* Render device with feedback */ - -struct acpi_nhlt_render_feedback_device_specific_config { - u8 feedback_virtual_slot; /* Render slot in case of capture */ - u16 feedback_channels; /* Informative only */ - u16 feedback_valid_bits_per_sample; -}; - -/* Non documented structures */ - -struct acpi_nhlt_device_info_count { - u8 structure_count; +struct acpi_nhlt_device_info { + u8 id[16]; + u8 instance_id; + u8 port_id; }; -struct acpi_nhlt_device_info { - u8 device_id[16]; - u8 device_instance_id; - u8 device_port_id; +struct acpi_nhlt_devices_info { + u8 devices_count; + struct acpi_nhlt_device_info devices[]; }; /******************************************************************************* @@ -2561,6 +3013,134 @@ enum acpi_rasf_status { /******************************************************************************* * + * RAS2 - RAS2 Feature Table (ACPI 6.5) + * Version 1 + * + * + ******************************************************************************/ + +struct acpi_table_ras2 { + struct acpi_table_header header; /* Common ACPI table header */ + u16 reserved; + u16 num_pcc_descs; +}; + +/* RAS2 Platform Communication Channel Descriptor */ + +struct acpi_ras2_pcc_desc { + u8 channel_id; + u16 reserved; + u8 feature_type; + u32 instance; +}; + +/* RAS2 Platform Communication Channel Shared Memory Region */ + +struct acpi_ras2_shmem { + u32 signature; + u16 command; + u16 status; + u16 version; + u8 features[16]; + u8 set_caps[16]; + u16 num_param_blks; + u32 set_caps_status; +}; + +/* RAS2 Parameter Block Structure for PATROL_SCRUB */ + +struct acpi_ras2_parameter_block { + u16 type; + u16 version; + u16 length; +}; + +/* RAS2 Parameter Block Structure for PATROL_SCRUB */ + +struct acpi_ras2_patrol_scrub_param { + struct acpi_ras2_parameter_block header; + u16 command; + u64 req_addr_range[2]; + u64 actl_addr_range[2]; + u32 flags; + u32 scrub_params_out; + u32 scrub_params_in; +}; + +/* Masks for Flags field above */ + +#define ACPI_RAS2_SCRUBBER_RUNNING 1 + +/* RAS2 Parameter Block Structure for LA2PA_TRANSLATION */ + +struct acpi_ras2_la2pa_translation_parameter { + struct acpi_ras2_parameter_block header; + u16 addr_translation_command; + u64 sub_inst_id; + u64 logical_address; + u64 physical_address; + u32 status; +}; + +/* Channel Commands */ + +enum acpi_ras2_commands { + ACPI_RAS2_EXECUTE_RAS2_COMMAND = 1 +}; + +/* Platform RAS2 Features */ + +enum acpi_ras2_features { + ACPI_RAS2_PATROL_SCRUB_SUPPORTED = 0, + ACPI_RAS2_LA2PA_TRANSLATION = 1 +}; + +/* RAS2 Patrol Scrub Commands */ + +enum acpi_ras2_patrol_scrub_commands { + ACPI_RAS2_GET_PATROL_PARAMETERS = 1, + ACPI_RAS2_START_PATROL_SCRUBBER = 2, + ACPI_RAS2_STOP_PATROL_SCRUBBER = 3 +}; + +/* RAS2 LA2PA Translation Commands */ + +enum acpi_ras2_la2_pa_translation_commands { + ACPI_RAS2_GET_LA2PA_TRANSLATION = 1, +}; + +/* RAS2 LA2PA Translation Status values */ + +enum acpi_ras2_la2_pa_translation_status { + ACPI_RAS2_LA2PA_TRANSLATION_SUCCESS = 0, + ACPI_RAS2_LA2PA_TRANSLATION_FAIL = 1, +}; + +/* Channel Command flags */ + +#define ACPI_RAS2_GENERATE_SCI (1<<15) + +/* Status values */ + +enum acpi_ras2_status { + ACPI_RAS2_SUCCESS = 0, + ACPI_RAS2_NOT_VALID = 1, + ACPI_RAS2_NOT_SUPPORTED = 2, + ACPI_RAS2_BUSY = 3, + ACPI_RAS2_FAILED = 4, + ACPI_RAS2_ABORTED = 5, + ACPI_RAS2_INVALID_DATA = 6 +}; + +/* Status flags */ + +#define ACPI_RAS2_COMMAND_COMPLETE (1) +#define ACPI_RAS2_SCI_DOORBELL (1<<1) +#define ACPI_RAS2_ERROR (1<<2) +#define ACPI_RAS2_STATUS (0x1F<<3) + +/******************************************************************************* + * * RGRT - Regulatory Graphics Resource Table * Version 1 * @@ -2587,6 +3167,159 @@ enum acpi_rgrt_image_type { /******************************************************************************* * + * RHCT - RISC-V Hart Capabilities Table + * Version 1 + * + ******************************************************************************/ + +struct acpi_table_rhct { + struct acpi_table_header header; /* Common ACPI table header */ + u32 flags; /* RHCT flags */ + u64 time_base_freq; + u32 node_count; + u32 node_offset; +}; + +/* RHCT Flags */ + +#define ACPI_RHCT_TIMER_CANNOT_WAKEUP_CPU (1) +/* + * RHCT subtables + */ +struct acpi_rhct_node_header { + u16 type; + u16 length; + u16 revision; +}; + +/* Values for RHCT subtable Type above */ + +enum acpi_rhct_node_type { + ACPI_RHCT_NODE_TYPE_ISA_STRING = 0x0000, + ACPI_RHCT_NODE_TYPE_CMO = 0x0001, + ACPI_RHCT_NODE_TYPE_MMU = 0x0002, + ACPI_RHCT_NODE_TYPE_RESERVED = 0x0003, + ACPI_RHCT_NODE_TYPE_HART_INFO = 0xFFFF, +}; + +/* + * RHCT node specific subtables + */ + +/* ISA string node structure */ +struct acpi_rhct_isa_string { + u16 isa_length; + char isa[]; +}; + +struct acpi_rhct_cmo_node { + u8 reserved; /* Must be zero */ + u8 cbom_size; /* CBOM size in powerof 2 */ + u8 cbop_size; /* CBOP size in powerof 2 */ + u8 cboz_size; /* CBOZ size in powerof 2 */ +}; + +struct acpi_rhct_mmu_node { + u8 reserved; /* Must be zero */ + u8 mmu_type; /* Virtual Address Scheme */ +}; + +enum acpi_rhct_mmu_type { + ACPI_RHCT_MMU_TYPE_SV39 = 0, + ACPI_RHCT_MMU_TYPE_SV48 = 1, + ACPI_RHCT_MMU_TYPE_SV57 = 2 +}; + +/* Hart Info node structure */ +struct acpi_rhct_hart_info { + u16 num_offsets; + u32 uid; /* ACPI processor UID */ +}; + +/******************************************************************************* + * + * RIMT - RISC-V IO Remapping Table + * + * https://github.com/riscv-non-isa/riscv-acpi-rimt + * + ******************************************************************************/ + +struct acpi_table_rimt { + struct acpi_table_header header; /* Common ACPI table header */ + u32 num_nodes; /* Number of RIMT Nodes */ + u32 node_offset; /* Offset to RIMT Node Array */ + u32 reserved; +}; + +struct acpi_rimt_node { + u8 type; + u8 revision; + u16 length; + u16 reserved; + u16 id; + char node_data[]; +}; + +enum acpi_rimt_node_type { + ACPI_RIMT_NODE_TYPE_IOMMU = 0x0, + ACPI_RIMT_NODE_TYPE_PCIE_ROOT_COMPLEX = 0x1, + ACPI_RIMT_NODE_TYPE_PLAT_DEVICE = 0x2, +}; + +struct acpi_rimt_iommu { + u8 hardware_id[8]; /* Hardware ID */ + u64 base_address; /* Base Address */ + u32 flags; /* Flags */ + u32 proximity_domain; /* Proximity Domain */ + u16 pcie_segment_number; /* PCIe Segment number */ + u16 pcie_bdf; /* PCIe B/D/F */ + u16 num_interrupt_wires; /* Number of interrupt wires */ + u16 interrupt_wire_offset; /* Interrupt wire array offset */ + u64 interrupt_wire[]; /* Interrupt wire array */ +}; + +/* IOMMU Node Flags */ +#define ACPI_RIMT_IOMMU_FLAGS_PCIE (1) +#define ACPI_RIMT_IOMMU_FLAGS_PXM_VALID (1 << 1) + +/* Interrupt Wire Structure */ +struct acpi_rimt_iommu_wire_gsi { + u32 irq_num; /* Interrupt Number */ + u32 flags; /* Flags */ +}; + +/* Interrupt Wire Flags */ +#define ACPI_RIMT_GSI_LEVEL_TRIGGERRED (1) +#define ACPI_RIMT_GSI_ACTIVE_HIGH (1 << 1) + +struct acpi_rimt_id_mapping { + u32 source_id_base; /* Source ID Base */ + u32 num_ids; /* Number of IDs */ + u32 dest_id_base; /* Destination Device ID Base */ + u32 dest_offset; /* Destination IOMMU Offset */ + u32 flags; /* Flags */ +}; + +struct acpi_rimt_pcie_rc { + u32 flags; /* Flags */ + u16 reserved; /* Reserved */ + u16 pcie_segment_number; /* PCIe Segment number */ + u16 id_mapping_offset; /* ID mapping array offset */ + u16 num_id_mappings; /* Number of ID mappings */ +}; + +/* PCIe Root Complex Node Flags */ +#define ACPI_RIMT_PCIE_ATS_SUPPORTED (1) +#define ACPI_RIMT_PCIE_PRI_SUPPORTED (1 << 1) + +struct acpi_rimt_platform_device { + u16 id_mapping_offset; /* ID Mapping array offset */ + u16 num_id_mappings; /* Number of ID mappings */ + char device_name[]; /* Device Object Name */ +}; + +/******************************************************************************* + * * SBST - Smart Battery Specification Table * Version 1 * @@ -2747,6 +3480,26 @@ enum acpi_svkl_format { }; /******************************************************************************* + * SWFT - SoundWire File Table + * + * Conforms to "Discovery and Configuration (DisCo) Specification for SoundWire" + * Version 2.1, 2 October 2023 + * + ******************************************************************************/ +struct acpi_sw_file { + u16 vendor_id; + u32 file_id; + u16 file_version; + u32 file_length; + u8 data[]; +}; + +struct acpi_table_swft { + struct acpi_table_header header; + struct acpi_sw_file files[]; +}; + +/******************************************************************************* * * TDEL - TD-Event Log * From: "Guest-Host-Communication Interface (GHCI) for Intel |