diff options
Diffstat (limited to 'include/dt-bindings/clock/exynos7885.h')
| -rw-r--r-- | include/dt-bindings/clock/exynos7885.h | 36 |
1 files changed, 21 insertions, 15 deletions
diff --git a/include/dt-bindings/clock/exynos7885.h b/include/dt-bindings/clock/exynos7885.h index 8256e7430b63..cfede84b46b9 100644 --- a/include/dt-bindings/clock/exynos7885.h +++ b/include/dt-bindings/clock/exynos7885.h @@ -69,7 +69,8 @@ #define CLK_GOUT_FSYS_MMC_EMBD 58 #define CLK_GOUT_FSYS_MMC_SDIO 59 #define CLK_GOUT_FSYS_USB30DRD 60 -#define TOP_NR_CLK 61 +#define CLK_MOUT_SHARED0_PLL 61 +#define CLK_MOUT_SHARED1_PLL 62 /* CMU_CORE */ #define CLK_MOUT_CORE_BUS_USER 1 @@ -86,7 +87,6 @@ #define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE 12 #define CLK_GOUT_TREX_P_CORE_PCLK 13 #define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE 14 -#define CORE_NR_CLK 15 /* CMU_PERI */ #define CLK_MOUT_PERI_BUS_USER 1 @@ -132,20 +132,26 @@ #define CLK_GOUT_SYSREG_PERI_PCLK 41 #define CLK_GOUT_WDT0_PCLK 42 #define CLK_GOUT_WDT1_PCLK 43 -#define PERI_NR_CLK 44 /* CMU_FSYS */ -#define CLK_MOUT_FSYS_BUS_USER 1 -#define CLK_MOUT_FSYS_MMC_CARD_USER 2 -#define CLK_MOUT_FSYS_MMC_EMBD_USER 3 -#define CLK_MOUT_FSYS_MMC_SDIO_USER 4 -#define CLK_MOUT_FSYS_USB30DRD_USER 4 -#define CLK_GOUT_MMC_CARD_ACLK 5 -#define CLK_GOUT_MMC_CARD_SDCLKIN 6 -#define CLK_GOUT_MMC_EMBD_ACLK 7 -#define CLK_GOUT_MMC_EMBD_SDCLKIN 8 -#define CLK_GOUT_MMC_SDIO_ACLK 9 -#define CLK_GOUT_MMC_SDIO_SDCLKIN 10 -#define FSYS_NR_CLK 11 +#define CLK_MOUT_FSYS_BUS_USER 1 +#define CLK_MOUT_FSYS_MMC_CARD_USER 2 +#define CLK_MOUT_FSYS_MMC_EMBD_USER 3 +#define CLK_MOUT_FSYS_MMC_SDIO_USER 4 +#define CLK_GOUT_MMC_CARD_ACLK 5 +#define CLK_GOUT_MMC_CARD_SDCLKIN 6 +#define CLK_GOUT_MMC_EMBD_ACLK 7 +#define CLK_GOUT_MMC_EMBD_SDCLKIN 8 +#define CLK_GOUT_MMC_SDIO_ACLK 9 +#define CLK_GOUT_MMC_SDIO_SDCLKIN 10 +#define CLK_MOUT_FSYS_USB30DRD_USER 11 +#define CLK_MOUT_USB_PLL 12 +#define CLK_FOUT_USB_PLL 13 +#define CLK_FSYS_USB20PHY_CLKCORE 14 +#define CLK_FSYS_USB30DRD_ACLK_20PHYCTRL 15 +#define CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_0 16 +#define CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_1 17 +#define CLK_FSYS_USB30DRD_BUS_CLK_EARLY 18 +#define CLK_FSYS_USB30DRD_REF_CLK 19 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */ |