diff options
Diffstat (limited to 'sound/soc/codecs/cs35l56-shared.c')
| -rw-r--r-- | sound/soc/codecs/cs35l56-shared.c | 68 |
1 files changed, 41 insertions, 27 deletions
diff --git a/sound/soc/codecs/cs35l56-shared.c b/sound/soc/codecs/cs35l56-shared.c index 98b1e63360ae..953ba066bab1 100644 --- a/sound/soc/codecs/cs35l56-shared.c +++ b/sound/soc/codecs/cs35l56-shared.c @@ -242,7 +242,7 @@ EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, SND_SOC_CS35L56_SHARED); int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base) { unsigned int reg; - unsigned int val; + unsigned int val = 0; int read_ret, poll_ret; if (cs35l56_base->rev < CS35L56_REVID_B0) @@ -439,13 +439,39 @@ EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, SND_SOC_CS35L56_SHARED); static const struct reg_sequence cs35l56_hibernate_seq[] = { /* This must be the last register access */ - REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_HIBERNATE_NOW), + REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE), }; static const struct reg_sequence cs35l56_hibernate_wake_seq[] = { REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_WAKEUP), }; +static void cs35l56_issue_wake_event(struct cs35l56_base *cs35l56_base) +{ + /* + * Dummy transactions to trigger I2C/SPI auto-wake. Issue two + * transactions to meet the minimum required time from the rising edge + * to the last falling edge of wake. + * + * It uses bypassed write because we must wake the chip before + * disabling regmap cache-only. + * + * This can NAK on I2C which will terminate the write sequence so the + * single-write sequence is issued twice. + */ + regmap_multi_reg_write_bypassed(cs35l56_base->regmap, + cs35l56_hibernate_wake_seq, + ARRAY_SIZE(cs35l56_hibernate_wake_seq)); + + usleep_range(CS35L56_WAKE_HOLD_TIME_US, 2 * CS35L56_WAKE_HOLD_TIME_US); + + regmap_multi_reg_write_bypassed(cs35l56_base->regmap, + cs35l56_hibernate_wake_seq, + ARRAY_SIZE(cs35l56_hibernate_wake_seq)); + + cs35l56_wait_control_port_ready(); +} + int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base) { unsigned int val; @@ -474,12 +500,6 @@ int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base) } /* - * Enable auto-hibernate. If it is woken by some other wake source - * it will automatically return to hibernate. - */ - cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE); - - /* * Must enter cache-only first so there can't be any more register * accesses other than the controlled hibernate sequence below. */ @@ -506,17 +526,9 @@ int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_sou if (!cs35l56_base->can_hibernate) goto out_sync; - if (!is_soundwire) { - /* - * Dummy transaction to trigger I2C/SPI auto-wake. This will NAK on I2C. - * Must be done before releasing cache-only. - */ - regmap_multi_reg_write_bypassed(cs35l56_base->regmap, - cs35l56_hibernate_wake_seq, - ARRAY_SIZE(cs35l56_hibernate_wake_seq)); - - cs35l56_wait_control_port_ready(); - } + /* Must be done before releasing cache-only */ + if (!is_soundwire) + cs35l56_issue_wake_event(cs35l56_base); out_sync: regcache_cache_only(cs35l56_base->regmap, false); @@ -545,11 +557,12 @@ out_sync: return 0; err: - regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, - CS35L56_MBOX_CMD_HIBERNATE_NOW); - regcache_cache_only(cs35l56_base->regmap, true); + regmap_multi_reg_write_bypassed(cs35l56_base->regmap, + cs35l56_hibernate_seq, + ARRAY_SIZE(cs35l56_hibernate_seq)); + return ret; } EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, SND_SOC_CS35L56_SHARED); @@ -583,13 +596,14 @@ int cs35l56_hw_init(struct cs35l56_base *cs35l56_base) unsigned int devid, revid, otpid, secured; /* - * If the system is not using a reset_gpio then issue a - * dummy read to force a wakeup. + * When the system is not using a reset_gpio ensure the device is + * awake, otherwise the device has just been released from reset and + * the driver must wait for the control port to become usable. */ if (!cs35l56_base->reset_gpio) - regmap_read(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, &devid); - - cs35l56_wait_control_port_ready(); + cs35l56_issue_wake_event(cs35l56_base); + else + cs35l56_wait_control_port_ready(); /* * The HALO_STATE register is in different locations on Ax and B0 |