diff options
Diffstat (limited to 'sound/soc/fsl/fsl_asrc.h')
| -rw-r--r-- | sound/soc/fsl/fsl_asrc.h | 141 |
1 files changed, 71 insertions, 70 deletions
diff --git a/sound/soc/fsl/fsl_asrc.h b/sound/soc/fsl/fsl_asrc.h index c60075112570..1c492eb237f5 100644 --- a/sound/soc/fsl/fsl_asrc.h +++ b/sound/soc/fsl/fsl_asrc.h @@ -10,9 +10,10 @@ #ifndef _FSL_ASRC_H #define _FSL_ASRC_H -#define IN 0 -#define OUT 1 +#include "fsl_asrc_common.h" +#define ASRC_M2M_INPUTFIFO_WML 0x4 +#define ASRC_M2M_OUTPUTFIFO_WML 0x2 #define ASRC_DMA_BUFFER_NUM 2 #define ASRC_INPUTFIFO_THRESHOLD 32 #define ASRC_OUTPUTFIFO_THRESHOLD 32 @@ -283,14 +284,6 @@ #define ASRMCR1i_OW16_MASK (1 << ASRMCR1i_OW16_SHIFT) #define ASRMCR1i_OW16(v) ((v) << ASRMCR1i_OW16_SHIFT) - -enum asrc_pair_index { - ASRC_INVALID_PAIR = -1, - ASRC_PAIR_A = 0, - ASRC_PAIR_B = 1, - ASRC_PAIR_C = 2, -}; - #define ASRC_PAIR_MAX_NUM (ASRC_PAIR_C + 1) enum asrc_inclk { @@ -308,6 +301,29 @@ enum asrc_inclk { INCLK_SSI3_TX = 0x0b, INCLK_SPDIF_TX = 0x0c, INCLK_ASRCK1_CLK = 0x0f, + + /* clocks for imx8 */ + INCLK_AUD_PLL_DIV_CLK0 = 0x10, + INCLK_AUD_PLL_DIV_CLK1 = 0x11, + INCLK_AUD_CLK0 = 0x12, + INCLK_AUD_CLK1 = 0x13, + INCLK_ESAI0_RX_CLK = 0x14, + INCLK_ESAI0_TX_CLK = 0x15, + INCLK_SPDIF0_RX = 0x16, + INCLK_SPDIF1_RX = 0x17, + INCLK_SAI0_RX_BCLK = 0x18, + INCLK_SAI0_TX_BCLK = 0x19, + INCLK_SAI1_RX_BCLK = 0x1a, + INCLK_SAI1_TX_BCLK = 0x1b, + INCLK_SAI2_RX_BCLK = 0x1c, + INCLK_SAI3_RX_BCLK = 0x1d, + INCLK_ASRC0_MUX_CLK = 0x1e, + + INCLK_ESAI1_RX_CLK = 0x20, + INCLK_ESAI1_TX_CLK = 0x21, + INCLK_SAI6_TX_BCLK = 0x22, + INCLK_HDMI_RX_SAI0_RX_BCLK = 0x24, + INCLK_HDMI_TX_SAI0_TX_BCLK = 0x25, }; enum asrc_outclk { @@ -325,9 +341,33 @@ enum asrc_outclk { OUTCLK_SSI3_RX = 0x0b, OUTCLK_SPDIF_RX = 0x0c, OUTCLK_ASRCK1_CLK = 0x0f, + + /* clocks for imx8 */ + OUTCLK_AUD_PLL_DIV_CLK0 = 0x10, + OUTCLK_AUD_PLL_DIV_CLK1 = 0x11, + OUTCLK_AUD_CLK0 = 0x12, + OUTCLK_AUD_CLK1 = 0x13, + OUTCLK_ESAI0_RX_CLK = 0x14, + OUTCLK_ESAI0_TX_CLK = 0x15, + OUTCLK_SPDIF0_RX = 0x16, + OUTCLK_SPDIF1_RX = 0x17, + OUTCLK_SAI0_RX_BCLK = 0x18, + OUTCLK_SAI0_TX_BCLK = 0x19, + OUTCLK_SAI1_RX_BCLK = 0x1a, + OUTCLK_SAI1_TX_BCLK = 0x1b, + OUTCLK_SAI2_RX_BCLK = 0x1c, + OUTCLK_SAI3_RX_BCLK = 0x1d, + OUTCLK_ASRCO_MUX_CLK = 0x1e, + + OUTCLK_ESAI1_RX_CLK = 0x20, + OUTCLK_ESAI1_TX_CLK = 0x21, + OUTCLK_SAI6_TX_BCLK = 0x22, + OUTCLK_HDMI_RX_SAI0_RX_BCLK = 0x24, + OUTCLK_HDMI_TX_SAI0_TX_BCLK = 0x25, }; #define ASRC_CLK_MAX_NUM 16 +#define ASRC_CLK_MAP_LEN 0x30 enum asrc_word_width { ASRC_WIDTH_24_BIT = 0, @@ -342,8 +382,8 @@ struct asrc_config { unsigned int dma_buffer_size; unsigned int input_sample_rate; unsigned int output_sample_rate; - enum asrc_word_width input_word_width; - enum asrc_word_width output_word_width; + snd_pcm_format_t input_format; + snd_pcm_format_t output_format; enum asrc_inclk inclk; enum asrc_outclk outclk; }; @@ -388,78 +428,39 @@ struct dma_block { }; /** - * fsl_asrc_pair: ASRC Pair private data + * fsl_asrc_soc_data: soc specific data + * + * @use_edma: using edma as dma device or not + * @channel_bits: width of ASRCNCR register for each pair + */ +struct fsl_asrc_soc_data { + bool use_edma; + unsigned int channel_bits; +}; + +/** + * fsl_asrc_pair_priv: ASRC Pair private data * - * @asrc_priv: pointer to its parent module * @config: configuration profile - * @error: error record - * @index: pair index (ASRC_PAIR_A, ASRC_PAIR_B, ASRC_PAIR_C) - * @channels: occupied channel number - * @desc: input and output dma descriptors - * @dma_chan: inputer and output DMA channels - * @dma_data: private dma data - * @pos: hardware pointer position - * @private: pair private area */ -struct fsl_asrc_pair { - struct fsl_asrc *asrc_priv; +struct fsl_asrc_pair_priv { struct asrc_config *config; - unsigned int error; - - enum asrc_pair_index index; - unsigned int channels; - - struct dma_async_tx_descriptor *desc[2]; - struct dma_chan *dma_chan[2]; - struct imx_dma_data dma_data; - unsigned int pos; - - void *private; }; /** - * fsl_asrc_pair: ASRC private data + * fsl_asrc_priv: ASRC private data * - * @dma_params_rx: DMA parameters for receive channel - * @dma_params_tx: DMA parameters for transmit channel - * @pdev: platform device pointer - * @regmap: regmap handler - * @paddr: physical address to the base address of registers - * @mem_clk: clock source to access register - * @ipg_clk: clock source to drive peripheral - * @spba_clk: SPBA clock (optional, depending on SoC design) * @asrck_clk: clock sources to driver ASRC internal logic - * @lock: spin lock for resource protection - * @pair: pair pointers - * @channel_bits: width of ASRCNCR register for each pair - * @channel_avail: non-occupied channel numbers - * @asrc_rate: default sample rate for ASoC Back-Ends - * @asrc_width: default sample width for ASoC Back-Ends + * @soc: soc specific data + * @clk_map: clock map for input/output clock * @regcache_cfg: store register value of REG_ASRCFG */ -struct fsl_asrc { - struct snd_dmaengine_dai_dma_data dma_params_rx; - struct snd_dmaengine_dai_dma_data dma_params_tx; - struct platform_device *pdev; - struct regmap *regmap; - unsigned long paddr; - struct clk *mem_clk; - struct clk *ipg_clk; - struct clk *spba_clk; +struct fsl_asrc_priv { struct clk *asrck_clk[ASRC_CLK_MAX_NUM]; - spinlock_t lock; - - struct fsl_asrc_pair *pair[ASRC_PAIR_MAX_NUM]; - unsigned int channel_bits; - unsigned int channel_avail; - - int asrc_rate; - int asrc_width; + const struct fsl_asrc_soc_data *soc; + unsigned char *clk_map[2]; u32 regcache_cfg; }; -#define DRV_NAME "fsl-asrc-dai" -extern struct snd_soc_component_driver fsl_asrc_component; -struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, bool dir); #endif /* _FSL_ASRC_H */ |