diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l1d_cache.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l1d_cache.json | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l1d_cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l1d_cache.json index da7c129f2569..799d106d5173 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l1d_cache.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l1d_cache.json @@ -1,11 +1,11 @@ [ { "ArchStdEvent": "L1D_CACHE_REFILL", - "PublicDescription": "Counts level 1 data cache refills caused by speculatively executed load or store operations that missed in the level 1 data cache. This event only counts one event per cache line. This event does not count cache line allocations from preload instructions or from hardware cache prefetching." + "PublicDescription": "Counts level 1 data cache refills caused by speculatively executed load or store operations that missed in the level 1 data cache. This event only counts one event per cache line." }, { "ArchStdEvent": "L1D_CACHE", - "PublicDescription": "Counts level 1 data cache accesses from any load/store operations. Atomic operations that resolve in the CPUs caches (near atomic operations) count as both a write access and read access. Each access to a cache line is counted including the multiple accesses caused by single instructions such as LDM or STM. Each access to other level 1 data or unified memory structures, for example refill buffers, write buffers, and write-back buffers, are also counted." + "PublicDescription": "Counts level 1 data cache accesses from any load/store operations. Atomic operations that resolve in the CPUs caches (near atomic operations) counts as both a write access and read access. Each access to a cache line is counted including the multiple accesses caused by single instructions such as LDM or STM. Each access to other level 1 data or unified memory structures, for example refill buffers, write buffers, and write-back buffers, are also counted." }, { "ArchStdEvent": "L1D_CACHE_WB", @@ -17,7 +17,7 @@ }, { "ArchStdEvent": "L1D_CACHE_RD", - "PublicDescription": "Counts level 1 data cache accesses from any load operation. Atomic load operations that resolve in the CPUs caches count as both a write access and read access." + "PublicDescription": "Counts level 1 data cache accesses from any load operation. Atomic load operations that resolve in the CPUs caches counts as both a write access and read access." }, { "ArchStdEvent": "L1D_CACHE_WR", |