diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l3_cache.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l3_cache.json | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l3_cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l3_cache.json index 45bfba532df7..4a2e72fc5ada 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l3_cache.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l3_cache.json @@ -9,11 +9,11 @@ }, { "ArchStdEvent": "L3D_CACHE", - "PublicDescription": "Counts level 3 cache accesses. level 3 cache is a unified cache for data and instruction accesses. Accesses are for misses in the lower level caches or translation resolutions due to accesses." + "PublicDescription": "Counts level 3 cache accesses. Level 3 cache is a unified cache for data and instruction accesses. Accesses are for misses in the lower level caches or translation resolutions due to accesses." }, { "ArchStdEvent": "L3D_CACHE_RD", - "PublicDescription": "TBD" + "PublicDescription": "Counts level 3 cache accesses caused by any memory read operation. Level 3 cache is a unified cache for data and instruction accesses. Accesses are for misses in the lower level caches or translation resolutions due to accesses." }, { "ArchStdEvent": "L3D_CACHE_LMISS_RD", |