diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/arm64/common-and-microarch.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/arm64/common-and-microarch.json | 310 |
1 files changed, 310 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/arm64/common-and-microarch.json b/tools/perf/pmu-events/arch/arm64/common-and-microarch.json index dddecc946575..e40be37addf8 100644 --- a/tools/perf/pmu-events/arch/arm64/common-and-microarch.json +++ b/tools/perf/pmu-events/arch/arm64/common-and-microarch.json @@ -228,6 +228,16 @@ "BriefDescription": "Attributable Level 1 instruction TLB access" }, { + "EventCode": "0x27", + "EventName": "L2I_CACHE", + "BriefDescription": "Level 2 instruction cache access" + }, + { + "EventCode": "0x28", + "EventName": "L2I_CACHE_REFILL", + "BriefDescription": "Level 2 instruction cache refill" + }, + { "PublicDescription": "Attributable Level 3 data cache allocation without refill", "EventCode": "0x29", "EventName": "L3D_CACHE_ALLOCATE", @@ -276,6 +286,16 @@ "BriefDescription": "Access to another socket in a multi-socket system" }, { + "EventCode": "0x32", + "EventName": "LL_CACHE", + "BriefDescription": "Last level cache access" + }, + { + "EventCode": "0x33", + "EventName": "LL_CACHE_MISS", + "BriefDescription": "Last level cache miss" + }, + { "PublicDescription": "Access to data TLB causes a translation table walk", "EventCode": "0x34", "EventName": "DTLB_WALK", @@ -396,6 +416,11 @@ "BriefDescription": "Level 2 data cache long-latency read miss" }, { + "EventCode": "0x400A", + "EventName": "L2I_CACHE_LMISS", + "BriefDescription": "Level 2 instruction cache long-latency miss" + }, + { "PublicDescription": "Level 3 data cache long-latency read miss. The counter counts each memory read access counted by L3D_CACHE that incurs additional latency because it returns data from outside the Level 3 data or unified cache of this processing element. The event indicates to software that the access missed in the Level 3 data or unified cache and might have a significant performance impact compared to the latency of an access that hits in the Level 3 data or unified cache.", "EventCode": "0x400B", "EventName": "L3D_CACHE_LMISS_RD", @@ -522,6 +547,11 @@ "BriefDescription": "Instruction architecturally executed, SVE." }, { + "EventCode": "0x8004", + "EventName": "SIMD_INST_SPEC", + "BriefDescription": "Operation speculatively executed, SIMD" + }, + { "PublicDescription": "ASE operations speculatively executed", "EventCode": "0x8005", "EventName": "ASE_INST_SPEC", @@ -1210,6 +1240,106 @@ "BriefDescription": "Integer Operation speculatively executed, Advanced SIMD or SVE matrix multiply." }, { + "EventCode": "0x8108", + "EventName": "BR_IMMED_TAKEN_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, immediate, taken" + }, + { + "EventCode": "0x810C", + "EventName": "BR_INDNR_TAKEN_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, indirect excluding procedure return, taken" + }, + { + "EventCode": "0x8110", + "EventName": "BR_IMMED_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, predicted immediate" + }, + { + "EventCode": "0x8111", + "EventName": "BR_IMMED_MIS_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, mispredicted immediate" + }, + { + "EventCode": "0x8112", + "EventName": "BR_IND_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, predicted indirect" + }, + { + "EventCode": "0x8113", + "EventName": "BR_IND_MIS_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, mispredicted indirect" + }, + { + "EventCode": "0x8114", + "EventName": "BR_RETURN_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, predicted procedure return" + }, + { + "EventCode": "0x8115", + "EventName": "BR_RETURN_MIS_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, mispredicted procedure return" + }, + { + "EventCode": "0x8116", + "EventName": "BR_INDNR_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, predicted indirect excluding procedure return" + }, + { + "EventCode": "0x8117", + "EventName": "BR_INDNR_MIS_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, mispredicted indirect excluding procedure return" + }, + { + "EventCode": "0x8118", + "EventName": "BR_TAKEN_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, predicted branch, taken" + }, + { + "EventCode": "0x8119", + "EventName": "BR_TAKEN_MIS_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, mispredicted branch, taken" + }, + { + "EventCode": "0x811A", + "EventName": "BR_SKIP_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, predicted branch, not taken" + }, + { + "EventCode": "0x811B", + "EventName": "BR_SKIP_MIS_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, mispredicted branch, not taken" + }, + { + "EventCode": "0x811C", + "EventName": "BR_PRED_RETIRED", + "BriefDescription": "Branch instruction architecturally executed, predicted branch" + }, + { + "EventCode": "0x811D", + "EventName": "BR_IND_RETIRED", + "BriefDescription": "Instruction architecturally executed, indirect branch" + }, + { + "EventCode": "0x811F", + "EventName": "BRB_FILTRATE", + "BriefDescription": "Branch Record captured" + }, + { + "EventCode": "0x8120", + "EventName": "INST_FETCH_PERCYC", + "BriefDescription": "Event in progress, INST FETCH" + }, + { + "EventCode": "0x8121", + "EventName": "MEM_ACCESS_RD_PERCYC", + "BriefDescription": "Event in progress, MEM ACCESS RD" + }, + { + "EventCode": "0x8124", + "EventName": "INST_FETCH", + "BriefDescription": "Instruction memory access" + }, + { "EventCode": "0x8128", "EventName": "DTLB_WALK_PERCYC", "BriefDescription": "Data translation table walks in progress." @@ -1220,6 +1350,66 @@ "BriefDescription": "Instruction translation table walks in progress." }, { + "EventCode": "0x812A", + "EventName": "SAMPLE_FEED_BR", + "BriefDescription": "Statisical Profiling sample taken, branch" + }, + { + "EventCode": "0x812B", + "EventName": "SAMPLE_FEED_LD", + "BriefDescription": "Statisical Profiling sample taken, load" + }, + { + "EventCode": "0x812C", + "EventName": "SAMPLE_FEED_ST", + "BriefDescription": "Statisical Profiling sample taken, store" + }, + { + "EventCode": "0x812D", + "EventName": "SAMPLE_FEED_OP", + "BriefDescription": "Statisical Profiling sample taken, matching operation type" + }, + { + "EventCode": "0x812E", + "EventName": "SAMPLE_FEED_EVENT", + "BriefDescription": "Statisical Profiling sample taken, matching events" + }, + { + "EventCode": "0x812F", + "EventName": "SAMPLE_FEED_LAT", + "BriefDescription": "Statisical Profiling sample taken, exceeding minimum latency" + }, + { + "EventCode": "0x8130", + "EventName": "L1D_TLB_RW", + "BriefDescription": "Level 1 data TLB demand access" + }, + { + "EventCode": "0x8131", + "EventName": "L1I_TLB_RD", + "BriefDescription": "Level 1 instruction TLB demand access" + }, + { + "EventCode": "0x8132", + "EventName": "L1D_TLB_PRFM", + "BriefDescription": "Level 1 data TLB software preload" + }, + { + "EventCode": "0x8133", + "EventName": "L1I_TLB_PRFM", + "BriefDescription": "Level 1 instruction TLB software preload" + }, + { + "EventCode": "0x8134", + "EventName": "DTLB_HWUPD", + "BriefDescription": "Data TLB hardware update of translation table" + }, + { + "EventCode": "0x8135", + "EventName": "ITLB_HWUPD", + "BriefDescription": "Instruction TLB hardware update of translation table" + }, + { "EventCode": "0x8136", "EventName": "DTLB_STEP", "BriefDescription": "Data TLB translation table walk, step." @@ -1250,6 +1440,46 @@ "BriefDescription": "Instruction TLB small page translation table walk." }, { + "EventCode": "0x813C", + "EventName": "DTLB_WALK_RW", + "BriefDescription": "Data TLB demand access with at least one translation table walk" + }, + { + "EventCode": "0x813D", + "EventName": "ITLB_WALK_RD", + "BriefDescription": "Instruction TLB demand access with at least one translation table walk" + }, + { + "EventCode": "0x813E", + "EventName": "DTLB_WALK_PRFM", + "BriefDescription": "Data TLB software preload access with at least one translation table walk" + }, + { + "EventCode": "0x813F", + "EventName": "ITLB_WALK_PRFM", + "BriefDescription": "Instruction TLB software preload access with at least one translation table walk" + }, + { + "EventCode": "0x8140", + "EventName": "L1D_CACHE_RW", + "BriefDescription": "Level 1 data cache demand access" + }, + { + "EventCode": "0x8141", + "EventName": "L1I_CACHE_RD", + "BriefDescription": "Level 1 instruction cache demand fetch" + }, + { + "EventCode": "0x8142", + "EventName": "L1D_CACHE_PRFM", + "BriefDescription": "Level 1 data cache software preload" + }, + { + "EventCode": "0x8143", + "EventName": "L1I_CACHE_PRFM", + "BriefDescription": "Level 1 instruction cache software preload" + }, + { "EventCode": "0x8144", "EventName": "L1D_CACHE_MISS", "BriefDescription": "Level 1 data cache demand access miss." @@ -1260,11 +1490,46 @@ "BriefDescription": "Level 1 instruction cache hardware prefetch." }, { + "EventCode": "0x8146", + "EventName": "L1D_CACHE_REFILL_PRFM", + "BriefDescription": "Level 1 data cache refill, software preload" + }, + { + "EventCode": "0x8147", + "EventName": "L1I_CACHE_REFILL_PRFM", + "BriefDescription": "Level 1 instruction cache refill, software preload" + }, + { + "EventCode": "0x8148", + "EventName": "L2D_CACHE_RW", + "BriefDescription": "Level 2 data cache demand access" + }, + { + "EventCode": "0x8149", + "EventName": "L2I_CACHE_RD", + "BriefDescription": "Level 2 instruction cache demand fetch" + }, + { + "EventCode": "0x814A", + "EventName": "L2D_CACHE_PRFM", + "BriefDescription": "Level 2 data cache software preload" + }, + { "EventCode": "0x814C", "EventName": "L2D_CACHE_MISS", "BriefDescription": "Level 2 data cache demand access miss." }, { + "EventCode": "0x814E", + "EventName": "L2D_CACHE_REFILL_PRFM", + "BriefDescription": "Level 2 data cache refill, software preload" + }, + { + "EventCode": "0x8152", + "EventName": "L3D_CACHE_MISS", + "BriefDescription": "Level 3 data cache demand access miss" + }, + { "EventCode": "0x8154", "EventName": "L1D_CACHE_HWPRF", "BriefDescription": "Level 1 data cache hardware prefetch." @@ -1375,6 +1640,21 @@ "BriefDescription": "Backend stall cycles, Memory Copy or Set operation." }, { + "EventCode": "0x8171", + "EventName": "CAS_NEAR_PASS", + "BriefDescription": "Atomic memory Operation speculatively executed, Compare and Swap pass" + }, + { + "EventCode": "0x8172", + "EventName": "CAS_NEAR_SPEC", + "BriefDescription": "Atomic memory Operation speculatively executed, Compare and Swap near" + }, + { + "EventCode": "0x8173", + "EventName": "CAS_FAR_SPEC", + "BriefDescription": "Atomic memory Operation speculatively executed, Compare and Swap far" + }, + { "EventCode": "0x8186", "EventName": "UOP_RETIRED", "BriefDescription": "Micro-operation architecturally executed." @@ -1440,6 +1720,16 @@ "BriefDescription": "Level 2 data cache demand access hit, write." }, { + "EventCode": "0x81D0", + "EventName": "L1I_CACHE_HIT_RD_FPRFM", + "BriefDescription": "Level 1 instruction cache demand fetch first hit, fetched by software preload" + }, + { + "EventCode": "0x81E0", + "EventName": "L1I_CACHE_HIT_RD_FHWPRF", + "BriefDescription": "Level 1 instruction cache demand fetch first hit, fetched by hardware prefetcher" + }, + { "EventCode": "0x8200", "EventName": "L1I_CACHE_HIT", "BriefDescription": "Level 1 instruction cache hit." @@ -1455,6 +1745,11 @@ "BriefDescription": "Level 2 data cache hit." }, { + "EventCode": "0x8208", + "EventName": "L1I_CACHE_HIT_PRFM", + "BriefDescription": "Level 1 instruction cache software preload hit" + }, + { "EventCode": "0x8240", "EventName": "L1I_LFB_HIT_RD", "BriefDescription": "Level 1 instruction cache demand fetch line-fill buffer hit." @@ -1480,6 +1775,16 @@ "BriefDescription": "Level 2 data cache demand access line-fill buffer hit, write." }, { + "EventCode": "0x8250", + "EventName": "L1I_LFB_HIT_RD_FPRFM", + "BriefDescription": "Level 1 instruction cache demand fetch line-fill buffer first hit, recently fetched by software preload" + }, + { + "EventCode": "0x8260", + "EventName": "L1I_LFB_HIT_RD_FHWPRF", + "BriefDescription": "Level 1 instruction cache demand fetch line-fill buffer first hit, recently fetched by hardware prefetcher" + }, + { "EventCode": "0x8280", "EventName": "L1I_CACHE_PRF", "BriefDescription": "Level 1 instruction cache, preload or prefetch hit." @@ -1510,6 +1815,11 @@ "BriefDescription": "Level 2 data cache refill, preload or prefetch hit." }, { + "EventCode": "0x829A", + "EventName": "LL_CACHE_REFILL", + "BriefDescription": "Last level cache refill" + }, + { "EventCode": "0x8320", "EventName": "L1D_CACHE_REFILL_PERCYC", "BriefDescription": "Level 1 data or unified cache refills in progress." |