diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json | 32 |
1 files changed, 0 insertions, 32 deletions
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json deleted file mode 100644 index be1a46312ac3..000000000000 --- a/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json +++ /dev/null @@ -1,32 +0,0 @@ -[ - { - "EventName": "ICACHE_RETIRED", - "EventCode": "0x0000102", - "BriefDescription": "Instruction cache miss" - }, - { - "EventName": "DCACHE_MISS_MMIO_ACCESSES", - "EventCode": "0x0000202", - "BriefDescription": "Data cache miss or memory-mapped I/O access" - }, - { - "EventName": "DCACHE_WRITEBACK", - "EventCode": "0x0000402", - "BriefDescription": "Data cache write-back" - }, - { - "EventName": "INST_TLB_MISS", - "EventCode": "0x0000802", - "BriefDescription": "Instruction TLB miss" - }, - { - "EventName": "DATA_TLB_MISS", - "EventCode": "0x0001002", - "BriefDescription": "Data TLB miss" - }, - { - "EventName": "UTLB_MISS", - "EventCode": "0x0002002", - "BriefDescription": "UTLB miss" - } -]
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