diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/riscv')
30 files changed, 555 insertions, 182 deletions
diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv index 3d3a809a5446..0a7e7dcc81be 100644 --- a/tools/perf/pmu-events/arch/riscv/mapfile.csv +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv @@ -14,7 +14,11 @@ # # #MVENDORID-MARCHID-MIMPID,Version,Filename,EventType -0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core +0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/bullet,core +0x489-0x8000000000000[1-9a-e]07-0x[78ac][[:xdigit:]]+,v1,sifive/bullet-07,core +0x489-0x8000000000000[1-9a-e]07-0xd[[:xdigit:]]+,v1,sifive/bullet-0d,core +0x489-0x8000000000000008-0x[[:xdigit:]]+,v1,sifive/p550,core +0x489-0x8000000000000[1-6]08-0x[9b][[:xdigit:]]+,v1,sifive/p650,core 0x5b7-0x0-0x0,v1,thead/c900-legacy,core 0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core 0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json new file mode 100644 index 000000000000..5c8124cfe926 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json @@ -0,0 +1,12 @@ +[ + { + "EventName": "CORE_CLOCK_CYCLES", + "EventCode": "0x165", + "BriefDescription": "Counts core clock cycles" + }, + { + "EventName": "INSTRUCTIONS_RETIRED", + "EventCode": "0x265", + "BriefDescription": "Counts instructions retired" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json new file mode 120000 index 000000000000..34e5c2870eee --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json @@ -0,0 +1 @@ +../bullet/firmware.json
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json new file mode 120000 index 000000000000..62eacc2d7497 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json @@ -0,0 +1 @@ +../bullet/instruction.json
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json new file mode 120000 index 000000000000..df50fc47a5fe --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json @@ -0,0 +1 @@ +../bullet/memory.json
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json new file mode 100644 index 000000000000..de8efd7b8b34 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json @@ -0,0 +1,62 @@ +[ + { + "EventName": "ADDRESSGEN_INTERLOCK", + "EventCode": "0x101", + "BriefDescription": "Counts cycles with an address-generation interlock" + }, + { + "EventName": "LONGLATENCY_INTERLOCK", + "EventCode": "0x201", + "BriefDescription": "Counts cycles with a long-latency interlock" + }, + { + "EventName": "CSR_INTERLOCK", + "EventCode": "0x401", + "BriefDescription": "Counts cycles with a CSR interlock" + }, + { + "EventName": "ICACHE_BLOCKED", + "EventCode": "0x801", + "BriefDescription": "Counts cycles in which the instruction cache was not able to provide an instruction" + }, + { + "EventName": "DCACHE_BLOCKED", + "EventCode": "0x1001", + "BriefDescription": "Counts cycles in which the data cache blocked an instruction" + }, + { + "EventName": "BRANCH_DIRECTION_MISPREDICTION", + "EventCode": "0x2001", + "BriefDescription": "Counts mispredictions of conditional branch direction (taken/not taken)" + }, + { + "EventName": "BRANCH_TARGET_MISPREDICTION", + "EventCode": "0x4001", + "BriefDescription": "Counts mispredictions of the target PC of control-flow instructions" + }, + { + "EventName": "PIPELINE_FLUSH", + "EventCode": "0x8001", + "BriefDescription": "Counts flushes of the core pipeline. Common causes include fence.i and CSR accesses" + }, + { + "EventName": "REPLAY", + "EventCode": "0x10001", + "BriefDescription": "Counts instruction replays" + }, + { + "EventName": "INTEGER_MUL_DIV_INTERLOCK", + "EventCode": "0x20001", + "BriefDescription": "Counts cycles with a multiply or divide interlock" + }, + { + "EventName": "FP_INTERLOCK", + "EventCode": "0x40001", + "BriefDescription": "Counts cycles with a floating-point interlock" + }, + { + "EventName": "TRACE_STALL", + "EventCode": "0x80001", + "BriefDescription": "Counts cycles in which the core pipeline is stalled due to backpressure from the Trace Encoder" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json new file mode 100644 index 000000000000..aa7a12818521 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json @@ -0,0 +1,42 @@ +[ + { + "EventName": "WATCHPOINT_0", + "EventCode": "0x164", + "BriefDescription": "Counts occurrences of watchpoint 0 with action=8" + }, + { + "EventName": "WATCHPOINT_1", + "EventCode": "0x264", + "BriefDescription": "Counts occurrences of watchpoint 1 with action=8" + }, + { + "EventName": "WATCHPOINT_2", + "EventCode": "0x464", + "BriefDescription": "Counts occurrences of watchpoint 2 with action=8" + }, + { + "EventName": "WATCHPOINT_3", + "EventCode": "0x864", + "BriefDescription": "Counts occurrences of watchpoint 3 with action=8" + }, + { + "EventName": "WATCHPOINT_4", + "EventCode": "0x1064", + "BriefDescription": "Counts occurrences of watchpoint 4 with action=8" + }, + { + "EventName": "WATCHPOINT_5", + "EventCode": "0x2064", + "BriefDescription": "Counts occurrences of watchpoint 5 with action=8" + }, + { + "EventName": "WATCHPOINT_6", + "EventCode": "0x4064", + "BriefDescription": "Counts occurrences of watchpoint 6 with action=8" + }, + { + "EventName": "WATCHPOINT_7", + "EventCode": "0x8064", + "BriefDescription": "Counts occurrences of watchpoint 7 with action=8" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json new file mode 120000 index 000000000000..ccd29278f61b --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json @@ -0,0 +1 @@ +../bullet-07/cycle-and-instruction-count.json
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json new file mode 120000 index 000000000000..34e5c2870eee --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json @@ -0,0 +1 @@ +../bullet/firmware.json
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json new file mode 120000 index 000000000000..62eacc2d7497 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json @@ -0,0 +1 @@ +../bullet/instruction.json
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json new file mode 120000 index 000000000000..df50fc47a5fe --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json @@ -0,0 +1 @@ +../bullet/memory.json
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json new file mode 100644 index 000000000000..6573b24788eb --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json @@ -0,0 +1,72 @@ +[ + { + "EventName": "ADDRESSGEN_INTERLOCK", + "EventCode": "0x101", + "BriefDescription": "Counts cycles with an address-generation interlock" + }, + { + "EventName": "LONGLATENCY_INTERLOCK", + "EventCode": "0x201", + "BriefDescription": "Counts cycles with a long-latency interlock" + }, + { + "EventName": "CSR_INTERLOCK", + "EventCode": "0x401", + "BriefDescription": "Counts cycles with a CSR interlock" + }, + { + "EventName": "ICACHE_BLOCKED", + "EventCode": "0x801", + "BriefDescription": "Counts cycles in which the instruction cache was not able to provide an instruction" + }, + { + "EventName": "DCACHE_BLOCKED", + "EventCode": "0x1001", + "BriefDescription": "Counts cycles in which the data cache blocked an instruction" + }, + { + "EventName": "BRANCH_DIRECTION_MISPREDICTION", + "EventCode": "0x2001", + "BriefDescription": "Counts mispredictions of conditional branch direction (taken/not taken)" + }, + { + "EventName": "BRANCH_TARGET_MISPREDICTION", + "EventCode": "0x4001", + "BriefDescription": "Counts mispredictions of the target PC of control-flow instructions" + }, + { + "EventName": "PIPELINE_FLUSH", + "EventCode": "0x8001", + "BriefDescription": "Counts flushes of the core pipeline. Common causes include fence.i and CSR accesses" + }, + { + "EventName": "REPLAY", + "EventCode": "0x10001", + "BriefDescription": "Counts instruction replays" + }, + { + "EventName": "INTEGER_MUL_DIV_INTERLOCK", + "EventCode": "0x20001", + "BriefDescription": "Counts cycles with a multiply or divide interlock" + }, + { + "EventName": "FP_INTERLOCK", + "EventCode": "0x40001", + "BriefDescription": "Counts cycles with a floating-point interlock" + }, + { + "EventName": "TRACE_STALL", + "EventCode": "0x80001", + "BriefDescription": "Counts cycles in which the core pipeline is stalled due to backpressure from the Trace Encoder" + }, + { + "EventName": "ITLB_MISS_STALL", + "EventCode": "0x100001", + "BriefDescription": "Counts cycles in which the core pipeline is stalled due to ITLB Miss" + }, + { + "EventName": "DTLB_MISS_STALL", + "EventCode": "0x200001", + "BriefDescription": "Counts cycles in which the core pipeline is stalled due to DTLB Miss" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json new file mode 120000 index 000000000000..e88b98bfc5c8 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json @@ -0,0 +1 @@ +../bullet-07/watchpoint.json
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/firmware.json index 7149caec4f80..7149caec4f80 100644 --- a/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet/firmware.json diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json new file mode 100644 index 000000000000..284e4c1566e0 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json @@ -0,0 +1,92 @@ +[ + { + "EventName": "EXCEPTION_TAKEN", + "EventCode": "0x100", + "BriefDescription": "Counts exceptions taken" + }, + { + "EventName": "INTEGER_LOAD_RETIRED", + "EventCode": "0x200", + "BriefDescription": "Counts integer load instructions retired" + }, + { + "EventName": "INTEGER_STORE_RETIRED", + "EventCode": "0x400", + "BriefDescription": "Counts integer store instructions retired" + }, + { + "EventName": "ATOMIC_MEMORY_RETIRED", + "EventCode": "0x800", + "BriefDescription": "Counts atomic memory instructions retired" + }, + { + "EventName": "SYSTEM_INSTRUCTION_RETIRED", + "EventCode": "0x1000", + "BriefDescription": "Counts system instructions retired (CSR, WFI, MRET, etc.)" + }, + { + "EventName": "INTEGER_ARITHMETIC_RETIRED", + "EventCode": "0x2000", + "BriefDescription": "Counts integer arithmetic instructions retired" + }, + { + "EventName": "CONDITIONAL_BRANCH_RETIRED", + "EventCode": "0x4000", + "BriefDescription": "Counts conditional branch instructions retired" + }, + { + "EventName": "JAL_INSTRUCTION_RETIRED", + "EventCode": "0x8000", + "BriefDescription": "Counts jump-and-link instructions retired" + }, + { + "EventName": "JALR_INSTRUCTION_RETIRED", + "EventCode": "0x10000", + "BriefDescription": "Counts indirect jump instructions (JALR) retired" + }, + { + "EventName": "INTEGER_MULTIPLICATION_RETIRED", + "EventCode": "0x20000", + "BriefDescription": "Counts integer multiplication instructions retired" + }, + { + "EventName": "INTEGER_DIVISION_RETIRED", + "EventCode": "0x40000", + "BriefDescription": "Counts integer division instructions retired" + }, + { + "EventName": "FP_LOAD_RETIRED", + "EventCode": "0x80000", + "BriefDescription": "Counts floating-point load instructions retired" + }, + { + "EventName": "FP_STORE_RETIRED", + "EventCode": "0x100000", + "BriefDescription": "Counts floating-point store instructions retired" + }, + { + "EventName": "FP_ADD_RETIRED", + "EventCode": "0x200000", + "BriefDescription": "Counts floating-point add instructions retired" + }, + { + "EventName": "FP_MUL_RETIRED", + "EventCode": "0x400000", + "BriefDescription": "Counts floating-point multiply instructions retired" + }, + { + "EventName": "FP_MULADD_RETIRED", + "EventCode": "0x800000", + "BriefDescription": "Counts floating-point fused multiply-add instructions retired" + }, + { + "EventName": "FP_DIV_SQRT_RETIRED", + "EventCode": "0x1000000", + "BriefDescription": "Counts floating point divide or square root instructions retired" + }, + { + "EventName": "OTHER_FP_RETIRED", + "EventCode": "0x2000000", + "BriefDescription": "Counts other floating-point instructions retired" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json new file mode 100644 index 000000000000..70441a55dd66 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json @@ -0,0 +1,32 @@ +[ + { + "EventName": "ICACHE_MISS", + "EventCode": "0x102", + "BriefDescription": "Counts instruction cache misses" + }, + { + "EventName": "DCACHE_MISS", + "EventCode": "0x202", + "BriefDescription": "Counts data cache misses" + }, + { + "EventName": "DCACHE_RELEASE", + "EventCode": "0x402", + "BriefDescription": "Counts writeback requests from the data cache" + }, + { + "EventName": "ITLB_MISS", + "EventCode": "0x802", + "BriefDescription": "Counts Instruction TLB misses caused by instruction address translation requests" + }, + { + "EventName": "DTLB_MISS", + "EventCode": "0x1002", + "BriefDescription": "Counts Data TLB misses caused by data address translation requests" + }, + { + "EventName": "UTLB_MISS", + "EventCode": "0x2002", + "BriefDescription": "Counts Unified TLB misses caused by address translation requests" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json new file mode 100644 index 000000000000..d9cdb7d747ee --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json @@ -0,0 +1,57 @@ +[ + { + "EventName": "ADDRESSGEN_INTERLOCK", + "EventCode": "0x101", + "BriefDescription": "Counts cycles with an address-generation interlock" + }, + { + "EventName": "LONGLATENCY_INTERLOCK", + "EventCode": "0x201", + "BriefDescription": "Counts cycles with a long-latency interlock" + }, + { + "EventName": "CSR_INTERLOCK", + "EventCode": "0x401", + "BriefDescription": "Counts cycles with a CSR interlock" + }, + { + "EventName": "ICACHE_BLOCKED", + "EventCode": "0x801", + "BriefDescription": "Counts cycles in which the instruction cache was not able to provide an instruction" + }, + { + "EventName": "DCACHE_BLOCKED", + "EventCode": "0x1001", + "BriefDescription": "Counts cycles in which the data cache blocked an instruction" + }, + { + "EventName": "BRANCH_DIRECTION_MISPREDICTION", + "EventCode": "0x2001", + "BriefDescription": "Counts mispredictions of conditional branch direction (taken/not taken)" + }, + { + "EventName": "BRANCH_TARGET_MISPREDICTION", + "EventCode": "0x4001", + "BriefDescription": "Counts mispredictions of the target PC of control-flow instructions" + }, + { + "EventName": "PIPELINE_FLUSH", + "EventCode": "0x8001", + "BriefDescription": "Counts flushes of the core pipeline. Common causes include fence.i and CSR accesses" + }, + { + "EventName": "REPLAY", + "EventCode": "0x10001", + "BriefDescription": "Counts instruction replays" + }, + { + "EventName": "INTEGER_MUL_DIV_INTERLOCK", + "EventCode": "0x20001", + "BriefDescription": "Counts cycles with a multiply or divide interlock" + }, + { + "EventName": "FP_INTERLOCK", + "EventCode": "0x40001", + "BriefDescription": "Counts cycles with a floating-point interlock" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json b/tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json new file mode 120000 index 000000000000..34e5c2870eee --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json @@ -0,0 +1 @@ +../bullet/firmware.json
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json b/tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json new file mode 120000 index 000000000000..62eacc2d7497 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json @@ -0,0 +1 @@ +../bullet/instruction.json
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json new file mode 100644 index 000000000000..8393f81b2cf0 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json @@ -0,0 +1,47 @@ +[ + { + "EventName": "ICACHE_MISS", + "EventCode": "0x102", + "BriefDescription": "Counts instruction cache misses" + }, + { + "EventName": "DCACHE_MISS", + "EventCode": "0x202", + "BriefDescription": "Counts data cache misses" + }, + { + "EventName": "DCACHE_RELEASE", + "EventCode": "0x402", + "BriefDescription": "Counts writeback requests from the data cache" + }, + { + "EventName": "ITLB_MISS", + "EventCode": "0x802", + "BriefDescription": "Counts Instruction TLB misses caused by instruction address translation requests" + }, + { + "EventName": "DTLB_MISS", + "EventCode": "0x1002", + "BriefDescription": "Counts Data TLB misses caused by data address translation requests" + }, + { + "EventName": "UTLB_MISS", + "EventCode": "0x2002", + "BriefDescription": "Counts Unified TLB misses caused by address translation requests" + }, + { + "EventName": "UTLB_HIT", + "EventCode": "0x4002", + "BriefDescription": "Counts Unified TLB hits for address translation requests" + }, + { + "EventName": "PTE_CACHE_MISS", + "EventCode": "0x8002", + "BriefDescription": "Counts Page Table Entry cache misses" + }, + { + "EventName": "PTE_CACHE_HIT", + "EventCode": "0x10002", + "BriefDescription": "Counts Page Table Entry cache hits" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json new file mode 120000 index 000000000000..ba5dd2960e9f --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json @@ -0,0 +1 @@ +../bullet/microarch.json
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/p650/cycle-and-instruction-count.json b/tools/perf/pmu-events/arch/riscv/sifive/p650/cycle-and-instruction-count.json new file mode 120000 index 000000000000..ccd29278f61b --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/p650/cycle-and-instruction-count.json @@ -0,0 +1 @@ +../bullet-07/cycle-and-instruction-count.json
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/p650/firmware.json b/tools/perf/pmu-events/arch/riscv/sifive/p650/firmware.json new file mode 120000 index 000000000000..34e5c2870eee --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/p650/firmware.json @@ -0,0 +1 @@ +../bullet/firmware.json
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/p650/instruction.json b/tools/perf/pmu-events/arch/riscv/sifive/p650/instruction.json new file mode 120000 index 000000000000..62eacc2d7497 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/p650/instruction.json @@ -0,0 +1 @@ +../bullet/instruction.json
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/p650/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/p650/memory.json new file mode 100644 index 000000000000..f1431b339c7f --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/p650/memory.json @@ -0,0 +1,57 @@ +[ + { + "EventName": "ICACHE_MISS", + "EventCode": "0x102", + "BriefDescription": "Counts instruction cache misses" + }, + { + "EventName": "DCACHE_MISS", + "EventCode": "0x202", + "BriefDescription": "Counts data cache misses" + }, + { + "EventName": "DCACHE_RELEASE", + "EventCode": "0x402", + "BriefDescription": "Counts writeback requests from the data cache" + }, + { + "EventName": "ITLB_MISS", + "EventCode": "0x802", + "BriefDescription": "Counts Instruction TLB misses caused by instruction address translation requests" + }, + { + "EventName": "DTLB_MISS", + "EventCode": "0x1002", + "BriefDescription": "Counts Data TLB misses caused by data address translation requests" + }, + { + "EventName": "UTLB_MISS", + "EventCode": "0x2002", + "BriefDescription": "Counts Unified TLB misses caused by address translation requests" + }, + { + "EventName": "UTLB_HIT", + "EventCode": "0x4002", + "BriefDescription": "Counts Unified TLB hits for address translation requests" + }, + { + "EventName": "PTE_CACHE_MISS", + "EventCode": "0x8002", + "BriefDescription": "Counts Page Table Entry cache misses" + }, + { + "EventName": "PTE_CACHE_HIT", + "EventCode": "0x10002", + "BriefDescription": "Counts Page Table Entry cache hits" + }, + { + "EventName": "ITLB_MULTI_HIT", + "EventCode": "0x20002", + "BriefDescription": "Counts Instruction TLB multi-hits" + }, + { + "EventName": "DTLB_MULTI_HIT", + "EventCode": "0x40002", + "BriefDescription": "Counts Data TLB multi-hits" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/sifive/p650/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/p650/microarch.json new file mode 100644 index 000000000000..de8efd7b8b34 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/p650/microarch.json @@ -0,0 +1,62 @@ +[ + { + "EventName": "ADDRESSGEN_INTERLOCK", + "EventCode": "0x101", + "BriefDescription": "Counts cycles with an address-generation interlock" + }, + { + "EventName": "LONGLATENCY_INTERLOCK", + "EventCode": "0x201", + "BriefDescription": "Counts cycles with a long-latency interlock" + }, + { + "EventName": "CSR_INTERLOCK", + "EventCode": "0x401", + "BriefDescription": "Counts cycles with a CSR interlock" + }, + { + "EventName": "ICACHE_BLOCKED", + "EventCode": "0x801", + "BriefDescription": "Counts cycles in which the instruction cache was not able to provide an instruction" + }, + { + "EventName": "DCACHE_BLOCKED", + "EventCode": "0x1001", + "BriefDescription": "Counts cycles in which the data cache blocked an instruction" + }, + { + "EventName": "BRANCH_DIRECTION_MISPREDICTION", + "EventCode": "0x2001", + "BriefDescription": "Counts mispredictions of conditional branch direction (taken/not taken)" + }, + { + "EventName": "BRANCH_TARGET_MISPREDICTION", + "EventCode": "0x4001", + "BriefDescription": "Counts mispredictions of the target PC of control-flow instructions" + }, + { + "EventName": "PIPELINE_FLUSH", + "EventCode": "0x8001", + "BriefDescription": "Counts flushes of the core pipeline. Common causes include fence.i and CSR accesses" + }, + { + "EventName": "REPLAY", + "EventCode": "0x10001", + "BriefDescription": "Counts instruction replays" + }, + { + "EventName": "INTEGER_MUL_DIV_INTERLOCK", + "EventCode": "0x20001", + "BriefDescription": "Counts cycles with a multiply or divide interlock" + }, + { + "EventName": "FP_INTERLOCK", + "EventCode": "0x40001", + "BriefDescription": "Counts cycles with a floating-point interlock" + }, + { + "EventName": "TRACE_STALL", + "EventCode": "0x80001", + "BriefDescription": "Counts cycles in which the core pipeline is stalled due to backpressure from the Trace Encoder" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/sifive/p650/watchpoint.json b/tools/perf/pmu-events/arch/riscv/sifive/p650/watchpoint.json new file mode 120000 index 000000000000..e88b98bfc5c8 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/p650/watchpoint.json @@ -0,0 +1 @@ +../bullet-07/watchpoint.json
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json deleted file mode 100644 index 5eab718c9256..000000000000 --- a/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json +++ /dev/null @@ -1,92 +0,0 @@ -[ - { - "EventName": "EXCEPTION_TAKEN", - "EventCode": "0x0000100", - "BriefDescription": "Exception taken" - }, - { - "EventName": "INTEGER_LOAD_RETIRED", - "EventCode": "0x0000200", - "BriefDescription": "Integer load instruction retired" - }, - { - "EventName": "INTEGER_STORE_RETIRED", - "EventCode": "0x0000400", - "BriefDescription": "Integer store instruction retired" - }, - { - "EventName": "ATOMIC_MEMORY_RETIRED", - "EventCode": "0x0000800", - "BriefDescription": "Atomic memory operation retired" - }, - { - "EventName": "SYSTEM_INSTRUCTION_RETIRED", - "EventCode": "0x0001000", - "BriefDescription": "System instruction retired" - }, - { - "EventName": "INTEGER_ARITHMETIC_RETIRED", - "EventCode": "0x0002000", - "BriefDescription": "Integer arithmetic instruction retired" - }, - { - "EventName": "CONDITIONAL_BRANCH_RETIRED", - "EventCode": "0x0004000", - "BriefDescription": "Conditional branch retired" - }, - { - "EventName": "JAL_INSTRUCTION_RETIRED", - "EventCode": "0x0008000", - "BriefDescription": "JAL instruction retired" - }, - { - "EventName": "JALR_INSTRUCTION_RETIRED", - "EventCode": "0x0010000", - "BriefDescription": "JALR instruction retired" - }, - { - "EventName": "INTEGER_MULTIPLICATION_RETIRED", - "EventCode": "0x0020000", - "BriefDescription": "Integer multiplication instruction retired" - }, - { - "EventName": "INTEGER_DIVISION_RETIRED", - "EventCode": "0x0040000", - "BriefDescription": "Integer division instruction retired" - }, - { - "EventName": "FP_LOAD_RETIRED", - "EventCode": "0x0080000", - "BriefDescription": "Floating-point load instruction retired" - }, - { - "EventName": "FP_STORE_RETIRED", - "EventCode": "0x0100000", - "BriefDescription": "Floating-point store instruction retired" - }, - { - "EventName": "FP_ADDITION_RETIRED", - "EventCode": "0x0200000", - "BriefDescription": "Floating-point addition retired" - }, - { - "EventName": "FP_MULTIPLICATION_RETIRED", - "EventCode": "0x0400000", - "BriefDescription": "Floating-point multiplication retired" - }, - { - "EventName": "FP_FUSEDMADD_RETIRED", - "EventCode": "0x0800000", - "BriefDescription": "Floating-point fused multiply-add retired" - }, - { - "EventName": "FP_DIV_SQRT_RETIRED", - "EventCode": "0x1000000", - "BriefDescription": "Floating-point division or square-root retired" - }, - { - "EventName": "OTHER_FP_RETIRED", - "EventCode": "0x2000000", - "BriefDescription": "Other floating-point instruction retired" - } -]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json deleted file mode 100644 index be1a46312ac3..000000000000 --- a/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json +++ /dev/null @@ -1,32 +0,0 @@ -[ - { - "EventName": "ICACHE_RETIRED", - "EventCode": "0x0000102", - "BriefDescription": "Instruction cache miss" - }, - { - "EventName": "DCACHE_MISS_MMIO_ACCESSES", - "EventCode": "0x0000202", - "BriefDescription": "Data cache miss or memory-mapped I/O access" - }, - { - "EventName": "DCACHE_WRITEBACK", - "EventCode": "0x0000402", - "BriefDescription": "Data cache write-back" - }, - { - "EventName": "INST_TLB_MISS", - "EventCode": "0x0000802", - "BriefDescription": "Instruction TLB miss" - }, - { - "EventName": "DATA_TLB_MISS", - "EventCode": "0x0001002", - "BriefDescription": "Data TLB miss" - }, - { - "EventName": "UTLB_MISS", - "EventCode": "0x0002002", - "BriefDescription": "UTLB miss" - } -]
\ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json deleted file mode 100644 index 50ffa55418cb..000000000000 --- a/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json +++ /dev/null @@ -1,57 +0,0 @@ -[ - { - "EventName": "ADDRESSGEN_INTERLOCK", - "EventCode": "0x0000101", - "BriefDescription": "Address-generation interlock" - }, - { - "EventName": "LONGLAT_INTERLOCK", - "EventCode": "0x0000201", - "BriefDescription": "Long-latency interlock" - }, - { - "EventName": "CSR_READ_INTERLOCK", - "EventCode": "0x0000401", - "BriefDescription": "CSR read interlock" - }, - { - "EventName": "ICACHE_ITIM_BUSY", - "EventCode": "0x0000801", - "BriefDescription": "Instruction cache/ITIM busy" - }, - { - "EventName": "DCACHE_DTIM_BUSY", - "EventCode": "0x0001001", - "BriefDescription": "Data cache/DTIM busy" - }, - { - "EventName": "BRANCH_DIRECTION_MISPREDICTION", - "EventCode": "0x0002001", - "BriefDescription": "Branch direction misprediction" - }, - { - "EventName": "BRANCH_TARGET_MISPREDICTION", - "EventCode": "0x0004001", - "BriefDescription": "Branch/jump target misprediction" - }, - { - "EventName": "PIPE_FLUSH_CSR_WRITE", - "EventCode": "0x0008001", - "BriefDescription": "Pipeline flush from CSR write" - }, - { - "EventName": "PIPE_FLUSH_OTHER_EVENT", - "EventCode": "0x0010001", - "BriefDescription": "Pipeline flush from other event" - }, - { - "EventName": "INTEGER_MULTIPLICATION_INTERLOCK", - "EventCode": "0x0020001", - "BriefDescription": "Integer multiplication interlock" - }, - { - "EventName": "FP_INTERLOCK", - "EventCode": "0x0040001", - "BriefDescription": "Floating-point interlock" - } -]
\ No newline at end of file |