diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/icelake/cache.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/icelake/cache.json | 94 |
1 files changed, 72 insertions, 22 deletions
diff --git a/tools/perf/pmu-events/arch/x86/icelake/cache.json b/tools/perf/pmu-events/arch/x86/icelake/cache.json index 3508340acd0e..e7bb2ca6f183 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/cache.json +++ b/tools/perf/pmu-events/arch/x86/icelake/cache.json @@ -75,11 +75,11 @@ "UMask": "0x2" }, { - "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.", + "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache.", "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.SILENT", - "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.", + "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache. These lines are typically in Shared or Exclusive state. A non-threaded event.", "SampleAfterValue": "200003", "UMask": "0x1" }, @@ -251,7 +251,6 @@ "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ALL_LOADS", - "PEBS": "1", "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.", "SampleAfterValue": "1000003", "UMask": "0x81" @@ -262,7 +261,6 @@ "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ALL_STORES", - "PEBS": "1", "PublicDescription": "Counts all retired store instructions.", "SampleAfterValue": "1000003", "UMask": "0x82" @@ -273,7 +271,6 @@ "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ANY", - "PEBS": "1", "PublicDescription": "Counts all retired memory instructions - loads and stores.", "SampleAfterValue": "1000003", "UMask": "0x83" @@ -284,7 +281,6 @@ "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.LOCK_LOADS", - "PEBS": "1", "PublicDescription": "Counts retired load instructions with locked access.", "SampleAfterValue": "100007", "UMask": "0x21" @@ -295,7 +291,6 @@ "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", - "PEBS": "1", "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.", "SampleAfterValue": "100003", "UMask": "0x41" @@ -306,7 +301,6 @@ "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.SPLIT_STORES", - "PEBS": "1", "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.", "SampleAfterValue": "100003", "UMask": "0x42" @@ -317,7 +311,6 @@ "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", - "PEBS": "1", "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).", "SampleAfterValue": "100003", "UMask": "0x11" @@ -328,7 +321,6 @@ "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", - "PEBS": "1", "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).", "SampleAfterValue": "100003", "UMask": "0x12" @@ -339,7 +331,6 @@ "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", - "PEBS": "1", "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.", "SampleAfterValue": "20011", "UMask": "0x2" @@ -350,7 +341,6 @@ "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", - "PEBS": "1", "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.", "SampleAfterValue": "20011", "UMask": "0x4" @@ -361,7 +351,6 @@ "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", - "PEBS": "1", "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", "SampleAfterValue": "20011", "UMask": "0x1" @@ -372,7 +361,6 @@ "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", - "PEBS": "1", "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.", "SampleAfterValue": "100003", "UMask": "0x8" @@ -383,7 +371,6 @@ "Data_LA": "1", "EventCode": "0xd4", "EventName": "MEM_LOAD_MISC_RETIRED.UC", - "PEBS": "1", "PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock).", "SampleAfterValue": "100007", "UMask": "0x4" @@ -394,7 +381,6 @@ "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.FB_HIT", - "PEBS": "1", "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.", "SampleAfterValue": "100007", "UMask": "0x40" @@ -405,7 +391,6 @@ "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L1_HIT", - "PEBS": "1", "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.", "SampleAfterValue": "1000003", "UMask": "0x1" @@ -416,7 +401,6 @@ "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L1_MISS", - "PEBS": "1", "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.", "SampleAfterValue": "200003", "UMask": "0x8" @@ -427,7 +411,6 @@ "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L2_HIT", - "PEBS": "1", "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.", "SampleAfterValue": "200003", "UMask": "0x2" @@ -438,7 +421,6 @@ "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L2_MISS", - "PEBS": "1", "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.", "SampleAfterValue": "100021", "UMask": "0x10" @@ -449,7 +431,6 @@ "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L3_HIT", - "PEBS": "1", "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.", "SampleAfterValue": "100021", "UMask": "0x4" @@ -460,12 +441,21 @@ "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L3_MISS", - "PEBS": "1", "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.", "SampleAfterValue": "50021", "UMask": "0x20" }, { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10004", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -526,6 +516,16 @@ "UMask": "0x1" }, { + "BriefDescription": "Counts demand data reads that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -586,6 +586,16 @@ "UMask": "0x1" }, { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10002", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -646,6 +656,16 @@ "UMask": "0x1" }, { + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10400", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -676,6 +696,16 @@ "UMask": "0x1" }, { + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10010", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -736,6 +766,16 @@ "UMask": "0x1" }, { + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10020", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", @@ -911,6 +951,16 @@ "UMask": "0x8" }, { + "BriefDescription": "Cycles with outstanding code read requests pending.", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", + "PublicDescription": "Cycles with outstanding code read requests pending. Code Read requests include both cacheable and non-cacheable Code Reads. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { "BriefDescription": "Cycles where at least 1 outstanding Demand RFO request is pending.", "Counter": "0,1,2,3", "CounterMask": "1", |