diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json | 353 |
1 files changed, 353 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json index d025e2c0cf1c..0cd571472dca 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles L1D locked", + "Counter": "0,1", "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Cycles L1D and L2 locked", + "Counter": "0,1", "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D_L2", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "L1D cache lines replaced in M state", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.M_EVICT", "SampleAfterValue": "2000000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "L1D cache lines allocated in the M state", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.M_REPL", "SampleAfterValue": "2000000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "L1D snoop eviction of cache lines in M state", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.M_SNOOP_EVICT", "SampleAfterValue": "2000000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "L1 data cache lines allocated", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.REPL", "SampleAfterValue": "2000000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "L1D prefetch load lock accepted in fill buffer", + "Counter": "0,1", "EventCode": "0x52", "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", "SampleAfterValue": "2000000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "L1D hardware prefetch misses", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "L1D_PREFETCH.MISS", "SampleAfterValue": "200000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "L1D hardware prefetch requests", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "L1D_PREFETCH.REQUESTS", "SampleAfterValue": "200000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "L1D hardware prefetch requests triggered", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "L1D_PREFETCH.TRIGGERS", "SampleAfterValue": "200000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in E state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.E_STATE", "SampleAfterValue": "100000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.I_STATE", "SampleAfterValue": "100000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "All L1 writebacks to L2", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.MESI", "SampleAfterValue": "100000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in M state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.M_STATE", "SampleAfterValue": "100000", @@ -99,13 +113,47 @@ }, { "BriefDescription": "L1 writebacks to L2 in S state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.S_STATE", "SampleAfterValue": "100000", "UMask": "0x2" }, { + "BriefDescription": "L1I instruction fetch stall cycles", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "L1I.CYCLES_STALLED", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "L1I instruction fetch hits", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "L1I.HITS", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "L1I instruction fetch misses", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "L1I.MISSES", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "L1I Instruction fetches", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "L1I.READS", + "SampleAfterValue": "2000000", + "UMask": "0x3" + }, + { "BriefDescription": "All L2 data requests", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.ANY", "SampleAfterValue": "200000", @@ -113,6 +161,7 @@ }, { "BriefDescription": "L2 data demand loads in E state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", "SampleAfterValue": "200000", @@ -120,6 +169,7 @@ }, { "BriefDescription": "L2 data demand loads in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", "SampleAfterValue": "200000", @@ -127,6 +177,7 @@ }, { "BriefDescription": "L2 data demand requests", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.MESI", "SampleAfterValue": "200000", @@ -134,6 +185,7 @@ }, { "BriefDescription": "L2 data demand loads in M state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", "SampleAfterValue": "200000", @@ -141,6 +193,7 @@ }, { "BriefDescription": "L2 data demand loads in S state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", "SampleAfterValue": "200000", @@ -148,6 +201,7 @@ }, { "BriefDescription": "L2 data prefetches in E state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", "SampleAfterValue": "200000", @@ -155,6 +209,7 @@ }, { "BriefDescription": "L2 data prefetches in the I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", "SampleAfterValue": "200000", @@ -162,6 +217,7 @@ }, { "BriefDescription": "All L2 data prefetches", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", "SampleAfterValue": "200000", @@ -169,6 +225,7 @@ }, { "BriefDescription": "L2 data prefetches in M state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", "SampleAfterValue": "200000", @@ -176,6 +233,7 @@ }, { "BriefDescription": "L2 data prefetches in the S state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", "SampleAfterValue": "200000", @@ -183,6 +241,7 @@ }, { "BriefDescription": "L2 lines allocated", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ANY", "SampleAfterValue": "100000", @@ -190,6 +249,7 @@ }, { "BriefDescription": "L2 lines allocated in the E state", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.E_STATE", "SampleAfterValue": "100000", @@ -197,6 +257,7 @@ }, { "BriefDescription": "L2 lines allocated in the S state", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.S_STATE", "SampleAfterValue": "100000", @@ -204,6 +265,7 @@ }, { "BriefDescription": "L2 lines evicted", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.ANY", "SampleAfterValue": "100000", @@ -211,6 +273,7 @@ }, { "BriefDescription": "L2 lines evicted by a demand request", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100000", @@ -218,6 +281,7 @@ }, { "BriefDescription": "L2 modified lines evicted by a demand request", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "SampleAfterValue": "100000", @@ -225,6 +289,7 @@ }, { "BriefDescription": "L2 lines evicted by a prefetch request", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", "SampleAfterValue": "100000", @@ -232,6 +297,7 @@ }, { "BriefDescription": "L2 modified lines evicted by a prefetch request", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", "SampleAfterValue": "100000", @@ -239,6 +305,7 @@ }, { "BriefDescription": "L2 instruction fetches", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.IFETCHES", "SampleAfterValue": "200000", @@ -246,6 +313,7 @@ }, { "BriefDescription": "L2 instruction fetch hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.IFETCH_HIT", "SampleAfterValue": "200000", @@ -253,6 +321,7 @@ }, { "BriefDescription": "L2 instruction fetch misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.IFETCH_MISS", "SampleAfterValue": "200000", @@ -260,6 +329,7 @@ }, { "BriefDescription": "L2 load hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.LD_HIT", "SampleAfterValue": "200000", @@ -267,6 +337,7 @@ }, { "BriefDescription": "L2 load misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.LD_MISS", "SampleAfterValue": "200000", @@ -274,6 +345,7 @@ }, { "BriefDescription": "L2 requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.LOADS", "SampleAfterValue": "200000", @@ -281,6 +353,7 @@ }, { "BriefDescription": "All L2 misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "SampleAfterValue": "200000", @@ -288,6 +361,7 @@ }, { "BriefDescription": "All L2 prefetches", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCHES", "SampleAfterValue": "200000", @@ -295,6 +369,7 @@ }, { "BriefDescription": "L2 prefetch hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_HIT", "SampleAfterValue": "200000", @@ -302,6 +377,7 @@ }, { "BriefDescription": "L2 prefetch misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_MISS", "SampleAfterValue": "200000", @@ -309,6 +385,7 @@ }, { "BriefDescription": "All L2 requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "SampleAfterValue": "200000", @@ -316,6 +393,7 @@ }, { "BriefDescription": "L2 RFO requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFOS", "SampleAfterValue": "200000", @@ -323,6 +401,7 @@ }, { "BriefDescription": "L2 RFO hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200000", @@ -330,6 +409,7 @@ }, { "BriefDescription": "L2 RFO misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "SampleAfterValue": "200000", @@ -337,6 +417,7 @@ }, { "BriefDescription": "All L2 transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.ANY", "SampleAfterValue": "200000", @@ -344,6 +425,7 @@ }, { "BriefDescription": "L2 fill transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.FILL", "SampleAfterValue": "200000", @@ -351,6 +433,7 @@ }, { "BriefDescription": "L2 instruction fetch transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.IFETCH", "SampleAfterValue": "200000", @@ -358,6 +441,7 @@ }, { "BriefDescription": "L1D writeback to L2 transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.L1D_WB", "SampleAfterValue": "200000", @@ -365,6 +449,7 @@ }, { "BriefDescription": "L2 Load transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.LOAD", "SampleAfterValue": "200000", @@ -372,6 +457,7 @@ }, { "BriefDescription": "L2 prefetch transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.PREFETCH", "SampleAfterValue": "200000", @@ -379,6 +465,7 @@ }, { "BriefDescription": "L2 RFO transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.RFO", "SampleAfterValue": "200000", @@ -386,6 +473,7 @@ }, { "BriefDescription": "L2 writeback to LLC transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.WB", "SampleAfterValue": "200000", @@ -393,6 +481,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in E state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.E_STATE", "SampleAfterValue": "100000", @@ -400,6 +489,7 @@ }, { "BriefDescription": "All demand L2 lock RFOs that hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.HIT", "SampleAfterValue": "100000", @@ -407,6 +497,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.I_STATE", "SampleAfterValue": "100000", @@ -414,6 +505,7 @@ }, { "BriefDescription": "All demand L2 lock RFOs", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.MESI", "SampleAfterValue": "100000", @@ -421,6 +513,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in M state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.M_STATE", "SampleAfterValue": "100000", @@ -428,6 +521,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in S state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.S_STATE", "SampleAfterValue": "100000", @@ -435,6 +529,7 @@ }, { "BriefDescription": "All L2 demand store RFOs that hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.HIT", "SampleAfterValue": "100000", @@ -442,6 +537,7 @@ }, { "BriefDescription": "L2 demand store RFOs in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.I_STATE", "SampleAfterValue": "100000", @@ -449,6 +545,7 @@ }, { "BriefDescription": "All L2 demand store RFOs", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.MESI", "SampleAfterValue": "100000", @@ -456,6 +553,7 @@ }, { "BriefDescription": "L2 demand store RFOs in M state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.M_STATE", "SampleAfterValue": "100000", @@ -463,6 +561,7 @@ }, { "BriefDescription": "L2 demand store RFOs in S state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.S_STATE", "SampleAfterValue": "100000", @@ -470,6 +569,7 @@ }, { "BriefDescription": "Longest latency cache miss", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "SampleAfterValue": "100000", @@ -477,6 +577,7 @@ }, { "BriefDescription": "Longest latency cache reference", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "SampleAfterValue": "200000", @@ -484,6 +585,7 @@ }, { "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", "MSRIndex": "0x3F6", @@ -493,6 +595,7 @@ }, { "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", "MSRIndex": "0x3F6", @@ -503,6 +606,7 @@ }, { "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", "MSRIndex": "0x3F6", @@ -513,6 +617,7 @@ }, { "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", "MSRIndex": "0x3F6", @@ -523,6 +628,7 @@ }, { "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", "MSRIndex": "0x3F6", @@ -533,6 +639,7 @@ }, { "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", "MSRIndex": "0x3F6", @@ -543,6 +650,7 @@ }, { "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", "MSRIndex": "0x3F6", @@ -553,6 +661,7 @@ }, { "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", "MSRIndex": "0x3F6", @@ -563,6 +672,7 @@ }, { "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", "MSRIndex": "0x3F6", @@ -573,6 +683,7 @@ }, { "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", "MSRIndex": "0x3F6", @@ -583,6 +694,7 @@ }, { "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", "MSRIndex": "0x3F6", @@ -593,6 +705,7 @@ }, { "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", "MSRIndex": "0x3F6", @@ -603,6 +716,7 @@ }, { "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", "MSRIndex": "0x3F6", @@ -613,6 +727,7 @@ }, { "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", "MSRIndex": "0x3F6", @@ -623,6 +738,7 @@ }, { "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", "MSRIndex": "0x3F6", @@ -633,6 +749,7 @@ }, { "BriefDescription": "Instructions retired which contains a load (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LOADS", "PEBS": "1", @@ -641,6 +758,7 @@ }, { "BriefDescription": "Instructions retired which contains a store (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.STORES", "PEBS": "1", @@ -649,6 +767,7 @@ }, { "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.HIT_LFB", "PEBS": "1", @@ -657,6 +776,7 @@ }, { "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.L1D_HIT", "PEBS": "1", @@ -665,6 +785,7 @@ }, { "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.L2_HIT", "PEBS": "1", @@ -673,6 +794,7 @@ }, { "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.LLC_MISS", "PEBS": "1", @@ -681,6 +803,7 @@ }, { "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", "PEBS": "1", @@ -689,6 +812,7 @@ }, { "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", "PEBS": "1", @@ -697,6 +821,7 @@ }, { "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM", "PEBS": "1", @@ -705,6 +830,7 @@ }, { "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", "PEBS": "1", @@ -713,6 +839,7 @@ }, { "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT", "PEBS": "1", @@ -721,6 +848,7 @@ }, { "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", "PEBS": "1", @@ -729,6 +857,7 @@ }, { "BriefDescription": "Load instructions retired IO (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", "PEBS": "1", @@ -737,6 +866,7 @@ }, { "BriefDescription": "All offcore requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY", "SampleAfterValue": "100000", @@ -744,6 +874,7 @@ }, { "BriefDescription": "Offcore read requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY.READ", "SampleAfterValue": "100000", @@ -751,6 +882,7 @@ }, { "BriefDescription": "Offcore RFO requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY.RFO", "SampleAfterValue": "100000", @@ -758,6 +890,7 @@ }, { "BriefDescription": "Offcore demand code read requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", "SampleAfterValue": "100000", @@ -765,6 +898,7 @@ }, { "BriefDescription": "Offcore demand data read requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", "SampleAfterValue": "100000", @@ -772,6 +906,7 @@ }, { "BriefDescription": "Offcore demand RFO requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", "SampleAfterValue": "100000", @@ -779,6 +914,7 @@ }, { "BriefDescription": "Offcore L1 data cache writebacks", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", "SampleAfterValue": "100000", @@ -786,6 +922,7 @@ }, { "BriefDescription": "Offcore uncached memory accesses", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.UNCACHED_MEM", "SampleAfterValue": "100000", @@ -793,6 +930,7 @@ }, { "BriefDescription": "Outstanding offcore reads", + "Counter": "0", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", "SampleAfterValue": "2000000", @@ -800,6 +938,7 @@ }, { "BriefDescription": "Cycles offcore reads busy", + "Counter": "0", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", @@ -808,6 +947,7 @@ }, { "BriefDescription": "Outstanding offcore demand code reads", + "Counter": "0", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", "SampleAfterValue": "2000000", @@ -815,6 +955,7 @@ }, { "BriefDescription": "Cycles offcore demand code read busy", + "Counter": "0", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY", @@ -823,6 +964,7 @@ }, { "BriefDescription": "Outstanding offcore demand data reads", + "Counter": "0", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", "SampleAfterValue": "2000000", @@ -830,6 +972,7 @@ }, { "BriefDescription": "Cycles offcore demand data read busy", + "Counter": "0", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY", @@ -838,6 +981,7 @@ }, { "BriefDescription": "Outstanding offcore demand RFOs", + "Counter": "0", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", "SampleAfterValue": "2000000", @@ -845,6 +989,7 @@ }, { "BriefDescription": "Cycles offcore demand RFOs busy", + "Counter": "0", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", @@ -853,6 +998,7 @@ }, { "BriefDescription": "Offcore requests blocked due to Super Queue full", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "OFFCORE_REQUESTS_SQ_FULL", "SampleAfterValue": "100000", @@ -860,6 +1006,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -869,6 +1016,7 @@ }, { "BriefDescription": "All offcore data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -878,6 +1026,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -887,6 +1036,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -896,6 +1046,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -905,6 +1056,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -914,6 +1066,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -923,6 +1076,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -932,6 +1086,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -941,6 +1096,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -950,6 +1106,7 @@ }, { "BriefDescription": "Offcore data reads that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -959,6 +1116,7 @@ }, { "BriefDescription": "Offcore data reads that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -968,6 +1126,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -977,6 +1136,7 @@ }, { "BriefDescription": "All offcore code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -986,6 +1146,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -995,6 +1156,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1004,6 +1166,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1013,6 +1176,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1022,6 +1186,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1031,6 +1196,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1040,6 +1206,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1049,6 +1216,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1058,6 +1226,7 @@ }, { "BriefDescription": "Offcore code reads that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1067,6 +1236,7 @@ }, { "BriefDescription": "Offcore code reads that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1076,6 +1246,7 @@ }, { "BriefDescription": "Offcore requests satisfied by any cache or DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1085,6 +1256,7 @@ }, { "BriefDescription": "All offcore requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1094,6 +1266,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1103,6 +1276,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1112,6 +1286,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1121,6 +1296,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1130,6 +1306,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1139,6 +1316,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1148,6 +1326,7 @@ }, { "BriefDescription": "Offcore requests satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1157,6 +1336,7 @@ }, { "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1166,6 +1346,7 @@ }, { "BriefDescription": "Offcore requests that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1175,6 +1356,7 @@ }, { "BriefDescription": "Offcore requests that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1184,6 +1366,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1193,6 +1376,7 @@ }, { "BriefDescription": "All offcore RFO requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1202,6 +1386,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1211,6 +1396,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1220,6 +1406,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1229,6 +1416,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1238,6 +1426,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1247,6 +1436,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1256,6 +1446,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1265,6 +1456,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1274,6 +1466,7 @@ }, { "BriefDescription": "Offcore RFO requests that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1283,6 +1476,7 @@ }, { "BriefDescription": "Offcore RFO requests that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1292,6 +1486,7 @@ }, { "BriefDescription": "Offcore writebacks to any cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1301,6 +1496,7 @@ }, { "BriefDescription": "All offcore writebacks", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1310,6 +1506,7 @@ }, { "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1319,6 +1516,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1328,6 +1526,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1337,6 +1536,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1346,6 +1546,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1355,6 +1556,7 @@ }, { "BriefDescription": "Offcore writebacks to a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1364,6 +1566,7 @@ }, { "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1373,6 +1576,7 @@ }, { "BriefDescription": "Offcore writebacks that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1382,6 +1586,7 @@ }, { "BriefDescription": "Offcore writebacks that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1391,6 +1596,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1400,6 +1606,7 @@ }, { "BriefDescription": "All offcore code or data read requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1409,6 +1616,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1418,6 +1626,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1427,6 +1636,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1436,6 +1646,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1445,6 +1656,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1454,6 +1666,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1463,6 +1676,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1472,6 +1686,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1481,6 +1696,7 @@ }, { "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1490,6 +1706,7 @@ }, { "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1499,6 +1716,7 @@ }, { "BriefDescription": "Offcore request = all data, response = any cache_dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1508,6 +1726,7 @@ }, { "BriefDescription": "Offcore request = all data, response = any location", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1517,6 +1736,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1526,6 +1746,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1535,6 +1756,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1544,6 +1766,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1553,6 +1776,7 @@ }, { "BriefDescription": "Offcore request = all data, response = local cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1562,6 +1786,7 @@ }, { "BriefDescription": "Offcore request = all data, response = local cache or dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1571,6 +1796,7 @@ }, { "BriefDescription": "Offcore request = all data, response = remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1580,6 +1806,7 @@ }, { "BriefDescription": "Offcore request = all data, response = remote cache or dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1589,6 +1816,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1598,6 +1826,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1607,6 +1836,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1616,6 +1846,7 @@ }, { "BriefDescription": "All offcore demand data requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1625,6 +1856,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1634,6 +1866,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1643,6 +1876,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1652,6 +1886,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1661,6 +1896,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1670,6 +1906,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1679,6 +1916,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1688,6 +1926,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1697,6 +1936,7 @@ }, { "BriefDescription": "Offcore demand data requests that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1706,6 +1946,7 @@ }, { "BriefDescription": "Offcore demand data requests that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1715,6 +1956,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1724,6 +1966,7 @@ }, { "BriefDescription": "All offcore demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1733,6 +1976,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1742,6 +1986,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1751,6 +1996,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1760,6 +2006,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1769,6 +2016,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1778,6 +2026,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1787,6 +2036,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1796,6 +2046,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1805,6 +2056,7 @@ }, { "BriefDescription": "Offcore demand data reads that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1814,6 +2066,7 @@ }, { "BriefDescription": "Offcore demand data reads that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1823,6 +2076,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1832,6 +2086,7 @@ }, { "BriefDescription": "All offcore demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1841,6 +2096,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1850,6 +2106,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1859,6 +2116,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1868,6 +2126,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1877,6 +2136,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1886,6 +2146,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1895,6 +2156,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1904,6 +2166,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1913,6 +2176,7 @@ }, { "BriefDescription": "Offcore demand code reads that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1922,6 +2186,7 @@ }, { "BriefDescription": "Offcore demand code reads that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1931,6 +2196,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1940,6 +2206,7 @@ }, { "BriefDescription": "All offcore demand RFO requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1949,6 +2216,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1958,6 +2226,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1967,6 +2236,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1976,6 +2246,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1985,6 +2256,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1994,6 +2266,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2003,6 +2276,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2012,6 +2286,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2021,6 +2296,7 @@ }, { "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2030,6 +2306,7 @@ }, { "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2039,6 +2316,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2048,6 +2326,7 @@ }, { "BriefDescription": "All offcore other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -2057,6 +2336,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -2066,6 +2346,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2075,6 +2356,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2084,6 +2366,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2093,6 +2376,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2102,6 +2386,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2111,6 +2396,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2120,6 +2406,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2129,6 +2416,7 @@ }, { "BriefDescription": "Offcore other requests that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2138,6 +2426,7 @@ }, { "BriefDescription": "Offcore other requests that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2147,6 +2436,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2156,6 +2446,7 @@ }, { "BriefDescription": "All offcore prefetch data requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -2165,6 +2456,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -2174,6 +2466,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2183,6 +2476,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2192,6 +2486,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2201,6 +2496,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2210,6 +2506,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2219,6 +2516,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2228,6 +2526,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2237,6 +2536,7 @@ }, { "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2246,6 +2546,7 @@ }, { "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2255,6 +2556,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2264,6 +2566,7 @@ }, { "BriefDescription": "All offcore prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -2273,6 +2576,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -2282,6 +2586,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2291,6 +2596,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2300,6 +2606,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2309,6 +2616,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2318,6 +2626,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2327,6 +2636,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2336,6 +2646,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2345,6 +2656,7 @@ }, { "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2354,6 +2666,7 @@ }, { "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2363,6 +2676,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2372,6 +2686,7 @@ }, { "BriefDescription": "All offcore prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -2381,6 +2696,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -2390,6 +2706,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2399,6 +2716,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2408,6 +2726,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2417,6 +2736,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2426,6 +2746,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2435,6 +2756,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2444,6 +2766,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2453,6 +2776,7 @@ }, { "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2462,6 +2786,7 @@ }, { "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2471,6 +2796,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2480,6 +2806,7 @@ }, { "BriefDescription": "All offcore prefetch RFO requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -2489,6 +2816,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -2498,6 +2826,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2507,6 +2836,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2516,6 +2846,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2525,6 +2856,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2534,6 +2866,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2543,6 +2876,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2552,6 +2886,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2561,6 +2896,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2570,6 +2906,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2579,6 +2916,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2588,6 +2926,7 @@ }, { "BriefDescription": "All offcore prefetch requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -2597,6 +2936,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -2606,6 +2946,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2615,6 +2956,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2624,6 +2966,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2633,6 +2976,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2642,6 +2986,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2651,6 +2996,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2660,6 +3006,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2669,6 +3016,7 @@ }, { "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2678,6 +3026,7 @@ }, { "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2687,6 +3036,7 @@ }, { "BriefDescription": "Super Queue LRU hints sent to LLC", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.LRU_HINTS", "SampleAfterValue": "2000000", @@ -2694,6 +3044,7 @@ }, { "BriefDescription": "Super Queue lock splits across a cache line", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.SPLIT_LOCK", "SampleAfterValue": "2000000", @@ -2701,6 +3052,7 @@ }, { "BriefDescription": "Loads delayed with at-Retirement block code", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "STORE_BLOCKS.AT_RET", "SampleAfterValue": "200000", @@ -2708,6 +3060,7 @@ }, { "BriefDescription": "Cacheable loads delayed with L1D block code", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "STORE_BLOCKS.L1D_BLOCK", "SampleAfterValue": "200000", |