summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* net: mvpp2: ptp: add support for transmit timestampingmcbinRussell King2020-09-092-11/+244
| | | | | | | Add support for timestamping transmit packets. We allocate SYNC messages to queue 1, every other message to queue 0. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: mvpp2: ptp: add support for receive timestampingRussell King2020-09-093-2/+194
| | | | | | | | | | | | | | | Add support for receive timestamping. When enabled, the hardware adds a timestamp into the receive queue descriptor for all received packets with no filtering. Hence, we can only support NONE or ALL receive filter modes. The timestamp in the receive queue contains two bit sof seconds and the full nanosecond timestamp. This has to be merged with the remainder of the seconds from the TAI clock to arrive at a full timestamp before we can convert it to a ktime for the skb hardware timestamp field. Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: mvpp2: ptp: add TAI supportRussell King2020-09-095-1/+521
| | | | | | | Add support for the TAI block in the mvpp2.2 hardware. Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: mvpp2: check first level interrupt status registersRussell King2020-09-092-2/+15
| | | | | | | | | | Check the first level interrupt status registers to determine how to further process the port interrupt. We will need this to know whether to invoke the link status processing and/or the PTP processing for both XLG and GMAC. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: mvpp2: rename mis-named "link status" interruptRussell King2020-09-092-18/+19
| | | | | | | | | | | | | | | The link interrupt is used for way more than just the link status; it comes from a collection of units to do with the port. The Marvell documentation describes the interrupt as "GOP port X interrupt". Since we are adding PTP support, and the PTP interrupt uses this, rename it to be more inline with the documentation. This interrupt is also mis-named in the DT binding, but we leave that alone. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: mvpp2: restructure "link status" interrupt handlingRussell King2020-09-091-32/+51
| | | | | | | | The "link status" interrupt is used for more than just link status. Restructure mvpp2_link_status_isr() so we can add additional handling. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: ethtool: allow MAC drivers to override ethtool get_ts_infoRussell King2020-09-021-2/+6
| | | | | | | | | | Check whether the MAC driver has implemented the get_ts_info() method first, and call it if present. If this method returns -EOPNOTSUPP, defer to the phylib or default implementation. XXX: review any drivers that use phylib and provide get_ts_info(). Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: mvpp2: split xlg and gmac pcsRussell King2020-09-021-55/+55
| | | | | | | Split the XLG and GMAC PCS implementations and switch between them during the mac_prepare() method. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: mvpp2: convert to phylink pcs operationsRussell King2020-09-022-118/+178
| | | | | | Convert mvpp2 to phylink's new pcs support. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: mvpp2: move GMAC reset handling into mac_prepare()/mac_finish()Russell King2020-09-021-32/+21
| | | | | | Move the GMAC reset handling into mac_prepare() / mac_finish() Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: mvpp2: ensure the port is forced down while changing modesRussell King2020-09-021-11/+36
| | | | | | | | Ensure that the port is forced down while reconfiguring, controlling this via mac_prepare() and mac_finish() so that it is down while we are configuring our (future) PCS. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: mvpp2: convert to use mac_prepare()/mac_finish()Russell King2020-09-021-11/+37
| | | | | | | Convert mvpp2 to use the mac_prepare() and mac_finish() methods in preparation to converting mvpp2 to split-PCS support. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: mvpp2: tidy up ACPI hackRussell King2020-09-021-18/+18
| | | | | | | Tidy up the ACPI hack so that we can minimise the function prototypes for this. This avoids adding further prototypes unnecessarily. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* Dont-Auto-BuildRussell King2020-09-021-0/+1
| | | | This commit is to tell the 0-day builder to avoid building this branch.
* arm64: hacks and debugging from initial mcbin bringupRussell King2020-09-021-0/+127
| | | | Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* arm64: dts: marvell: mcbin: use in-band-status for eth2Russell King2020-09-021-0/+1
| | | | | | Use in-band-status for the SGMII PHY on Macchiatobin platforms. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* arm64: dts: marvell: mcbin: workaround wrongly wired i2c1 busRussell King2020-09-023-2/+29
| | | | | | | | The I2C1 bus on early mcbin hardware is mis-wired, swapping SCL and SDA. Work around this by using the i2c-gpio driver instead. XXX Caught early and this commit should be removed for mainline. XXX Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* arm64: dts: marvell: mcbin: use sfp+ compatible for sfp+ slotsRussell King2020-09-021-2/+2
| | | | Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* arm64: dts: marvell: mcbin: add pinctrls for 10G PHYsRussell King2020-09-021-0/+38
| | | | | | Add the pinctrl settings and interrupts for the 10G PHYs. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* arm64: dts: marvell: mcbin: add remainder of pinctrlsRussell King2020-09-021-1/+14
| | | | | | | Add several pinctrls for functions brought out to connectors but not yet usable with the core DT description. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* arm64: dts: marvell: mcbin: add comments about unused MPP pinsRussell King2020-09-021-0/+1
| | | | | | Comment about the use of currently unconfigured MPP pins. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* arm64: dts: marvell: mcbin: add pwm-fanRussell King2020-09-021-0/+11
| | | | | | | | | | | Add pwm-fan support for controlling the fan speed, which allows the fan speed to be controlled via sysfs. Alternatively, users can also add their cooling maps to DT which will be specific to the environment that they house the Macchiatobin, as well as their fan setup. For example, one may connect PWM controlled case fans to this connector, and use the PWM signal to control the case fans. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* arm64: dts: marvell: clearfog-gt-8k: add cooling mapsRussell King2020-09-021-1/+121
| | | | | | | | | Add cooling maps suitable for a Noctua NF-A4/10 fan attached to the heat sink. The fan will toggle between two speeds in operation which seems to be normal behaviour. More fine-grained steps may help to reduce this. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* arm64: dts: marvell: clearfog-gt-8k: add pwm-fanRussell King2020-09-021-0/+7
| | | | | | Add pwm-fan support for controlling the fan speed. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* arm64: dts: marvell: armada-cp11x: add pwm support to GPIO blocksRussell King2020-09-021-0/+6
| | | | | | Add PWM support to the GPIO blocks. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* gpio: mvebu: add PWM support for Armada 8kRussell King2020-09-021-45/+110
| | | | | | | | Add support for PWM devices on the Armada 8k, which are useful on the Macchiatobin and Clearfog GT 8K platforms for controlling the fan speed. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* gpio: mvebu: honour EPROBE_DEFER for devm_clk_get()Russell King2020-09-021-0/+3
| | | | | | | Honour deferred probing for devm_clk_get() so that we can get the clock for PWM. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* gpio: mvebu: convert pwm to regmapRussell King2020-09-021-28/+37
| | | | | | | Convert mvebu's pwm support to use regmap to access the registers to prepare the driver to support the "blink" support on CP110. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* gpio: mvebu: fix PWM period calculationRussell King2020-09-021-14/+10
| | | | | | | | The period of a PWM signal is the sum of the on and off durations. The calculation being used by gpio-mvebu is not correct, resulting in the period being miscalculated and invalid. Fix this. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* usb: host: xhci: mvebu: add reset on resume quirkOfer Heifetz2020-09-021-0/+10
| | | | | | | | | | | | The resume operation of mvebu xHCI host have some issues, so The XHCI_RESET_ON_RESUME quirk is added for it. Signed-off-by: Ofer Heifetz <oferh@marvell.com> Tested-by: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Lior Amsalem <alior@marvell.com> Tested-by: Lior Amsalem <alior@marvell.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: mvgmac: support different hw versionsRussell King2020-09-023-10/+108
| | | | Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: mvneta: split out GMACRussell King2020-09-025-276/+438
| | | | | | | Split out the code handling the GMAC from the rest of the driver. This block appears to be shared amongst several revisions of the IP. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: mvneta: convert to phylink pcs operationsRussell King2020-09-021-69/+109
| | | | | | | An initial stab at converting mvneta to PCS operations. There's a few FIXMEs to be solved. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: mvneta: move 1ms clock control into mac_prepare/mac_finishRussell King2020-09-021-11/+16
| | | | | | | Move the 1ms clock control out of mac_config() into mac_prepare() and mac_finish(), which simplifies the mac_config() code. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: mvneta: convert to use mac_prepare()/mac_finish()Russell King2020-09-021-24/+53
| | | | | | | Convert mvneta to use the mac_prepare() and mac_finish() methods in preparation to converting mvneta to split-PCS support. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: mvneta: program 1ms autonegotiation clock divisorRussell King2020-09-021-2/+6
| | | | | | | | Program the 1ms autonegotiation clock divisor according to the clocking rate of neta - without this, the 1ms clock ticks at about 660us on Armada 38x configured for 250MHz. Bring this into correct specification. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* phy: armada-38x: further augmentation of setupRussell King2020-09-022-20/+132
| | | | | | Further augmentation of the comphy setup. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* phy: armada-38x: fix NETA lockup when repeatedly switching speedsRussell King2020-09-021-7/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mvneta hardware appears to lock up in various random ways when repeatedly switching speeds between 1G and 2.5G, which involves reprogramming the COMPHY. It is not entirely clear why this happens, but best guess is that reprogramming the COMPHY glitches mvneta clocks causing the hardware to fail. It seems that rebooting resolves the failure, but not down/up cycling the interface alone. Various other approaches have been tried, such as trying to cleanly power down the COMPHY and then take it back through the power up initialisation, but this does not seem to help. It was finally noticed that u-boot's last step when configuring a COMPHY for "SGMII" mode was to poke at a register described as "GBE_CONFIGURATION_REG", which is undocumented in any external documentation. All that we have is the fact that u-boot sets a bit corresponding to the "SGMII" lane at the end of COMPHY initialisation. Experimentation shows that if we clear this bit prior to changing the speed, and then set it afterwards, mvneta does not suffer this problem on the SolidRun Clearfog when switching speeds between 1G and 2.5G. This problem was found while script-testing phylink. This fix also requires the corresponding change to DT to be effective. See "ARM: dts: armada-38x: fix NETA lockup when repeatedly switching speeds". Fixes: 14dc100b4411 ("phy: armada38x: add common phy support") Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* dt: update Marvell Armada 38x COMPHY bindingRussell King2020-09-021-1/+9
| | | | | | | | | | | | | | | | | | | | | Update the Marvell Armada 38x COMPHY binding with an additional optional register pair describing the location of an undocumented system register controlling something to do with the Gigabit Ethernet and COMPHY. There is one bit for each COMPHY lane that may be using the serdes, but exactly what this register does is completely unknown. This register only appears to exist on Armada 38x devices, and not other SoCs using the NETA ethernet block, so it seems logical that it should be part of the COMPHY. This is also how u-boot groups this register; it is dealt with as part of the COMPHY initialisation there. However, at the end of the day, due to the undocumented nature of this register, we can only guess. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: dsa/bcm_sf2: fix pause mode validationnet-queueRussell King2020-09-021-2/+10
| | | | | | | | | | The implementation appears not to support pause modes on anything but RGMII, RGMII_TXID, MII and REVMII interface modes. Let phylink know that detail. (This may not be correct; particularly see the FIXMEs in this patch.) Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: phylink: use phy interface mode bitmapsRussell King2020-09-021-11/+46
| | | | | | | Use the phy interface mode bitmaps for SFP modules and PHYs to select the operating interface for SFPs and PHYs with SFPs. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: phy: add supported_interfaces to marvell10g PHYsRussell King2020-09-021-0/+4
| | | | Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: phy: add supported_interfaces to marvell PHYsRussell King2020-09-021-0/+9
| | | | Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: phy: add supported_interfaces to bcm84881Russell King2020-09-021-0/+4
| | | | Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: phy: add supported_interfaces to phylibRussell King2020-09-021-0/+21
| | | | | | | | Add a supported_interfaces member to phylib so we know which interfaces a PHY supports. Currently, set any unconverted driver to indicate all interfaces are supported. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: phy: marvell10g: select host interface configurationRussell King2020-09-021-6/+47
| | | | | | | | Select the host interface configuration according to the capabilities of the host; this allows the kernel to support SFP modules using the 88x3310. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: phy: pass supported PHY interface types to phylibRussell King2020-09-022-0/+21
| | | | | | | | | | Pass the supported PHY interface types to phylib so that PHY drivers can select an appropriate host configuration mode for their interface according to the host capabilities. This is only done for SFP modules presently. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: mvpp2: fill in phy interface mode bitmapRussell King2020-09-011-0/+23
| | | | | | | Fill in the phy interface mode bitmap for the Marvell mvpp2 driver, so phylink can know which interfaces are supported by the MAC. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: mvneta: fill in phy interface mode bitmapRussell King2020-09-011-0/+16
| | | | | | | Fill in the phy interface mode bitmap for the Marvell mvneta driver, so phylink can know which interfaces are supported by the MAC. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
* net: phylink: use phy interface mode bitmaps for optical modulesRussell King2020-09-011-7/+49
| | | | | | | | Where a MAC provides the PHY interface mode capabilities, use the PHY interface mode bitmaps to select the operating interface mode for optical SFP modules, rather than using the linkmode bitmaps. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>