| Age | Commit message (Collapse) | Author |
|---|
|
Convert AMD (Xilinx) VCU bindings to yaml format.
Additional changes:
- move xlnx_vcu DT binding to clock from soc following commit
a2fe7baa27a4 ("clk: xilinx: move xlnx_vcu clock driver from soc")
- corrected clock sequence as per xilinx device-tree generator
Signed-off-by: Rohit Visavalia <rohit.visavalia@xilinx.com>
Link: https://lore.kernel.org/r/20250107044038.100945-2-rohit.visavalia@amd.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
When DT overlay is applied at run time compatible string or model AFAIK is
not updated. But when fdtoverlay tool is used it actually creates full
description for used SOM and carrier card(CC). That's why there is no
reason to use generic SOM name and its compatible strings because they are
not properly reflected in newly created DT.
Composing dt overlays together was introduced by commit 7a4c31ee877a
("arm64: zynqmp: Add support for Xilinx Kria SOM board") and later renamed
by commit 45fe0dc4ea2e ("arm64: xilinx: Use zynqmp prefix for SOM dt
overlays").
DTB selection is done prior booting OS that's why there is no need to do
run time composition for SOM and CC combination. And user space can use
compatible string and all listed revisions to figured it out which SOM and
CC combinations OS is running at.
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/14c184225cc4f0a61da5f8c98bc0767f8deba0df.1706019781.git.michal.simek@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
|
|
Revision 2 is SW compatible with revision 1 but it is necessary to reflect
it in model and compatible properties which are parsed by user space.
Rev 2 has improved a power on boot reset and MIO34 shutdown glich
improvement done via an additional filter in the GreenPak chip.
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/90e1a393154c3d87e8ee7dc9eef07fc937c1eaf7.1706019397.git.michal.simek@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
|
|
MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
It is hardware compatible with classic MicroBlaze processor. Processor can
be used with standard AMD/Xilinx IPs including interrupt controller and
timer.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Michal Simek <michal.simek@amd.com>
|
|
All Xilinx boards can hosts also soft core CPUs like MicroBlaze or
MicroBlaze V (RISC-V ISA) that's why move boards description from arm
folder to soc folder.
Similar change was done for Renesas by commit c27ce08b806d ("dt-bindings:
soc: renesas: Move renesas.yaml from arm to soc").
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Michal Simek <michal.simek@amd.com>
|
|
When running make dt_binding_check, the xlnx,vcu-settings binding
triggers the following two warnings:
'additionalProperties' is a required property
example-0: vcu@a0041000:reg:0: [0, 2684620800, 0, 4096] is too long
Fix the binding and make the checker happy.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201202090522.251607-1-m.tretter@pengutronix.de
Signed-off-by: Rob Herring <robh@kernel.org>
|
|
The xlnx,vcu binding comprises two adjacent register banks:
The first register bank ("vcu_slcr") contains registers for setting the
clocks of the vcu and controlling the performance monitors. The second
bank ("logicoreip") contains the configuration settings of the video codec
unit, which are set before synthesizing the bitstream.
Drivers that drive the actual video codec unit need to read the
registers from the logicoreip register bank for configuring the vcu
firmware.
As logicoreip is a too generic name for this register bank, use
"vcu-settings" as a binding name, because the register bank basically
provides the configuration settings of the VCU.
Therefore, add the vcu-settings binding to provide a syscon interface
for other drivers to read these registers.
The alternative would have been to merge the two register banks of the
xlnx,vcu binding into one register bank and make xlnx,vcu provide a
syscon interface, but that would lead to more incompatibility than
making second register bank of xlnx,vcu optional.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201109134818.4159342-3-m.tretter@pengutronix.de
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
|
Add Device Tree binding document for logicoreIP. This logicoreIP
provides the isolation between the processing system and
programmable logic. Also provides the clock related information.
Signed-off-by: Dhaval Shah <dshah@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
