linux-arm.git - Russell King's ARM Linux kernel tree

Age	Commit message (Collapse)	Author
2022-08-18	ARM: remove obsolete Makefile.boot infrastructure	Arnd Bergmann
	There are a number of old Makefile.boot files that remain from the multiplatform conversion, and three that are still in use. These provide the "ZRELADDR", "PARAMS_PHYS" and "INITRD_PHYS" values that are platform specific. It turns out that we can generally just derive this from information that is available elsewhere: - ZRELADDR is normally detected at runtime with the CONFIG_AUTO_ZRELADDR flag, but also needed to be passed to for 'make uImage'. In a multiplatform kernel, one always has to pass this as the $(LOADADDR) variable, but in the StrongARM kernels we can derive it from the sum of $(CONFIG_PHYS_OFFSET) and $(TEXT_OFFSET) that are already known. - PARAMS_PHYS and INITRD_PHYS are only used for bootpImage, which in turn is only used for the pre-ATAGS 'param_struct' based boot interface on StrongARM based machines with old boot loaders. They can both be derived from CONFIG_PHYS_OFFSET and a machine specific offset for the initrd, so all of the logic for these can be part of arch/arm/boot/bootp/Makefile. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-05-21	treewide: Add SPDX license identifier - Makefile/Kconfig	Thomas Gleixner
	Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-15	ARM: lpc18xx: add basic support for NXP LPC18xx/43xx SoCs	Joachim Eastwood
	Add support for NXP's LPC18xx (Cortex-M3) and LPC43xx (Cortex-M4) SoCs. These SoCs are NXP's high preformance MCU line and can run at clock speeds up to 180 MHz for LPC18xx and 204 MHz for LPC43xx. LPC43xx is more or less a LPC18xx with a Cortex-M4F core and a few extra peripherals. The LPC43xx series also features one or two Cortex-M0 cores that can be used to offload the main M4 core. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Arnd Bergmann <arnd@arndb.de>