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path: root/arch/arm/mm/proc-v7-2level.S
AgeCommit message (Expand)Author
2013-04-03ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP insteadWill Deacon
2013-02-16ARM: 7650/1: mm: replace direct access to mm->context.id with new macroBen Dooks
2012-11-09ARM: mm: introduce present, faulting entries for PAGE_NONEWill Deacon
2012-11-09ARM: mm: introduce L_PTE_VALID for page table entriesWill Deacon
2012-11-09ARM: mm: don't use the access flag permissions mechanism for classic MMUWill Deacon
2012-07-09ARM: 7445/1: mm: update CONTEXTIDR register to contain PID of current processWill Deacon
2012-04-17ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on ASID-capable CPUsCatalin Marinas
2012-04-17ARM: Use TTBR1 instead of reserved context IDWill Deacon
2011-12-08ARM: LPAE: Factor out classic-MMU specific code into proc-v7-2level.SCatalin Marinas