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path: root/arch/arm64/include/asm/cache.h
AgeCommit message (Expand)Author
2019-07-08Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a...Linus Torvalds
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Thomas Gleixner
2019-06-17arm64/mm: Correct the cache line size warning with non coherent deviceMasayoshi Mizuma
2019-06-04arm64: cacheinfo: Update cache_line_size detected from DT or PPTTShaokun Zhang
2019-01-16kasan, arm64: remove redundant ARCH_SLAB_MINALIGN defineAndrey Konovalov
2019-01-08kasan, arm64: use ARCH_SLAB_MINALIGN instead of manual aligningAndrey Konovalov
2018-10-16arm64: cpufeature: Fix handling of CTR_EL0.IDC fieldSuzuki K Poulose
2018-07-05arm64: Fix mismatched cache line size detectionSuzuki K Poulose
2018-05-15arm64: Increase ARCH_DMA_MINALIGN to 128Catalin Marinas
2018-05-11Revert "arm64: Increase the max granular size"Catalin Marinas
2018-03-27Revert "arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size)"Will Deacon
2018-03-09arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDCShanker Donthineni
2018-03-06arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size)Catalin Marinas
2017-03-20arm64: cache: Identify VPIPT I-cachesWill Deacon
2017-03-20arm64: cache: Merge cachetype.h into cache.hWill Deacon
2015-10-28arm64: Increase the max granular sizeTirumalesh Chalamarla
2014-12-03arm64: Implement support for read-mostly sectionsJungseok Lee
2014-05-09arm64: Implement cache_line_size() based on CTR_EL0.CWGCatalin Marinas
2012-09-17arm64: Cache maintenance routinesCatalin Marinas
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