summaryrefslogtreecommitdiff
path: root/arch/arm64/include/asm/tlbflush.h
AgeCommit message (Expand)Author
2024-04-11arm64: tlb: Allow range operation for MAX_TLBI_RANGE_PAGESGavin Shan
2024-04-11arm64: tlb: Improve __TLBI_VADDR_RANGE()Gavin Shan
2024-04-10arm64: tlb: Fix TLBI RANGE operandGavin Shan
2024-02-22arm64/mm: dplit __flush_tlb_range() to elide trailing DSBRyan Roberts
2023-11-27arm64/mm: Update tlb invalidation routines for FEAT_LPA2Ryan Roberts
2023-11-27arm64/mm: Modify range-based tlbi to decrement scaleRyan Roberts
2023-11-02Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds
2023-10-16arm64: Avoid cpus_have_const_cap() for ARM64_WORKAROUND_REPEAT_TLBIMark Rutland
2023-10-16arm64: Avoid cpus_have_const_cap() for ARM64_HAS_ARMv8_4_TTLMark Rutland
2023-09-22arm64: tlbflush: Rename MAX_TLBI_OPSOliver Upton
2023-09-07Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds
2023-08-21arm64: tlbflush: add some comments for TLB batched flushingYicong Yang
2023-08-18mmu_notifiers: rename invalidate_range notifierAlistair Popple
2023-08-18mmu_notifiers: call invalidate_range() when invalidating TLBsAlistair Popple
2023-08-18arm64: support batched/deferred tlb shootdown during page reclamation/migrationBarry Song
2023-08-17arm64: tlb: Implement __flush_s2_tlb_range_op()Raghavendra Rao Ananta
2023-08-17arm64: tlb: Refactor the core flush algorithm of __flush_tlb_rangeRaghavendra Rao Ananta
2021-08-06arm64: mm: Fix TLBI vs ASID rolloverWill Deacon
2021-08-03arm64: fix typo in a commentJason Wang
2020-08-28arm64: use a common .arch preamble for inline assemblySami Tolvanen
2020-07-15arm64: tlb: Use the TLBI RANGE feature in arm64Zhenyu Ye
2020-07-10arm64: tlb: don't set the ttl value in flush_tlb_page_nosyncZhenyu Ye
2020-07-07arm64: Shift the __tlbi_level() indentation leftCatalin Marinas
2020-07-07arm64: tlb: Set the TTL field in flush_tlb_rangeZhenyu Ye
2020-07-07arm64: Add tlbi_user_level TLB invalidation helperZhenyu Ye
2020-07-07arm64: Add level-hinted TLB invalidation helperMarc Zyngier
2019-08-27arm64: tlb: Ensure we execute an ISB following walk cache invalidationWill Deacon
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Thomas Gleixner
2019-06-12arm64: tlbflush: Ensure start/end of address range are aligned to strideWill Deacon
2018-12-25Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a...Linus Torvalds
2018-11-29arm64: Add workaround for Cortex-A76 erratum 1286807Catalin Marinas
2018-11-27arm64: tlbi: Set MAX_TLBI_OPS to PTRS_PER_PTEWill Deacon
2018-11-26arm64: mm: Don't wait for completion of TLB invalidation when page agingAlex Van Brunt
2018-09-11arm64: tlb: Rewrite stale comment in asm/tlbflush.hWill Deacon
2018-09-11arm64: tlb: Avoid synchronous TLBIs when freeing page tablesWill Deacon
2018-09-11arm64: tlbflush: Allow stride to be specified for __flush_tlb_range()Will Deacon
2018-09-11arm64: tlb: Justify non-leaf invalidation in flush_tlb_range()Will Deacon
2018-09-11arm64: tlb: Add DSB ISHST prior to TLBI in __flush_tlb_[kernel_]pgtable()Will Deacon
2018-09-11arm64: tlb: Use last-level invalidation in flush_tlb_kernel_range()Will Deacon
2018-07-06arm64: tlbflush: Introduce __flush_tlb_kernel_pgtableChintan Pandya
2018-03-28arm64: tlbflush: avoid writing RES0 bitsPhilip Elcan
2017-12-11arm64: mm: Invalidate both kernel and user ASIDs when performing TLBIWill Deacon
2017-02-01arm64: Work around Falkor erratum 1009Christopher Covington
2016-09-28arm64: tlbflush.h: add __tlbi() macroMark Rutland
2015-10-07arm64: tlb: remove redundant barrier from __flush_tlb_pgtableWill Deacon
2015-10-07arm64: tlbflush: remove redundant ASID casts to (unsigned long)Will Deacon
2015-10-07arm64: flush: use local TLB and I-cache invalidationWill Deacon
2015-07-28arm64: Use last level TLBI for user pte changesCatalin Marinas
2015-07-28arm64: Clean up __flush_tlb(_kernel)_range functionsCatalin Marinas
2015-07-27arm64: move update_mmu_cache() into asm/pgtable.hWill Deacon
generated by cgit (git 2.34.1) at 2025-03-18 17:07:55 +0000