| Age | Commit message (Expand) | Author |
|---|
| 2024-02-28 | MIPS: mipsregs: Parse fp and sp register by name in parse_r | Jiaxun Yang |
| 2024-02-23 | MIPS: mipsregs: Set proper ISA level for virt extensions | Jiaxun Yang |
| 2024-02-23 | MIPS: Implement microMIPS MT ASE helpers | Jiaxun Yang |
| 2024-02-20 | MIPS: Unify define of CP0 registers for uasm code | Jiaxun Yang |
| 2024-01-08 | MIPS: Fix typos | Bjorn Helgaas |
| 2023-01-26 | MIPS: Always use -Wa,-msoft-float and eliminate GAS_HAS_SET_HARDFLOAT | Nathan Chancellor |
| 2022-07-14 | MIPS: Remove VR41xx support | Thomas Bogendoerfer |
| 2022-02-22 | MIPS: remove asm/war.h | Thomas Bogendoerfer |
| 2021-09-23 | MIPS: Avoid macro redefinitions | Paul Cercueil |
| 2021-06-29 | MIPS: set mips32r5 for virt extensions | Nick Desaulniers |
| 2021-02-11 | MIPS: Make check condition for SDBBP consistent with EJTAG spec | Tiezhu Yang |
| 2020-09-21 | MIPS: Loongson-3: Enable COP2 usage in kernel | Huacai Chen |
| 2020-09-07 | MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config option | Thomas Bogendoerfer |
| 2020-08-24 | MIPS: Remove PNX833x alias NXP_STB22x | Thomas Bogendoerfer |
| 2020-07-31 | MIPS: handle Loongson-specific GSExc exception | WANG Xuerui |
| 2020-07-31 | MIPS: add definitions for Loongson-specific CP0.Diag1 register | WANG Xuerui |
| 2020-07-08 | MIPS: Unify naming style of vendor CP0.Config6 bits | Huacai Chen |
| 2020-06-04 | KVM: MIPS: Add CONFIG6 and DIAG registers emulation | Huacai Chen |
| 2020-05-24 | MIPS: Tidy up CP0.Config6 bits definition | Huacai Chen |
| 2020-05-22 | mips: Add CONFIG/CONFIG6/Cause reg fields macro | Serge Semin |
| 2020-05-22 | mips: Add CP0 Write Merge config support | Serge Semin |
| 2020-05-21 | mips: MAAR: Use more precise address mask | Serge Semin |
| 2020-05-19 | mips: MAAR: Add XPA mode support | Serge Semin |
| 2020-05-17 | MIPS: define more Loongson CP0.Config6 and CP0.Diag feature bits | WANG Xuerui |
| 2020-01-22 | MIPS: Add MAC2008 Support | Jiaxun Yang |
| 2019-11-22 | MIPS: Ingenic: Disable abandoned HPTLB function. | Zhou Yanjie |
| 2019-08-05 | MIPS: Ingenic: Disable broken BTB lookup optimization. | Zhou Yanjie |
| 2019-02-04 | MIPS: MemoryMapID (MMID) Support | Paul Burton |
| 2019-02-04 | MIPS: Add GINVT instruction helpers | Paul Burton |
| 2018-11-09 | MIPS: Avoid using .set mips0 to restore ISA | Paul Burton |
| 2018-10-16 | MIPS: Cleanup DSP ASE detection | Paul Burton |
| 2018-08-13 | Merge tag 'mips_4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/l... | Linus Torvalds |
| 2018-08-07 | MIPS: Use dins to simplify __write_64bit_c0_split() | Paul Burton |
| 2018-08-07 | MIPS: Use read-write output operand in __write_64bit_c0_split() | Paul Burton |
| 2018-07-27 | Revert "MIPS: BCM47XX: Enable 74K Core ExternalSync for PCIe erratum" | Rafał Miłecki |
| 2018-07-23 | MIPS: Loongson64: Define and use some CP0 registers | Huacai Chen |
| 2018-06-18 | MIPS: BCM47XX: Enable 74K Core ExternalSync for PCIe erratum | Tokunori Ikegami |
| 2018-05-15 | MIPS: Probe for MIPS MT perf counters per TC | Matt Redfearn |
| 2018-02-19 | MIPS: Add crc instruction support flag to elf_hwcap | Marcin Nowakowski |
| 2018-01-22 | MIPS: XPA: Standardise readx/writex accessors | James Hogan |
| 2018-01-22 | MIPS: XPA: Allow use of $0 (zero) to MTHC0 | James Hogan |
| 2018-01-22 | MIPS: XPA: Use XPA instructions in assembly | James Hogan |
| 2018-01-22 | MIPS: VZ: Pass GC0 register names in $n format | James Hogan |
| 2018-01-22 | MIPS: VZ: Update helpers to use new asm macros | James Hogan |
| 2018-01-22 | MIPS: Add helpers for assembler macro instructions | James Hogan |
| 2018-01-09 | MIPS: mipsregs.h: Make read_c0_prid use const accessor | James Hogan |
| 2018-01-09 | MIPS: mipsregs.h: Add read const Cop0 macros | James Hogan |
| 2017-11-08 | MIPS: Use SLL by 0 for 32-bit truncation in `__read_64bit_c0_split' | Maciej W. Rozycki |
| 2017-09-21 | MIPS: Fix input modify in __write_64bit_c0_split() | James Hogan |
| 2017-08-30 | MIPS: Add accessor & bit definitions for GlobalNumber | Paul Burton |
