summaryrefslogtreecommitdiff
path: root/arch/riscv/include/asm/tlbflush.h
AgeCommit message (Expand)Author
2024-01-31riscv: mm: execute local TLB flush after populating vmemmapVincent Chen
2024-01-20Merge tag 'riscv-for-linus-6.8-mw4' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds
2024-01-11riscv: Add support for BATCHED_UNMAP_TLB_FLUSHAlexandre Ghiti
2023-12-14mm: Introduce flush_cache_vmap_early()Alexandre Ghiti
2023-11-06riscv: Improve flush_tlb_kernel_range()Alexandre Ghiti
2023-11-06riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlbAlexandre Ghiti
2023-11-06riscv: Improve tlb_flush()Alexandre Ghiti
2023-03-21riscv: mm: Fix incorrect ASID argument when flushing TLBDylan Jhong
2023-03-09Revert "riscv: mm: notify remote harts about mmu cache updates"Sergey Matyukevich
2022-12-08riscv: mm: notify remote harts about mmu cache updatesSergey Matyukevich
2021-06-08riscv: fix build error when CONFIG_SMP is disabledBixuan Cui
2021-04-26riscv: sifive: Apply errata "cip-1200" patchVincent Chen
2019-11-17riscv: add nommu supportChristoph Hellwig
2019-10-14riscv: tlbflush: remove confusing comment on local_flush_tlb_all()Paul Walmsley
2019-09-05riscv: move the TLB flush logic out of lineChristoph Hellwig
2019-09-05riscv: cleanup riscv_cpuid_to_hartid_maskChristoph Hellwig
2019-08-13riscv: fix flush_tlb_range() end address for flush_tlb_page()Paul Walmsley
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner
2018-10-22RISC-V: Use Linux logical CPU number instead of hartidAtish Patra
2018-06-07riscv: use NULL instead of a plain 0Luc Van Oostenryck
2018-01-30RISC-V: Limit the scope of TLB shootdownsAndrew Waterman
2018-01-07riscv: remove CONFIG_MMU ifdefsChristoph Hellwig
2017-12-01RISC-V: User-Visible ChangesPalmer Dabbelt
2017-11-30RISC-V: Flush I$ when making a dirty page executableAndrew Waterman
2017-11-28RISC-V: `sfence.vma` orderes the instruction cachePalmer Dabbelt
2017-09-26RISC-V: Atomic and Locking CodePalmer Dabbelt