| Age | Commit message (Expand) | Author |
|---|
| 2024-09-15 | Merge patch series "Svvptc extension to remove preventive sfence.vma" | Palmer Dabbelt |
| 2024-09-15 | riscv: Add ISA extension parsing for Svvptc | Alexandre Ghiti |
| 2024-07-31 | riscv: cpufeature: Do not drop Linux-internal extensions | Samuel Holland |
| 2024-07-22 | riscv: Extend cpufeature.c to detect vendor extensions | Charlie Jenkins |
| 2024-07-12 | Merge patch series "riscv: Apply Zawrs when available" | Palmer Dabbelt |
| 2024-07-12 | riscv: Add Zawrs support for spinlocks | Christoph Müllner |
| 2024-06-26 | riscv: add ISA extension parsing for Zcmop | Clément Léger |
| 2024-06-26 | riscv: add ISA parsing for Zca, Zcf, Zcd and Zcb | Clément Léger |
| 2024-06-26 | riscv: add ISA extensions validation callback | Clément Léger |
| 2024-06-26 | riscv: add ISA extension parsing for Zimop | Clément Léger |
| 2024-05-30 | riscv: vector: adjust minimum Vector requirement to ZVE32X | Andy Chiu |
| 2024-05-30 | riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection | Andy Chiu |
| 2024-05-30 | riscv: cpufeature: call match_isa_ext() for single-letter extensions | Andy Chiu |
| 2024-05-30 | riscv: vector: add a comment when calling riscv_setup_vsize() | Andy Chiu |
| 2024-05-22 | riscv: cpufeature: Fix extension subset checking | Charlie Jenkins |
| 2024-05-22 | riscv: cpufeature: Fix thead vector hwcap removal | Charlie Jenkins |
| 2024-03-22 | Merge tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/ker... | Linus Torvalds |
| 2024-03-13 | Merge patch series "riscv: Use Kconfig to set unaligned access speed" | Palmer Dabbelt |
| 2024-03-13 | riscv: Set unaligned access speed at compile time | Charlie Jenkins |
| 2024-03-13 | riscv: Decouple emulated unaligned accesses from access speed | Charlie Jenkins |
| 2024-03-13 | riscv: lib: Introduce has_fast_unaligned_access() | Charlie Jenkins |
| 2024-03-12 | perf: RISC-V: Introduce Andes PMU to support perf event sampling | Yu Chien Peter Lin |
| 2024-02-29 | Merge patch series "riscv: cbo.zero fixes" | Palmer Dabbelt |
| 2024-02-29 | riscv: Add a custom ISA extension for the [ms]envcfg CSR | Samuel Holland |
| 2024-02-29 | riscv: Fix enabling cbo.zero when running in M-mode | Samuel Holland |
| 2024-02-23 | RISC-V: Ignore V from the riscv,isa DT property on older T-Head CPUs | Conor Dooley |
| 2024-01-17 | Merge patch series "riscv: Add fine-tuned checksum functions" | Palmer Dabbelt |
| 2024-01-17 | riscv: Add static key for misaligned accesses | Charlie Jenkins |
| 2024-01-09 | Merge patch series "riscv: hwprobe: add Zicond, Zacas and Ztso support" | Palmer Dabbelt |
| 2024-01-09 | riscv: add ISA extension parsing for Zacas | Clément Léger |
| 2024-01-09 | riscv: add ISA extension parsing for Ztso | Clément Léger |
| 2024-01-03 | RISC-V: Remove the removed single-letter extensions | Palmer Dabbelt |
| 2023-12-12 | riscv: add ISA extension parsing for Zfa | Clément Léger |
| 2023-12-12 | riscv: add ISA extension parsing for Zvfh[min] | Clément Léger |
| 2023-12-12 | riscv: add ISA extension parsing for Zihintntl | Clément Léger |
| 2023-12-12 | riscv: add ISA extension parsing for Zfh/Zfh[min] | Clément Léger |
| 2023-12-12 | riscv: add ISA extension parsing for vector crypto | Clément Léger |
| 2023-12-12 | riscv: add ISA extension parsing for scalar crypto | Evan Green |
| 2023-12-12 | riscv: add ISA extension parsing for Zbc | Clément Léger |
| 2023-11-10 | Merge tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/ker... | Linus Torvalds |
| 2023-11-08 | Merge tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/ker... | Linus Torvalds |
| 2023-11-07 | RISC-V: Probe misaligned access speed in parallel | Evan Green |
| 2023-11-05 | riscv: don't probe unaligned access speed if already done | Jisheng Zhang |
| 2023-11-05 | Merge patch series "Add support to handle misaligned accesses in S-mode" | Palmer Dabbelt |
| 2023-11-01 | riscv: report misaligned accesses emulation to hwprobe | Clément Léger |
| 2023-11-01 | riscv: annotate check_unaligned_access_boot_cpu() with __init | Clément Léger |
| 2023-10-31 | RISC-V: clarify the QEMU workaround in ISA parser | Tsukasa OI |
| 2023-10-12 | RISC-V: Detect Zicond from ISA string | Anup Patel |
| 2023-10-12 | RISC-V: Detect Smstateen extension | Mayuresh Chitale |
| 2023-09-21 | RISC-V: Enable cbo.zero in usermode | Andrew Jones |
