linux-arm.git - Russell King's ARM Linux kernel tree

Age	Commit message (Expand)	Author
2024-02-29	Merge patch series "riscv: cbo.zero fixes"	Palmer Dabbelt
2024-02-29	riscv: Add a custom ISA extension for the [ms]envcfg CSR	Samuel Holland
2024-02-29	riscv: Fix enabling cbo.zero when running in M-mode	Samuel Holland
2024-02-23	RISC-V: Ignore V from the riscv,isa DT property on older T-Head CPUs	Conor Dooley
2024-01-17	Merge patch series "riscv: Add fine-tuned checksum functions"	Palmer Dabbelt
2024-01-17	riscv: Add static key for misaligned accesses	Charlie Jenkins
2024-01-09	Merge patch series "riscv: hwprobe: add Zicond, Zacas and Ztso support"	Palmer Dabbelt
2024-01-09	riscv: add ISA extension parsing for Zacas	Clément Léger
2024-01-09	riscv: add ISA extension parsing for Ztso	Clément Léger
2024-01-03	RISC-V: Remove the removed single-letter extensions	Palmer Dabbelt
2023-12-12	riscv: add ISA extension parsing for Zfa	Clément Léger
2023-12-12	riscv: add ISA extension parsing for Zvfh[min]	Clément Léger
2023-12-12	riscv: add ISA extension parsing for Zihintntl	Clément Léger
2023-12-12	riscv: add ISA extension parsing for Zfh/Zfh[min]	Clément Léger
2023-12-12	riscv: add ISA extension parsing for vector crypto	Clément Léger
2023-12-12	riscv: add ISA extension parsing for scalar crypto	Evan Green
2023-12-12	riscv: add ISA extension parsing for Zbc	Clément Léger
2023-11-10	Merge tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/ker...	Linus Torvalds
2023-11-08	Merge tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/ker...	Linus Torvalds
2023-11-07	RISC-V: Probe misaligned access speed in parallel	Evan Green
2023-11-05	riscv: don't probe unaligned access speed if already done	Jisheng Zhang
2023-11-05	Merge patch series "Add support to handle misaligned accesses in S-mode"	Palmer Dabbelt
2023-11-01	riscv: report misaligned accesses emulation to hwprobe	Clément Léger
2023-11-01	riscv: annotate check_unaligned_access_boot_cpu() with __init	Clément Léger
2023-10-31	RISC-V: clarify the QEMU workaround in ISA parser	Tsukasa OI
2023-10-12	RISC-V: Detect Zicond from ISA string	Anup Patel
2023-10-12	RISC-V: Detect Smstateen extension	Mayuresh Chitale
2023-09-21	RISC-V: Enable cbo.zero in usermode	Andrew Jones
2023-09-21	RISC-V: Make zicbom/zicboz errors consistent	Andrew Jones
2023-09-08	Merge patch series "RISC-V: Probe for misaligned access speed"	Palmer Dabbelt
2023-09-01	RISC-V: Probe for unaligned access speed	Evan Green
2023-09-01	Merge tag 'riscv-for-linus-6.6-mw1' of git://git.kernel.org/pub/scm/linux/ker...	Linus Torvalds
2023-08-30	Merge tag 'devicetree-header-cleanups-for-6.6' of git://git.kernel.org/pub/sc...	Linus Torvalds
2023-08-28	riscv: Explicitly include correct DT includes	Rob Herring
2023-07-25	RISC-V: provide Kconfig & commandline options to control parsing "riscv,isa"	Conor Dooley
2023-07-25	RISC-V: enable extension detection from dedicated properties	Conor Dooley
2023-07-25	RISC-V: split riscv_fill_hwcap() in 3	Conor Dooley
2023-07-25	RISC-V: add single letter extensions to riscv_isa_ext	Conor Dooley
2023-07-25	RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap()	Conor Dooley
2023-07-25	RISC-V: shunt isa_ext_arr to cpufeature.c	Conor Dooley
2023-07-12	RISC-V: Don't include Zicsr or Zifencei in I from ACPI	Palmer Dabbelt
2023-06-23	Merge patch series "ISA string parser cleanups"	Palmer Dabbelt
2023-06-21	RISC-V: always report presence of extensions formerly part of the base ISA	Conor Dooley
2023-06-21	RISC-V: remove decrement/increment dance in ISA string parser	Conor Dooley
2023-06-21	RISC-V: rework comments in ISA string parser	Conor Dooley
2023-06-21	RISC-V: validate riscv,isa at boot, not during ISA string parsing	Conor Dooley
2023-06-21	RISC-V: simplify register width check in ISA string parsing	Conor Dooley
2023-06-19	Merge patch series "RISC-V: Export Zba, Zbb to usermode via hwprobe"	Palmer Dabbelt
2023-06-19	RISC-V: Track ISA extensions per hart	Evan Green
2023-06-19	RISC-V: Add Zba, Zbs extension probing	Evan Green